Compact Disc Player IC

Ordering
Orderingnumber
number: :ENA2080A
ENA2080
LC786960E
CMOS LSI
Compact Disc Player IC
http://onsemi.com
Overview
The LC786960E integrates ARM7TDMI-S™, CD servo control, CD signal processing, compressed audio decode
processing, audio signal processing, USB host processing, SD memory card host processing and a flash memory to
store the program for ARM7TDMI-S™ and various data in a package. Furthermore, various kinds of interface
functions such as SIO, UART etc. reduce the external main controller’s processing load and make high performance
and much functional CD player system, using with less components.
Features
 RF signal processing for CD-DA/R/RW, servo control, and EFM signal processing
 MP3*, WMA*, AAC* decoder processing
 Sampling rate convertor, High frequency compensation filter and other various audio signal processing
 USB host function (Full speed as 12Mbps), SD memory card host function
 ARM7TDMI-S™ as internal CPU core, flash memory for program and various data storage
 Operating voltage: 3.3V typical
 Operating temperature: -40C to +85C
 Packages: QIP100E (14  20)
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of this data sheet.
QIP100E(14X20)
is a registered trademark of ARM Limited.
* MP3(MPEG Layer-3 Audio Coding)
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor imply
any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required.
For details, please visit http://mp3licensing.com/.
* Windows Media Audio
Windows MediaTM is a trademark and a registered trademark in the United States and other countries of United States Microsoft Corporation.
* AAC
Advanced Audio Coding
* This product is licensed from Silicon Storage Technology Inc. (USA).
Semiconductor Components Industries, LLC, 2013
September, 2013 Ver. 1.0.0
91113HK/80112HK 20120531-S00007 No.A2080-1/24
LC786960E
Detail of Functions
CD DSP functions
<Playback functions>
 Playback mode: CLV playback/Jitter free playback (VCEC)
 Playback speed: Normal speed, double speed
<RF Processing block>
 RF system: AGC, CD-R and CD-R/W playback support, peak hold, bottom hold
 Error system: TE signal generation, FE signal generation
 Detection: Track count signal, Jitter, Defect (black, mirror)
 LASER power controller (APC)
 DC offset voltage cancellation
<Servo control block>
 All servo systems as tracking, focus, sled and spindle are implemented with digital processing.
 Automatic adjustment functions: focus gain, focus bias, focus offset,
tracking gain, tracking offset and tracking balance
 Shock detection / Interruption detection
<CD signal processing block>
 EFM signal synchronization detection, protection and interpolation
 Error detection, correction (C1=double, C2=quadruple/double)
 Jitter margin ±19 frames
<CD TEXT processing block>
 Buffers CD-TEXT data
 Starts buffering desired ID3/ID4 of CD-TEXT data.
<CD-ROM processing block>
 CD-ROM decoding (Mode1, Mode2 <form1, form2>)
 Outputs CD-ROM decoded data
Compressed audio decode functions
 MP3 decode (ISO/IEC 11172-3, ISO/IEC 13818-3)
Sampling rate support:
MPEG1-Layer1/2/3 (32kHz, 44.1kHz, 48kHz)
MPEG2-Layer1/2/3 (16kHz, 22.05kHz, 24kHz)
MPEG2.5-Layer3 ( 8kHz, 11.025kHz, 12kHz)
Bit rate support:
All Bit Rate (Variable Bit Rate support)
MPEG header read support
 WMA decode (Version 9 standard)
Sampling rate support:
8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz, 48kHz
Bit rate support:
5kbps to 384kbps (Variable Bit Rate support)
 AAC decode (ISO/IEC 14496-3, ISO/IEC 13818-7)
Profile:
MPEG4-AAC-LowComplexity
Sampling rate support:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,
48kHz
Bit rate support:
Monaural 8kbps to 160kbps (Variable bit rate support)
Stereo
16kbps to 320kbps (Variable bit rate support)
 Decodes both the compressed data read from the disc and input from outside through the interface pins
No.A2080-2/24
LC786960E
Audio processing functions
<Audio processing block>
 Sampling rate converter (SRC) for compressed audio data playback
 High frequency compensation filter for compressed audio data playback
 Interpolation (CD-DA only)
 Mute function (-12dB, -∞)
 Digital attenuator
 De-emphasis filter
 Bilingual function
 Bass / Treble filter
<Digital filter and D/A convertor processing block>
 Eight-fold over-sampling digital filter (24bit)
 One bit DAC (tertiary  noise shaper type)
 Secondary LPF for audio output
<Interface block>
 Allows external audio data supply to the digital filter and D/A converter (Uses four signals)
 Various external audio data output format
IIS (48fs/64fs), MSB first right justified (32fs/48fs/64fs), 16 bit data length
External interface functions
<USB host control block>
 Open Host Controller Interface 1.0a
 Universal Serial Bus Specification 1.1
Supports up to Full speed (12MHz)for USB2.0
 Supports four kinds of transfer type (Control/Bulk/Interrupt/Isochronous)
<SD memory card host control block>
 Multimedia Card Specification v2.11
 Secure Digital Memory Card Physical Layer Specification v0.96
* Individual contract is necessary to use SD memory card controller. For detail, please contact to us.
Internal Microcontroller functions
<Sequencer control>
 CD, USB, SD memory card playback control
Servo control, CD-ROM/USB/SD file analysis, etc.
<Communication control between main controller>
 Communication format: SIO
<Peripheral interface block>
 GPIO port
27ports maximum (Shared with other functions. Several pins are 5V tolerant.)
 External interrupt pins 4pins maximum (Shared with other functions.)
 Serial interface
SIO
clock synchronized full duplex (3 lines) 2 channel
UART
full duplex
2 channel
IIC
master function
1 channel
<Program memory block>
 Flash memory
Program version up from the external media (CD-ROM/USB)or main controller is available.
<Others>
 Watch Dog Timer
Notify to outside from the pin or reset internally.
 Power management
2 kinds of sleep mode
(1) Only CPU core operates at slow clock and clocks for other blocks are stopping.
(2) All clocks are stopping.
Others
<Internal power supply>
 1.5V regulator for internal blocks
No.A2080-3/24
LC786960E
Specifications
Absolute Maximum Ratings at Ta = 25C, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Maximum supply voltage
Symbol
Pin names
VDD max
DVDD, AVDD, LRVDD, XVDD1,
Input voltage 1
VIN1
XVDD2, UVDD, VVDD1, VVDD2,
VVDD3
Input pins other than VIN2
Input voltage 2
VIN2
RESB, SIFCK, SIFDI, SIFDO,
Conditions
Ratings
Unit
-0.3 to +3.95
V
-0.3 to DVDD+0.3
V
-0.3 to +5.6
V
-0.3 to DVDD+0.3
V
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, JTRSTB, JTCK,
JTDI, JTMS
Output voltage
VOUT
Allowable power dissipation
Pd max
Ta  85C
519
Mounted reference PCB (*)
mW
Operating temperature
Topr
-40 to +85
C
Storage temperature
Tstg
-40 to +125
C
(*)Reference PCB: 114.3mm×76.1mm×1.6mm, glass epoxy resin
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85C,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Supply voltage
High-level input voltage
Symbol
VDD1
VIH(1)
Pin names
Conditions
DVDD, AVDD, LRVDD, XVDD1,
XVDD2, UVDD, VVDD1, VVDD2,
min
typ
max
Unit
3.00
3.60
V
Schmitt
2.00
5.50
V
Schmitt
2.00
VDD1
V
Schmitt
0
0.80
V
Schmitt
0
0.80
V
VVDD3
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
JTMS, JTRSTB, JTCK, JTDI
VIH(2)
GP13, GP30, GP31, GP32,
GP33, GP34, GP35, GP36,
GP37, GP43, GP44, GP45,
GP50, GP51, GP52, GP53
Low-level input voltage
VIL(1)
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
JTMS, JTRSTB, JTCK, JTDI
VIL(2)
GP13, GP30, GP31, GP32,
GP33, GP34, GP35, GP36,
GP37, GP43, GP44, GP45,
GP50, GP51, GP52, GP53,
MODE0, MODE1, MODE2
Crystal oscillator frequency
FX1
XIN
XOUT
FX2
Oscillator circuit
12.0
MHz
Oscillator circuit
16.9344
MHz
X16IN
X16OUT
No.A2080-4/24
LC786960E
Electrical Characteristics at Ta = -40 to +85C, VDD1 = 3.0V to 3.6V,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Current drain
High-level input current
Symbol
IDD1
IIH(1)
Pin names
min
typ
DVDD, AVDD, LRVDD,
XVDD1, XVDD2, UVDD,
VVDD1, VVDD2, VVDD3
RESB, SIFCK, SIFDI,
JTMS, JTRSTB, JTCK, JTDI,
IIH(2)
Conditions
max
125
Unit
144
mA
10.00
A
10.00
A
Schmitt,
SIFDO, SIFCE, BUSYB,
VIN = 5.50V
Built-in
GP03, GP04, GP05, GP06,
Pull-down
GP07, GP10, GP11, GP12
resistor OFF
GP13, GP30, GP31, GP32,
Schmitt,
GP33, GP34, GP35, GP36,
GP37, GP43, GP44, GP45,
VIN = VDD1
Built-in
GP50, GP51, GP52, GP53
Pull-down
resistor OFF
Low-level input current
IIL(1)
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP30, GP31, GP32,
Schmitt,
GP33, GP34, GP35, GP36,
VIN = 0V
-10.00
A
VDD1-0.6
V
VDD1-0.6
V
GP37, GP43, GP44, GP45,
GP50, GP51, GP52, GP53,
JTMS, JTRSTB, JTCK, JTDI,
MODE0, MODE1, MODE2
High-level output voltage
VOH(1)
GP04, GP05, GP06, GP07,
GP12, GP13, GP30, GP31,
GP32, GP33, GP34, GP35,
GP36, GP37, GP43, GP44,
CMOS,
IOH = -2mA
GP50, GP51, GP52, GP53
VOH(2)
SIFDI, SIFDO, SIFCE,
BUSYB, GP03, GP10, GP11,
GP45, JTDO, JTRTCK
Low-level output voltage
VOL(1)
CMOS,
IOH = -4mA
GP04, GP05, GP06, GP07,
GP12, GP13, GP30, GP31,
GP32, GP33, GP34, GP35,
GP36, GP37, GP43, GP44,
CMOS,
IOL = 2mA
0.40
V
0.40
V
GP50, GP51, GP52, GP53
VOL(2)
SIFDI, SIFDO, SIFCE,
BUSYB, GP03, GP10, GP11,
GP45, JTDO, JTRTCK
Output off-leakage current
Built-in pull down resistor
CMOS,
IOL = 4mA
IOFF(1)
PDOUT0, PDOUT1, AFILT
Hi-Z Out
-10.00
10.00
A
IOFF(2)
SIFDO
Hi-Z Out
-10.00
10.00
A
RPD
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP30, GP31, GP32,
50
100
200
k
42.50
50.00
57.50
A
-57.50
-50.00
-42.50
A
GP33, GP34, GP35, GP36,
GP37, GP43, GP44, GP45,
GP50, GP51, GP52, GP53
Charge pump output current
IPDOH
PDOUT1, PDOUT0
PCKIST = 100k
IPDOL
PDOUT1, PDOUT0
Current value
setting: 1x
IAFILH
AFILT
15.0
A
IAFILL
AFILT
15.0
A
<Note>
 Put a internal pull down resistor or external pull down resistor or external pull up resistor to the SIFDO pin if its
output condition is set to 3-State mode.
No.A2080-5/24
LC786960E
Package Dimensions
unit : mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.3
0.15
0.1
3.0max
(2.7)
(0.58)
SANYO : QIP100E(14X20)
No.A2080-6/24
LC786960E
81 MODE2
82 JTRSTB
83 JTCK
84 JTDI
85 JTMS
86 JTDO
87 JTRTCK
88 DVDD
89 DVSS
90 DVDD15
91 XVSS2
92 X16OUT
93 X16IN
94 XVDD2
95 LRVDD
96 LCHO
97 LRREF
98 RCHO
99 LRVSS
100 SLCO
Pin Assignment
1
80 VVDD3
RFOUT
2
79 AFILT
LPF
3
78 VVSS2
PHLPF
4
77 VVDD2
AIN
5
76 UVDD
CIN
6
75 UDP
BIN
7
74 UDM
DIN
8
73 XVSS1
SLCISET
9
LC786960
EFMIN
RFMON 10
VREF 11
JITTC 12
EIN 13
FIN 14
TE 15
TEIN 16
LDD 17
LDS 18
AVSS 19
AVDD 20
FDO 21
72 XOU T
71 XIN
70 XVDD1
69 GP07
68 GP06
67 GP05
66 GP04
65 GP03
64 BUSYB
63 SIFCE
62 SIFDO
61 SIFDI
60 SIFCK
TDO 22
59 RESB
SLDO 23
58 DVSS
SPDO 24
57 DVDD
GP33 50
GP32 49
GP31 48
GP30 47
GP53 46
GP52 45
GP51 44
GP50 43
DVDD15 42
DVSS 41
51 GP34
DVDD 40
52 GP35
VVSS1 30
GP45 39
PCKIST 29
GP44 38
53 GP36
GP43 37
PCNCNT 28
DVSS 36
54 GP37
DVDD 35
PDOUT0 27
GP13 34
55 MODE0
GP12 33
PDOUT1 26
GP 11 32
56 MODE1
GP10 31
VVDD1 25
Top view
No.A2080-7/24
LC786960E
Pin Description
Pin
Pin name
No.
I/O
State when
Function
"Reset"
1
EFMIN
AI
Input
2
RFOUT
AO
Undefined
RF signal input
RF signal output
3
LPF
AO
Undefined
RF signal DC level detection low-pass filter capacitor connection
4
PHLPF
AO
Undefined
5
AIN
AI
Input
6
CIN
AI
Input
C signal input
7
BIN
AI
Input
B signal input
8
DIN
AI
Input
D signal input
SLCO output current setting resistor connection
Defect detection low-pass filter capacitor connection
A signal input
9
SLCISET
AI
Input
10
RFMON
AO
Undefined
11
VREF
AO
AVDD/2
12
JITTC
AO
Undefined
13
EIN
AI
Input
E signal input
14
FIN
AI
Input
F signal input
15
TE
AO
Undefined
IC internal analog signal monitor
VREF voltage output
Jitter detection capacitor connection
TE signal output
16
TEIN
AI
Input
17
LDD
AO
Undefined
Laser power control signal output
TE signal input used for TES signal generation
18
LDS
AI
Input
Laser power detection signal input
19
AVSS
-
-
20
AVDD
-
-
21
FDO
AO
AVDD/2
22
TDO
AO
AVDD/2
Tracking control signal output
23
SLDO
AO
AVDD/2
Sled control signal output
24
SPDO
AO
AVDD/2
Spindle control signal output
Analog system ground. This pin must be connected to the 0V level.
Analog system power supply
Focus control signal output
25
VVDD1
-
-
26
PDOUT1
AO
Undefined
EFMPLL power supply
EFMPLL charge pump output 1
27
PDOUT0
AO
Undefined
EFMPLL charge pump output 0
28
PCNCNT
AI
Input
EFMPLL charge pump control voltage input
29
PCKIST
AI
Input
EFMPLL charge pump current setting resistor connection pin
30
VVSS1
-
-
EFMPLL ground. This pin must be connected to the 0V level.
31
GP10
I/O
Input (L)
32
GP11
I/O
Input (L)
33
GP12
I/O
Input (L)
34
GP13
I/O
Input (L)
35
DVDD
-
-
Digital system power supply
36
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
37
GP43
I/O
Input (L)
General purpose I/O port with pull down resistor
38
GP44
I/O
Input (L)
General purpose I/O port with pull down resistor
39
GP45
I/O
Input (L)
General purpose I/O port with pull down resistor
40
DVDD
-
-
Digital system power supply
41
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
42
DVDD15
AO
High
43
GP50
I/O
Input (L)
General purpose I/O port with pull down resistor
44
GP51
I/O
Input (L)
General purpose I/O port with pull down resistor
45
GP52
I/O
Input (L)
General purpose I/O port with pull down resistor
46
GP53
I/O
Input (L)
General purpose I/O port with pull down resistor
General purpose I/O port with pull down resistor
UART1 data transmit
General purpose I/O port with pull down resistor
UART1 data receive
General purpose I/O port with pull down resistor
Clock control input 1
General purpose I/O port with pull down resistor
Clock control input 2
Capacitor connection pin for internal regulator
Continued to the next page.
No.A2080-8/24
LC786960E
Continued from the previous page.
Pin
Pin name
No.
I/O
State when
Function
"Reset"
47
GP30
I/O
Input (L)
General purpose I/O port with pull down resistor
48
GP31
I/O
Input (L)
General purpose I/O port with pull down resistor
49
GP32
I/O
Input (L)
50
GP33
I/O
Input (L)
51
GP34
I/O
Input (L)
52
GP35
I/O
Input (L)
53
GP36
I/O
Input (L)
54
GP37
I/O
Input (L)
55
MODE0
I
Input
56
MODE1
I
Input
57
DVDD
-
-
58
DVSS
-
-
59
RESB
I
-
60
SIFCK
I
Input
61
62
63
64
SIFDI
SIFDO
SIFCE
BUSYB
I/O
I/O
I/O
I/O
Input
Input
Input
Input (L)
General purpose I/O port with pull down resistor
Data 1 input/output for SD memory card
General purpose I/O port with pull down resistor
Data 0 input/output for SD memory card
General purpose I/O port with pull down resistor
Clock output for SD memory card
General purpose I/O port with pull down resistor
Command input/output for SD memory card
General purpose I/O port with pull down resistor
Data 3 input/output for SD memory card
General purpose I/O port with pull down resistor
Data 2 input/output for SD memory card
LSI mode set pin 0 This pin must be connected to the 0V level.
LSI mode set pin 1 This pin must be connected to the 0V level.
Digital system power supply
Digital system ground. This pin must be connected to the 0V level.
IC reset input ("L"-active)
This pin must be set low once after power is first applied.
Host-I/F
Data transmit clock input for serial communication 1
Host-I/F
Data input for serial communication 1
Host-I/F
Data output for serial communication 1 (CMOS or 3-State output)
Host -I/F
Enable signal input for serial communication 1 ("H"-active)
Host -I/F
System busy signal output ("L"-active)
General purpose I/O port with pull down resistor
65
GP03
I/O
Input (L)
66
GP04
I/O
Input (L)
67
GP05
I/O
Input (L)
68
GP06
I/O
Input (L)
General purpose I/O port with pull down resistor
69
GP07
I/O
Input (L)
General purpose I/O port with pull down resistor
70
XVDD1
-
-
71
XIN
I
Oscillation
12MHz oscillator connection
72
XOUT
O
Oscillation
12MHz oscillator connection
73
XVSS1
-
-
Oscillator ground. This pin must be connected to the 0V level.
74
UDM
I/O
-
USB data input/output D- signal connection
75
UDP
I/O
-
USB data input/output D+ signal connection
76
UVDD
-
-
USB power supply
77
VVDD2
-
-
System PLL power supply
78
VVSS2
-
-
System PLL ground. This pin must be connected to the 0V level.
79
AFILT
AO
Undefined
80
VVDD3
-
-
81
MODE2
I
Input
USB device detection flag output
General purpose I/O port with pull down resistor
IIC (master) clock output
General purpose I/O port with pull down resistor
IIC (master) data input/output
Oscillator power supply
Audio PLL charge pump output
Audio PLL power supply
LSI mode set pin 2 This pin must be connected to the 0V level.
Continued to the next page.
No.A2080-9/24
LC786960E
Continued from the previous page.
Pin
No.
Pin name
I/O
State when
Function
"Reset"
JTAG reset input
82
JTRSTB
I
Input
83
JTCK
I
Input
84
JTDI
I
Input
85
JTMS
I
Input
86
JTDO
O
Low
87
JTRTCK
O
Low
88
DVDD
-
-
Digital system power supply
89
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
90
DVDD15
AO
High
91
XVSS2
-
-
92
X16OUT
O
Oscillation
(Connect to pll-down resister or 0V level in normal mode.)
JTAG clock input
(Connect to pll-down resister or 0V level in normal mode.)
JTAG data input
(Connect to pll-down resister or 0V level in normal mode.)
JTAG mode input
(Connect to pll-up resister or DVDD level in normal mode.)
JTAG data output (Leave open in normal mode.)
JTAG return clock output (Leave open in normal mode.)
Capacitor connection pin for internal regulator
Oscillator ground. This pin must be connected to the 0V level.
16.9344MHz oscillator connection
93
X16IN
I
Oscillation
94
XVDD2
-
-
Oscillator power supply
16.9344MHz oscillator connection
95
LRVDD
-
-
Audio LPF power supply
96
LCHO
AO
LRVDD/2
Audio Lch data output
97
LRREF
AO
LRVDD/2
Reference voltage for audio LPF
98
RCHO
AO
LRVDD/2
Audio Rch data output
99
LRVSS
-
-
100
SLCO
AO
Undefined
Audio LPF ground. This pin must be connected to the 0V level.
Slice Level Control output
<Note>
(1) For unused pins:
 The unused input pins must be connected to the GND (0V) level if there is no individual note in the above table.
 The unused output pins must be left open (No connection) if there is no individual note in the above table.
 The unused input/output pins must be connected to the GND (0V) or power supply pin for I/O block with internal
pull down resistor OFF or be left open with internal pull down resistor ON when input pin mode or must be left
open (No connection) when output pin mode if there is no individual note in the above table.
When you connect an I/O pin which is an input pin without internal pull-down resistor at reset mode to the GND
or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe.
(2) For power supply pins:
 Same voltage level must be supplied to DVDD, AVDD, XVDD1, XVDD2, VVDD1, VVDD2, VVDD3, UVDD
and LRVDD power supply pins.
(Refer to“Allowable operating ranges”.)
(3) For “Reset” condition:
 This LSI is not reset only by making the RESB pin “Low”.
Refer to “Power on and Reset control” for detail of “Reset” condition.
No.A2080-10/24
LC786960E
Block Diagram
CD
RF Signal
Processor
AD/DA
DATA Trans
Controller
CD
EFM/ECC
Decoder
CD PLL
CDTEXT
Decoder
ARM7 Core
Cache
Flash
memory
USB
Host
Controller
Buffer
SRAM
CDROM
Decoder
CD
Servo
Controller
BUFRAM
I/F
Boot
ROM
MP3/WMA/AAC
Decoder
Audio
Data-I/F
Audio Control
DeEMPHASIS/
MUTE/ATT
External-IN/OUT
Work
RAM
8Fs Digital Filter
1bit DAC
WatchDog
Timer
USB-I/F
Analog LPF
Interrupt
SD
Memory Card
Controller
SRC
&
HFC-Filter
UART
Host-I/F
(SIO/IIC)
APLL
X’tal-2
(16.9344MHz)
SYSPLL
X’tal-1
(12MHz)
IIC
SIO
GPIO
Regulator
1.5V
3.3V
No.A2080-11/24
LC786960E
Power on and Reset control
 Attention when power on
The RESB pin must be set to “Low” level to initialize the operating state of internal flash memory.
If the power is on during the RESB pin is “High” level, this LSI may operate incorrectly because the internal flash
memory is not initialized. In this case, this LSI is not initialized even if a low level supplied to RESB pin.
Therefore, the RESB pin must be set to “Low” level when power is first supplied.
You may input the voltage of 3.6V or less to each input pin when the power supply is off. However, it is necessary
to supply a regulated voltage to the power supply pin beforehand when more than 3.6V voltage is input to the 5V
tolerant input pins.
Power ON/Power Down/Reset timing
3.3V Power
VDD1
vBOT
0V
tPWD
3.3V Power
VDD1
tRESW1
tRESW2
RESB
During normal operation
(Oscillation clock is valid)
Power on stage
Parameter
Symbol
min
typ
max
unit
Power down time
tPWD
10
Power down voltage
vBOT
0
ms
Reset time (Power on)
tRESW1
20
ms
Reset time (Normal) (*1)
tRESW2
1
ms
0.2
V
*1: The specification of tRESW2 above is the time defined while steady the X16 clock and having oscillated.
When the X16 clock has been stopped by the command etc. , the specification of tRESW2 could be larger than the
value shown above, because it takes time that the X16 oscillator becomes stable.
No.A2080-12/24
LC786960E
Host interface
The data transmission between this LSI and Host controller is performed with SPI type synchronous SIO protocol.
The transmission procedure is as follows.
 Refer to the internal software specification of this LSI about M5 to M0 code in Mode code transmission.
When the input data of M5 to M0 coincide to the data in the internal register, the SIFDO pin becomes to “Low”
level (Ack) then the transmission is enabled.
When not coincide, the SIFDO pin keeps “High” level (Nack) then the transmission is not enabled.
 The seventh data in Mode code transmission shows whether the following procedure is the Command transmission
or the Data reception. When the seventh data is “Low”, the following procedure is Command transmission. When
the seventh data is “High”, the following procedure is Data reception.
 Attention because the specifications of transmission timings are different depending on the internal CPU’s operating
speed modes (Low speed or Normal speed). Refer to the table in next page.
Communication Interface format between Host controller
SIFCE
SIFCK
SIFDI
MODE
(Send)
SIFDO
Command
1
Command
2
MODE
(Receive)
Command
N
Ack
Data
1
Ack
Data
2
Data
N
BUSYB
Transmission/Reception format between Host controller
(1) Host: Command Transmission
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
WR
8
1
2
3
6
7
8
D2
D1
D0
SIFCK
SIFDI
D7
Mode Code
byte
D6 D5
1st-data
byte
Last-data
byte
Nack
Ack
SIFDO
BUSYB
(2) Host: Data Reception
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
RD
8
1
2
3
6
7
8
D2
D1
D0
SIFCK
SIFDI
Mode Code
byte
SIFDO
Nack
Ack D7
D6 D5
1st-data
byte
Last-data
byte
BUSYB
No.A2080-13/24
LC786960E
Communication Timing specification between Host controller
SIFCE
(Input)
1/fCLK
tCSU
tCKH
tCKL
tCHD
SIFCK
(Input)
tCE
tCWSU tCWHD
SIFDI
(Input)
tCRAS
tCDOF
SIFDO
(Output)
BUSYB
(Output)
tCDON
tCDOH
tCBST
Parameter
Symbol
Pin names
SIFCK clock frequency
fCLK
SIFCK
SIFCK clock "H" level width
tCKH
SIFCK
SIFCK clock "L" level width
tCKL
SIFCK
Transfer start enable time
tCE
BUSYB, SIFCE
Setup time for transfer start
tCSU
SIFCE, SIFCK
Hold time for transfer end
tCHD
SIFCE, SIFCK
Setup time for SIFDI
tCWSU
SIFDI, SIFCK
Hold time for SIFDI
tCWHD
SIFDI, SIFCK
Output delay time for SIFDO “H”
tCDOH
SIFDO, SIFCK
Output delay time for SIFDO
tCRAS
SIFDO, SIFCK
Turn on time for SIFDO *1
tCDON
SIFDO, SIFCE
Turn off time for SIFDO *1
tCDOF
SIFDO, SIFCE
BUSYB "L" level output delay time
tCBST
BUSYB
min
typ
max
unit
3.3
0.725
150
MHz
ns
690
150
ns
690
0
ns
0
100
ns
200
100
ns
200
75
ns
75
75
ns
200
100
350
100
350
100
100
150
150
150
350
ns
ns
ns
ns
ns
Internal CPU operating speed mode
Upper step : Normal speed
Lower step : Low speed
*1: The tCDON and tCDOF specifications are for when the SIFDO pin is set to the 3-State mode.
No.A2080-14/24
LC786960E
USB Specification at Ta = -40C to +85C, VDD1 = 3.0V to 3.6V,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Pin names
High-level input voltage
VIH (USB)
Low-level input voltage
VIL (USB)
Conditions
min
typ
max
unit
2.0
0.8
ILI
Output driver: OFF
Differential input sensitivity
VDI
|(UDP) - (UDM)|
0.2
0.8
2.5
V
2.8
3.6
V
0
0.3
V
1.3
2.0
V
4.0
20.0
4.0
20.0
VCM
Includes VDI range
High-level output voltage
VOH (USB)
Connect 15k ±5% pull-down
UDM, UDP
resistor to GND (0V).
Low-level output voltage
VOL (USB)
Connect 1.5k ±5% pull-up
resistor to VDD1.
Crossover voltage
VCR
USB data rising time
TUR
USB data falling time
TUF
CL = 50pF
10.0
A
Input leakage current
Common mode voltage range
-10.0
V
V
ns
Example circuit for USB application
LC786960
VDD1
UVDD
UDP
15 Ω
5pF
UDM
15k Ω
* The value of resistors and capacitors in this
circuit might be needed to be adjusted for each
application.
15 Ω
5pF
15k Ω
No.A2080-15/24
LC786960E
SD Memory Card Interface
SD Memory Card Input/Output Timing specification
tSDCKL tSDCKH
1/fSDCKF
SDCCLK
(Output)
SDCMDIO
(Inout)
tSDCMS
tSDCMH
tSDCMO
tSDCDH
tSDCDO
SDCDAT[3:0]
(Inout)
tSDCDS
* Relationship between signal name and pin name
SDCCLK
: GP34
SDCMDIO
: GP35
SDCDAT [2] : GP37
SDCDAT [1] : GP32
Parameter
Symbol
SDCDAT [3] : GP36
SDCDAT [0] : GP33
Pin names
min
typ
max
unit
SDCCLK clock frequency
fSDCKF
SDCCLK
6.0
SDCCLK clock "H" level width
tSDCKH
SDCCLK
83.3
MHz
ns
SDCCLK clock "L" level width
tSDCKL
SDCCLK
83.3
ns
Setup time for command input
tSDCMS
SDCMDIO, SDCCLK
30.0
ns
Hold time for command input
tSDCMH
SDCMDIO, SDCCLK
30.0
ns
Command output valid time
tSDCMO
SDCMDIO, SDCCLK
Setup time for data input
tSDCDS
SDCDAT [3:0], SDCCLK
30.0
ns
Hold time for data input
tSDCDH
SDCDAT [3:0], SDCCLK
30.0
ns
Data output valid time
tSDCDO
SDCDAT [3:0], SDCCLK
30.0
30.0
ns
ns
Note: Internal CPU (ARM7) must be set to normal mode. Never use the SD Memory Card interface at the internal
CPU’s Low speed mode.
No.A2080-16/24
LC786960E
Internal Voltage Regulator at Ta = -40C to +85C,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Condition
Output voltage
DVDD15
VDD1 = 3.0V to 3.6V
Load current
Iope
VDD1 = 3.3V
min
typ
1.35
max
1.50
unit
1.65
V
200
mA
Note : The spec. of “load current” above is sum of the load current of two internal voltage regulator.
Example circuit for Regulator
* Same circuit need to be mounted both for two regulator pins.
(No.42 and No.90)
* The capacitor C1 must be greater than 50F and low Secure
50F or more for low ESR and the capacity value in the range
of the operating temperature so that there is a possibility of the
oscillation when the capacity value changes by the temperature
change etc.
(The recommended value is 100F.)
LC786960
DVDD
DVSS
DVDD15
100μF
C1
A/D, D/A converter Characteristics for servo
at Ta = -40C to +85C, VDD1 = 3.3V, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Resolution
Res
Maximum input/output range
Minimum input/output range
Condition
min
typ
max
unit
8
bit
Vaio1
4/5VDD1
V
Vaio2
1/5VDD1
V
1-Bit D/A converter Characteristics
at Ta = 25C, VDD1 = 3.3V, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Output level
LEVEL
Pin names
Conditions
LCHO,
min
typ
With a 1kHz, 0dB data signal
0.63
RCHO
Total harmonics distortion
THD+N
max
LCHO,
With a 1kHz, 0dB data signal,
RCHO
Using the 20kHz Low-pass filter (built-in
0.008
unit
Vrms
0.012
%
AD725D)
Dynamic range
DR
LCHO,
With a 1kHz, -60dB data signal,
RCHO
Using the 20kHz Low-pass filter and A-filter
92
96
dB
95
98
dB
82
85
dB
(built-in AD725D)
Signal to noise ratio
S/N
LCHO,
With a 1kHz, 0dB data signal,
RCHO
Using the 20kHz Low-pass filter and A-filter
(built-in AD725D)
Cross talk
CT
LCHO,
With a 1kHz, 0dB data signal,
RCHO
Using the 20kHz Low-pass filter
(built-in AD725D)
Note : Measured in normal speed playback mode in Ours 1-bit D/A converter block reference circuit.
1-Bit D/A converter output reference circuit
LC786960
LRVDD
Analog output
Left Channel
680Ω
LCHO
LRREF
LPF
10μF
100μF
1000pF
100kΩ
Shibasoku Co.,Ltd.
AD725D
RCHO
LRVSS
RCHO :
Same circuit as for LCHO
No.A2080-17/24
LC786960E
Oscillator
Example circuit for Oscillator
LC786960
XVDD2
X16IN
X16OUT
Rd2
XV SS2
C2
XVDD1 XIN
XOUT
C2
XV SS1
Rd1
C1
C1
(1) XIN/XOUT: 12.0000MHz
 For System Main clock, USB control
 Recommended Oscillator
Nihon Dempa Kogyo Co., Ltd.
Type
Recommended value
NX5032GA
Rd1 = 0, C1 = 4pF
NX8045GB
Rd1 = 0, C1 = 4pF
(2) X16IN/X16OUT: 16.9344MHz
 For CD control, Audio control
 Recommended Oscillator
Murata Manufacturing Co., Ltd.
Type
Recommended value
CSTCE16M9V53-R0
Rd2 = 0, C2 = open
CSTCW16M9X51008-R0
Rd2 = 0, C2 = open
CSTLS16M9X53-B0
Rd2 = 0, C2 = open
Nihon Dempa Kogyo Co., Ltd.
Type
Recommended value
AT51-CD2
Rd2 = 0, C2 = 8pF
Notes
 Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the
individual original circuit board to the oscillator maker.
 The accuracy of 12MHz oscillator (XIN/XOUT) must be in ±500ppm when this oscillator clock is used for USB
Host function.
 Concerning about internal circuit for XIN/XOUT and X16IN/X16OUT, refer to the “Analog Pin Internal Equivalent
Circuits” section.
No.A2080-18/24
LC786960E
Analog Pin Internal Equivalent Circuits
Pin Name (Pin No.)
Equivalent circuit
AVDD
EFMIN (1)
AVSS
AVDD
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
AVSS
RFOUT (2)
LPF (3)
AVDD
PHLPF (4)
AVSS
AVDD
AIN (5)
CIN (6)
BIN (7)
DIN (8)
AVSS
AVDD
SLCISET (9)
AVSS
AVDD
AVDD
RFMON (10)
AVSS
AVSS
Continued to the next page.
No.A2080-19/24
LC786960E
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
AVDD
AVDD
AVSS
AVSS
VREF (11)
AVDD
JITTC (12)
AVSS
AVDD
EIN (13)
FIN (14)
AVSS
AVDD
AVDD
AVSS
AVSS
TE (15)
AVDD
TEIN (16)
AVSS
AVDD
AVDD
AVDD
LDD (17)
AVSS
AVSS
AVDD
LDS (18)
AVSS
Continued to the next page.
No.A2080-20/24
LC786960E
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
AVDD
AVDD
AVSS
AVSS
VVDD1
VVDD1
VVSS1
VVSS1
VVDD1
VVDD1
VVSS1
VVSS1
FDO (21)
TDO (22)
SLDO (23)
SPDO (24)
PDOUT1 (26)
PDOUT0 (27)
VVDD1
VVDD1
PCNCNT (28)
VVSS1
VVDD1
PCKIST (29)
VVSS1
XVDD1
XIN (71)
VVSS1
XVDD1
XIN
XOUT
XOUT (72)
XVSS1
XVSS1
Continued to the next page.
No.A2080-21/24
LC786960E
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
VVDD3
VVDD3
AFILT (79)
VVSS3
XVDD2
X16OUT (92)
VVSS3
XVDD2
XIN
XOUT
X16IN (93)
XVSS2
XVSS2
LRVDD
LRVDD
LRVSS
LRVSS
LRVDD
LRVDD
LRVSS
LRVSS
AVDD
AVDD
AVSS
AVSS
LHCO (96)
RCHO (98)
LRREF (97)
SLCO (100)
No.A2080-22/24
LC786960E
Sample Application Circuit
SLCO
VDD1
)
)
)
)
(Reference
voltage)
(
E
(
F
)
)
To PICKUP
Vref
LDD
LDS
AVSS
AVDD
LD
MD
VVDD3
AFILT
VVSS2
VVDD2
UVDD
UDP
UDM
From/To
USB-Device
D+
D-
LC786960
(
(
(
(
A
B
C
D
EFMIN
RFOUT
LPF
PHLPF
AIN
CIN
BIN
DIN
SLCISET
RFMON
VREF
JITTC
EIN
FIN
TE
TEIN
To Driver
FDO
TDO
SLDO
SPDO
VVDD1
PDOUT1
PDOUT0
PCNCNT
PCKIST
VVSS1
GND
* This sample circuit is only for CD servo block, each PLL block and USB block.
The value of each component needs to be adjusted under the target conditions.
The circuit for CD servo shown above could be changed depending on the CD mechanism used.
Concerning to the application circuit for Regulator, Audio DAC and Oscillator, refer to the page 17 and 18
respectively.
No.A2080-23/24
LC786960E
ORDERING INFORMATION
Device
LC786960E-H
Package
QIP100E(14X20)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
250 / Tray Foam
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
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warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
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PS No.A2080-24/24
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