Compressed Audio signal Processor IC with USB host controller

Ordering
Orderingnumber
number: :ENA2082A
ENA2082
LC786800E
CMOS LSI
Compressed Audio signal Processor IC
with USB host controller
http://onsemi.com
Overview
The LC786800E integrates ARM7TDMI-S™, USB host processing, SD memory card host processing, Compressed
audio encode/decode processing, Audio signal processing, Electronic volume and a flash memory which stores the
program for ARM7TDMI-S™ and the various data. The sophisticated programs in the flash memory for the USB
host processing or for the SD memory card processing or Electronic Volume control processing, etc. make the load of
external main micro controller to be light and are very useful to develop a much features/high performance audio
player system with less development burden.
Features
 USB host function (Full speed as 12Mbps), SD memory card host function
 MP3*, WMA*, AAC* decoder processing and normal speed MP3* encoder processing of external input with
Sampling rate convertor and High frequency compensation filter
 Various Audio processing functions such as original Surround(AViSS®), seven band Equalizer, etc.
Continued to the next page.
ORDERING INFORMATION
See detailed ordering and shipping information on page 26 of this data sheet.
QIP100E(14X20)
is a registered trademark of ARM Limited.
* MP3(MPEG Layer-3 Audio Coding)
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license nor imply any right to distribute content created with this product in revenue-generating
broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet, intranets and/or
networks), other content distribution systems (pay-audio or audio-on-demand applications and the like) or on physical media (compact discs,
digital versatile discs, semiconductor chips, hard drives, memory cards and the like). An independent license for such use is required. For
details, please visit http://mp3licensing.com/.
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor imply
any right to use this product in any finished end user or ready-to-use final product. An independent license for such useis required.
For details, please visit http://mp3licensing.com/.
* Windows Media Audio
Windows MediaTM is a trademark and a registered trademark in the United States and other countries of United States Microsoft Corporation.
* AAC
Advanced Audio Coding
* This product is licensed from Silicon Storage Technology, Inc. (USA).
* AViSS is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
September, 2013 Ver. 1.0.0
91113HK/80112HKPC 20120531-S00005 No.A2082-1/26
LC786800E
Continued from the previous page.
 Three stereo channels of analog input and four channels of Electronic Volume output (LF, LR, RF, RR)
 ARM7TDMI-S™ as internal CPU core, flash memory for program and various data storage
 Operating voltage: 3.3V typical
 Operating temperature: -40C to +85C
 Packages: QIP100 (14  20)
Detail of Functions
Compressed audio functions
 MP3 decode (ISO/IEC 11172-3, ISO/IEC 13818-3)
Sampling rate support:
MPEG1-Layer1/2/3 (32kHz, 44.1kHz, 48kHz)
MPEG2-Layer1/2/3 (16kHz, 22.05kHz, 24kHz)
MPEG2.5-Layer3 (8kHz, 11.025kHz, 12kHz)
Bit rate support:
All Bit Rate (Variable Bit Rate support)
MPEG header read support
 MP3 encode (ISO/IEC 11172-3)
MPEG1-Layer3
Sampling rate:
44.1kHz
Bit rate:
32kbps to 320kbps (Not support variable bit rate)
 WMA decode (Version 9 standard)
Sampling rate support:
8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz, 48kHz
Bit rate support:
5kbps to 384kbps (Variable Bit Rate support)
 AAC decode (ISO/IEC 14496-3, ISO/IEC 13818-7)
Profile:
MPEG4-AAC-LowComplexity
Sampling rate support:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,
48kHz
Bit rate support:
Monaural 8kbps to 160kbps (Variable bit rate support)
Stereo
16kbps to 320kbps (Variable bit rate support)
Audio processing functions
<Audio data processing block>
 Our original surround (AViSS)
 7band graphic equalizer
 Sampling Rate Converter (Fs = 44.1kHz) and High frequency compensation filter for compressed audio
playback
 Mute function (-12dB, -)and Digital attenuator
 De-emphasis filter
<Audio input processing block>
 Analog Audio data input (Three channels by stereo)
Single Ended input:
2 channels
Differential input:
1 channel (single end operation is also available)
Input Gain:
-12.5dB to +18.5dB (1dB step)
24bit accuracy AD converter (Three input selector)
 Digital Audio data input (Three channels by stereo)
Four signals connection (384Fs, LRCK, BCK and DATA) is required.
Corresponding in one of two ways.
(1) 384Fs input and three lines input synchronized.
(2) 384Fs output and three lines input synchronized.
Data Format: IIS, MSB first right justified, etc.
No.A2082-2/26
LC786800E
<Audio output processing block>
 Analog Audio data output (One channel by stereo)
Eight-fold over-sampling digital filter (24bit)
Secondary LPF for audio output
 Electronic Volume/Fader
Output channel : Left Front (LF)/Left Rear (LR), Right Front (RF)/Right Rear (RR)
Output Range : 0dB to -90dB, -
0dB to -32dB : Analog control, 0.25dB step
-32dB to -70dB : Analog control, 1.0dB step
-70dB to -90dB : Digital attenuator control
Decrease the noise at the volume change timing by the digital and analog composite control.
Individual volume control for LF, LR, RF and RR output is available.
 Digital Audio data output (One channel by stereo)
Four lines interface, Format: IIS, MSB first right justified, etc.
External interface functions
<USB host control block>
 Open Host Controller Interface 1.0a
 Universal Serial Bus Specification 1.1
Supports up to Full speed (12MHz)for USB2.0
Only detection at the device insertion is available for Low speed specification.
 Supports four kinds of transfer type (Control/Bulk/Interrupt/Isochronous)
 Two USB ports
<SD memory card host control block>
 Multimedia Card Specification v2.11
 Secure Digital Memory Card Physical Layer Specification v0.96
* Individual contract is necessary to use SD memory card controller. For detail, please contact to us.
Internal Microcontroller functions
<Sequencer control>
 USB, SD memory card playback control
USB/SD files analysis, etc.
 Audio playback control
Various digital audio filter control, Electronic volume control, etc.
<Communication control between main controller>
 Communication format: SIO
<Peripheral interface block>
 GPIO port
37 ports maximum (Shared with other functions. Several pins are 5V tolerant.)
 External interrupt pins 4 pins maximum (Shared with other functions.)
 Serial interface
SIO
clock synchronized full duplex (3 lines) 3 channels
UART
full duplex
2 channels
IIC
master function
1 channel
<Program memory block>
 Flash memory
Program version up from the external media (USB/CDROM*) or main controller is available.
* The update of program from CDROM will only be available if CD system is used with this IC.
<Others>
 Watch Dog Timer
Notify to outside from the pin or reset internally.
 Power management
2 kinds of sleep mode
(1) Only CPU core operates at slow clock and clocks for other blocks are stopping.
(2) All clocks are stopping.
No.A2082-3/26
LC786800E
Useful functions for CD-DSP IC connection usage
<CD TEXT processing block>
 Buffers CD-TEXT data
 Starts buffering from desired ID3/ID4 of CD-TEXT data.
* Necessary to connect subcode synchronization signals (SBSY and SFSY), shift clock (SBCK) and data
(PW).
<CD-ROM processing block>
 Up to quadruple speed operation available
 CD-ROM decoding (Mode1, Mode2<form1, form2>)
 Outputs CD-ROM decoded data
* Necessary to connect three signals (LRCK, BCK and DATA).
It is possible if desired to connect C2 error flag.
Others
<Internal power supply>
 1.5V regulator for internal blocks
No.A2082-4/26
LC786800E
Specifications
Absolute Maximum Ratings at Ta = 25C, DVSS = AVSS1 = AVSS2 = XVSS = 0V
Parameter
Maximum supply voltage
Symbol
Pin names
VDD max
DVDD, AVDD1, AVDD2,
Input voltage 1
VIN1
XVDD, VVDD2, VVDD3
Input pins other than VIN2
Input voltage 2
VIN2
RESB, SIFCK, SIFDI, SIFDO,
Conditions
Ratings
Unit
-0.3 to +3.95
V
-0.3 to DVDD+0.3
V
-0.3 to +5.6
V
-0.3 to DVDD+0.3
V
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, GP13, GP14,
JTRSTB, JTCK, JTDI, JTMS
Output voltage
VOUT
All digital output pins and
input/output pins
Allowable power dissipation
Ta  85C
Pd max
519
Mounted reference PCB (*)
mW
Operating temperature
Topr
-40 to +85
C
Storage temperature
Tstg
-40 to +125
C
(*)Reference PCB: 114.3mm×76.1mm×1.6mm, glass epoxy resin
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85C, DVSS = AVSS1 = AVSS2 = XVSS = 0V
Parameter
Symbol
Pin names
Supply voltage
VDD1
DVDD, AVDD1, AVDD2,
XVDD, VVDD2, VVDD3
High-level input voltage
VIH(1)
RESB, SIFCK, SIFDI, SIFDO,
Conditions
min
typ
max
Unit
3.00
3.60
V
Schmitt
2.00
5.50
V
Schmitt
2.00
VDD1
V
Schmitt
0
0.80
V
Schmitt
0
0.80
V
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, GP13, GP14,
JTMS, JTRSTB, JTCK, JTDI
VIH(2)
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53
Low-level input voltage
VIL(1)
RESB, SIFCK, SIFDI, SIFDO,
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, GP13, GP14,
JTMS, JTRSTB, JTCK, JTDI
VIL(2)
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53,
TEST0, TEST1
Oscillator frequency
FX1
XIN
XOUT
12.0
Oscillator circuit
or
MHz
16.9344
No.A2082-5/26
LC786800E
Electrical Characteristics at Ta = -40 to +85C, VDD1 = 3.0V to 3.6V, DVSS = AVSS1 = AVSS2 = XVSS = 0V
Parameter
Symbol
Pin names
Conditions
Current drain
IDD1
DVDD, AVDD1, AVDD2,
XVDD, VVDD2, VVDD3
High-level input current
IIH(1)
RESB, SIFCK, SIFDI, SIFDO,
Schmitt,
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
VIN = 5.50V
Built-in
GP11, GP12, GP13, GP14,
Pull-down
IIH(2)
Low-level input current
IIL(1)
min
typ
max
85
JTMS, JTRSTB, JTCK, JTDI
resistor OFF
GP30, GP31, GP32, GP33,
Schmitt,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
VIN = VDD1
Built-in
GP44, GP45, GP46, GP47,
Pull-down
GP50, GP51, GP52, GP53
resistor OFF
Unit
135
mA
10.00
A
10.00
A
RESB, SIFCK, SIFDI, SIFDO,
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, GP13, GP14,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
Schmitt,
VIN = 0V
-10.00
A
VDD1-0.6
V
VDD1-0.6
V
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53,
JTMS, JTRSTB, JTCK, JTDI,
TEST0, TEST1
High-level output voltage
VOH(1)
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP30,
GP31, GP32, GP33, GP34,
GP35, GP36, GP37, GP40,
GP41, GP42, GP43, GP44,
CMOS,
IOH = -2mA
GP45, GP46, GP47, GP50,
GP51, GP52, GP53
VOH(2)
SIFDI, SIFDO, SIFCE, BUSYB,
GP03, GP10, GP11,
JTDO, JTRTCK
Low-level output voltage
VOL(1)
CMOS,
IOH = -4mA
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP30,
GP31, GP32, GP33, GP34,
GP35, GP36, GP37, GP40,
GP41, GP42, GP43, GP44,
CMOS,
IOL = 2mA
0.40
V
0.40
V
200
k
A
GP45, GP46, GP47, GP50,
GP51, GP52, GP53
VOL(2)
SIFDI, SIFDO, SIFCE, BUSYB,
GP03, GP10, GP11,
JTDO, JTRTCK
Built-in Pull down resistor
RPD
CMOS,
IOL = 4mA
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP30, GP31,
50
GP32, GP33, GP34, GP35,
100
GP36, GP37, GP40, GP41,
GP42, GP43, GP44, GP45,
GP46, GP47, GP50, GP51,
GP52, GP53
Output off-leakage current
Charge pump output current
IOFF(1)
AFILT
Hi-Z Out
-10.00
10.00
IOFF(2)
SIFDO
Hi-Z Out
-10.00
10.00
IAFILH
AFILT
15.0
A
IAFILL
AFILT
15.0
A
A
<Note>
 Put a internal pull down resistor or external pull down resistor or external pull up resistor to the SIFDO pin if its
output condition is set to 3-State mode.
No.A2082-6/26
LC786800E
Package Dimensions
unit : mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.3
0.15
0.1
3.0max
(2.7)
(0.58)
SANYO : QIP100E(14X20)
No.A2082-7/26
LC786800E
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
LRREF
AVSS1
AVDD1
TEST1
JTRTCK
JTDO
JTMS
JTDI
JTCK
JTRSTB
DVDD15
DVSS
DVDD
TEST0
GP14
GP07
GP06
GP05
GP04
DVDD
Pin Assignment
DVSS
VVDD3
VVDD2
AFILT
XVSS
XOUT
XIN
XVDD
UDP2
UDM2
DVSS
UDP1
UDM1
DVDD
DVSS
GP47
GP46
GP45
GP44
GP43
GP42
GP41
GP40
GP03
BUSYB
SIFCE
SIFDO
SIFDI
SIFCK
RESB
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVDD
DVSS
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
DVDD
DVSS
REG1EXTR
DVDD15
GP10
GP11
GP12
GP13
DVDD
DVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LC786800
LFOUT
LROUT
LVRIN
DACOUTL
DACOUTR
RVRIN
RROUT
RFOUT
L1IN
R1IN
L2IN
R2IN
L3INP
L3INN
R3INP
R3INN
ATESTO1
ATESTO2
VREFOUT
VREF_ADC
AVSS2
AVDD2
NC
NC
NC
NC
GP50
GP51
GP52
GP53
Top view
No.A2082-8/26
LC786800E
Pin Description
Pin
Pin name
No.
I/O
State when
Function
"Reset"
1
LFOUT
AO
Undefined
Electronic Volume : Left channel Front output
2
LROUT
AO
Undefined
Electronic Volume : Left channel Rear output
3
LVRIN
AI
Input
4
DACOUTL
AO
Undefined
Audio DAC : Left channel output
Electronic Volume : Left channel volume input
5
DACOUTR
AO
Undefined
Audio DAC : Right channel output
6
RVRIN
AI
Input
Electronic Volume : Right channel volume input
7
RROUT
AO
Undefined
Electronic Volume : Right channel Rear output
8
RFOUT
AO
Undefined
Electronic Volume : Right channel Front output
9
L1IN
AI
Input
10
R1IN
AI
Input
Analog stereo Left channel Single Ended input 1
Analog stereo Right channel Single Ended input 1
11
L2IN
AI
Input
Analog stereo Left channel Single Ended input 2
12
R2IN
AI
Input
Analog stereo Right channel Single Ended input 2
13
L3INP
AI
Input
14
L3INN
AI
Input
Analog stereo Left channel Differential input (Positive) /
Analog stereo Left channel Single Ended input 3
Analog stereo Left channel Differential input (Negative)
Analog stereo Right channel Differential input (Positive) /
15
R3INP
AI
Input
16
R3INN
AI
Input
17
ATESTO1
AO
Undefined
Analog test output 1. This pin must be left open.
18
ATESTO2
AO
Undefined
Analog test output 2. This pin must be left open.
19
VREFOUT
AO
AVDD2/2
Reference voltage output
20
VREF_ADC
AO
AVDD2/2
21
AVSS2
-
-
Analog system ground. This pin must be connected to the 0V level.
22
AVDD2
-
-
Analog system power supply
23
NC
-
-
NC pin. This pin must be left open.
24
NC
-
-
NC pin. This pin must be left open.
25
NC
-
-
NC pin. This pin must be left open.
26
NC
-
-
NC pin. This pin must be left open.
27
GP50
I/O
Input (L)
General purpose I/O port with pull down resistor
28
GP51
I/O
Input (L)
General purpose I/O port with pull down resistor
29
GP52
I/O
Input (L)
General purpose I/O port with pull down resisto
30
GP53
I/O
Input (L)
General purpose I/O port with pull down resistor
31
DVDD
-
-
Digital system power supply
32
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
33
GP30
I/O
Input (L)
General purpose I/O port with pull down resistor
34
GP31
I/O
Input (L)
General purpose I/O port with pull down resistor
35
GP32
I/O
Input (L)
36
GP33
I/O
Input (L)
37
GP34
I/O
Input (L)
38
GP35
I/O
Input (L)
39
GP36
I/O
Input (L)
40
GP37
I/O
Input (L)
41
DVDD
-
-
Digital system power supply
42
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
43
REG1EXTR
AO
Undefined
44
DVDD15
AO
High
Analog stereo Right channel Single Ended input 3
Analog stereo Right channel Differential input (Negative)
Capacitor connection pin for audio ADC reference voltage
General purpose I/O port with pull down resistor
Data 1 input/output for SD memory card
General purpose I/O port with pull down resistor
Data 0 input/output for SD memory card
General purpose I/O port with pull down resistor
Clock output for SD memory card
General purpose I/O port with pull down resistor
Command input/output for SD memory card
General purpose I/O port with pull down resistor
Data 3 input/output for SD memory card
General purpose I/O port with pull down resistor
Data 2 input/output for SD memory card
Reserved pin for internal regulator. This pin must be left open.
Capacitor connection pin for internal regulator
Continued to the next page.
No.A2082-9/26
LC786800E
Continued from the previous page.
Pin
Pin name
No.
I/O
State when
Function
"Reset"
General purpose I/O port with pull down resistor
45
GP10
I/O
Input (L)
46
GP11
I/O
Input (L)
47
GP12
I/O
Input (L)
48
GP13
I/O
Input (L)
49
DVDD
-
-
Digital system power supply
50
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
51
RESB
I
-
52
SIFCK
I
Input
53
54
55
56
SIFDI
SIFDO
SIFCE
BUSYB
I/O
I/O
I/O
I/O
Input
Input
Input
Input (L)
UART1 data transmit
General purpose I/O port with pull down resistor
UART1 data receive
General purpose I/O port with pull down resistor
Clock control input 1
General purpose I/O port with pull down resistor
Clock control input 2
IC reset input ("L"-active)
This pin must be set low once after power is first applied.
Host-I/F
Data transmit clock input for serial communication 1
Host-I/F
Data input for serial communication 1
Host-I/F
Data output for serial communication 1 (CMOS or 3-State output)
Host -I/F
Enable signal input for serial communication 1 ("H"-active)
Host -I/F
System busy signal output ("L"-active)
General purpose I/O port with pull down resistor
57
GP03
I/O
Input (L)
58
GP40
I/O
Input (L)
General purpose I/O port with pull down resistor
59
GP41
I/O
Input (L)
General purpose I/O port with pull down resistor
60
GP42
I/O
Input (L)
General purpose I/O port with pull down resistor
61
GP43
I/O
Input (L)
General purpose I/O port with pull down resistor
62
GP44
I/O
Input (L)
General purpose I/O port with pull down resistor
63
GP45
I/O
Input (L)
General purpose I/O port with pull down resistor
64
GP46
I/O
Input (L)
General purpose I/O port with pull down resistor
65
GP47
I/O
Input (L)
General purpose I/O port with pull down resistor
66
DVSS
-
-
67
DVDD
-
-
68
UDM1
I/O
-
69
UDP1
I/O
-
70
DVSS
-
-
71
UDM2
I/O
-
72
UDP2
I/O
-
73
XVDD
-
-
USB device detection flag output
Digital system ground. This pin must be connected to the 0V level.
Digital system power supply
USB data input/output 1 D- signal connection
General purpose I/O port (GP22)
USB data input/output 1 D+ signal connection
General purpose I/O port (GP23)
Digital system ground. This pin must be connected to the 0V level.
USB data input/output 2 D- signal connection
General purpose I/O port (GP20)
USB data input/output 2 D+ signal connection
General purpose I/O port (GP21)
Oscillator power supply
74
XIN
I
Oscillation
75
XOUT
O
Oscillation
76
XVSS
-
-
77
AFILT
AO
Undefined
78
VVDD2
-
-
PLL2 power supply
79
VVDD3
-
-
PLL1 power supply
80
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
81
DVDD
-
-
82
GP04
I/O
Input (L)
83
GP05
I/O
Input (L)
X'tal oscillator connection
X'tal oscillator connection
Oscillator ground. This pin must be connected to the 0V level.
PLL2 charge pump output (for filter connection)
Digital system power supply
General purpose I/O port with pull down resistor
IIC (master) clock output
General purpose I/O port with pull down resistor
IIC (master) data input/output
Continued to the next page.
No.A2082-10/26
LC786800E
Continued from the previous page.
Pin
No.
Pin name
I/O
State when
Function
"Reset"
84
GP06
I/O
Input (L)
General purpose I/O port with pull down resistor
85
GP07
I/O
Input (L)
General purpose I/O port with pull down resistor
86
GP14
I/O
Input (L)
General purpose I/O port with pull down resistor
87
TEST0
I
Input
88
DVDD
-
-
Digital system power supply
89
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
90
DVDD15
AO
High
91
92
93
JTRSTB
JTCK
JTDI
I
I
I
Input
Input
Input
Test input. This pin must be connected to the 0V level.
Capacitor connection pin for internal regulator
JTAG reset input
(Connect to pull-down resistor or 0V level in normal mode.)
JTAG clock input
(Connect to pull-down resistor or 0V level in normal mode.)
JTAG data input
(Connect to pull-down resistor or 0V level in normal mode.)
JTAG mode input
94
JTMS
I
Input
95
JTDO
O
Low
(Connect to pull-down resistor or DVDD level in normal mode.)
JTAG data output (Leave open in normal mode.)
96
JTRTCK
O
Low
JTAG return clock output (Leave open in normal mode.)
97
TEST1
I
Input
Test input. This pin must be connected to the 0V level.
98
AVDD1
-
-
Analog system power supply
99
AVSS1
-
-
Analog system ground. This pin must be connected to the 0V level.
100
LRREF
AO
AVDD1/2
Capacitor connection pin for reference voltage for Audio DAC and Electronic Volume.
<Note>
(1) For unused pins:
 The unused input pins must be connected to the GND (0V) level if there is no individual note in the above table.
 The unused output pins must be left open (No connection) if there is no individual note in the above table.
 The unused input/output pins must be connected to the GND (0V) or power supply pin for I/O block with internal
pull down resistor OFF or be left open with internal pull down resistor ON when input pin mode or must be left
open (No connection) when output pin mode if there is no individual note in the above table.
When you connect an I/O pin which is an input pin with internal pull-down resistor OFF at reset mode to the GND
or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe.
(2) For power supply pins:
 Same voltage level must be supplied to DVDD, AVDD1, AVDD2, XVDD, VVDD2 and VVDD3 power supply
pins.
(Refer to“Allowable operating ranges”.)
(3) For “Reset” condition:
 This IC is not reset only by making the RESB pin “Low”.
Refer to “Power on and Reset control” for detail of “Reset” condition.
(4) For “Analog Source” unused pins (9 pin to 16 pin):
 The “Analog Source” unused pins (9 pin to 16 pin) must be connected to the GND (0V) level through the input
coupling capacitor.
No.A2082-11/26
LC786800E
Block Diagram
CDROM
Decoder
X’tal
(12MHz
or
16.9344MHz)
PLL1
PLL2
CDTEXT
Decoder
External Input
Data Interface
ASS
&
ADC
Buffer
SRAM
DATA Trans
Controller
MP3/WMA/AAC
Encoder/Decoder
ARM7 Core
Cache
Flash
memory
BUFRAM
I/F
Audio
Data-I/F
Boot
ROM
USB
Host
Controller
Work
RAM
Watch Dog
Timer
USB-I/F
Interrupt
SD
Memory Card
Controller
SRC
&
HFC-Filter
Audio Control
AVISS/
7Band-EQ/
ATT/MUTE
8Fs Digital Filter
Audio DAC
Analog LPF
UART
IIC
Host-I/F
(SIO/IIC)
SIO
EVR
EVR
EVR
GPIO
Regulator
1.5V
EVR
3.3V
No.A2082-12/26
LC786800E
Power on and Reset control
 Attention when power on
(1) Reset Control
The RESB pin must be set to “Low” level to initialize the operating state of internal flash memory.
If the power is switched on when the RESB pin is “High” level, this IC may operate incorrectly because the
internal flash memory is not initialized. In this case, this IC is not initialized even if a low level supplied to
RESB pin. Therefore, the RESB pin must be set to “Low” level when power is first supplied.
(2) Electronic Volume output
Because the output state of Electronic Volume pins is undefined when the power voltage is first supplied, it is
necessary to mute the Electronic Volume output signals externally.
(3) Input voltage for Input pins
You may input the voltage of 3.6V or less to each input terminal when the power supply is off. However, it is
necessary to supply a regulated voltage to the power supply beforehand when more than 3.6V voltage is input to
the 5V tolerant input pins.
Power ON/Power Down/Reset timing
3.3V Power
VDD1
vBOT
0V
tPWD
3.3V Power
VDD1
tRESW1
tRESW2
RESB
During normal operation
(Oscillation clock is valid)
Power on stage
Parameter
Symbol
min
typ
max
unit
Power down time
tPWD
10
Power down voltage
vBOT
0
ms
Reset time (Power on)
tRESW1
20
ms
Reset time (Normal) (*1)
tRESW2
1
ms
0.2
V
*1: The x'tal oscillation must be stable during tRESW2.
When the x'tal clock has been stopped by the command etc., the specification of tRESW2 could be longer than the
value shown above, because it takes time that the x'tal oscillator becomes stable.
No.A2082-13/26
LC786800E
Host interface
The data transmission between this IC and Host controller is performed with SPI type synchronous SIO protocol. The
transmission procedure is as follows.
 Refer to the internal software specification of this IC about M5 to M0 code in Mode code transmission.
When the input data of M5 to M0 coincide to the data in the internal register, the SIFDO pin becomes to “Low”
level (Ack) then the transmission is enabled.
When not coincide, the SIFDO pin keeps “High” level (Nack) then the transmission is not enabled.
 The seventh data in Mode code transmission shows whether the following procedure is the Command transmission
or the Data reception. When the seventh data is “Low”, the following procedure is Command transmission. When
the seventh data is “High”, the following procedure is Data reception.
 Attention because the specifications of transmission timings are different depending on the internal CPU’s operating
speed modes (Low speed or Normal speed). Refer to the table in next page.
Communication Interface format between Host controller
SIFCE
SIFCK
SIFDI
MODE
(Send)
SIFDO
Command
1
Command
2
MODE
(Receive)
Command
N
Ack
Data
1
Ack
Data
2
Data
N
BUSYB
Transmission/Reception format between Host controller
(1) Host: Command Transmission
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
WR
8
1
2
3
6
7
8
D2
D1
D0
SIFCK
SIFDI
D7
Mode Code
byte
D6 D5
1st-data
byte
Last-data
byte
Nack
Ack
SIFDO
BUSYB
(2) Host: Data Reception
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
RD
8
1
2
3
6
7
8
D2
D1
D0
SIFCK
SIFDI
Mode Code
byte
SIFDO
Nack
Ack D7
D6 D5
1st-data
byte
Last-data
byte
BUSYB
No.A2082-14/26
LC786800E
Communication Timing specification between Host controller
SIFCE
(Input)
1/fCLK
tCSU
tCKH
tCKL
tCHD
SIFCK
(Input)
tCE
tCWSU tCWHD
SIFDI
(Input)
tCRAS
tCDOF
SIFDO
(Output)
BUSYB
(Output)
tCDON
tCDOH
tCBST
Parameter
Symbol
Pin names
SIFCK clock frequency
fCLK
SIFCK
SIFCK clock "H" level width
tCKH
SIFCK
SIFCK clock "L" level width
tCKL
SIFCK
Transfer start enable time
tCE
BUSYB, SIFCE
Setup time for transfer start
tCSU
SIFCE, SIFCK
Hold time for transfer end
tCHD
SIFCE, SIFCK
Setup time for SIFDI
tCWSU
SIFDI, SIFCK
Hold time for SIFDI
tCWHD
SIFDI, SIFCK
Output delay time for SIFDO “H”
tCDOH
SIFDO, SIFCK
Output delay time for SIFDO
tCRAS
SIFDO, SIFCK
Turn on time for SIFDO *1
tCDON
SIFDO, SIFCE
Turn off time for SIFDO *1
tCDOF
SIFDO, SIFCE
BUSYB "L" level output delay time
tCBST
BUSYB
min
typ
max
unit
3.3
0.725
150
MHz
ns
690
150
ns
690
0
ns
0
100
ns
200
100
ns
200
75
ns
75
75
ns
200
100
350
100
350
100
100
150
150
150
350
ns
ns
ns
ns
ns
Internal CPU operating speed mode
Upper step : Normal speed
Lower step : Low speed
*1: The tCDON and tCDOF specifications are for when the SIFDO pin is set to the 3-State mode.
No.A2082-15/26
LC786800E
USB Specification at Ta = -40C to +85C, VDD1 = 3.0V to 3.6V, DVSS = AVSS1 = AVSS2 = XVSS = 0V
Parameter
Symbol
Pin names
Conditions
min
typ
max
VIH (USB)
Low-level input voltage
VIL (USB)
Input leakage current
ILI
Output driver: OFF
Differential input sensitivity
VDI
|(UDP) - (UDM)|
0.2
Common mode voltage range
VCM
Includes VDI range
0.8
2.5
V
High-level output voltage
VOH (USB)
2.8
3.6
V
0
0.3
V
1.3
2.0
V
4.0
20.0
4.0
20.0
Low-level output voltage
2.0
unit
High-level input voltage
0.8
UDM1, UDP1,
Connect 15k ±5% pull-down
UDM2, UDP2
resistor to GND (0V).
Connect 1.5k ±5% pull-up
VOL (USB)
resistor to VDD1.
Crossover voltage
VCR
USB data rising time
TUR
USB data falling time
TUF
CL = 50pF
-10.0
10.0
V
A
V
ns
Example circuit for USB application
LC786800
UDP1
/UDP2
15
5pF
UDM1
/UDM2
15k
* The value of resistors and capacitors in this
circuit might be needed to be adjusted for each
application.
15
5pF
15k
No.A2082-16/26
LC786800E
SD Memory Card Interface
SD Memory Card Input/Output Timing specification
tSDCKL tSDCKH
1/fSDCKF
SDCCLK
(Output)
SDCMDIO
(Inout)
tSDCMS
tSDCMH
tSDCMO
tSDCDH
tSDCDO
SDCDAT[3:0]
(Inout)
tSDCDS
* Relationship between signal name and pin name
SDCCLK
: GP34
SDCMDIO
: GP35
SDCDAT [2] : GP37
SDCDAT [1] : GP32
Parameter
Symbol
SDCDAT [3] : GP36
SDCDAT [0] : GP33
Pin names
min
typ
max
unit
SDCCLK clock frequency
fSDCKF
SDCCLK
6.0
SDCCLK clock "H" level width
tSDCKH
SDCCLK
83.3
MHz
ns
SDCCLK clock "L" level width
tSDCKL
SDCCLK
83.3
ns
Setup time for command input
tSDCMS
SDCMDIO, SDCCLK
30.0
ns
Hold time for command input
tSDCMH
SDCMDIO, SDCCLK
30.0
ns
Command output valid time
tSDCMO
SDCMDIO, SDCCLK
Setup time for data input
tSDCDS
SDCDAT [3:0], SDCCLK
30.0
ns
Hold time for data input
tSDCDH
SDCDAT [3:0], SDCCLK
30.0
ns
Data output valid time
tSDCDO
SDCDAT [3:0], SDCCLK
30.0
30.0
ns
ns
Note: Internal CPU (ARM7) must be set to normal mode. Never use the SD Memory Card interface at the internal
CPU’s Low speed mode.
No.A2082-17/26
LC786800E
Audio Data Input/Output Function
AC Electrical Characteristics at Ta = 25C, VDD1 = 3.3V, DVSS = AVSS1 = AVSS2 = XVSS = 0V,
Fs=44.1kHz, Audio Signal Frequency: 1kHz, Measurement Range: 10Hz to 20kHz
Parameter
Symbol
Pin names
Conditions
min
typ
max
unit
(Input selector+ADC)
2.605
Full scale analog input level
Input impedance
20
Gain setting level
L1IN,
Gain setting step error
R1IN,
Dynamic range
S/N
DR
Total harmonic distortion
THD+N
Cross talk1
CT1
Cross talk2
CT2
3.005
30
-12
Gain setting step
Signal to noise ratio
2.805
(0.85  VDD1)
kΩ
19
1
-0.5
L2IN,
0dB Data,
R2IN,
20kHz-LPF,
L3INP,
A-filter
L3INN,
-60dB Data,
R3INP,
20kHz-LPF,
R3INN
A-filter
Vp-p
dB
dB
0.5
dB
90
95
dB
90
95
dB
Input condition :
-85
-80
dB
Between Channels
-100
-85
dB
Between Sources
-100
-85
dB
-3dBFS
(ADC digital filter)
Passband frequency
±0.04dB
Stopband frequency
0
0.4535
0.5465
Passband ripple
±0.04
24.1kHz
Stopband attenuation
-69
HPF cut off Frequency for DC
dB
dB
0.00002
offset cancelation
Fs
Fs
Fs
(Audio DAC)
Full scale analog output level
2.605
2.805
(0.85  VDD1)
3.005
Vp-p
0dB Data,
Signal to noise ratio
S/N
20kHz-LPF,
95
98
dB
94
98
dB
A-filter
Dynamic range
DR
DACOUTL,
-60dB Data,
DACOUTR
20kHz-LPF,
A-filter
Total harmonic distortion
THD+N
Cross talk
CT
0dB Data,
20kHz-LPF
0dB Data,
20kHz-LPF
-85
-80
dB
-100
-85
dB
(DAC digital filter)
±0.015dB
Passband frequency
Stopband frequency
0
0.4535
0.5465
Passband ripple
±0.015
Stopband attenuation
-62
HPF cut off frequency for DC offset
-3dB
cancelation
Fs
Fs
dB
dB
0.0000385
Fs
10
k
(Electronic volume)
Input impedance
LVRIN,RVRIN
7.5
Volume setting range
Mute level
Volume setting step
Volume setting step error
-70
80
LFOUT,
LROUT,
0dB to -32dB
RFOUT,
-32dB to -70dB
RROUT
0 dB to -32dB
-32 dB to -70dB
0
dB
90
dB
0.25
dB
1.0
dB
-0.125
0.125
dB
-0.5
0.5
dB
No.A2082-18/26
LC786800E
Digital Audio Data Interface
 Digital Audio Interface Format
Mode
Data Length
IIS
Input
16bit
MSB first right justified
IIS
16bit
MSB first right justified
Internal clock
External input clock
32fs, 48fs, 64fs
24bit
MSB first left justified
Fs384 clock
32fs, 48fs, 64fs
24bit
MSB first left justified
Output
Slot Length
Output internal 384fs clock
 Used pins
Input
Output
LRCK
BCK
DATA
Fs384 clock
GP30
GP31
GP32
GP33
GP40
GP41
GP42
GP43
GP52
GP51
GP50
GP53
GP30
GP31
GP32
GP33
GP40
GP41
GP42
GP43
GP52
GP51
GP50
GP53
De-emphasis
GP14, GP46
-
Note : There is a priority level about Digital Audio input setting for the pins from GP30 to GP33 and the pins from
GP40 to GP43 and the pins from GP50 to GP53. The priority level is as follows.
(1) GP30 to GP33  (2) GP40 to GP43  (3) GP50 to GP53
Only the setting for the pins from GP30 to GP33 will become effective even if all the pins above are set to be
the Digital Audio input pins at the same time. Set the Digital Audio input pins only to either of the pins from
GP30 to GP33 or the pins from GP40 to GP43 or the pins from GP50 to GP53 if necessary.
 Others
 Audio output can support 3 types of Fs (32kHz/44.1kHz/48kHz) when 12MHz is used to the oscillator.
When 16.9344MHz is used to the oscillator, only Fs=44.1kHz is supported.
 During external audio input, emphasis signal is input from GP14/GP46.
Digital Audio Data Input timing
tFCKIH
tFCKIL
1/fFCKI
Fs384ck
(=Fs384 clock)
tALRIH
tALRIS
LRCK
tABKIH
BCK
1/fABCKI
tABKIL
DATA
tADTIS
Parameter
Fs384 clock frequency
Symbol
fFCKI
Pin Names
tADTIH
min
typ
Fs384ck
max
20.0
unit
MHz
Fs384 clock "H" level width
tFCKIH
Fs384ck
20
ns
Fs384 clock "L" level width
tFCKIL
Fs384ck
20
ns
Bit clock frequency
fABCKI
BCK
Bit clock "H" level width
tABKIH
BCK
120
ns
Bit clock "L" level width
tABKIL
BCK
120
ns
Setup time for LRCK input
tALRIS
LRCK, BCK
30
ns
Hold time for LRCK input
tALRIH
LRCK, BCK
30
ns
Setup time for DATA input
tADTIS
DATA, BCK
30
ns
Hold time for DATA input
tADTIH
DATA, BCK
30
ns
3.3
MHz
No.A2082-19/26
LC786800E
Digital Audio Data Output timing
tFCKOH
tFCKOL
1/fFCKO
Fs384ck
(=Fs384 clock)
tDL1
LRCK
tABKOH tABKOL
tDL2
1/fABCKO
BCK
DATA
tDL3
Parameter
Symbol
Pin Names
min
typ
max
Fs384 clock frequency
fFCKO
Fs384ck
16.9344
Fs384 clock "H" level width
tFCKOH
Fs384ck
29.5
unit
MHz
*1
ns
*1
Fs384 clock "L" level width
tFCKOL
Fs384ck
29.5
ns
*1
Bit clock frequency
fABCKO
BCK
2.1168
MHz
*1
Bit clock "H" level width
tABKOH
BCK
236.2
ns
*1
Bit clock "L" level width
tABKOL
BCK
236.2
ns
*1
LRCK output delay time
tDL1
LRCK, Fs384ck
0
50
ns
BCK output delay time
tDL2
BCK, Fs384ck
0
50
ns
DATA output delay time
tDL3
DATA, Fs384ck
0
50
ns
*1: In case of setting the 48-slot length for output format as Fs = 44.1kHz.
No.A2082-20/26
LC786800E
Internal Voltage Regulator at Ta = -40C to +85C, DVSS = AVSS1 = AVSS2 = XVSS = 0V
Parameter
Symbol
Condition
Output voltage
DVDD15
VDD1 = 3.0V to 3.6V
Load current
Iope
VDD1 = 3.3V
min
1.35
typ
1.50
max
unit
1.65
V
200
mA
Note : The specification of “load current” above is sum of the load current of two internal voltage regulator.
Example circuit for Regulator
* Same circuit need to be mounted both for two regulator pins.
(No.44 and No.90)
* The capacitor C1 must be greater than 50F and low Secure
50F or more for low ESR and the capacity value in the range
of the operating temperature so that there is a possibility of the
oscillation when the capacity value changes by the temperature
change etc.
(The recommended value is 100F.)
LC786800
DVDD
DVSS
DVDD15
100F
C1
Oscillator
Example circuit for Oscillator
LC786800
XVDD
XIN
Rd1
XOUT
XVSS
C1
C1
(1) XIN/XOUT: 12.0000MHz or 16.9344MHz
 For System Main clock and USB control
 Recommended Oscillator
Nihon Dempa Kogyo Co., Ltd.
Type
Oscillation frequency
Recommended value
NX5032GA
12MHz
Rd1 = 0, C1 = 4pF
NX8045GB
12MHz
Rd1 = 0, C1 = 4pF
AT51-CD2
16.9344MHz
Rd2 = 0, C2 = 8pF
Notes
 Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the
individual original circuit board to the oscillator maker.
 The precision of oscillator used in XIN/XOUT should meet the USB standard.
 If oscillation clock is disturbed by noise or by the other factors, it may lead to operation failure. Hence, make sure to
connect resistor and capacitor for oscillation circuit as close as XIN/XOUT and the wire should be as short as
possible. Also you need to select parts with caution so as to obtain stable external constant value within the
guaranteed operating temperature range because the variation of external constant due to temperature change could
affect the oscillation precision.
 Concerning about internal circuit for XIN/XOUT, refer to the “Analog Pin Internal Equivalent Circuits” section.
No.A2082-21/26
LC786800E
PLL circuit
Example of PLL circuit
LC786800
VVDD3
VVDD2
AFILT
Rp1
Cp2
Cp1
 PLL
LC786800 includes PLL1 and PLL2.
The functions of PLL1/ PLL2 varies depends on the oscillator connected to XIN/XOUT.
When 12MHz oscillator is used
When 16.9344MHz oscillator is used
PLL1
PLL2
For system clock generation
For audio clock generation
Unused
For system clock generation
 External filter constant for PLL2
PLL2 constant
When 12MHz oscillator is used
When 16.9344MHz oscillator is used
Rp1 = 4.7k/Cp1 = 3300pF/Cp2 = 220pF
Rp1 = 4.7k/Cp1 = 0.033F/Cp2 = 2200pF
Caution
 This PLL filter circuit is for resistor (Rp1), capacitance (Cp1, Cp2), audio generation/ system clock generation
connected to AFILT. If oscillation clock is disturbed by noise or by the other factors, it may lead to operation failure.
Hence, make sure to connect resistor and capacitor that constitute filter circuit as close as AFILT and the wire
should be as short as possible. Also if filter constant changes due to temperature change, oscillation of PLL may
become unstable and the following problem may occur.
(1) 12MHz oscillator
Due to unstable audio playback clock, audio playback is affected with unstable audio signal input (ADC
operation) and output (various filter, DAC operation).
(2) 16.9344MHz oscillator
As the internal system clock used in built-in CPU and USB becomes unstable, the LSI operation is affected as
well.
Hence, you need to select parts with caution so as to obtain stable filter constant value within the guaranteed
operating temperature range.
 See the section on “Analog Pin Internal Equivalent Circuits” for the internal configuration of AFILT.
No.A2082-22/26
LC786800E
Analog Pin Internal Equivalent Circuits
Pin Name (Pin No.)
Equivalent circuit
AVDD1
AVDD1
AVSS1
AVSS1
LFOUT (1)
LROUT (2)
RROUT (7)
RFOUT (8)
AVDD1
LVRIN (3)
RVRIN (6)
AVSS1
AVDD1
AVDD1
AVSS1
AVSS1
DACOUTL (4)
DACOUTR (5)
L1IN (9)
AVDD2
R1IN (10)
L2IN (11)
R2IN (12)
L3INP (13)
L3INN (14)
R3INP (15)
AVSS2
R3INN (16)
AVDD2
AVDD2
AVSS2
AVSS2
VREFOUT (19)
AVDD2
AVDD2
AVSS2
AVSS2
VREF_ADC (20)
XVDD
XIN (74)
XOUT (75)
XVDD
XIN
XOUT
XVSS
XVSS
Continued to the next page.
No.A2082-23/26
LC786800E
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
VVDD2
VVDD2
XVSS
XVSS
AVDD1
AVDD1
AVSS1
AVSS1
AFILT (77)
LRREF (100)
No.A2082-24/26
LC786800E
Sample Application Circuit
VDD1
GP04
DVDD
GP05
GP06
GP07
GP14
TEST0
DVSS
DVDD
JTRSTB
DVDD15
JTDI
JTCK
JTMS
JTDO
JTRTCK
AVSS1
AVDD1
TEST1
LVRIN
DACOUTL
AFILT
DACOUTR
XVSS
XOUT
RVRIN
RROUT
XIN
RFOUT
L1IN
XVDD
UDP2
R1IN
UDM2
L2IN
DVSS
L3INP
UDP1
L3INN
R3INN
ATEST01
ATEST02
UDM1
DVDD
DVSS
GP47
GP46
GP45
VREFOUT
GP44
VREF_ADC
GP43
AVSS2
GP42
AVDD2
GP41
NC
GP40
NC
GP03
NC
BUSYB
SIFCE
GP50
SIFDO
SIFCK
DVSS
DVDD
GP13
GP12
GP11
RESB
GP10
DVSS
DVDD
GP37
GP36
GP35
GP34
GP33
GP32
GP31
GP30
DVSS
GP53
DVDD15
SIFDI
GP52
REG1EXTR
GP51
Host-I/F
NC
DVDD
To USB1
R2IN
R3INP
Digital Audio
INPUT
DVSS
VVDD3
VVDD2
LROUT
LC786800
From
Turner, AUX
etc
LFOUT
To USB2
To Power AMP
LRREF
Serial-l/F
To SD-Card
GND
 Take care to the input voltage level of the analog audio input.
 Concerning to the application circuit for USB, Regulator and Oscillator, refer to the page 16 and 21 respectively.
No.A2082-25/26
LC786800E
ORDERING INFORMATION
Device
LC786800E-H
Package
QIP100E(14X20)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
250 / Tray Foam
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PS No.A2082-26/26
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