AX5051 Programming Manual

APPLICATION NOTE AND9348/D
AX5051
Programming Manual
Revision 2
2
Table of Contents
1.
Overview ....................................................................................................................................... 5
1.1. Connecting the AX5051 to a Micro-Controller.......................................................................... 5
1.2. Pin Function Descriptions ................................................................................................................ 6
1.3. SPI Register Access ........................................................................................................................... 7
Status Bits............................................................................................................................................. 8
2.
Programming the Chip ................................................................................................................ 9
2.1. Parameter Programming .............................................................................................................. 13
Choosing the Fundamental Communication Characteristics............................................... 13
Setting-up the Chip......................................................................................................................... 15
2.2. Synthesizer VCO Auto-Ranging ................................................................................................... 19
2.3. AFC .................................................................................................................................................... 20
Frequency Tracking ........................................................................................................................ 21
Frequency Acquisition ................................................................................................................... 22
Factory Calibration ......................................................................................................................... 23
2.4. Receive and Transmit .................................................................................................................... 24
HDLC .................................................................................................................................................. 25
802.15.4 (ZigBee) ............................................................................................................................. 29
Raw Mode ........................................................................................................................................ 30
Raw Soft-Decision Mode ............................................................................................................... 30
Raw Mode with Preamble Match ............................................................................................... 30
2.5. Interrupts ........................................................................................................................................... 31
Interrupt Strategies .......................................................................................................................... 33
2.6. Preamble .......................................................................................................................................... 34
Choosing the Preamble Bit Pattern ............................................................................................. 34
Choosing the Preamble Duration ................................................................................................ 35
PSK Frequency Lock ....................................................................................................................... 36
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Table of Contents
2.7. Postamble......................................................................................................................................... 36
2.8. RSSI ..................................................................................................................................................... 37
3.
Register Bank Description ......................................................................................................... 39
3.1. Control Register Map ..................................................................................................................... 40
3.2. Register Descriptions....................................................................................................................... 44
REVISION ............................................................................................................................................ 44
SCRATCH ........................................................................................................................................... 44
PWRMODE ......................................................................................................................................... 44
XTALOSC ............................................................................................................................................ 44
FIFOCTRL ............................................................................................................................................ 45
FIFODATA ........................................................................................................................................... 45
IRQMASK ............................................................................................................................................ 46
IRQREQUEST ...................................................................................................................................... 46
IFMODE .............................................................................................................................................. 46
PINCFG1 ............................................................................................................................................ 47
PINCFG2 ............................................................................................................................................ 48
PINCFG3 ............................................................................................................................................ 48
IRQINVERSION................................................................................................................................... 49
MODULATION ................................................................................................................................... 49
ENCODING........................................................................................................................................ 50
FRAMING ........................................................................................................................................... 52
CRCINIT3, CRCINIT2, CRCINIT1, CRCINIT0 ................................................................................... 53
VREG .................................................................................................................................................. 53
FREQ3, FREQ2, FREQ1, FREQ0 ........................................................................................................ 54
FSKDEV2, FSKDEV1, FSKDEV0.......................................................................................................... 54
IFFREQHI, IFFREQLO .......................................................................................................................... 55
PLLLOOP ............................................................................................................................................ 55
PLLRANGING ..................................................................................................................................... 56
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Table of Contents
TXPWR ................................................................................................................................................ 56
TXRATEHI, TXRATEMID, TXRATELO .................................................................................................. 56
MODMISC ......................................................................................................................................... 57
FIFOCOUNT ....................................................................................................................................... 57
FIFOTHRESH ....................................................................................................................................... 57
FIFOCONTROL2 ................................................................................................................................ 58
AGCATTACK ..................................................................................................................................... 58
AGCDECAY ...................................................................................................................................... 59
AGCCOUNTER ................................................................................................................................. 59
CICSHIFT ............................................................................................................................................ 59
CICDEC ............................................................................................................................................. 60
DATARATEHI, DATARATELO ............................................................................................................ 60
TMGGAINHI, TMGGAINLO ............................................................................................................. 60
PHASEGAIN ....................................................................................................................................... 61
FREQGAIN ......................................................................................................................................... 61
FREQGAIN2 ....................................................................................................................................... 61
AMPLGAIN ........................................................................................................................................ 61
TRKAMPLHI, TRKAMPLLO ................................................................................................................. 61
TRKPHASEHI, TRKPHASELO .............................................................................................................. 62
TRKFREQHI, TRKFREQLO .................................................................................................................. 62
XTALCAP ........................................................................................................................................... 62
PLLVCOI ............................................................................................................................................ 62
LOCURST ............................................................................................................................................ 63
REF ...................................................................................................................................................... 63
RXMISC .............................................................................................................................................. 63
4.
References .................................................................................................................................. 64
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AND9348/D
Overview
1. Overview
AX5051 is a true single chip low-power CMOS transceiver primarily for use in SRD bands. The
on-chip transceiver consists of a fully integrated RF front-end with modulator, and
demodulator. Base band data processing is implemented in an advanced and flexible
communication controller that enables user friendly communication via the SPI interface.
1.1.
Connecting the AX5051 to a Micro-Controller
The AX5051 can easily be connected to any micro-controller. The micro-controller
communicates with the AX5051 via a register file that is implemented in the AX5051 and that
can be accessed serially via an industry standard Serial Peripheral Interface (SPI) protocol.
Reset can be performed via a dedicated signalling line or via the register file. Therefore, and
due to an integrated power-on-reset (POR) block this signal is optional.
The AX5051 sends and receives data via the SPI port in frames. This standard operation mode
is called frame mode.
In frame mode, the internal communication controller performs frame delimiting, and data is
received and transmitted via a 4 level x 10 bit FIFO, accessible via the register file. Figure 1
shows the corresponding diagram. Connecting the interrupt line is highly recommended,
though not strictly required.
RESET_N
IRQ
AX5051
optional
recommended
Interrupt in
microcontroller
MOSI
MISO
SPI
communication
CLK
SEL
SYSCLK
optional
µC clock input
Figure 1: Connection diagram with a micro-controller
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Overview
1.2.
Pin Function Descriptions
Symbol
Pin(s)
Type
NC
1
N
Not to be connected
VDD
2
P
Power supply, must be supplied with regulated voltage VREG
GND
3
P
Ground
ANTP
4
A
Antenna input/output
ANTN
5
A
Antenna input/output
GND
6
P
Ground
VDD
7
P
Power supply, must be supplied with regulated voltage VREG
NC
8
N
Not to be connected
TST1
9
I
Must be connected to GND
TST2
10
I
Must be connected to GND
GND
11
P
Ground
RESET_N
12
I
Optional reset pin
If this pin is not used it must be connected to VDD_IO
SYSCLK
13
I/O
SEL
14
I
Serial peripheral interface select
CLK
15
I
Serial peripheral interface clock
MISO
16
O
MOSI
17
I
Serial peripheral interface data input
TST3
18
I
Must be connected to GND
IRQ
19
I/O
VDD_IO
20
P
Unregulated power supply
NC
21
N
Not connected
GND
22
P
Ground
NC
23
N
Not to be connected
VREG
24
P
Regulated output voltage
VDD pins must be connected to this supply voltage
A 1µF low ESR capacitor to GND must be connected to this pin
NC
25
N
Not to be connected
VDD
26
P
Power supply, must be supplied with regulated voltage VREG
CLK16P
27
A
Crystal oscillator input/output
CLK16N
28
A
Crystal oscillator input/output
A =
I =
O =
analog signal
digital input signal
digital output signal
Description
Default functionality: Crystal oscillator (or divided) clock output
Can be programmed to be used as a general purpose I/O pin
Serial peripheral interface data output
Default functionality: Transmit and receive interrupt
Can be programmed to be used as a general purpose I/O pin
I/O
N
P
=
=
=
digital input/output signal
not to be connected
power or ground
All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5V
tolerant.
The centre pad of the QFN28 package should be connected to GND.
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AND9348/D
Overview
1.3.
SPI Register Access
Registers are accessed via a synchronous Serial Peripheral Interface (SPI). Most registers are 8
bit wide and accessed using the waveforms detailed in Figure 2. These waveforms are
compatible to most hardware SPI master controllers, and can easily be generated in
software. MISO changes on the falling edge of CLK, while MOSI is latched on the rising edge
of CLK.
SEL
CLK
MOSI
R/W
MISO
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
D0
Figure 2: SPI 8 bit read/write access
It is necessary to deactivate and reactivate SEL between register accesses. Some registers
perform preparatory actions on the falling edge of SEL and perform cleanup actions on the
rising edge of SEL, so if SEL is left active between register accesses, some registers may fail.
Some device registers (TRKAMPL, TRKPHASE, TRKFREQ) are 16 bit registers that are
continuously updated by the chip. These registers should not be accessed by two individual 8
bit accesses, as both halves may be inconsistent if the chip updates the register between the
two accesses.
The chip therefore supports atomic 16 bit register read accesses. Figure 3 shows the 16 bit
read waveform if the address of the high byte is supplied, and Figure 4 shows the waveform if
the address of the low byte is supplied.
SEL
CLK
MOSI
0
MISO
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S6
S5
S4
S3
S2
S1
S0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3: SPI 16 bit read access, most significant byte first
SEL
CLK
MOSI
MISO
0
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
Figure 4: SPI 16 bit read access, least significant byte first
16 bit write accesses are not supported.
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Overview
Status Bits
During the address phase of the access, the chip outputs the most important status bits. This
feature is designed to speed up software decision on what to do in an interrupt handler.
Table 1 shows which register bit is transmitted during the status timeslots.
SPI Bit Cell
Status
Register Bit
0
–
0
1
S6
PLL LOCK
2
S5
FIFO OVER
3
S4
FIFO UNDER
4
S3
FIFO FULL
5
S2
FIFO EMPTY
6
S1
FIFOSTAT(1)
7
S0
FIFOSTAT(0)
Table 1: SPI Status bits
For information on the meaning of the status bits see the Receive and Transmit section of the
next chapter as well as the description of the register FIFOCTRL in the Register Description
section.
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AND9348/D
Programming the Chip
2. Programming the Chip
The operation sequences of the chip are controlled using the PWRMODE register.
PWRMODE
register
Name
Description
All digital and analog functions, except the register file, are
disabled. The core supply voltage is reduced to conserve leakage
power. SPI registers are still accessible, but at a slower speed.
0.5 μA
POWERDOWN
200 μA
0100
VREGON
All digital and analog functions, except the register file, are
disabled. The core voltage, however is at its nominal value for
operation, and all SPI registers are accessible at the maximum
speed.
0101
STANDBY
The crystal oscillator is powered on; receiver and transmitter are
off.
650 μA
SYNTHRX
The synthesizer is running on the receive frequency. Transmitter and
receiver are still off. This mode is used to let the synthesizer settle on
the correct frequency for receive.
11 mA
1000
1001
FULLRX
Synthesizer and receiver are running.
1100
SYNTHTX
The synthesizer is running on the transmit frequency. Transmitter
and receiver are still off. This mode is used to let the synthesizer
settle on the correct frequency for transmit.
FULLTX
Synthesizer and transmitter are running. Do not switch into this
mode before the synthesizer has completely settled on the transmit
frequency (in SYNTHTX mode), otherwise spurious spectral
transmissions will occur.
0000
1101
Typical Idd
17 - 20 mA
10 mA
11 - 50 mA
Table 2: PWRMODE register states
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Programming the Chip
Figure 5 shows the basic programming flow chart of the device for transmitting, and Figure 6
for receiving.
1.
Power up references and oscillators: Set PWRMODE to STANDBY
First, the on-chip references and the crystal oscillator are powered up, but the synthesizer
is still powered down. Settling time of this phase is dominated by the crystal oscillator
start-up time, which depends on the specific crystal used but is typically 3 ms.
2.
Program parameters
Then the desired modulation, carrier frequency and encoding is set (see section 2.1). This
can be done while the crystal oscillator is settling.
3.
Power up synthesizer: Set PWRMODE to SYNTHTX (transmit mode) or to SYNTHRX (receive
mode)
After all the modulation parameters are set, the synthesizer can be powered up. The
settling time of the synthesizer is 5 – 50 μs depending on settings (see section AC
Characteristics in the AX5051 Datasheet)
4.
Auto-ranging
After powering up, the VCO in the synthesizer needs to be auto-ranged to the correct
range setting. This is done using the auto-ranging procedure, for details see section 2.2:
Synthesizer VCO Auto-Ranging. The auto-ranging needs to be performed, if it has not
been done in a previous RX/TX session, if the temperature or VDD have changed or if the
frequency has changed.
5.
Start transmitter/receiver: Set PWRMODE to FULLTX (transmit mode) or FULLRX (receive
mode)
6.
Power down synthesizer: Set PWRMODE to SYNTHTX (transmit mode) or SYNTHRX (receive
mode)
If the bit LOCURST in register LOCURST is set to 1 then the following applies: After FULLTX
mode it is mandatory to set PWRMODE to SYNTHTX, if this is omitted the device will not
enter STANDBY or PWRDOWN correctly.
After FULLRX mode switching to PWRDOWN directly is possible under all circumstances.
7.
Power down: Set PWRMODE to POWERDOWN
When transmission or reception is finished, the chip can be powered down.
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AND9348/D
Programming the Chip
Set PWRMODE to STANDBY
Set PWRMODE to STANDBY
Receive
Program Parameters
Program Parameters
Set PWRMODE to SYNTHTX
Set PWRMODE to SYNTHTX
Set PWRMODE to SYNTHRX
Wait 3 - 30 ms
(synthesizer settling)
Perform Auto-ranging
Perform Auto-ranging
Set PWRMODE to FULLTX
Set PWRMODE to FULLTX
Set PWRMODE to FULLRX
Transmit
Transmit
Receive
Set PWRMODE to SYNTHTX
Set PWRMODE to SYNTHTX
Set PWRMODE to
POWERDOWN
Set PWRMODE to SYNTHRX
Wait 3 - 30 ms
(synthesizer settling)
Set PWRMODE to
POWERDOWN
Set PWRMODE to FULLRX
Receive
Figure 5: Transmit flow chart
Figure 6: Receive flow chart
Figure 7: Receive interrupted by
transmit flow chart
The register contents are preserved as long as the chip is powered, therefore, registers that
do not change between receiving and transmitting do not need to be reprogrammed.
Figure 7 shows the recommended sequence for transmitting packets during packet
reception. This sequence avoids powering down the crystal oscillator and reference, thereby
avoiding start-up delays. The synthesizer VCO does not need to be re-auto-ranged, but, since
this is not a zero IF receiver, the synthesizer needs approximately 3 – 30 μs to settle on the
correct frequency. The value depends on the synthesizer settings, see section AC
characteristics of the AX5051 Datasheet.
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Programming the Chip
Transmit on Freq 0
Receive on Freq 0
Set PWRMODE to SYNTHTX
Set FLT (PLLLOOP) to 10
Set FLT (PLLLOOP) to 10
Set PLLRANGING to range of
Freq 1
Set PLLRANGING to range of
Freq 1
Set FREQ3 to Freq 1 Bits
31:24
Set FREQ3 to Freq 1 Bits
31:24
Set FREQ2 to Freq 1 Bits
23:16
Set FREQ2 to Freq 1 Bits
23:16
Set FREQ1 to Freq 1 Bits 15:8
Set FREQ1 to Freq 1 Bits 15:8
Set FREQ0 to Freq 1 Bits 7:0
Set FREQ0 to Freq 1 Bits 7:0
Wait 3us (synthesizer settling)
Wait 3us (synthesizer settling)
Set FLT (PLLLOOP) to 01
Set FLT (PLLLOOP) to 01
Receive on Freq 1
Set PWRMODE to FULLTX
Transmit on Freq 1
Figure 8: Transmit frequency change flow chart
Figure 9: Receive frequency change flow chart
In Frequency Hopping systems, it is important to perform fast frequency changes. Figure 9
shows the recommended frequency change flow chart for frequency hopping receivers,
while Figure 8 shows the recommended frequency change flow chart for frequency hopping
transmitters.
These flow charts detail the recommended sequence to change the transmit/receive
frequency. They do not detail the synchronization necessary to keep transmitter and receiver
hopping schedules synchronous.
It is assumed that auto-ranging has been performed offline for all frequencies of the hopping
schedule, and the auto-ranging results (VCOR bits of register PLLRANGING) have been
stored in the micro-controller.
In the transmit case, the transmitter must be disabled before starting the frequency change
and must only be re-enabled once the synthesizer has settled on the new frequency, in order
to avoid spurious transmissions. In the receive case, this is not necessary, the receiver can be
left running.
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AND9348/D
Programming the Chip
2.1.
Parameter Programming
Choosing the Fundamental Communication Characteristics
Table 3 lists the fundamental communication characteristics that need to be chosen before
the device can be programmed.
Parameter
Description
fXTAL
Frequency of the connected crystal in Hz
modulation
FSK, MSK, ASK, PSK or OQPSK (for recommendations see Table 4: Modulation trade-offs)
fCARRIER
Carrier frequency (i.e. center frequency of the signal) in Hz
fIF
Intermediate frequency in Hz, nominally 1MHz
BITRATE
Desired bit rate in bit/s
Modulation index, determines the frequency deviation for FSK
h
32 > h ≥ 0.5 for FSK, fdeviation = 0.5 * h* BITRATE
h = 0.5 for MSK and OQPSK
h = 0 for all other modulations
TMGCORRFRAC
Determines the timing recovery speed and the preamble length required
The relationship between TMGCORRFRAC and the preamble length is
preamble length in bits = 3*TMGCORRFRAC,
for details see section: Choosing the Preamble Duration
Choose TMGCORRFRAC=32 for best noise performance at the expense of long synchronization
time
Choose TMGCORRFRAC=8 for faster synchronization time at the expense of noise performance
Note that there is a lower bound for this value given in point 9 of section: Setting-up the Chip.
encoding
Inversion, differential, manchester, scrambled, for recommendations see the description of the
register ENCODING and Table 13: Customary telecom modes description.
Table 3 Fundamental communication characteristics
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Programming the Chip
Table 4 gives an overview of the trade-offs between the different modulations that AX5051
offers, they should be considered when making a choice.
Modulation
Trade-offs
ASK
For bit rates up to 600 kbit/s
The sensitivity for equivalent peak output power is 3 dB lower than for other modulation types, as the
average transmit power is only half the maximum transmit power.
It is recommended to use shaped ASK for data transmissions, as the spectral efficiency is greatly
improved vs. non- shaped ASK. For receive operation there is no difference between shaped and nonshaped.
FSK
For bit rates up to 350 kbit/s
Frequency deviation is a free parameter
MSK
For bit rates up to 350 kbit/s
Robust and spectrally efficient form of FSK (Modulation is the same as FSK with h=0.5)
Frequency deviation given by bit rate
The advantage of MSK over FSK is that it can be demodulated with higher sensitivity.
Slightly longer pre-ambles required than for FSK
PSK
For bit rates up to 600 kbit/s. Bit rates blow 10 kbps are not recommended.
Slightly longer pre-ambles required than for FSK
It is recommended to use shaped PSK for data transmissions, as the spectral efficiency is greatly
improved vs. non- shaped PSK. For receive operation there is no difference between shaped and nonshaped.
OQPSK
For bit rates up to 350 kbit/s
Very similar to MSK, with added precoding / postdecoding
For new designs, use MSK instead
Table 4: Modulation trade-offs
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Programming the Chip
Setting-up the Chip
The AX5051 should be programmed according to the following guide-line, for more detailed
recommendations and descriptions see the corresponding register descriptions in the section
Register Bank Description:
1. General set-up registers
Set bits IFMODE=0000 in register IFMODE
Set register PINCFG2 to 1100’0000
Set bits VCO_I=001 in register PLLVCOI
Set bits RXIMIX=01 in register RXMISC
These settings are mandatory for optimal performance of AX5051
For low power mode set bits REF_I=101 in register REF, for high sensitivity mode leave
the bits at their default value REF_I=011
2. Program the PLLLOOP register
Bits FLT and PLLCPI must be set to program the synthesizer loop bandwidth
Recommended settings are given in Table 5.
Bit BANDSEL is programmed to select the appropriate frequency band for fcarrier, set to 0
for 868/915 MHz band set to 1 for 433 MHz band.
Register
settings
Characteristics
Usage
FLT
01
PLLCPI
010
Loop bandwidth
100 kHz
Start-up
time
25 μs
RX/TX switch
time
15 μs
01
001
50 kHz
50 μs
30 μs
11
010
200 kHz
12 μs
7 μs
10
010
500 kHz
5 μs
3 μs
•
Recommended setting for all modulations, all
values of BITRATE, RX and TX
•
Mandatory for FSK, MSK, OQPSK with BITRATE > 50
kHz
•
Use for TX if phase noise between 300kHz and
1MHz from carrier is critical
•
Cannot be used for FSK, MSK, OQPSK with BITRATE
> 50 kHz
•
Use to speed up start-up or switching
•
Do not use for RX or TX
•
Use to speed up start-up or switching
•
Do not use for RX or TX
Table 5: Recommended synthesizer loop bandwidth settings
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Programming the Chip
3. Program the frequency registers FREQ3, FREQ2, FREQ1, FREQ0
f
1
FREQ =  CARRIER 2 24 +  ;
2
 f XTAL
ensure that the bit 0 of FREQ0 is set to one; this ensures that the built-in ΔΣ modulator
does not exhibit tonal behaviour. 1
For other limitations on the frequency programming see the register description for
FREQ3, FREQ2, FREQ1, FREQ0.
Note that to program frequencies in the 433 MHz band registers FREQ3, FREQ2, FREQ1,
FREQ0 must be programmed to appropriate values and the bit BANDSEL in the PLLLOOP
register must be set to 1.
4. Program the TXPWR register according to the desired output power
5. Program the IF frequency registers IFFREQHI and IFFREQLO;
 f
1
IFFREQ =  IF 217 + 
2
 f XTAL
6. Program the frequency deviation registers FSKDEV2, FSKDEV1 and FSKDEV0;
f DEVIATION =
h
BITRATE
2
f
1
FSKDEV =  DEVIATION 2 24 + 
2
 f XTAL
7. Program the transmit bit-rate registers TXRATEHI, TXRATEMID and TXRATELO;
 BITRATE 24 1 
TXRATE = 
2 + 
2
 f XTAL
8. Program the receiver IF bandwidth register CICDEC;
 1.5 ⋅ f XTAL 
CICDEC = 

 8 ⋅ 1.2 ⋅ BW  , if TMGCORRFRAC>16, or
 1.5 ⋅ f XTAL 
CICDEC = 

 8 ⋅ 1.4 ⋅ BW  , if TMGCORRFRAC≤16,
with
1
x 
BW = (1 + h) BITRATE
denotes the floor function of the real number x. It returns the highest integer less than or equal x.
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Programming the Chip
Note CICDEC must lie between 2≤CICDEC≤63. If the above formulas results in a CICDEC
less than 2, the chosen bandwidth is too high. Reduce the bit rate, or in the case of FSK,
the modulation factor h. If the resulting CICDEC value is larger than 63, the chosen
bandwidth is too narrow and not supported by the channel filter. Increase the bandwidth
(set CICDEC to 63). The chip will work with BW>(1+h)BITRATE, at somewhat reduced
sensitivity.
9. Determine the FSK over-sampling factor FSKMUL
For all modulations other than FSK, FSKMUL=1.
For FSK, first, make sure that your choice of TMGCORRFRAC fulfils the following inequality:
TMGCORRFRAC ≥
f XTAL
4 ⋅ BITRATE ⋅ CICDEC
Then compute FSKMUL:




1

FSKMUL = 
1

 4 ⋅ BITRATE ⋅ CICDEC
+

TMGCORRFRAC 
f XTAL

10. Program the modulation register MODULATION
See Table 12 for the coding; for FSK FSKMUL is used to set the appropriate mode.
Note that for RX operation, there is no difference between shaped and non-shaped
modulations.
11. Program the receiver bit rate registers DATARATEHI, DATARATELO

210 f XTAL
1
+ 
DATARATE = 
 BITRATE ⋅ CICDEC ⋅ FSKMUL 2 
12. Program the timing recovery dynamics registers TMGGAINHI, TMGGAINLO
 FSKMUL ⋅ DATARATE 1 
TMGGAIN = 
+ 
2
 TMGCORRFRAC
DATARATE and TMGGAIN must fulfil the following inequality in order to function correctly:
DATARATE ≥ TMGGAIN + 212
The bandwidth computation in point 8 above and the condition on TMGCORRFRAC in
point 9 above ensure that this inequality holds.
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Programming the Chip
13. Program the tracking loop dynamics registers PHASEGAIN, FREQGAIN, FREQGAIN2 and
AMPLGAIN according to Table 6:
Modulation
PHASEGAIN[3:0]
FREQGAIN[3:0]
FREQGAIN2[3:0]
AMPLGAIN[3:0]
ASK
0
6
6
6
PSK, MSK,
OQPSK
3
6
6
6
FSK
3
3
6
6
Table 6: Tracking loop dynamics register values
14. Program the AGC dynamics registers AGCATTACK and AGCDECAY according to the
following table
Modulation
Register
Recommended Setting
ASK
AGCATTACK

 BITRATE 

AGCATTACK = 27 + log 2 
 10 ⋅ f XTAL 

ASK
AGCDECAY

 BITRATE
AGCDECAY = 27 + log 2 
 100 ⋅ f XTAL

FSK, MSK,
(OQ)PSK
AGCATTACK

 BITRATE 

AGCATTACK = 27 + log 2 
 f XTAL 

FSK, MSK,
(OQ)PSK
AGCDECAY

 BITRATE 

AGCDECAY = 27 + log 2 
 10 ⋅ f XTAL 




Table 7: AGC dynamics register values
15. Program the ENCODING register according to the desired bit encoding
16. Program the FRAMING register according to the desired framing mode
17. Program the PINCFG1, PINCFG2, PINCFG3 according to the desired pin usage
Note Care must be taken to keep the reserved bits PINCFG1[7:6] at their default value of
11 and the bit PINCFG2[4] at its default value of 0, as well as writing the bits TST_PINS[1:0]
to 11 in register PINCFG2. If this is not done, then large currents may flow through the
device pins TST1, TST2 or TST3.
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2.2.
Synthesizer VCO Auto-Ranging
Whenever the frequency or the environment (e.g. temperature, voltage) of the chip
changes, the synthesizer VCO should be set to the correct range using the built-in autoranging. A re-ranging of the VCO is required if the frequency change required is larger than 5
MHz in the 868/915 MHz band or 2.5 MHz in the 433 MHz band.
Figure 10 shows the flow chart of the auto-ranging process.
Set RNGSTART of
PLLRANGING
yes
RNGSTART == 1?
no
yes
RNGERR == 1?
Error
no
Figure 10: Synthesizer VCO auto-ranging flow chart
Before starting the auto-ranging, the frequency registers (FREQ3, FREQ2, FREQ1 and FREQ0)
need to be programmed, and the chip should be in SYNTHRX or SYNTHTX mode.
Auto-ranging starts at the VCOR (register PLLRANGING) setting; if you already know the
approximately correct synthesizer VCO range, you should set VCOR to this value prior to
starting auto-ranging; this can speed up the ranging process considerably. If you have no
prior knowledge about the correct range, set VCOR to 8. Starting with VCOR < 6 should be
avoided, as the initial synthesizer frequency can exceed the maximum frequency
specification.
Hardware clears the RNG START bit automatically as soon as the ranging is finished; the
device may be programmed to deliver an interrupt on resetting of the RNG START bit.
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Programming the Chip
2.3.
AFC
Commercial Crystals only have a limited accuracy. Furthermore, since the crystal runs at a
fraction of the RF carrier frequency, any crystal frequency offset is multiplied by the
synthesizer by approximately a factor of 25 or 50, depending on the RF frequency band.
While the receiver does have automatic frequency tracking, it can only track transmit signals
that fall within its digital channel pass-band. It is therefore important to transmit and receive
on the correct frequency. The smaller the bit rate, the higher the accuracy requirements for
the reference crystal.
There are three primary methods to deal with frequency offset:
•
Frequency Tracking
•
Frequency Acquisition
•
Factory Calibration
Frequency Tracking is normally automatically performed by the chip.
Whenever the frequency uncertainties are larger than the maximum tracking range of the
frequency tracking logic, Frequency Acquisition and/or Factory Calibration may be used to
augment Frequency Tracking.
As an example, consider a 433 MHz communication system utilizing a 16 MHz reference
frequency with ±10 ppm frequency uncertainty. This translates into a RF carrier frequency
uncertainty of 4.33 kHz. Since both the receiver and the transmitter will exhibit this
uncertainty, the maximum frequency offset is ±8.66 kHz. For bit rates ≥40 kbit/s, the built in
frequency tracking circuit is enough (the following section lists the maximum frequency
offsets for frequency tracking). For bit rates down to about 5 kbit/s, FSK with large h may be
used, at the expense of a worse BER performance, to avoid having to use additional means
for frequency acquisition. For lower bit rates, or ASK/PSK modulation with bit rates less than 40
kbit/s, Frequency Acquisition, Factory Calibration or a better reference frequency must be
used in addition to Frequency Tracking
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Frequency Tracking
The receiver contains circuitry to compensate for transmitter frequency offsets. This circuitry is
fully automatic. The current frequency offset can be read out from the TRKFREQHI,
TRKFREQLO registers. These registers are valid whenever the receiver is locked to a transmit
signal.
The frequency tracking circuitry can compensate offsets up to approximately ±¼⋅BITRATE in
PSK mode. In FSK mode, the frequency tracking circuitry can compensate for the offset of all
signals that fit within the chosen digital channel filter bandwidth (see programming of
CICDEC register). Thus, by artificially choosing a wider digital channel filter bandwidth, the
tracking range can be enlarged at the expense of a lower noise performance. In ASK mode,
the frequency tracking circuitry is not used, the received signal must simply pass the receiver
filter.
The frequency tracking logic can also be used to compensate for environmental conditions
and crystal aging. To do this, the receiver should monitor frequency offsets over long
timeframes. To make sure that a valid transmit signal is present, the receiver should read the
tracking registers (TRKFREQHI, TRKFREQLO) immediately after receiving a correct packet. If
the observed frequency is consistently off the expected frequency over a longer timeframe,
the micro-controller can assume that its crystal has drifted off and should compensate for the
frequency change. Compensation should be performed by changing the frequency registers
(FREQ3, FREQ2, FREQ1 and FREQ0) accordingly.
The exact algorithm for the frequency compensation varies widely with MAC protocol and
other system considerations, but the following guidelines are recommended:
•
In a peer-to-peer scenario with two stations, both stations should adjust only their
receive frequency, to avoid instability of the whole system.
•
In a master-slave system with higher quality masters, only the slaves should adjust both
their receive and transmit frequencies.
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Programming the Chip
Frequency Acquisition
Frequency Acquisition makes use of the on-chip frequency tracking hardware with
progressively narrower bandwidths to widen the range of initial frequency offsets that can be
dealt with.
One side transmits a long preamble (or even just an unmodulated carrier), during which the
other side measures the frequency of this transmit signal. This frequency acquisition step can
be performed during system setup, upon user interaction, or before each transmission.
On the receiver side, the frequency tracking circuit is used to measure the signal frequency.
This is possible because the frequency tracking circuit works at approximately 10 dB lower
signal levels than data reception is possible. So the receiver should perform the following
actions:
1. Set the receiver to FSK, bandwidth approximately 10 times the modulation
bandwidth. FSK should be used during acquisition irrespective of the data transmission
modulation. Also, DATARATE should be set to 0x1000, which results in a datarate being
tied to the filter bandwidth, and having no relationship to the actual transmission
datarate. Furthermore, TMGGAIN should be set to 0 to disable timing acquisition.
2. Wait until TRKFREQHI, TRKFREQLO is settled (see section 2.6 for the time required for
TRKFREQHI, TRKFREQLO settling)
3. Read TRKFREQHI, TRKFREQLO, and compute the offset that needs to be applied to
FREQ3, FREQ2, FREQ1, FREQ0
4. Repeat steps 1—3 with approximately 3 times the modulation bandwidth
5. Set the receiver to the modulation parameters, and start receiving
6. Check the received data for plausibility — start over if only garbage is received, as
there may not have been a carrier transmitted during acquisition.
The AX5051-RNG Range Evaluation Kit contains example software to perform Frequency
Acquisition.
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Factory Calibration
Depending on the desired bit rate and the manufacturing tolerances of the chosen crystal, it
may be necessary to calibrate the crystal frequency during production.
In order to be able to calibrate the crystal, one needs to measure its frequency. The
recommended method to measure its frequency is to use the SYSCLK pin, which can be
programmed to output the crystal clock frequency (or a fraction of it). Directly probing the
CLK16P or CLK16N pins is not recommended, as the load capacitance of the measuring
equipment will change the frequency of the crystal. Also make sure that identical values for
registers XTALCAP and XTALOSC are being used during measurement and normal
operation, as these register settings may slightly affect the crystal oscillator frequency.
An alternative method to measure the actual crystal frequency is to transmit on a nominal
frequency, and then measure the deviation of the actual transmit signal frequency from the
nominal one with an RF counter. Measurements with a spectrum analyzer are generally not
accurate enough.
Once the actual crystal frequency is known, it is recommended to correct for the crystal
frequency deviation by changing the frequency registers (FREQ3, FREQ2, FREQ1 and
FREQ0) accordingly.
An alternative method to correct for crystal frequency deviation is to change the register
XTALCAP. This method however is inferior in resolution to the frequency register method.
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Programming the Chip
2.4.
Receive and Transmit
During receive and transmit, the software communicates with the receiver and the
transmitter through a 10 bit wide and 4 levels deep FIFO. Figure 11 shows the FIFO write
process and Figure 12 shows the FIFO read process.
FIFO full, empty, overrun and underrun flags are also transmitted during the status phase of
SPI transfers. See section 1.3 SPI Register Access and Table 1: SPI Status bits for details. FIFO
flags may also be used to generate interrupts. The AX5051 also features an arbitrary FIFO
level threshold interrupt.
The AX5051 can also be programmed to automatically stop the receiver on FIFO overrun
and to stop the transmitter on FIFO underrun.
yes
yes
FIFOEMPTY == 1?
FIFOFULL == 1?
no
no
Read Bits 9:8 from FIFOCTRL[7:6]
Read Bits 7:0 from FIFODATA[7:0]
Write Bits 9:8 to FIFOCTRL[1:0]
Write Bits 7:0 to FIFODATA[7:0]
Figure 11: Write FIFO flow chart
Figure 12: Read FIFO flow chart
Bits [7:0] are data information in both read and write. During a write access to the FIFO, Bits 9
and 8 hold the FIFOCMD[1:0] bits of the FIFOCTRL register. During a read access to the FIFO,
Bits 9 and 8 are read from FIFOSTAT[1:0] of the FIFOCTRL register bits[7:6]. The function of
these bits depends on the framing mode (for more information see following sections). The
device offers two different framing modes, namely HDLC and 802.15.4 (ZigBee). Additionally,
Raw Mode and Raw Mode with Preamble Match allow the implementation of legacy
protocols in software. FIFO operation differs slightly depending on the framing mode.
Write Access:
Read Access:
Bits 9 and 8 hold the bits FIFOCMD[1:0] of the FIFOCTRL
register during a write access to the FIFO.
During a read access to the FIFO Bits 9 and 8 are read
from FIFOSTAT[1:0] of the FIFOCTRL register Bits[7:6].
FIFO
9 8
7
6
5
FIFOCMD
7 6 5 4 3 2 1 0
FIFOCTRL[1:0]
4
3
2
1
FIFO
9 8
0
FIFODATA
7 6 5 4 3 2 1 0
7
FIFOCMD
7 6 5 4 3 2 1 0
6
5
4
3
2
1
0
FIFODATA
7 6 5 4 3 2 1 0
FIFOSTAT[1:0]
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HDLC
In HDLC mode, frames start and end with the bit pattern 01111110.
HDLC uses bit-stuffing: In order to ensure that no bit pattern inside the frame can be
erroneously detected as a frame end, the transmitter inserts a 0 bit after five consecutive one
bits; the receiver automatically removes those inserted 0 bits, making the process transparent
to the user.
At the end of a HDLC frame, a checksum is transmitted. Seven or more consecutive one bits
are treated as an ABORT, causing the current packet to be discarded. See [4] for a more
elaborate description of HDLC.
In HDLC mode the meaning of the additional 2 bits in the 10 bit FIFO describe the content of
FIFODATA[7:0]:
Bit [9:8]
00
Transmit
FIFOCTRL[1:0]
Receive
FIFOSTAT[1:0]
Data Byte (bit stuffed)
Data Byte
Packet End (Data holds status information)
Packet End is also an indication for Packet Start
01
10
11
Status Information
CRC Byte
Not used
Bit[3]=1:
CRC ok
Bit[2:0]=110:
full byte transfers only
Abort detected
RAW Byte (not bit-stuffing, CRC is initialized)
Used for flags (e.g. EOF)
Abort detected
Table 8: HDLC mode bits
In transmit the bits [9:8] describe the type of data in the FIFODATA[7:0] to be transmitted. This
controls the internal framing block and enables or disables bit stuffing for data or flags,
respectively. It also initiates CRC calculation. However the flag content and the CRC bytes
have to be written by the host processor according to the sequence shown in Figure 13. The
number of CRC bytes has to be chosen according to the type of CRC chosen in the
FRAMING register (16 bit or 32 bit). For CRC insertion it does not matter what is written in the
CRC bytes, as the chip will calculate the CRC value and will change the values.
In receive the bits [9:8] describe the type of data received. If an end of packet delimiter flag
is detected, the chip automatically evaluates the CRC and sets the bits [3:0] of the data in
the flag to signal the result of the CRC.
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Programming the Chip
Data Packet
CRC Packet
Transmit
0
0
0
1
Receive
FIFODATA[7:0]
0
0
0
0
0
0
0
0
0
write 2 or 4 times
0
0
1
FIFODATA[7:0]
x
x
x
x
1
1
1
0
CRC received and ok
0
1
x
x
x
x
0
x
x
x
CRC received and failed
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
Abort detected
HDLC Flag Packet
1
1
0
1
1
1
1
1
1
HDLC Packet delimiter
0
1
1
x
x
x
Abort detected
Figure 13 shows the HDLC transmit process, while Figure 14 shows the HDLC receive process.
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Preamble
Programming the Chip
Write ten times 0x3AA to FIFO
(Preamble for Receiver
Synchronisation)
Write 0x37E to FIFO
(HDLC Flag, Packet Delimiter)
Write Packet Bytes to FIFO
(with Bits 9:8 set to zero)
Write two times
(CRC CCITT, CRC 16)
or four times (CRC 32) 0x100 to
FIFO
Write 0x37E to FIFO
(HDLC Flag, Packet Delimiter)
yes
more packets?
no
no
Postamble
Write two times 0x3FF to FIFO
(HDLC Abort)
FIFO EMPTY == 1?
yes
Figure 13: HDLC transmit flow chart
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Programming the Chip
Read FIFO Word
no
Bits [9:8] == 01?
Search for delimiter
yes
Read FIFO Word
ABORT detected
discard packet
yes
Bit 9 == 1?
Packet Buffer
Overrun
discard packet
no
yes
no
no
Bit 8 == 1?
Packet Buffer Full?
Store Bits 7:0 to Packet Buffer
yes
yes
yes
Bit 3 == 1?
Bit 2:0 == 6?
no
no
CRC incorrect
discard packet
correct packet received
discard last 2 (CRC CCITT,
CRC16)
or 4 (CRC32) bytes
process packet
number of packet bits not
divisible by 8
discard packet
Figure 14: HDLC receive flow chart
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Programming the Chip
802.15.4 (ZigBee)
Receiver and transmitter operation differs slightly in 802.15.4 mode versus HDLC mode, due to
IEEE 802.15.4 not having a PHY CRC, and 802.15.4 determining packet length from the first
byte transmitted. See [3] for a description of the 802.15.4 PHY.
Read FIFO Word
Write four times 0x000 to FIFO
(Preamble for Receiver
Synchronisation)
no
Bits [9:0] == 0x1A7?
Write 0x0A7 to FIFO
(ZigBee Packet Start)
yes
Read FIFO Word
Write Packet Bytes to FIFO
(with Bits 9:8 set to zero)
no
Bit [9:8] == 00?
Write 1 to FABORT bit
of FRAMING register
yes
Write two times 0x000 to FIFO
Store Bits 7:0 to Packet Buffer (PKT)
yes
no
Length <= PKT[0]?
FIFO EMPTY == 1?
process packet
yes
Figure 15: 802.15.4 Transmit flow chart
Figure 16: 802.15.4 Receive flow chart
Figure 15 details the 802.15.4 transmit operation, while Figure 16 details the 802.15.4 receive
operation.
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Programming the Chip
Raw Mode
In Raw Mode, no framing is performed. Received bits are grouped into 8 bit bytes and stored
in the FIFO. Transmit bits are retrieved from the FIFO as 8 bit bytes and then serialized. The bits
are received and transmitted LSB first, that means that bit 0 was received first or will be
transmitted first. No byte synchronisation is performed.
Raw mode is useful to implement legacy protocols in software on the micro-controller.
Raw Soft-Decision Mode
In Raw Soft-Decision Mode, no framing is performed. During receive, for each received bit, a
10-bit signed value is written into the FIFO. The sign of the value determines the received bit
value, and the magnitude indicates the likelihood of the value being correct.
This mode can be used to improve the performance of error correcting codes implemented
in software on the micro-controller.
Transmission works exactly the same as in Raw Mode.
Raw Mode with Preamble Match
Raw Mode with Preamble Match works the same as Raw Mode. Additionally, the receiver
only starts receiving after the received bit stream matches a programmable preamble. The
preamble length is also programmable between 4 and 32 in multiples of 4. The preamble is
stored in the CRCINIT3, CRCINIT2, CRCINIT1, CRCINIT0 registers, the length is programmed
via the bits MATCHLEN[3:0] in the register FRAMING.
During transmission, no special preamble handling is performed by the AX5051. The preamble
needs to be transmitted in software.
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2.5.
Interrupts
The AX5051 supports interrupts for all non-immediate actions. Interrupts, while not strictly
necessary, allow the micro-controller to perform other tasks instead of waiting for the AX5051.
The AX5051 supports level triggered interrupts.
FIFO EMPTY
IRQRQFIFONOTEMPTY
IRQINVFIFONOTEMPTY
IRQMFIFONOTEMPTY
FIFO FULL
IRQRQFIFONOTFULL
IRQINVFIFONOTFULL
IRQMFIFONOTFULL
PLL UNLOCK
IRQRQPLLUNLOCK
IRQINVPLLUNLOCK
IRQMPLLUNLOCK
PLL RANGINGDONE
IRQRQPLLRNGDONE
IRQI
IRQ
IRQINVPLLRNGDONE
IRQMPLLRNGDONE
FIFOCOUNT>FIFOTHRESH
IRQRQFIFOTHRESH
IRQINVFIFOTHRESH
IRQMFIFOTHRESH
FIFO OVERRUN
IRQRQFIFOERROR
FIFO UNDERRUN
IRQINVFIFOERROR
IRQMFIFOERROR
Figure 17: Interrupt logic diagram
Figure 17 shows the interrupt logic. The AX5051 supports 6 interrupt sources. Each source may
be individually inverted and masked. The final interrupt pin may also be inverted, to support
both level active high and level active low interrupts. Table 9 lists all interrupt sources, and
how they can be cleared.
Registers used for interrupt configuration programming are
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Programming the Chip
IRQMASK, IRQREQUEST and IRQINVERSION.
Source
When Active
How to Clear
FIFO Not Full
The FIFO contains less than 4 words. At least
one word can be written without causing an
overrun
Write words into the FIFO until it is full. Be
careful not to cause overruns.
FIFO Not Empty
The FIFO contains at least one word. At least
one word can be read without causing an
underrun
Read words from the FIFO until it is empty. Be
careful not to cause underruns.
This interrupt can be cleared by reading the
PLLRANGING register. After switching the
synthesizer on, and after frequency changes
(including receive↔transmit switches), the
synthesizer requires some time to settle on the
correct frequency and to achieve phase lock
with the reference crystal. After that, it should
remain locked. The synthesizer losing lock
after that point indicates a severe problem.
Check the following:
PLL Unlock
The PLL has lost lock
•
Synthesizer programming (esp.
frequency, loop filter settings,
charge pump settings, VCO
settings) are correct
•
Synthesizer has been auto-ranged
properly
•
VDD is within spec and not too noisy
•
Temperature is within spec
•
Synthesizer is enabled
PLL Ranging Done can be cleared only by
restarting a new auto-ranging process. If no
more ranging processes are needed, mask
the interrupt.
PLL Ranging Done
The synthesizer has finished auto-ranging its
VCO
FIFO Threshold
This interrupt can be cleared by writing words
into the FIFO until FIFOCOUNT >
The FIFO contains more words than FIFOTHRESH,
FIFOTHRESH, or by writing a value greater
i.e. FIFOCOUNT > FIFOTHRESH
than or equal to FIFOCOUNT into the
FIFOTHRESH register.
FIFO Error
A FIFO overrun or underrun has occurred
This interrupt is cleared as soon as the FIFO
OVER and FIFO UNDER bits in the FIFOCTRL
register are cleared, i.e. by reading the
FIFOCTRL register.
Table 9: Interrupt sources
Edge triggered interrupts are not directly supported. In the unlikely event that the chosen
micro-controller does not support level triggered interrupts and only supports edge triggered
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Programming the Chip
interrupts, they need to be emulated in software. The following C pseudo code illustrates how
this can be done:
void interrupt_handler(void)
{
acknowledge_interrupt();
do {
handle_interrupt();
} while (IRQ);
}
The first line, acknowledge_interrupt(), acknowledges the interrupt in the interrupt controller
of the micro-controller. How this is done is specific to the micro-controller in question, and
may even be implicit. The following loop handles interrupts as long as the IRQ line is still
active. It is important that the interrupt handler is not terminated before IRQ goes inactive,
because otherwise no new edges will be produced by the AX5051, and the interrupt
becomes stuck.
Interrupt Strategies
The AX5051 supports three interrupt strategies:
1. The default strategy is to assert IRQ as soon as there is one word in the FIFO (receive,
using the FIFONOTEMPTY interrupt) or there is one word empty space in the FIFO
(transmit, using the FIFONOTFULL interrupt). The micro-controller is required to service
the interrupt within 24 bit times (24/BITRATE) to prevent a FIFO overrun or underrun. The
micro-controller will receive one interrupt per received FIFO word (message byte). This
strategy is recommended for micro-controllers with low interrupt overhead (which is
true for most micro-controllers).
2. The second strategy is to assert IRQ only when absolutely necessary, i.e. when the
FIFO is full (receive, using the inverted FIFONOTEMPTY interrupt) or when the FIFO is
empty (transmit, using the inverted FIFONOTEMPTY interrupt). The micro-controller will
receive one interrupt every three FIFO words (message bytes). This strategy is useful for
micro-controllers with a very high interrupt overhead. Care must be taken to avoid
FIFO overruns and underruns.
3. The FIFOTHRESH interrupt allows an arbitrary trade-off between interrupt rate and
interrupt service latency.
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Programming the Chip
2.6.
Preamble
At the beginning of a data transfer, a preamble must be transmitted, before the actual data
can be transmitted. The preamble has many purposes:
•
The preamble allows the power amplifier to ramp up to operational power levels. This
is not an issue with the built-in amplifier of the AX5051, which is nearly instantaneous,
but may be an issue if external amplifiers are used.
•
The preamble allows the receiver to achieve lock
•
The preamble allows the encoder (transmitter) and the decoder (receiver) to initialise
The AX5042 /AX5051 Preamble Calculator [5] summarizes the rest of this chapter and allows
to calculate recommended preamble lengths.
Choosing the Preamble Bit Pattern
In 802.15.4, the preamble bit pattern is specified by the standards committee. This
specification, which is four bytes of 0x00, should be followed.
In all other modes, the preamble bit pattern as it enters the modulator should be chosen such
that:
•
It is DC-free, to ensure that frequency offset estimation works correctly
•
It contains as many transitions as possible
Now the transmitter cannot directly control the modulator bits, only the bits that enter the
encoder. Thus, the bytes transmitted during the preamble should be chosen according to
the selected encoder mode:
Encoder Settings
Preamble Byte
INV=X, DIFF=0, SCRAM=0, MANCH=0
0x55 or 0xAA
INV=0, DIFF=1, SCRAM=0, MANCH=0
0xFF
INV=1, DIFF=1, SCRAM=0, MANCH=0
0x00
INV=X, DIFF=X, SCRAM=1, MANCH=X
0x55 or 0xAA.
INV=X, DIFF=0, SCRAM=0, MANCH=1
0x00 or 0xFF
INV=0, DIFF=1, SCRAM=0, MANCH=1
0x00
INV=1, DIFF=1, SCRAM=0, MANCH=1
0xFF
Table 10: Recommended preamble values
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Programming the Chip
Choosing the Preamble Duration
A recommended choice for the preamble duration for FSK is 32 bytes (TMGCORRFRAC = 32)
for full frequency offset compensation capabilities. The receiver can work with preambles as
short as 3 byte, TMGCORRFRAC must be set to 8 accordingly. With a 3 byte preamble it may
not be possible to reach optimal sensitivities and to correct for the full frequency offset range.
All sensitivities quoted in the AX5051 Data Sheet refer to TMGCORRFRAC = 32 and a
preamble length long enough to correct for the full frequency offset range.
The following section gives some details for a more complete understanding of the factors
affecting the preamble duration choice:
The preamble duration should be chosen to be the sum of the following components,
rounded up the next higher integral number of bytes (numbers below are given in bits)
•
Power amplifier startup time. Zero for the built-in amplifier of the AX5051. Consult
documentation in case an external amplifier is used.
•
The decoder needs 18-19 bits to synchronize the descrambler, if the descrambler is
used, otherwise 1-2 bits
•
The time the receiver needs to achieve bit lock is a probabilistic process, and
depends on the bit recovery speed settings, the frequency of transitions in the
transmit signal, as well as on the signal-to-noise ratio of the received signal. A
reasonable estimate would be 3⋅TMGCORRFRAC if the preamble values detailed
above are used and the scrambler is disabled, or 4⋅TMGCORRFRAC if the scrambler is
used.
•
The time the receiver needs to achieve frequency offset and phase lock is again a
probabilistic process that depends on the initial frequency offset, the signal-to-noise
ratio of the received signal, the modulation, and the bandwidth (speed) setting of
the frequency recovery loop.
o
ASK: For ASK, achieving frequency lock is not required for demodulation, so no
additional preamble for achieving frequency lock needs to be used. TRKFREQ
is valid after approximately 600-800 bits.
o
FSK: FSK frequency lock is achieved within 150 bits with FREQGAIN= 3 for the
full supported frequency offset range (±½∙BITRATE∙FSKMUL). Frequency lock
time is approximately proportional to the frequency offset, so if the frequency
offset can be guaranteed to be lower than the maximum supported range,
correspondingly shorter preambles can be used. Setting FREQGAIN=2 halves
the number of bits required for frequency lock at the expense of a slightly
worse BER performance (<1dB). For small h (h≤1), FREQGAIN=1 or FREQGAIN=0
can be used to further shorten the required number of preamble bits, at the
expense of a larger BER performance penalty.
For very large h (h≥16), it is recommended to turn off frequency acquisition
completely by setting FREQGAIN and FREQGAIN2 to 0x0F. The large
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AND9348/D
35
36
Programming the Chip
frequency deviation ensures a corresponding frequency offset tolerance, and
switching on the frequency acquisition circuitry would result in it trying to
remove part of the modulation, causing BER degradation or long acquisition
times.
o
PSK: PSK frequency lock is required for demodulation, and is achieved within
140 bits over the full supported offset range (±¼∙BITRATE). Guaranteeing lower
frequency offset does not shorten the required preamble. Additional time may
be needed to ensure lock at the correct offset, see the next section for more
information.
PSK Frequency Lock
PSK transmits information bits by using a carrier phase angle of 0 or π. The transmit waveform
is therefore periodic. The frequency tracking circuit can therefore lock at either the correct
offset, or the correct offset ±½∙DATARATE. In the latter case, every second bit at the input of
the decoder will be inverted, because the receiver applies an additional π rotation per
received bit. Differential encoding is usually used together with PSK, so after differential
decoding, the bitstream will look inverted if the frequency acquisition circuitry is locked to the
correct offset ±½⋅DATARATE.
In order to prevent false lock of the frequency acquisition, the microcontroller should
periodically check whether the current frequency offset is outside the range –
¼∙DATARATE…+¼∙DATARATE, and restart frequency acquisition if this is the case.
The following C code fragment performs this task and should be called periodically:
if (abs((int8_t)spi_read(TRKFREQHI)) >= 0x40) {
spi_write(TRKFREQHI, 0xC0);
}
Furthermore, the preamble duration should be prolonged by the periodicity of executing this
code fragment, to ensure that the receiver is fully synchronized before packet data is
transmitted.
For example, if 100 kbit/s PSK is used and this fragment is executed once per millisecond (ms),
the preamble should be prolonged by 1ms or 100 bits.
2.7.
Postamble
After the data is transmitted, the micro-controller must write two additional postamble bytes
to the FIFO. These bytes are used to clear the transmit pipeline. Their contents do not matter;
HDLC flags can be used in HDLC mode.
After these preamble bytes are written to the FIFO, the micro-controller must wait until the
FIFO is fully drained (empty). Only then can the transmitter be turned off.
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AND9348/D
Programming the Chip
2.8.
RSSI
A first order approximation of the received signal strength (RSSI) is
RSSI1 = − AGCCOUNTER • 0.625dB − C1
C1 is a constant that is hardware specific. For the AX5051-DVK it is 38 dBm.
The first order approximation degrades for low S/N and low bit rates.
A more accurate RSSI formula is
RSSI2 = − AGCCOUNTER[7:1] • 1.25dB + 20 • log10(
TRKAMPL
)
0 x8000
+ {C2 − 80 • log10(CICDEC ) + 6 • CICSHIFT }
= − AGCCOUNTER[7:1] • 1.25dB + 20 • log10(TRKAMPL)
+ {C2 − 80 • log10(CICDEC ) + 6 • CICSHIFT − 20 • log10 (0 x8000)}
As soon as the device has been set-up according to section 2: Programming the Chip the
register CICSHIFT can be read and the term in {} can be pre-computed. C2 is a
hardware specific constant, for the AX5051-DVK it is 16 dBm for 433 MHz, 12 dBm for 868
MHz, and 14 dBm for 915 MHz. The formula for RSSI2 does not need to be computed with
double precision floating point. It can be approximated precisely using a few integer shifts
and adds. The following code is used in the AX5051-DVK firmware:
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AND9348/D
37
38
Programming the Chip
/** \brief RSSI correction table
*
* This table contains the values of 80*log10(x) for 0.5<=x<1.0
*/
static const int8_t yf_rssilogtable[32] = {
-24, -23, -22, -21, -20, -19, -18, -17,
-16, -15, -15, -14, -13, -12, -11, -11,
-10, -9, -9, -8, -7, -7, -6, -5,
-5, -4, -3, -3, -2, -2, -1, -1
};
/**
* \brief Return bandwidth specific AGC reference level
*
* Due to the gain of internal filters, the reference level for the
* AGC routine is bandwidth specific. This routine computes the AGC
* reference level. It is 14dBm-80*log10(CICDEC)+6*CICSHIFT
* \returns the bandwidth specific AGC reference level in dBm
*/
static int8_t yellowfoot_get_agcref(void)
{
// 240: 80*log10(1024)
// 14: board specific reference level
int8_t r = 14-240;
uint16_t t = spi_read(AX5051_REG_CICDEC);
if (!t)
return -128;
while (t < 512) {
t <<= 1;
r += 24;
}
t >>= 4;
r -= yf_rssilogtable[((uint8_t)t) - 32];
r += 6 * (spi_read(AX5051_REG_CICSHIFT) & 0x1F);
return r;
}
/**
* \brief Return current AGC value
*
* \returns the current AGC value in dBm
*/
int8_t yellowfoot_get_agc(void)
{
int16_t agc = spi_read(AX5051_REG_AGCCOUNTER) & 0xfe;
uint16_t trkampl = spi_read16(AX5051_REG_TRKAMPLITUDEHI);
if (!trkampl)
return -128;
agc <<= 1;
agc += (agc >> 2);
agc = -agc;
while (trkampl < 0x4000) {
trkampl <<= 1;
agc -= 24;
}
trkampl >>= 9;
agc += yf_rssilogtable[((uint8_t)trkampl) - 32];
return (int8_t)(agc >> 2) + yellowfoot_get_agcref();
}
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AND9348/D
Register Bank Description
3.
Register Bank Description
This section describes the bits of the register bank in detail. The registers are grouped by
functional block to facilitate programming.
No checks are made whether the programmed combination of bits makes sense! Bit 0 is
always the LSB.
Note Whole registers or register bits marked as reserved should be kept at their default values
Note All addresses not documented here must not be accessed, neither in reading or in writing.
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AND9348/D
39
40
Register Bank Description
3.1.
Control Register Map
Addr
Name
Dir
Reset
Bit
7
6
5
Description
4
3
2
1
0
Revision & Interface Probing
0
REVISION
1
SCRATCH
R
SILICONREV(7:0)
00010100
RW 11000101
Silicon Revision
SCRATCH(7:0)
Scratch Register
Operating Mode
2
PWRMODE
RW 0---0000
RST
-
-
-
PWRMODE(3:0)
Power Mode
RW ----0010
-
-
-
-
XTALOSCGM(3:0)
GM of Crystal Oscillator
FIFOSTAT(1:0)
FIFO OVER
FIFO UNDER
FIFO EMPTY
FIFO Control
Crystal Oscillator, Part 1
3
XTALOSC
FIFO, Part 1
4
FIFOCTRL
RW ------11
5
FIFODATA
RW --------
FIFO FULL
FIFODATA(7:0)
FIFOCMD(1:0)
FIFO Data
Interrupt Control
6
IRQMASK
7
IRQREQUEST
RW --000000
R
-
-
IRQMASK(5:0)
IRQ Mask
--------
-
-
IRQREQUEST(5:0)
-
-
IRQ Request
Interface & Pin Control
8
IFMODE
RW ----0011
0C
PINCFG1
RW 11111000
reserved
-
-
IFMODE(3:0)
Interface Mode
Must be set to 0000
IRQZ
reserved
SYSCLK(3:0)
Pin Configuration 1
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AND9348/D
Register Bank Description
0D
PINCFG2
0E
PINCFG3
0F
IRQINVERSION
RW 00000000
R
TST_PINS
--------
-
-
RW --000000
-
-
IRQE
reserved
reserved
IRQI
reserved
-
SYSCLKR
reserved
IRQR
reserved
IRQINVERSION(5:0)
Pin Configuration 2
TST_PINS(1:0) must be set to 11
Pin Configuration 3
IRQ Inversion
Modulation & Framing
10
MODULATION
RW -0000010
-
11
ENCODING
RW ----0010
-
-
12
FRAMING
RW 00000000
FRMRX
HSUPP
14
CRCINIT3
RW 11111111
CRCINIT(31:24)
CRC Initialization Data or
Preamble
15
CRCINIT2
RW 11111111
CRCINIT(23:16)
CRC Initialization Data or
Preamble
16
CRCINIT1
RW 11111111
CRCINIT(15:8)
CRC Initialization Data or
Preamble
17
CRCINIT0
RW 11111111
CRCINIT(7:0)
CRC Initialization Data or
Preamble
MODULATION(6:0)
-
-
ENC MANCH
CRCMODE(1:0)
Modulation
ENC SCRAM
ENC DIFF
FRMMODE(2:0)
ENC INV
Encoder/Decoder Settings
FABORT
Framing settings
Voltage Regulator
1B
VREG
R
--------
-
-
-
-
SSDS
SSREG
SDS
SREG
Voltage Regulator Status
Synthesizer
20
FREQ3
RW 00111001
FREQ(31:24)
Synthesizer Frequency
21
FREQ2
RW 00110100
FREQ(23:16)
Synthesizer Frequency
22
FREQ1
RW 11001100
FREQ(15:8)
Synthesizer Frequency
23
FREQ0
RW 11001101
FREQ(7:0)
Synthesizer Frequency
25
FSKDEV2
RW 00000010
FSKDEV(23:16)
FSK Frequency Deviation
26
FSKDEV1
RW 01100110
FSKDEV(15:8)
FSK Frequency Deviation
27
FSKDEV0
RW 01100110
FSKDEV(7:0)
FSK Frequency Deviation
28
IFFREQHI
RW 00100000
IFFREQ(15:8)
2nd LO / IF Frequency
29
IFFREQLO
RW 00000000
IFFREQ(7:0)
2nd LO / IF Frequency
2C
PLLLOOP
RW -0011101
reserved
BANDSEL
2D
PLLRANGING
RW 00001000 STICKY LOCK PLL LOCK
RNGERR
-
PLLCPI(2:0)
RNG START
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FLT(1:0)
VCOR(3:0)
Synthesizer Loop Filter Settings
Synthesizer VCO Auto-Ranging
AND9348/D
41
42
Register Bank Description
Transmitter
30
TXPWR
RW ----1000
31
TXRATEHI
RW 00001001
TXRATE(23:16)
Transmitter Bitrate
32
TXRATEMID
RW 10011001
TXRATE(15:8)
Transmitter Bitrate
33
TXRATELO
RW 10011010
TXRATE(7:0)
Transmitter Bitrate
34
MODMISC
RW ––––––11
–
–
–
–
TXRNG(3:0)
–
Transmit Power
reserved
PTTCLK
GATE
–
–
–
–
–
Misc RF Flags
--------
-
-
-
-
-
FIFOCOUNT(2:0)
FIFO Fill state
FIFOTHRESH(2:0)
FIFO Threshold
FIFO, Part 2
35
FIFOCOUNT
36
FIFOTHRESH
RW -----000
-
-
-
-
-
37
FIFOCONTROL2
RW 0-----00
CLEAR
-
-
-
-
3A
AGCATTACK
RW 00010110
-
-
-
AGCATTACK(4:0)
AGC Attack
3B
AGCDECAY
RW 0–010011
reserved
–
reserved
AGCDECAY(4:0)
AGC Decay
3C
AGCCOUNTER
R
––––––––
3D
CICSHIFT
R
--000100
-
-
3F
CICDEC
RW 00000100
-
-
40
DATARATEHI
RW 00011010
DATARATE(15:8)
Datarate
41
DATARATELO
RW 10101011
DATARATE(7:0)
Datarate
42
TMGGAINHI
RW 00000000
TIMINGGAIN(15:8)
Timing Gain
43
TMGGAINLO
RW 11010101
TIMINGGAIN(7:0)
Timing Gain
44
PHASEGAIN
RW 00––0011
45
FREQGAIN
RW 00001010
0
46
FREQGAIN2
RW ––––1010
–
–
47
AMPLGAIN
RW –––00110
–
–
48
TRKAMPLHI
R
––––––––
TRKAMPL(15:8)
Amplitude Tracking
49
TRKAMPLLO
R
––––––––
TRKAMPL(7:0)
Amplitude Tracking
4A
TRKPHASEHI
R
––––––––
4B
TRKPHASELO
R
––––––––
R
-
STOPONERR(1:0)
Additional FIFO control
Receiver
AGCCOUNTER(7:0)
reserved
–
reseved
CICSHIFT(4:0)
CICDEC(5:0)
–
CIC Shift Factor
CIC Decimation Factor
–
PHASEGAIN(3:0)
Phase Gain
FREQGAIN(3:0)
Frequency Gain
–
–
FREQGAIN2(3:0)
Frequency Gain 2
–
reserved
AMPLGAIN(3:0)
Amplitude Gain
reserved
–
AGC Current Value
–
–
TRKPHASE(7:0)
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TRKPHASE(11:8)
Phase Tracking
Phase Tracking
AND9348/D
Register Bank Description
4C
TRKFREQHI
R
––––––––
TRKFREQ(15:8)
Frequency Tracking
4D
TRKFREQLO
R
––––––––
TRKFREQ(7:0)
Frequency Tracking
Crystal Oscillator, Part 2
XTALCAP
RW --000000
-
-
72
PLLVCOI
RW --000100
-
-
7A
LOCURST
RW 00110000
LOCURST
7C
REF
RW --100011
-
-
7D
RXMISC
RW --110110
-
-
4F
Crystal oscillator tuning
capacitance
XTALCAP(5:0)
Misc
reserved
VCO_I[2:0]
reserved
reserved
reserved
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Synthesizer VCO current
Must be set to 001
Transmitter mode
REF_I[2:0]
RXIMIX(1:0)
Reference adjust
Misc RF settings
RXIMIX(1:0) must be set to 01
AND9348/D
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Register Bank Description
3.2.
Register Descriptions
REVISION
The register holds the revision index of the chip.
Name
Bits
R/W
Reset
REVISION
7:0
R
00010100
Description
Silicon Revision
SCRATCH
The SCRATCH register does not affect the function of the chip in any way. It is intended for
the micro-controller to test communication to the AX5051.
Name
Bits
R/W
Reset
Description
SCRATCH
7:0
R
11000101
Scratch Register
PWRMODE
This register controls the powering and reset of the various blocks on the chip.
Name
RST
PWRMODE
Bits
R/W
Reset
7
RW
0
3:0
RW
0000
Description
Reset; setting this bit to 1 resets the whole chip.
This bit does not auto-reset – the chip remains in
reset state until this bit is cleared.
Powermode; see Table 2: PWRMODE register states
Note Before RST can be written to 1, the SPI interface of the chip needs to be reset. This is done by
setting the SEL line to high.
See register LOCURST for limitations on the sequences of PWRMODE settings.
XTALOSC
This register controls the transconductance of the crystal oscillator. Optimal settings will
depend on the characteristics of the specific crystal that is used. For a table containing the
values as a function of the register settings see the AX5051 Datasheet.
Name
Bits
R/W
Reset
Description
XTALOSCGM
3:0
RW
0010
Transconductance of the Crystal Oscillator
For other crystal oscillator settings see the register XTALCAP.
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AND9348/D
Register Bank Description
FIFOCTRL
This register is used to send control commands (depending on the selected frame mode)
and holds the FIFO status information. For further FIFO settings see the registers FIFODATA,
FIFOCOUNT, FIFOTHRESH, FIFOCONTROL2.
Name
FIFOCMD
FIFO EMPTY
FIFO FULL
FIFO UNDER
FIFO OVER
FIFOSTAT
Bits
R/W
Reset
1:0
RW
11
2
R
-
FIFO is empty if 1
3
R
-
FIFO is full if 1; if 1, the FIFO contains 4 words.
-
FIFO under run occurred since last read of FIFOCTRL
when 1. This bit is set when a read operation by the
transmitter (transmit mode) or the micro-controller
(receive mode) was attempted while the FIFO was
empty.
4
R
Description
FIFO command bits (written to FIFO during next write
to FIFODATA); see section 2.4 Receive and Transmit
for exact operation of these bits
5
R
-
FIFO over run occurred since last read of FIFOCTRL
when 1. This bit is set when a write operation by the
receiver (receive mode) or the micro-controller
(transmit mode) was attempted while the FIFO was
full.
7:6
R
-
FIFO Status bits associated with current FIFO top
word; see section 2.4 Receive and Transmit for exact
operation of these bits
FIFODATA
This register is used to read from and write to the 4 level x 10 bit FIFO. For further information
on FIFO settings see section 2.4: Receive and Transmit and the register FIFOCTRL.
Name
FIFODATA
Bits
R/W
Reset
7:0
RW
-
Description
FIFO access register
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AND9348/D
45
46
Register Bank Description
IRQMASK
This register allows to mask or de-mask interrupts. For further information on interrupt related
settings see section 2.5: Interrupts and the registers IRQREQUEST and IRQINVERSION as well
as PINCFG1 and PINCFG2.
Name
IRQMFIFONOTEMPTY
IRQMFIFONOTFULL
IRQMPLLUNLOCK
IRQMPLLRNGDONE
IRQMFIFOTHRESH
IRQMFIFOERROR
Bits
R/W
Reset
Description
0
RW
0
FIFO not empty interrupt enable
1
RW
0
FIFO not full interrupt enable
2
RW
0
Synthesizer lock lost interrupt enable
3
RW
0
Synthesizer auto-ranging done interrupt enable
4
RW
0
FIFO count >= threshold interrupt enable
5
RW
0
FIFO error (overrun or underrun) interrupt enable
IRQREQUEST
This register indicates pending interrupts. For further information on interrupt related settings
see section 2.5: Interrupts and the registers IRQMASK and IRQINVERSION as well as
PINCFG1 and PINCFG2.
Name
IRQRQFIFONOTEMPTY
IRQRQFIFONOTFULL
IRQRQPLLUNLOCK
IRQRQPLLRNGDONE
IRQRFIFOTHRESH
IRQRFIFOERROR
Bits
R/W
Reset
Description
0
R
-
FIFO not empty interrupt pending
1
R
-
FIFO not full interrupt pending
2
R
-
Synthesizer lock lost interrupt pending
3
R
-
Synthesizer auto-ranging done interrupt pending
4
RW
0
FIFO count >= threshold interrupt pending
5
RW
0
FIFO error (overrun or underrun) interrupt pending
IFMODE
This register allows to set the chip into production test modes, the test modes are not
intended for usage in an application.
Name
IFMODE
Bits
R/W
Reset
Description
3:0
RW
0011
This register must be set to 0000
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AND9348/D
Register Bank Description
PINCFG1
This register allows to configure the SYSCLK and IRQ pins for application specific use.
Name
SYSCLK
IRQZ
Bits
R/W
Reset
Description
3:0
RW
1000
See Table 11
5
RW
1
1: configure IRQ pin as input (tri-state)
0: configure IRQ pin as output
This bit is only active when IRQE=1
SYSCLK Bits
Meaning
0000
SYSCLK pin outputs static ’0’
0001
SYSCLK pin outputs static ’1’
0010
SYSCLK pin is an input (tri-state)
0011
SYSCLK pin outputs inverted fXTAL
0100
SYSCLK pin outputs fXTAL
0101
SYSCLK pin outputs fXTAL/2
0110
SYSCLK pin outputs fXTAL/4
0111
SYSCLK pin outputs fXTAL/8
1000
SYSCLK pin outputs fXTAL/16
1001
SYSCLK pin outputs fXTAL/32
1010
SYSCLK pin outputs fXTAL/64
1011
SYSCLK pin outputs fXTAL/128
1100
SYSCLK pin outputs fXTAL/256
1101
SYSCLK pin outputs fXTAL/512
1110
SYSCLK pin outputs fXTAL/1024
1111
SYSCLK pin outputs fXTAL/2048
Table 11: SYSCLK bit values
Note Care must be taken to keep the reserved bits PINCFG1[7:6] at their default value of 11. If this is
not done, then large currents may flow through the device pins TST1, TST2 or TST3.
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AND9348/D
47
48
Register Bank Description
PINCFG2
This register allows to configure the IRQ pin to function as a General Purpose I/O (GPIO) pin
rather than having its special default function.
IRQE is used to enable the special function of the IRQ pin or set it to GPIO. IRQI is used to set
the state of the pin, if defined as GPIO and configured as output in PINCFG1. If the pin is
configured as special function pin, then bit IRQI is used to chose if the output signal should be
inverted.
Name
IRQI
IRQE
TST_PINS
Bits
R/W
1
Reset
RW
0
5
RW
0
7:6
RW
00
Description
GPIO pin
Special pin
0: set IRQ pin to ‘1’
0: level high active interrupt
1: set IRQ pin to ‘0’
1: level low active interrupt
0: IRQ pin carries the interrupt signal
1: IRQ pin is a general purpose I/O (GPIO)
Configuration of TST pins
Must be set to 11
Note Care must be taken to keep the reserved bit PINCFG2[4] at its default value of 0, as well as
writing the bits TST_PINS[1:0] to 11. If this is not done, then large currents may flow through the
device pins TST1, TST2 or TST3.
PINCFG3
GPIO state register: This register holds the signals on the GPIO pins. (can be used to read
back signals, if PINCFG1 configures the respective pin as input).
Name
IRQR
SYSCLKR
Bits
R/W
Reset
Description
1
R
–
Logic State of IRQ Pin
4
R
–
Logic State of SYSCLK Pin
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AND9348/D
Register Bank Description
IRQINVERSION
This register allows to invert the logic levels of the level-triggered interrupts.
Name
IRQINVFIFONOTEMPTY
IRQINVFIFONOTFULL
IRQINVPLLUNLOCK
IRQINVPLLRNGDONE
IRQINVFIFOTHRESH
IRQINVFIFOERROR
Bits
R/W
Reset
Description
0
RW
0
FIFO not empty interrupt inversion
1
RW
0
FIFO not full interrupt inversion
2
RW
0
Synthesizer lock lost interrupt inversion
3
RW
0
Synthesizer auto-ranging done interrupt inversion
4
RW
0
FIFO count >= threshold interrupt inversion
5
RW
0
FIFO error (overrun or underrun) interrupt inversion
MODULATION
This register sets the modulation type. For details on coding see also section 2: Programming
the Chip.
Name
MODULATION
Bits
R/W
Reset
6:0
RW
0000010
MODULATION Bits
Description
See Table 12
Meaning
0000000
ASK
0000010
ASK Shaped
0000100
PSK
0000101
PSK Shaped
0000110
OQSK
0000111
MSK
10nnnnn
FSK; nnnnn = FSKMUL - 1
Table 12: Modulation bit values
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AND9348/D
49
50
Register Bank Description
ENCODING
The register configures the encoder.
Name
Bits
R/W
Reset
Description
ENC INV
ENC DIFF
ENC SCRAM
0
RW
0
Invert data if set to 1
1
RW
1
Differential encode / decode data if set to 1
2
RW
0
Enable scrambler / descrambler if set to 1
ENC MANCH
3
RW
0
Enable manchester encoding / decoding. FM0/FM1
may be achieved by also appropriately setting ENC
DIFF and ENC INV
The intention of the scrambler is the removal of tones contained in the transmit data, i.e. to
randomize the transmit spectrum. The scrambler polynomial is 1+X12+X17, it is therefore
compatible to the K9NG/G3RUH Satellite Modems.
0
1
2
3
5
4
6
7
8
9 10 11 12 13 14 15 16
Figure 18: Scrambler operation
0
1
2
3
4
5
6
7
8
9 10 11
12 13 14 15 16
Figure 19: Descrambler operation
Figure 18 shows a schematic circuit diagram for the scrambler, and Figure 19 for the descrambler. The numbered boxes represent a delay by one bit.
NRZ
1
1
0
0
1
0
NRZI
FM1 (Biphase Mark)
FM0 (Biphase Space)
Manchester
Figure 20: Customary telecom encoding modes
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AND9348/D
Register Bank Description
Name
Bits
Description
NRZ
INV=0, DIFF=0,
SCRAM=0, MANCH=0
NRZ represents 1 as a high signal level, 0 as a low signal level. NRZ
performs no change
INV=1, DIFF=1,
SCRAM=0, MANCH=0
NRZI represents 1 as no change in the signal level, and 0 as a change
in the signal level. NRZI is recommended for HDLC. The HDLC bit
stuffing ensures that there are periodic zeros and thus transitions, and
the encoding is inversion invariant, and therefore useable for PSK.
INV=1, DIFF=1,
SCRAM=0, MANCH=1
FM1 (Biphase Mark) always ensures transitions at bit edges. It encodes
1 as a transition at the bit centre, and 0 as no transition at the bit
centre.
INV=0, DIFF=1,
SCRAM=0, MANCH=1
FM0 (Biphase Space) always ensures transitions at bit edges. It
encodes 1 as no transition at the bit centre, and 0 as a transition at
the bit centre.
INV=0, DIFF=0,
SCRAM=0, MANCH=1
Manchester encodes 1 as a 10 pattern, and 0 as a 01 pattern.
Manchester is not inversion invariant.
NRZI
FM1
FM0
Manchester
Table 13: Customary telecom modes description
Figure 20 shows a few well known encoding formats used in telecom and Table 13 describes
them.
Guidelines:
•
Manchester, FM0, and FM1 are not recommended for new systems, as they double
the bit rate
•
In HDLC mode, use NRZI, NRZI+Scrambler, or NRZ+Scrambler. If HDLC is to be
transmitted over PSK, NRZI and NRZI+Scrambler are valid choices.
•
In 802.15.4, use NRZ mode.
•
In Raw modes, the choice depends on the legacy system to be implemented.
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52
Register Bank Description
FRAMING
This register sets the framing mode and the CRC type.
Name
Bits
R/W
Reset
Description
FABORT
FRMMODE
0
S
0
3:1
RW
000
CRCMODE
5:4
RW
00
Defines the CRC type. See Table 15. This field is only
available in HDLC mode.
6
RW
0
Suppress unneeded abort / flag / data indications.
This field is only available in HDLC mode.
6:4
RW
000
Defines the preamble length. The preamble length is
4⋅(MATCHLEN+1) bits. This field is only available in
Raw with Preamble Match mode.
7
R
0
If one, packet reception is in progress. Otherwise, the
receiver searches for a preamble / HDLC Flag.
HSUPP
MATCHLEN
FRMRX
FRMMODE Bits
Write 1 to abort current HDLC packet
Defines framing type. See Table 14
Meaning
000
Raw
001
Raw, Soft-Decision
010
HDLC
011
Raw, Preamble Match
110
802.15.4 900MHz
111
reserved for future use
Table 14: Frame mode bit values
CRCMODE Bits
Meaning
00
CCITT (16bit)
01
CRC-16
10
CRC-32
11
Invalid
Table 15: CRC mode bit values
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AND9348/D
Register Bank Description
CRCINIT3, CRCINIT2, CRCINIT1, CRCINIT0
This register can be used to set the reset value of the CRC calculation. Normally this register is
left at all ones.
Name
CRCINIT
Bits
R/W
Reset
31:0
RW
0xFFFFFFFF
Description
CRC Reset Value; normally all ones
In Raw Mode with Preamble Match mode, this register holds the preamble against which the
incoming bit stream is compared. The comparison is LSB first. The preamble should be written
to CRCINIT with the MSB aligned. For example, if MATCHLEN is 2, i.e. a 12 bit match is
requested, the pattern should be written to CRCINIT(31:20). CRCINIT(20) should be
transmitted first.
VREG
This contains status information of the internal voltage regulator.
Name
Bits
R/W
Reset
SREG
0
R
-
This bit is 1 if the voltage regulator is in high-power
mode and the output voltage is > 2.3V
SDS
1
R
-
1 if the voltage regulator start-up is complete
SSREG
2
R
-
Sticky version of SREG, meaning that this bit is 0 if
it was 0 at any time since the last read access
SSDS
3
R
-
Sticky version of SDS, meaning that this bit is 0 if it
was 0 at any time since the last read access
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Description
AND9348/D
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54
Register Bank Description
FREQ3, FREQ2, FREQ1, FREQ0
This register sets the carrier frequency.
Name
Bits
R/W
Reset
Description
Frequency;
FREQ
31:0
RW
0x3934CCCD
f
1
FREQ =  CARRIER 2 24 + 
2
 f XTAL
Note that to program frequencies in the 433 MHz band registers FREQ3, FREQ2, FREQ1,
FREQ0 must be programmed to appropriate values and the bit BANDSEL in the PLLLOOP
register must be set to 1.
For the 868/930 MHz band the ratio
For the 433 MHz band the ratio
f CARRIER FREQ
=
should not be in the range [62.5 .. 64.5].
f XTAL
2 24
2 • f CARRIER FREQ
=
should not be in the range [62.5 .. 64.5].
f XTAL
2 23
If a 16 MHz reference crystal is used, then all SRD frequencies can be reached without
limitation.
FSKDEV2, FSKDEV1, FSKDEV0
This register is used to set the FSK frequency deviation.
Name
Bits
R/W
Reset
Description
FSK Frequency Deviation;
FSKDEV
23:0
RW
0x026666
f
1
FSKDEV =  DEVIATION 2 24 + 
2
 f XTAL
Note that fDEVIATION is actually half the deviation. The mark (bit=1) frequency is fCARRIER+fDEVIATION, the
space (bit=0) frequency is fCARRIER–fDEVIATION.
f DEVIATION =
h
BITRATE
2
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AND9348/D
Register Bank Description
IFFREQHI, IFFREQLO
These registers are used to set the IF frequency, for most cases the nominal frequency of 1
MHz is suitable.
Name
Bits
R/W
Reset
Description
IF Frequency;
IFFREQ
23:0
RW
0x2000
 f
1
IFFREQ =  IF 217 + 
2
 f XTAL
PLLLOOP
This register allows to configure the synthesizer loop bandwidth and the frequency band. For
recommendations on settings see Table 5: Recommended synthesizer loop bandwidth
settings.
Name
Bits
R/W
Reset
FLT
PLLCPI
BANDSEL
1:0
RW
01
4:2
RW
111
5
RW
0
FLT Bits
Description
Loop Filter configuration. See Table 16
Charge pump current multiplier
Band selection. See Table 17
Meaning
00
Invalid
01
Loop filter configuration with nominal bandwidth
10
Boosted loop filter configuration with x5 nominal bandwidth
11
Boosted loop filter configuration with x2 nominal bandwidth
Table 16: Filter bit values
BANDSEL Bit
Meaning
0
868/915 MHz
1
433 MHz
Table 17: Band selection bit values
Note that to program frequencies in the 433 MHz band registers FREQ3, FREQ2, FREQ1,
FREQ0 must be programmed to appropriate values and the bit BANDSEL in the PLLLOOP
register must be set to 1.
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Register Bank Description
PLLRANGING
This register is used to initiate ranging of the synthesizer VCO. It also holds the VCO range that
is currently being used. For a description of the VCO ranging procedure see section 2.2:
Synthesizer VCO Auto-Ranging.
Name
Bits
R/W
Reset
Description
VCOR
3:0
RW
1000
VCO Range
RNG START
4
RS
0
Synthesizer VCO auto-ranging; Write 1 to start
auto-ranging, bit clears when auto-ranging done
RNGERR
5
R
-
Ranging Error; this bit is set when RNG START
transitions from 1 to 0 and the programmed
frequency cannot be achieved
PLL LOCK
6
R
-
Synthesizer LOCK indicates the state of the
synthesizer at the moment of the register access.
Synthesizer is locked if 1
STICKY LOCK
7
R
-
STICKY LOCK indicates, the state of synthesizer
since last read of the register.
if 0, synthesizer lost lock after last read of
PLLRANGING register
TXPWR
This register programs the transmit output power.
Name
Bits
R/W
Reset
Description
TXRNG
3:0
RW
1000
Transmit Power; see AX5051 Datasheet for
details.
TXRATEHI, TXRATEMID, TXRATELO
These registers set the transmit bit rate.
Name
Bits
R/W
Reset
Description
Transmit Bitrate;
TXRATE
23:0
RW
0x09999A
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 BITRATE 24 1 
TXRATE = 
2 + 
2
 f XTAL
AND9348/D
Register Bank Description
MODMISC
The behaviour of the transmitter if the synthesizer looses lock is set with this register.
Name
PTTLCK GATE
Bits
R/W
Reset
0
RW
1
Description
if set to 1 then the transmitter is automatically
disabled if the synthesizer looses lock
FIFOCOUNT
This register allows the micro-controller to obtain the number of words contained in the FIFO.
FIFOCOUNT returns the number of words that can be read without underrun. Since the
AX5051 contains a 4 level deep FIFO, the FIFO will contain 4 – FIFOCOUNT empty words. 4 –
FIFOCOUNT can be written without an overrun error.
Name
Bits
R/W
Reset
FIFOCOUNT
2:0
R
---
Description
Current number of FIFO words
FIFOTHRESH
This register specifies the FIFO count that must be exceeded to activate the FIFO threshold
interrupt. That is, if IRQMFIFOTHRESH is one and FIFOCOUNT > FIFOTHRESH, an interrupt is
requested. IRQINVFIFOTHRESH may be used to invert the sense of this interrupt.
Name
Bits
R/W
Reset
FIFOTHRESH
2:0
RW
000
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Description
FIFO threshold
AND9348/D
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58
Register Bank Description
FIFOCONTROL2
This register specifies the action the transceiver should take on FIFO error, and allows the FIFO
to be cleared.
If a FIFO error (an overrun or an underrun) occurs, the transceiver performs the action
specified in STOPONERR, but does not change the PWRMODE register. Thus, to recover from
the error, the software must first write SYNTHRX, SYNTHTX or STANDBY into PWRMODE, and then
clear the overrun and underrun bits by reading FIFOSTAT.
Name
Bits
R/W
Reset
Description
This bitfield determines what should happen on
FIFO overrun or underrun
STOPONERR
CLEAR
1:0
7
RW
W
00
0
Bits
Meaning
00
No action taken, transceiver continues
01
Switch off transceiver, continue synthesizer
10
Switch off transceiver and synthesizer,
continue crystal oscillator
11
Switch off everything
Clear the FIFO by writing 1. This bit is self clearing.
Do not use STOPONERR=10 or 11 if bit LOCURST=1 in register LOCURST.
AGCATTACK
This register along with AGCDECAY controls the AGC (automatic gain control) loop slopes,
and thus the speed of the gain adjustments. The higher the bit rate, the faster the AGC loop
should be set.
Name
Bits
R/W
Reset
AGCATTACK
4:0
RW
10110
Description
AGC gain reduction speed
2.5dB ⋅ f XTAL 2 AGCATTACK − 27
[dB/s]
The recommended AGCATTACK settings can be found Table 7: AGC dynamics register
values.
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AND9348/D
Register Bank Description
AGCDECAY
This register along with AGCATTACK controls the AGC (automatic gain control) loop slopes,
and thus the speed of the gain adjustments. The higher the bit rate, the faster the AGC loop
should be set.
Name
Bits
R/W
Reset
AGCDECAY
4:0
RW
10011
Description
AGC gain increase speed
2.5dB ⋅ f XTAL 2 AGCDECAY − 27
[dB/s]
The recommended AGCDECAY settings can be found Table 7: AGC dynamics register
values.
AGCCOUNTER
This register contains the current setting of the automatic gain control (AGC) and can be
used to calculate an RSSI (RSSI1) value. See section 2.8: RSSI for details.
Name
Bits
R/W
Reset
AGCCOUNTER
7:0
R
-
Description
Current AGC Gain, in 0.625dB steps
CICSHIFT
This register must be read to be able to make the calculations for RSSI2, the calculation is
described in section 2.8: RSSI. CICSHIFT is updated when CICDEC is written.
Name
Bits
R/W
Reset
Description
CICSHIFT
4:0
RW
00100
CIC Shift factor, used for RSSI2 calculation
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AND9348/D
59
60
Register Bank Description
CICDEC
This register sets the bandwidth of the digital channel filter. For detailed information on
programming this register see section 2.1: Parameter Programming.
Name
Bits
R/W
Reset
Description
CIC Decimation factor;
 1.5 ⋅ f XTAL 
CICDEC = 

 8 ⋅1.2 ⋅ BW  , if TMGCORRFRAC>16,
CICDEC
5:0
RW
0x04
or
 1.5 ⋅ f XTAL 
CICDEC = 

 8 ⋅1.4 ⋅ BW  , if TMGCORRFRAC≤16
DATARATEHI, DATARATELO
These registers specify the receiver bit rate, relative to the channel filter band-width. For
detailed information on programming these registers see section 2.1: Parameter
Programming.
Name
Bits
R/W
Reset
DATARATE
15:0
RW
0x1AAB
Description

210 ⋅ f XTAL
1
DATARATE = 
+ 
BITRATE
CICDEC
FSKMUL
⋅
⋅
2 

TMGGAINHI, TMGGAINLO
These registers specify the aggressiveness of the receiver bit timing recovery. More aggressive
settings allow the receiver to synchronize with shorter preambles, at the expense of more
timing jitter and thus a higher bit error rate at a given signal-to-noise ratio. For detailed
information on programming this register see section 2.1: Parameter Programming.
Name
Bits
R/W
Reset
TMGGAIN
15:0
RW
0x00D5
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Description
 FSKMUL ⋅ DATARATE 1 
TMGGAIN = 
+ 
2
 TMGCORRFRAC
AND9348/D
Register Bank Description
PHASEGAIN
This register controls the bandwidth of the phase tracking loop. For detailed information on
programming this register see section 2.1: Parameter Programming.
Name
Bits
R/W
Reset
Description
PHASEGAIN
3:0
RW
0011
Bandwidth of the phase recovery loop
FREQGAIN
This register controls the bandwidth of the frequency tracking loop. For detailed information
on programming this register see section 2.1: Parameter Programming.
Name
Bits
R/W
Reset
Description
FREQGAIN
3:0
RW
1010
Bandwidth of the frequency recovery loop
FREQGAIN2
This register controls the bandwidth of the frequency tracking loop. For detailed information
on programming this register see section 2.1: Parameter Programming.
Name
Bits
R/W
Reset
Description
FREQGAIN2
3:0
RW
1010
Bandwidth of the frequency recovery loop
AMPLGAIN
This register controls the bandwidth of the amplitude tracking loop. For detailed information
on programming this register see section 2.1: Parameter Programming.
Name
Bits
R/W
Reset
Description
AMPLGAIN
3:0
RW
0110
Bandwidth of the amplitude recovery loop
TRKAMPLHI, TRKAMPLLO
This register holds the current value of the amplitude of the received signal.
Name
Bits
R/W
Reset
TRKAMPL
15:0
R
-
Description
Current amplitude tracking value
Used for RSSI2 calculation
This is a signed 16 bit register and should only be read using the 16 bit read access sequence.
See section 2.8: RSSI for details on how to use this register to derive a high resolution RSSI value
(RSSI2).
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Register Bank Description
TRKPHASEHI, TRKPHASELO
This register holds the current value of the phase offset to the received signal.
Name
Bits
R/W
Reset
TRKPHASE
11:0
R
-
Description
Current phase tracking value
This is an unsigned 16 bit register (only 12 bits used) and should only be read using the 16 bit
TRKPHASE
read access sequence.
⋅ π converts the register contents to radians.
211
TRKFREQHI, TRKFREQLO
This register holds the current value of the frequency offset of the received signal.
Name
Bits
R/W
Reset
TRKFREQ
15:0
R
-
Description
Current frequency tracking value
This is a signed 16 bit register and should only be read using the 16 bit read access sequence.
The current frequency offset estimate is ∆f =
TRKFREQ
⋅ BITRATE ⋅ FSKMUL .
216
For a description of the special handling required for this register to guarantee correct PSK
reception see the section PSK Frequency Lock.
XTALCAP
This register allows to program the tuning capacitor array at pins CLK16P and CLK16N.
Name
Bits
R/W
Reset
XTALCAP
5:0
RW
000000
Description
Crystal oscillator tuning capacitance
For the capacitance values see the AX5051 Datasheet.
PLLVCOI
This register is used to control the current through the synthesizer VCO.
Name
Bits
R/W
Reset
VCO_I
2:0
RW
100
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Description
Must be set to 001
AND9348/D
Register Bank Description
LOCURST
This bit controls the internal transmitter mode
Name
LOCURST
Bits
R/W
Reset
7
RW
0
Description
Transmitter mode
Writing the bit LOCURST=1 sets the transmitter to a mode where efficiency and output power
are higher than if LOCURST=0. The LOCURST bit setting does not impact data reception in any
way. If LOCURST=1 is used, then care must be taken to
1. Never switch from PWRMODE setting FULLTX straight to VREGON or POWERDOWN if
LOCURST=1. Always switch first to SYNTHTX after FULLTX.
2. Do not reset the device, neither with the RESET_N pin nor with the RST bit, during
FULLTX mode if LOCURST=1.
3. Do not use the settings STOPONERR=10 or 11 in register FIFOCONTROL2 together with
LOCURST=1.
4. Do not set LOCURST=1 in PWRMODE settings POWERDOWN or STANDBY if the
sequence FULLTX  SXNTHTX has never been executed since the last device powerup.
If LOCURST=0 then none of the above limitations apply.
Failure to take note of 1-3 can lead to a device state that can only be left with a powerdown/power-up sequence. Failure to take note of 4 can lead to the device drawing a large
current before entering SYNTHTX or SYNTHRX modes for the first time after power-up.
REF
This register is used to program the master reference current of the AX5051.
Name
Bits
R/W
Reset
REF_I
2:0
RW
011
Description
Master reference current
For low power mode set to 101
RXMISC
This register is used to program internal settings of the receiver.
Name
Bits
R/W
Reset
RXIMIX
1:0
RW
10
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Description
Mixer current
Must be set to 01
AND9348/D
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References
4. References
[1]
ON Semiconductor AX5051 Datasheet, see http://www.onsemi.com
[2]
ON Semiconductor AX5051 Evaluation Software, see http://www.onsemi.com
[3]
LAN MAN Standards Committee. Part 15.4: Wireless Medium Access Control (MAC)
and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks
(LR-WPANs). IEEE Computer Society, 2003.
[4]
Wikipedia. High-Level Data Link Control. http://en.wikipedia.org/wiki/HDLC.
[5]
ON Semiconductor AX5042 / AX5051 Preamble Calculator, see
http://www.onsemi.com
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
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coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey
any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a
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AND9348/D
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