LC72717PW Application Note http://onsemi.com Overview The LC72717PW is a data demodulation LSI for receiving FM multiplex broadcasts for mobile reception in the DARC format. This LSI includes an on-chip bandpass filter for extracting the DARC signal from the FM baseband signal. It also supports ITU-R recommended FM multiplex frame structures (methods A, A’, B, and C) and can implement a compact, multifunction DARC reception system. Note that a contract with the NHK Engineering System, Inc. may be required to produce DARC compatible products in case, please contact with the NHK Engineering System, Inc. Function Adjustment-free 76kHz SCF bandpass filter Supports all FM multiplex frame structures (methods A, A’, B and C) under CPU control. MSK delay detection system based on a 1T delay. Error correction function based on a 2T delay (in the MSK detection stage) Digital PLL based clock regeneration function Shift-register 1T and 2T delay circuits Block and frame synchronization detection circuits Functions for setting the number of allowable BIC errors and the number of synchronization protection operations. Error correction using (272, 190) codes Built-in layer 4 CRC code checking circuit On-chip frame memory and memory control circuit for vertical correction 7.2MHz crystal oscillator circuit Two power saving modes: STNBY and EC STOP Applications can use either a parallel CPU interface (DMA) or a CCB serial interface. Supply voltage: 2.7V to 3.6V The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing products, if you wish to use any such products, please be sure to refer the datasheet, which can be obtained upon request. CCB is ON Semiconductor® ’s original bus format. All bus addresses are managed by ON Semiconductor® for this format. CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 November, 2013 20131112V101E 1/42 LC72717PW Application Note Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0V Parameter Symbol Maximum supply voltage VDD Input voltage VIN1 Conditions Ratings A0/CL, A1/CE, A2/DI, RST, STNBY (VDD is equal to 2.7V or more.) A0/CL, A1/CE, A2/DI, RST, STNBY (VDD is less than 2.7V.) Unit -0.3 to +4.0 V -0.3 to +5.6 V -0.3 to VDD+0.3 V V VIN2 Input pin other than VIN1 -0.3 to VDD+0.3 Output voltage VOUT Output pin -0.3 to VDD+0.3 Output current IOUT1 INT, RDY, DREQ, D0 to D15, DO 0 to 2.0 mA IOUT2 Output pin other than IOUT1 0 to 1.0 mA Allowable output current (total) ITTL Total for all the output pins Allowable power dissipation Pd max Operating temperature Topr Storage temperature Tstg V 10 mA 200 mW -40 to +85 C -55 to +125 C Ta85C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -40C to +85C, VSS = 0V Ratings Parameter Symbol Pin Name Type Conditions unit min Supply voltage VDD Input high-level voltage VIH1 A0/CL, A1/CE, A2/DI, RST, Schmitt STNBY VIH2 IOCNT1, IOCNT2, DACK typ max 2.7 3.6 V 0.7VDD 5.5 V 0.7VDD VDD V 0.7VDD VDD V 0.0 0.3VDD V 0.0 0.3VDD V 0.0 0.3VDD V Schmitt D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS VIH3 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 Input low-level voltage VIL1 A0/CL, A1/CE, A2/DI, RST, Schmitt STNBY VIL2 IOCNT1, IOCNT2, DACK Schmitt D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS VIL3 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 Oscillation frequency XIN input sensitivity FOSC VXI XIN, XOUT Oscillation Within circuit 250ppm XIN Capacitive coupling Input amplitude VMPX1 MPXIN SCF 7.2 MHz 400 mVrms 100% demodulation composite 120 500 mVrms 120 450 mVrms VDD=3.3V VMPX2 MPXIN SCF 100% demodulation composite VDD=2.7V 20131112V101E 2/42 LC72717PW Application Note Electrical Characteristics at Ta = -40C to +85C, VDD = 2.7V to 3.6V, VSS = 0V Ratings Parameter Symbol Pin Name Type Conditions unit min Input high-level current IIH1 A0/CL, A1/CE, A2/DI, RST, STNBY Schmitt IIH2 IOCNT1, IOCNT2, DACK Schmitt typ max D0, D1, D2, D3, D4, D5, D6, D7 1.0 A 1.0 A 1.0 A WR, RD, A3, CS IIH3 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 Input low-level current IIL1 A0/CL, A1/CE, A2/DI, RST, STNBY Schmitt IIL2 IOCNT1, IOCNT2, DACK Schmitt -1.0 A -1.0 A -1.0 A IOH=-1mA VDD-0.4 V IOH=-2mA VDD-0.4 V D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS IIL3 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 Output high-level voltage VOH1 CLK16, DATA, FLOCK, BLOCK, CMOS FCK, BCK, CRC4 VOH2 DREQ, RDY, D0, D1, D2, D3, D4, CMOS D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, INT Output low-level voltage VOL1 CLK16, DATA, FLOCK, BLOCK, CMOS FCK, BCK, CRC4 VOL2 DREQ, RDY, D0, D1, D2, D3, D4, IOL=1mA 0.4 V IOL=2mA 0.4 V IOL=2mA 0.4 V VO=VDD 1.0 A CMOS D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, INT VOL3 DO Nch-Open Drain Output leakage current IOFF DO Hysteresis voltage VHYS A0/CL, A1/CE, A2/DI, RST, STNBY, IOCNT1, IOCNT2, DACK 0.1VDD D0, D1, D2, D3, D4, D5, D6, D7 V WR, RD, A3, CS Internal feedback RF XIN, XOUT 1.0 resistance Current drain IDD M 6 12 mA Bandpass Filter Characteristics at Ta = 25C, VDD = 2.7V to 3.6V, VSS = 0V Ratings Parameter Symbol Conditions unit min Input resistance RMPX Reference supply voltage output VREF Vref, Vdda=3V BPF center frequency FC -3dB band width typ max 50 k 1.5 V FLOUT 76.0 kHz FBW FLOUT 19.0 Group-delay in band width DGD FLOUT Gain Gain FLOUT-MPXIN, f=76kHz Attenuation characteristic ATT1 FLOUT, f=50kHz 25 dB ATT2 FLOUT, f=100kHz 15 dB ATT3 FLOUT, f=30kHz 50 dB ATT4 FLOUT, f=150kHz 50 dB 20131112V101E kHz 7.5 20 s dB 3/42 LC72717PW Application Note Package Dimensions unit : mm (typ) 12.0 0.5 10.0 48 33 64 12.0 32 10.0 49 17 1 16 0.5 0.15 0.18 (1.5) 0.1 1.7max (1.25) SANYO : SQFP64(10X10) BUSWD SP RST STNBY CS A3 A2/DI A1/CE A0/CL RD WR NC DO Vssd Vddd INT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Pin Assignment TIN 49 32 D15 NC 50 31 D14 Vssa 51 30 D13 Vref 52 29 D12 MPXIN 53 28 D11 Vdda 54 27 D10 FLOUT 55 26 D9 CIN 56 25 D8 NC 57 24 D7 TPC1 58 23 D6 TPC2 59 22 D5 TEST 60 21 D4 TOSEL1 61 20 D3 TOSEL2 62 19 D2 Vssd 63 18 D1 XIN 64 17 D0 20131112V101E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XOUT Vddd IOCNT1 IOCNT2 CLK16 DATA FLOCK BLOCK FCK BCK CRC4 DREQ DACK Vssd Vddd RDY LC72717PW 4/42 LC72717PW Application Note Frame memory Reference voltage Vssa Vref MPXIN Error correction and Layer 2 CRC Antialiasing filter Vdda FLOUT 76kHz BPF(SCF) Timing control Vref CCB IF Output control and CPU register Parallel IF PN demodulation + CIN LPF Internal clock Vssd Vddd INT CS A3 A2/DI A1/CE A0/CL RD WR DO BUSWD SP RST STNBY Block Diagram MSK correction circuit 2T Delay Divider Clock regeneration 1T Delay Vssd XIN Synchronization regeneration Layer 4 CRC LPF D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Land Pattern (Recommended) Reference Symbol eD eE e b3 l1 SQFP64 (10X10) 11.40 11.40 0.50 0.28 1.00 Notice) The dimensions are reference value, not guaranteed value. 20131112V101E 5/42 LC72717PW Application Note List of Pin Functions Pin Name of Pin No. IO State with State with Form RST=”L” STNBY=”H” Oscillation Description of Functions Pin for system clock (crystal oscillator) 1 XOUT O Oscillation 2 Vddd - - - 3 IOCNT1 I Input Input 4 IOCNT2 I Input Input 5 CLK16 O L L Clock regeneration monitor pin 6 DATA O L L Demodulation data monitor pin 7 FLOCK O L L Frame synchronization flag output pin (H: synchronized) 8 BLOCK O L L Block synchronization flag output pin (H: synchronized) stop Digital power pin Data bus I/O control 1 input pin (Parallel IF) * Connect to Vssd when CCB IF (SP=H) is to be used. Data bus I/O control 2 input pin (Parallel IF) * Connect to Vssd when CCB IF (SP=H) is to be used. 9 FCK O L L Frame start signal output pin 10 BCK O L L Block start signal output pin 11 CRC4 O H H Layer 4 CRC check result output pin 12 DREQ O H H DMA REQ signal output pin (parallel IF) 13 DACK I Input Input 14 Vssd - - - Digital GND pin 15 Vddd - - - Digital power pin 16 RDY O H H Read data READY signal output pin (parallel IF) 17 D0 I/O Input Input Data bus 0 to 7 I/O pins (parallel IF) 18 D1 I/O Input Input Bus width switched to 8 bits or 16 bits according to the BUSWD setting 19 D2 I/O Input Input 20 D3 I/O Input Input 21 D4 I/O Input Input 22 D5 I/O Input Input 23 D6 I/O Input Input 24 D7 I/O Input Input 25 D8 O Hi-Z Hi-Z Data bus 8 to 15 output pins (parallel IF) 26 D9 O Hi-Z Hi-Z * Output OFF for 8 bit bus width (BUSWD=L) 27 D10 O Hi-Z Hi-Z 28 D11 O Hi-Z Hi-Z 29 D12 O Hi-Z Hi-Z 30 D13 O Hi-Z Hi-Z 31 D14 O Hi-Z Hi-Z 32 D15 O Hi-Z Hi-Z 33 INT O H H Interrupt output pin for external CPU 34 Vddd - - - Digital power pin 35 Vssd - - - Digital GND pin 36 DO O Hi-Z(H) Hi-Z(H) 37 NC - - - 38 WR I Input Input 39 RD I Input Input 40 A0/CL I Input Input CL input pin (CCB IF)/ address input pin 0 (parallel IF) 41 A1/CE I Input Input CE input pin (CCB IF)/ address input pin 1 (parallel IF) 42 A2/DI I Input Input DI input pin (CCB IF)/ address input pin 2 (parallel IF) 43 A3 I Input Input 44 CS I Input Input 45 STNBY I Input Input Standby mode input pin (H: standby) 46 RST I Input Input System reset input pin (L: reset) 20131112V101E DMA ACK signal input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. * Connect to Vssd when CCB IF (SP=H) is to be used. D O output pin (CCB IF) NC pin (This pin must be open.) Write control signal input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. Read control signal input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. Address input pin 3 (parallel IF) * Connect to Vssd when CCB IF (SP=H) is to be used. Chip selector input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. 6/42 LC72717PW Application Note Continued from preceding page. Pin Name of Pin No. IO State with State with Form RST=”L” STNBY=”H” Description of Functions CCB/parallel setting input pin (H: CCB, L: parallel) 47 SP I Input 48 BUSWD I Input Input Data bus width setting input pin (L: 8 bits, H: 16 bits) 49 TIN I Input Input Test input pin (This pin must be connected to Vssd.) 50 NC - - - NC pin (This pin must be open.) 51 Vssa - - - Analog GND pin 52 Vref AO Vdda/2 L Reference voltage output pin (Vdda/2) 53 MPXIN AI Input Input 54 Vdda - - - Analog power pin 55 FLOUT AO Vdda/2 L Subcarrier output pin (76kHz BPF output) 56 CIN AI Input Input 57 NC - - - 58 TPC1 I Input Input Test input pin (This pin must be connected to Vssd.) 59 TPC2 I Input Input Test input pin (This pin must be connected to Vssd.) 60 TEST I Input Input Test mode setting pin (This pin must be connected to Vssd.) 61 TOSEL1 I Input Input Test input pin (This pin must be connected to Vssd.) 62 TOSEL2 I Input Input Test input pin (This pin must be connected to Vssd.) 63 Vssd - - - 64 XIN 20131112V101E I Oscillation Oscillation Baseband (multiplex) signal input pin Subcarrier input pin (comparator input) NC pin (This pin must be open.) Digital GND pin System clock pin (crystal oscillator/external clock input) stop 7/42 LC72717PW Application Note Application Circuit Example (1) Serial Interface (CCB) This is an application circuit example when the serial interface (CCB) is selected, using a microcomputer operating on the supply voltage of 3V. The DO pin is an open-drain type output, so it must be pulled up externally. CPU Interface 5.1k VDD 0.1 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 0.1 FM composite 330p 560p 22H 22H 0.1 TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN LC72717PW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3.3 BUSWD SP RST STNBY CS A3 A2/DI A1/CE A0/CL RD WR NC DO Vssd Vddd INT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.1 XOUT Vddd IOCNT1 IOCNT2 CLK16 DATA FLOCK BLOCK FCK BCK CRC4 DREQ DACK Vssd Vddd RDY GND 0.1 Xtal 7.2MHz 22p 22p Crystal oscillator 7.200MHz DSX530GA made by DAISHINKU CORP. <Note> (1)This example of an application circuit is a circuit of reference, and does not guarantee the characteristic. (2)The capacitance value to be connected to the above crystal oscillator is the reference value. Before use, confirm by crystal supplier that oscillation is free from trouble using the actual substrate. The crystal oscillation frequency must be within 7.200MHz±250ppm. (3)A bypass capacitor needs to be connected near the power supply terminal. 20131112V101E 8/42 LC72717PW Application Note (2) 8bits Parallel Interface This is an application circuit example when the parallel interface 8bits is selected. CPU Interface VDD 0.1 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 0.1 FM composite 330p 560p 22H 22H 0.1 TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN LC72717PW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CPU Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3.3 BUSWD SP RST STNBY CS A3 A2/DI A1/CE A0/CL RD WR NC DO Vssd Vddd INT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.1 XOUT Vddd IOCNT1 IOCNT2 CLK16 DATA FLOCK BLOCK FCK BCK CRC4 DREQ DACK Vssd Vddd RDY GND Xtal 7.2MHz 22p 0.1 22p Crystal oscillator 7.200MHz DSX530GA made by DAISHINKU CORP. <Note> (1)This example of an application circuit is a circuit of reference, and does not guarantee the characteristic. (2)The capacitance value to be connected to the above crystal oscillator is the reference value. Before use, confirm by crystal supplier that oscillation is free from trouble using the actual substrate. The crystal oscillation frequency must be within 7.200MHz±250ppm. (3)A bypass capacitor needs to be connected near the power supply terminal. 20131112V101E 9/42 LC72717PW Application Note (3) 16bits Parallel Interface This is an application circuit example when the parallel interface 16bits is selected. CPU Interface VDD 0.1 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 0.1 FM composite 330p 560p 22H 22H 0.1 TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN LC72717PW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CPU Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3.3 BUSWD SP RST STNBY CS A3 A2/DI A1/CE A0/CL RD WR NC DO Vssd Vddd INT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.1 XOUT Vddd IOCNT1 IOCNT2 CLK16 DATA FLOCK BLOCK FCK BCK CRC4 DREQ DACK Vssd Vddd RDY GND Xtal 7.2MHz 22p 0.1 22p Crystal oscillator 7.200MHz DSX530GA made by DAISHINKU CORP. <Note> (1)This example of an application circuit is a circuit of reference, and does not guarantee the characteristic. (2)The capacitance value to be connected to the above crystal oscillator is the reference value. Before use, confirm by crystal supplier that oscillation is free from trouble using the actual substrate. The crystal oscillation frequency must be within 7.200MHz±250ppm. (3)A bypass capacitor needs to be connected near the power supply terminal. 20131112V101E 10/42 LC72717PW Application Note Example of the connection with FM tuner LSI (LC01707PLF) The example of the connection with FM tuner LSI (LC01707PLF) is shown below. Output signal from the LPFO pin of LC01707PLF is input to the MPXIN pin. GND VDD Vssd 0.1 100 GND 44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 0.1 NC 43 FM composite NC 42 330p NC 41 NC 40 DEMOC 39 LPFI 38 DEMOO 37 LPFO 36 56p 22H 11k 0.22u 1500p 0.1 0.022u 0.68u VDD 35 SMETER 34 22H 220p LC72717PW 1 XOUT 2 Vddd LC01707PLF (FM-Tuner LSI) 560p TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN 3.3 15k Xtal 7.2MHz 22p 22p Vssd Crystal oscillator 7.200MHz DSX530GA made by DAISHINKU CORP. <Note> (1)This example of an application circuit is a circuit of reference, and does not guarantee the characteristic. (2)The capacitance value to be connected to the above crystal oscillator is the reference value. Before use, confirm by crystal supplier that oscillation is free from trouble using the actual substrate. The crystal oscillation frequency must be within 7.200MHz±250ppm. (3)A bypass capacitor needs to be connected near the power supply terminal. 20131112V101E 11/42 LC72717PW Application Note The Flow of Receiving the FM Multiplex Broadcast This document shows the whole flow of receiving the FM Multiplex Broadcast. In this flow, the processing flow of this LSI begins from the input of the composite signal. Then, MSK demodulation, synchronization detection, error correction and data output from microcontroller are performed. In the microcomputer, the layer 4 CRC data group is composed from the output data. Then layer 4 CRC check is performed. To perform the layer 4 CRC check, both the check circuit included in this LSI and the software in the microcomputer are available. After confirming that there is no error by layer 4 CRC check, the display-related processing of the received data is performed. FM multiplex (DARC) broadcast airwaves FM Tuner Processing of this LSI BPF Composite signal Comparator MSK Demodulation (2T error correction) Synchronization Detection (Block/Frame) Error Correction (Horizontal/Vertical/ 2nd Horizontal) Processing of Microcomputer Data Output (Horizontal/Vertical) Data Group Composition Layer 4 CRC check (Hardware) Layer 4 CRC check (Software) Display-related processing 20131112V101E 12/42 LC72717PW Application Note Layer Structure of DARC Layer-6 Presentation Layer Coding of the character Layer-5 Program Session Layer Layer-4 Data Group Transport Layer Data header Data group header SOH Data units Data group data END CRC Data block Layer-3 Data Packet Network Layer Prefix Data block The layers above layer-3 are in case of ARIB*. *Association of Radio industries and Business. 16 Layer-2 Error Correction Data Link Layer 176 14 DATA CRC 82 190 BIC 82 PARITY L-MSK Demodulation (16kbps) Pilot Layer-1 Transmission Channel Physical Layer L+R 0 L-R 19 38 DARC 76 Baseband Frequency (kHz) 20131112V101E 13/42 LC72717PW Application Note Layer-2 Frame Structure (Method-B) Mainly, this frame structure is used in Japan, China, and so on. 16 bits 176 bits 82 bits 14 bits BIC1 BIC1 BIC1 Packet 1 Packet 2 Packet 3 CRC CRC CRC Parity Parity Parity BIC1 BIC3 BIC3 BIC4 BIC3 BIC3 BIC4 Packet13 Packet14 Packet15 Parity packet 1 Packet16 Packet17 Parity packet 2 CRC CRC CRC CRC CRC CRC CRC Parity Parity Parity Parity Parity Parity Parity BIC3 BIC3 BIC4 BIC2 Packet94 Packet95 Parity packet 41 Packet 96 CRC CRC CRC CRC Parity Parity Parity Parity BIC2 BIC3 BIC3 BIC4 Packet 108 Packet 109 Packet 110 Parity packet 42 CRC CRC CRC CRC Parity Parity Parity Parity BIC3 BIC3 BIC4 Packet 189 Packet 190 Parity packet 82 CRC CRC CRC Parity Parity Parity 13 block 123 block 272 block =1 frame 13 block 123 block Transmission order 20131112V101E 14/42 LC72717PW Application Note Layer-2 Frame Structure (Method-A) 16 bits 176 bits 82 bits 14 bits BIC3 BIC3 BIC3 Packet 1 Packet 2 Packet 3 CRC CRC CRC Parity Parity Parity BIC3 BIC2 BIC2 BIC2 Packet 60 Packet 61 Packet 62 Packet 63 CRC CRC CRC CRC Parity Parity Parity Parity BIC2 BIC1 BIC1 BIC1 Packet 130 Packet 131 Packet 132 Packet 133 CRC CRC CRC CRC Parity Parity Parity Parity BIC1 BIC4 BIC4 BIC4 Packet 190 Parity packet 1 Parity packet 2 Parity packet 3 CRC CRC CRC CRC Parity Parity Parity Parity BIC4 BIC4 BIC4 Parity packet 80 Parity packet 81 Parity packet 82 CRC CRC CRC Parity Parity Parity 60 block 70 block 272 block =1 frame 60 block 82 block Transmission order 20131112V101E 15/42 LC72717PW Application Note Layer-2 Frame Structure (Method-A’) 16 bits 176 bits 14 bits 82 bits BIC3 BIC3 BIC3 Packet 1 Packet 2 Packet 3 CRC CRC CRC Parity Parity Parity BIC3 BIC2 BIC2 BIC2 Packet 60 Packet 61 Packet 62 Packet 63 CRC CRC CRC CRC Parity Parity Parity Parity BIC2 BIC1 BIC1 BIC1 Packet 130 Packet 131 Packet 132 Packet 133 CRC CRC CRC CRC Parity Parity Parity Parity BIC1 BIC4 Packet 190 Parity packet 1 CRC CRC Parity Parity BIC4 BIC2 Parity packet 21 Real time information 1 CRC CRC Parity Parity BIC2 BIC4 Real time information 4 Parity packet 22 CRC CRC Parity Parity BIC4 BIC2 Parity packet 41 Real time information 5 CRC CRC Parity Parity BIC2 BIC4 Real time information 8 Parity packet 42 CRC CRC Parity Parity BIC4 BIC2 Parity packet 61 Real time information 9 CRC CRC Parity Parity BIC2 BIC4 Real time information 12 Parity packet 43 CRC CRC Parity Parity BIC4 Parity packet 82 CRC Parity 60 block 70 block 60 block 272 block +12 block =1 frame 21 block 4 block 20 block 4 block 20 block 4 block 21 block Transmission order 20131112V101E 16/42 LC72717PW Application Note Layer-2 Frame Structure (Method-C) This frame is consists of BIC3 blocks only. The frame synchronization is not established. 16 bits BIC3 176 bits Packet 1 14 bits CRC 82 bits Parity Transmission order 20131112V101E 17/42 LC72717PW Application Note Error Correction (1) Error Correction and Output Conditions of Error-corrected Data (in the default state) The received data is subject to error detection by the layer 2 CRC and error correction by the (272,190) code for each one block (272 bits). At the end of correction, preparation for transmission to CPU is made and the INT signal is output. This is called “horizontal correction”. In the default state, this INT signal is output only when the output data concerned meets all of three conditions as follows: Data whose error correction is completed and for which layer 2 CRC detects no error Data received during block and frame synchronizations Data in the data packet *Depending on the register mode setting, horizontally-corrected data may be output regardless of conditions of to above. When horizontal correction cannot cover completely, correction by the product code is made frame by frame. For data that cannot be horizontally corrected, the second horizontal correction is made. This series of operations is called “vertical correction”. Conditions for the data obtained from vertically-corrected output are as follows in the default state: Data that cannot be corrected by horizontal correction, but that has been completely corrected by the vertical correction Data in the data packet Accordingly, horizontally-corrected data is not output. Packet data that cannot be corrected horizontally or vertically is not output. The parity packet data after vertical correction is not output either. Vertical correction is applied to the whole packet data that have been received during frame synchronization, and is executed when horizontal correction cannot correct all packet (block) data. Vertical correction is not made when the error-free data is received for one frame or when the received data is not synchronous in flame synchronization during reception. For the packet whose error has been corrected by horizontal correction and any error-free packet, vertical correction is not made to prevent faulty correction. In the default setting, the applicable vertically-corrected output is not output when vertical correction has not been made. * Depending on the register mode setting, the vertically-corrected data may be output regardless of whether or not vertical correction is to be made. 20131112V101E 18/42 LC72717PW Application Note (2) Error-corrected Data Output Timing (Basic Restrictions) Data received by LSI is corrected error and written sequentially without any interruption into the output data buffer memory. Since this data buffer memory has a capacity for one-block data, the corrected data before reading is over-written by the next data if data read is delayed. In consequence, it is essential to read data according to the timing stipulations shown below. This LSI specifies the output timing for each of horizontally and vertically corrected data as follows: Upon completion of preparation for the output data, LSI lowers the INT pin to “L” as a request for transmission. Data output has the period during which only horizontal data can be read and the period during which horizontal and vertical data are read according to the time division. Complete data transmission within about 8ms after INT = “L”. When only the horizontally-corrected data can be output, data transmission is possible for about 17ms. Even when CPU is in the course of reading, the output buffer is overwritten by the next output data once the specified time period is expired. The data amount that can be read by one horizontal and vertical transmission request (INT) is one block only. Vertically-corrected data is output sequentially beginning with the first block after completion of vertical correction, but the data of parity block is not output. Output of only horizontal data INT 18ms 1ms Horizontal data output period Divided output for horizontal and vertical data INT 9ms 1ms Horizontal data output period Vertical data output period 990s 990s Period during which data guarantee is impossible If the read operation is performed in the period during which data guarantee is impossible, the data after the next INT =”L” also can not be read correctly. 20131112V101E 19/42 LC72717PW Application Note (3) Horizontally-corrected Data Output Timing (Relationship With The Received Data) The timing relationship between the received data and interrupt control signal (INT) for horizontary-corrected data output is shown. But the delay from the actual received signal caused by demodulation in the MSK demodulation block is ignored. Block synchronization is established by determining the BIC code. Data of the Nth packet can be output during receiving of the next (N + 1) packet data. (N-1) packet (N+1) packet N packet BIC Received data BIC 18ms 300ns max 62.5s BCK 300ns max INT (N-1) packet data output period 1ms N packet data output period 990s Period during which data cannot be guaranteed (4) Vertically-corrected Data Output Timing Vertical correction is made when the data of one frame is stored in the memory, frame synchronization has been established, and when horizontal correction cannot correct all of packet data. Vertical correction start timing is the head of a frame. During receiving of the first to 28 th packets of the N-th frame, horizontal correction of each packet is made, transferring data to the CPU interface. Using the idling time in this period, vertical correction of the previous (N-1)-th frame data is made. Vertically-corrected data is output for the amount equivalent to 190 blocks sequentially beginning with reception of the 29th packet (block), in such a manner that one block data is output each time one block is received. Only data of data block in the FM multiplex broadcasting frame is output. The final 190th block is output during reception of the 218 th block. In the vertically-corrected data output timing, the packet data corrected by vertical correction is not output (INT not issued). However, vertical correction data output order is not shortened for the amount equivalent to the packet data that is not output. For example, if the first to 100 th data packets have been horizontally corrected, the 101 st vertically corrected packet data is output, not at the reception point of the block Number 29 th, but at the 129th packet data reception point. (N-1)-th frame Reception block No. 271 N-th frame 272 1 2 3 28 29 30 31 218 2 189 219 220 BCK 62.5s FCK 18ms 1 190 INT 1ms 18ms 18ms28=504ms 20131112V101E 9ms 9ms Data output period after vertical correction of previous frame 20/42 LC72717PW Application Note (5) List of Operation Modes Depending on the set value of INT_MOVE (bit 5 of control register 1) and VEC_OUT (bit 2 of control register 2), the INT signal output timing and output data are modified. In the table below, indicates “output”, indicates “no output.” and - indicates “none applicable.” Horizontal Parameter Default value Mode 1 Mode 2 Mode 3 INT_MOVE VEC_OUT 0 OK data NG data Parity OK data NG data OK - - NG *1 OK - *2 - NG *2 1 1 OK - *3 - NG *4 OK - - NG 0 0 output results/frame** 0 1 Vertically-corrected Horizontally-corrected output correction 1 *1 Only data whose horizontal correction result is NG and whose vertical correction result is OK is output. *2 All of vertically-corrected outputs (190 blocks/frame) are output, in both cases of horizontal correction result of OK and NG, regardless of whether the vertical correction result is OK or NG. *3 The vertically-corrected data is not output when there is no data that is determined to be NG because all the horizontal correction results are OK. *4 When there is any data whose horizontal correction result becomes NG, all of vertically-corrected outputs (190 blocks/frame) are output regardless of whether the vertical correction result is OK or NG. **The definition of OK and NG in “horizontal correction result/frame” column OK: In one frame, there is no NG block in the horizontal error correction results of all the blocks. NG: In one frame, there is at least one NG block in the horizontal error correction results of all the blocks. (6) Output Format with DO_MOVE=1 The relationship between INT and DO is shown below. DO becomes “L” in synchronous with the falling edge of INT, and return to “H” before 3ms or more against the next falling edge of INT. Therefore, when the data read is started while DO is “L”, there is margin time 3ms or more against the falling edge of INT. This timing diagram is for the case when the data read is not performed. When the data read is performed, DO returns to “H” after completion of read. 18ms INT 1ms 3ms or more DO (Output of only horizontal data) Horizontal data output period 990s Period during which data cannot be guaranteed 9ms INT 1ms 3ms or more DO (Output of horizontal and vertical data) Horizontal data output period 3ms or more Vertical data output period 990s 990s Period during which data cannot be guaranteed 20131112V101E 21/42 LC72717PW Application Note Data Reception Control Flow After power on, perform the reset operation and then perform the initial settings as the reception frame setting, the output mode setting and so on. After that, read the data till the data group is completed and then perform the layer 4 CRC check after the completion of the data group. Data group data whose layer 4 CRC check result has no error is to be performed the display of the information. Power ON RST pin “L” After crystal was oscillated and stabilized, and the supply voltage (VDD) become 2.5V or more, set the RST pin “L” level for 300ns or more RST pin “H” Reception Frame Setting When Method-A or Method-A’ is used, this setting is needed. (Details are described in the following pages.) Output Mode Setting When the error corrected data output format is changed, this setting is needed. (Details are described in the following pages.) CPU I/F Setting Corrected Data Read Data Group Complete? When the CPU I/F is changed, this setting is needed. DO pin output format RDY signal timing, etc. Details are described in the following pages No Yes Layer 4 CRC Check Details are described in the following pages Layer 4 CRC No Error? No Yes Display-related Processing 20131112V101E 22/42 LC72717PW Application Note Reception Frame Setting Frame Selection Method-A Method-A’ Method-B (Japan, China, etc.) Method-C Method-A Frame Selection Method-A’ Control Register Value (Default) FRAME=0 RTIB=0 Control Register Setting Control Register Setting FRAME=1 FRAME=1 RTIB=1 Reception Frame Setting Complete Output Mode Setting the others The data output formats of the each setting are described in “List of Operation Modes” chapter. Output Mode Selec Control Register Mode 1 Value (Default) INT_MOVE=0 Control Register VEC_OUT=0 Setting INT_MOVE=1 VEC_OUT=1 Mode 2 Mode 3 Control Register Setting Control Register Setting INT_MOVE=1 VEC_OUT=0 INT_MOVE=0 VEC_OUT=1 Output Mode Setting Complete 20131112V101E 23/42 LC72717PW Application Note Layer 4 CRC check method (Hardware) To perform layer 4 CRC check, transmit the data group to be checked. After transmission, it is determined that the data group is free from error if the CRC4 pin becomes the H-level output or the status register CRC4 (layer 4 CRC check result) is ‘1’. The CRC4 pin or CRC4 flag of status register is either “H” or “1” when all bits of check register in LSI are “0”. To perform layer 4 CRC check using this function, it is necessary to initialize the CRC check register in LSI before transmission of one data group. Initialization is made by setting the CRC4_RST (layer 4 CRC check circuit reset) of control register to ‘1’. Subsequently, to transmit the layer 4 CRC check data, set CRC4_RST back to 0 to cancel reset. The generating polynomial of CRC code is as follows: G(X) = X16 + X12 + X5 + 1 Layer 4 CRC Check CRC Check Register Reset “ON” CRC4_RST=1 CRC Check Register Reset “OFF” CRC4_RST=0 Data Group Data Write INT signal Negative Edge? Yes No At the falling edge of the INT signal, status register value is updated. Status Read Confirm CRC4 Flag CRC4=1 (No Error) CRC4=0 (Error) Layer 4 CRC Check Complete 20131112V101E 24/42 LC72717PW Application Note Serial Interface (CCB) CCB (Computer Control Bus), which is the serial bus format, performs data input and output. The CCB address is transmitted with CE= “L”, acknowledging the CCB I/O mode when CE is set to “H”. To use the CCB interface, SP pin is to be set to “H”. List of CCB Modes CCB address I/O mode FAh 0 1 0 1 1 1 1 1 Input FBh 1 1 0 1 1 1 1 1 Output FCh 0 0 1 1 1 1 1 1 Input FDh 1 0 1 1 1 1 1 1 Output Description Write registers Read error corrected data Write data for layer 4 CRC check Read registers (1) Write registers (CCB address FAh) This is to set data to the LSI internal register. DI input includes both CCB address FAh and 16-bit data (DI0 to DI15) are input. Assignment of each bit is as shown in the table below. Though DI12 to DI15 are reserved data, it is necessary to enter the “0” or “1” so that the total of 16 bits can be obtained. DI0 DI1 DI2 DI3 (LSB) DI4 DI5 Input data 8bits DI6 DI7 (MSB) tEL DI8 DI9 DI10 DI11 Register address DI12 - DI15 Reserved tES CE tCL tCH tEH CL tSU tHD DI DI0 DI1 DI13 DI14 DI15 List of write registers Address R/W Register Name Description 0h - - 1h W BIC 2h W SYNCB Block synchronization: error protection count 3h W SYNCF Frame synchronization: error protection count 4h W CTL1 Control register 1 5h W CTL2 Control register 2 6h and beyond - - Reserved (setting prohibited) Allowable number of BIC errors Reserved (setting prohibited) 1h <BIC>: Number of allowable BIC errors <Write Only> Register to set the allowable number of BIC error bits for determination of synchronization Address Register Name Bit Name 1h BIC 7-4 BIC_F Description Forward protection value (initial value 2) Sets the allowable number of BIC error bits (when synchronized). 3-0 BIC_B Backward protection value (initial value 2) Sets the number of allowable BIC error bits (when not synchronized). Reset 0010b 0010b When the block synchronization determination output (BLOCK) is to be used determination of whether or not there is any FM multiplex data, it is recommended to set the allowable number of BIC errors during backward protection to ‘0001b’ or ‘0000b’. 20131112V101E 25/42 LC72717PW Application Note 2h <SYNCB>: Block synchronization: error protection count <Write Only> Register to set the number of block synchronization protections for determination of block synchronization. Address Register Name Bit Name Description 2h SYNCB 7-4 SYNCB_B Backward protection value (Register initial value 1: Number of backward protections 2) Number of backward protections = Backward protection value +1 3-0 SYNCB_F Forward protection value (Register initial value 7: Number of forward protections 8) Number of forward protections = Forward protection value +1 Reset 0001b 0111b To change the set value, it is necessary to set the value determined by deducting 1 from the desired number of protections. The number of forward and backward protections can be set separately. The conditions for counting the number of protections are as follows: Number of backward protections (not synchronized): BLOCK=L) When the timing of the free-run counter for LSI internal synchronization agrees with that of received BIC, the protection counter is incremented by 1. Similarly, when the timing between the LSI internal counter and the received BIC is lost, the protection counter is cleared to zero. The count timing is the timing of the LSI internal counter. Number of forward protections (synchronized: BLOCK=H) Contrarily to the case of backward protection, the number of protections is counted up when the timing of LSI internal free-run counter is deviated from the received BIC detection timing. The number of protections is cleared to zero when they agree. The figure below shows the agreement/disagreement between the LSI internal timing and received BIC timing and the relationship between the protection counter value and BLOCK signal. For the number of forward/backward protections of 3, the protection counter value at a timing of BLOCK signal changeover is 2, that is, smaller by 1. The number of protections is determined in the internal circuit by comparing the register set value for the number of forward/backward protections and the protection counter. Accordingly, the register set value must be set to the value smaller than the desired number of protections by 1. For example, when the number of both forward and backward protections is 3 as shown below, it is necessary to set ‘22h’. If the set value is ‘00h’, the number of protections becomes 1 by definition for forward and backward protections. However, the operation becomes the same as for the state without the protection circuit. When the block synchronization flag output (BLOCK) is to be used for determination whether or not there is FM multiplex data, it is recommended to reset the value severer than the initial value. BIC Received data 1 2 3 Reset BIC position of synchronization counter 0 Protection counter 1 2 BLOCK 0 3 2 1 1 2 0 1 0 For the register set value of 22h: the number of both the forward and backward protections become 3. 3h <SYNCF>: Frame synchronization: error protection count <Write Only> Register to set the number of frame synchronization protections for determination of frame synchronization Address Register Name Bit Name 3h SYNCF 7-4 SYNCF_B Description Reset Backward protection value (Register initial value 1: Number of backward protections 2) 0001b Number of backward protections = Backward protection value +1 3-0 SYNCF_F Forward protection value (Register initial value 7: Number of forward protections 8) 0111b Number of forward protections = Forward protection value +1 To change the set value, it is necessary to set the value determined by deducting 1 from the desired number of protections. This LSI detects BIC peculiar change points exist at four points in one frame and increases/decreases the counts of protection counter by determining agreement/disagreement with the timing counter for LSI internal frame synchronization. 20131112V101E 26/42 LC72717PW Application Note 4h <CTL1>: Control register 1 <Write Only> Register to control the block reset ON/OFF, function activation/stop, and the data output method. Address Register Name Bit Name 4h CTL1 7 CRC4_RST Description Reset Layer 4 CRC check circuit reset setting 1: Reset ON 0: Reset OFF 0 To cancel reset, it is necessary to set 0. 6 D O _MOVE Sets the D O pin output method changeover 0: Hi-Z state retained in states other than data output 0 1: Changes in an interlocked manner with the INT signal *6 5 INT_MOVE Sets changeover of corrected data output method *4 0: Outputs only data received at completion of correction & layer 2 CRC completion as well as during synchronization 0 1: Outputs all of data 4 SYNC_RST Synchronization regeneration circuit reset setting *1 1: Reset ON 0: Reset OFF 0 0 to be set to cancel reset 3 EC_STOP Error correction function down setting *2 0: All functions activated 0 1: Only MSK detector circuit and synchronization regeneration circuit activated 2 VEC_HALT Vertical error correction function down function *3 0: Executes vertical error correction and second horizontal correction. 0 1: Does not execute vertical error correction and second horizontal correction. 1 RTIB Real-time information block setting *5 0 0: Real-time information blocks present. 1: No-real-time information block. 0 FRAME Frame setting 0 0: Specifies method B. 1: Specifies method A. *1 With SYNC_RST=1, the synchronization status and the synchronization protection status are cleared, resulting in the unsynchronized state. This function enables rapid pull-in of frame synchronization when the frame synchronization of new tuned and received data is deviated during tuning of a radio receiver. In this case, registers such as the number of allowable BIC errors, the number of block forward/backward protections, and the number of frame forward/backward protections are not initialized. During reset, the INT signal is not output and the DO pin becomes the HI-Z output. *2 With EC_STOP=1, all of operations and data output related to error correction is shut down. MSK demodulation, synchronization circuits, serial data input, and layer 4 CRC circuit remain operative. *3 With VEC_HALT=1 setting, all of LSI operation related to vertical correction and second horizontal correction are shut down. Only the data after first horizontal correction is output. *4 Since the output mode will be modified depending on the setting of the VEC_OUT flag or the result of horizontal error correction, refer to the “List of operation modes” section for detail. *5 In the ITU-R recommended frame structure method A, a total of 12 data blocks can be inserted in the parity data area (the area that consists of 82 consecutive blocks of parity packets). If this IC is used in a system that has no real-time information blocks (RTIB), this flag must be set. Note that if this flag is changed, frame synchronization is retained in the synchronized state for the time corresponding to the forward protection count, and then switches to the unsynchronized state. To quickly reestablish frame synchronization, applications must reset the synchronization circuit using the SYNC_RST flag. *6 About the relationship between INT and DO, refer to the “Output Format with DO_MOVE=1”section in the “Error Correction” chapter. 20131112V101E 27/42 LC72717PW Application Note 5h <CTL2>: Control register 2 <Write Only> Register to control the parallel IF setting, vertically-corrected data output method, etc. address Register Name Bit Name 5h CTL2 7 Reserved Either keep an initial value or set it to 0. Description 6 BLK_RST Block synchronization circuit reset setting *1 1: Reset ON 0: Reset OFF Reset 0 0 0 to be set to cancel reset 5 DACK DACK signal polarity setting (effective for SP=L only) 0: Negative logic for DACK signal polarity 0 1: Positive logic for DACK signal polarity 4 DREQ DREQ signal polarity setting (effective for SP=L only) 0: Negative logic for DREQ signal polarity 0 1: Positive logic for DREQ signal polarity 3 RDY RDY signal timing setting (effective for SP=L only) 0: Outputs the RDY signal in the timing 1. 0 1: Outputs the RDY signal in the timing 2. 2 VEC_OUT Vertically error corrected data output method changeover setting *2 0: No vertically error corrected output if vertical error correction has not been made 0 1: All data output even when vertical error correction has not been made 1 DMA_RD DMA read control signal selection setting (effective for SP=L only) 0: RD signal used 0 1: DACK signal used 0 DMA DMA transmission function enable setting (effective for SP=L only) 0: DMA transmission not used for reading of corrected data 0 1: DMA transmission used for reading of corrected data *1 With BLK_RST=1, the block synchronization state and block synchronization protection counter value are cleared. But this does not affect the functions related to frame synchronization. *2 With VEC_OUT=1, one frame of data completely free from error. The data similar to the horizontally-corrected data is output in the timing of output of vertically-corrected data even when vertical correction has not been made. 20131112V101E 28/42 LC72717PW Application Note (2)Read registers This is the dedicated register that can read only the status register (STAT) and block number register (BLNO) in LSI. To DI, the CCB address (Fad) is input. Data is output in order of the status register and the block number register. DO0 to DO7 DO8 to DO15 STAT (8) BLNO (8) tEL tES CE tCH tEH tCL CL tSU tHD DI tDDO DO DO0 tDDO2 DO1 DO2 DO13 DO14 DO15 <STAT>: Status register <Read Only> Register to confirm various states Address Register Name Bit Name 1h STAT 7 VH Description Reset Determination on vertically error corrected data 0: Data for which only horizontal correction is performed 1: Data for which vertical and second horizontal correction after horizontal correction 0 are performed 6 BLK Block synchronization state 0: Data that is received when block synchronization is not established 0 1: Data that is received when block synchronization is established 5 FRM Frame synchronization state 0: Data that is received when frame synchronization is not established 0 1: Data that is received when frame synchronization is established 4 ERR Error correction state 0: Data whose correction is completed and for which error is not detected by the layer 2 CRC check 0 1: Data whose correction is impossible or for which error is detected by the layer 2 CRC check. 3 PRI Determination of parity block 0: Data that is estimated to be data block by the frame synchronization circuit 0 1: Data that is estimated to be parity block by the frame synchronization circuit 2 HEAD Frame head determination 1: Data that is estimated to be the frame head block by the frame synchronization circuit 0 0: Data other than above 1 CRC4 Layer 4 CRC check result 0: Error in layer 4 CRC check result 1 1: No error in layer 4 CRC check result 0 RTIB Real-time information block state 0 1: Indicates the data is a real-time information block.(This bit is valid only in method A’.) 0: The others The value in the “Reset” column is the readable value immediately after canceling the reset. <BLNO>: Block Number register <Read Only> Register to confirm the output data block Number Address Register Name Bit Name 2h BLNO 7 BLN7 Description 6 BLN6 5 BLN5 4 BLN4 0 3 BLN3 0 2 BLN2 0 1 BLN1 0 0 BLN0 0 Indicates the block Number or parity block Number of output data Reset 0 0 Data block Number 0 to 189 Parity block Number 0 to 81 0 The value in the “Reset” column is the readable value immediately after canceling the reset. 20131112V101E 29/42 LC72717PW Application Note The timing for rewriting of read register (STAT, BLNO) data is the timing for changing of INT from H to L. It is possible to read the register in a manner a synchronous with the interrupt signal when INT_MOVE is set to “1”. For example, to check the current receiving state, read the status register to check BLK (data received during block synchronization) and FRM (data received during frame synchronization). In this case, read data is more close to the current receiving state, when VH=0 (data subject to horizontal correction only) information is used. (3) Read error corrected data (CCB address FBh) The corrected packet data is output from LSI. The CCB address, FBh, is input in DI. The valid data to be output is maximum 288 bits. If the clock input (CL input) is interrupted halfway to set CE to the “L” level, data output is not troubled by the next interrupt. The maximum data to be output is 288 bits (36 bytes) and the leading two bytes, to which the status register (STAT) contents and the block number register (BLNO) contents are added, are output. STAT and BLNO, which are the register contents outputs, are output respectively with LSB first. The corrected data is output sequentially beginning with the leading bit in data of one block. The BIC code is not output. Data reading for one times by one interrupt signal (INT) is possible, but for two times is impossible. DO0 to DO7 DO8 to DO15 DO16 STAT (8) BLN0 (8) Data block (176) DO191 DO192 to DO205 DO206 to DO287 Error-corrected data Layer 2 CRC (14) Parity (82) to tEL tES CE tCH tEH tCL CL tSU tHD DI tDDO DO0 DO 20131112V101E DO1 tDDO2 DO2 DO285 DO286 DO287 30/42 LC72717PW Application Note (4) Write data for layer 4 CRC check (CCB address FCh) This is a function to detect the error in the data group (Layer 4 CRC), transmitting the data group of specified number of bytes, via the CCB interface, to LSI. The CCB address is FCh. In this case, it is not necessary to send register address. The length of data group to be transmitted is on the 8-bit units. Here is not any upper limit (such as N pieces in the figure below) for the length of data to be transmitted at a time and data transmission can be divided into multiple times. The data transmission is performed at a time Layer 4 data group Data group header SOH DI0 DI1 Data group data DI2 to DI(N-2) END CRC END CRC DI(N-1) The data transmission is divided into two times. Layer 4 data group SOH DI0 Data group header DI2 to Data group data DI(N-1) DI0 DI2 to DI(N-1) tES tEL CE tCH tCL tEH CL tSU tHD DI DI0 DI1 DI (N-1) tCRC CRC4 pin output Note: The number of Ns must be on the 8-bit units. Symbol Parameter min typ max unit tCL Clock “L” level time 0.7 s tCH Clock “H” level time 0.7 s tSU Data setup time 0.7 s tHD Data hold time 0.7 s tEL CE wait time 0.7 s tES CE setup time 0.7 s tEH CE hold time 0.7 tDDO*1 DO data output time 135 TDDO2 DO data output off time 135 tCRC CRC4 change period Output after transmission of N pieces s 320 ns 0.7 s ns *1 DO data output change time from the “H” level to the “L” level. Output change time from the “L” level to the “H” level is determined by the external pull-up resistance value and load capacitance value. 20131112V101E 31/42 LC72717PW Application Note Parallel Interface This LSI can perform control via the parallel interface, in addition to the CCB interface. To use the parallel interface, it is necessary to set the SP pin = L. The data bus width can be selected with the BUSWD pin. (BUSWD pin - L: 8 bits, H: 16 bits) (1)Write Registers List of write registers Address R/W Register Name Description 0h - - 1h W BIC 2h W SYNCB Block synchronization: error protection count 3h W SYNCF Frame synchronization: error protection count 4h W CTL1 Control register 1 5h W CTL2 Control register 2 6h W CRC4 Layer 4 CRC register 7h and beyond - - Reserved (setting prohibited) Allowable number of BIC errors Reserved (setting prohibited) Data is set to the register in LSI. For accessing, input the register address to A0 to A3 pins and the write data to the D(n) pin. Set the CS pin = L, and then the WR pin = L. Subsequently, by setting the WR pin = H and the CS pin = H after the tWWRL period, the data can be set to the register. It is necessary to keep an interval of tCYWR or more before the next data input. tWWRL tSAWR tHAWR A0 to A3 CS tCYWR WR tWDH tWDS D(n) 1h <BIC>: Number of allowable BIC errors <Write Only> Register to set the allowable number of BIC error bits for determination of synchronization Address Register Name Bit Name 1h BIC 7-4 BIC_F Description Forward protection value (initial value 2) Sets the allowable number of BIC error bits (when synchronized). 3-0 BIC_B Backward protection value (initial value 2) Sets the number of allowable BIC error bits (when not synchronized). Reset 0010b 0010b When the block synchronization determination output (BLOCK) is to be used determination of whether or not there is any FM multiplex data, it is recommended to set the allowable number of BIC errors during backward protection to ‘0001b’ or ‘0000b’. 20131112V101E 32/42 LC72717PW Application Note 2h <SYNCB>: Block synchronization: error protection count <Write Only> Register to set the number of block synchronization protections for determination of block synchronization. Address Register Name Bit Name Description 2h SYNCB 7-4 SYNCB_B Backward protection value (Register initial value 1: Number of backward protections 2) Number of backward protections = Backward protection value +1 3-0 SYNCB_F Forward protection value (Register initial value 7: Number of forward protections 8) Number of forward protections = Forward protection value +1 Reset 0001b 0111b To change the set value, it is necessary to set the value determined by deducting 1 from the desired number of protections. The number of forward and backward protections can be set separately. The conditions for counting the number of protections are as follows: Number of backward protections (not synchronized): BLOCK=L) When the timing of the free-run counter for LSI internal synchronization agrees with that of received BIC, the protection counter is incremented by 1. Similarly, when the timing between the LSI internal counter and the received BIC is lost, the protection counter is cleared to zero. The count timing is the timing of the LSI internal counter. Number of forward protections (synchronized: BLOCK=H) Contrarily to the case of backward protection, the number of protections is counted up when the timing of LSI internal free-run counter is deviated from the received BIC detection timing. The number of protections is cleared to zero when they agree. The figure below shows the agreement/disagreement between the LSI internal timing and received BIC timing and the relationship between the protection counter value and BLOCK signal. For the number of forward/backward protections of 3, the protection counter value at a timing of BLOCK signal changeover is 2, that is, smaller by 1. The number of protections is determined in the internal circuit by comparing the register set value for the number of forward/backward protections and the protection counter. Accordingly, the register set value must be set to the value smaller than the desired number of protections by 1. For example, when the number of both forward and backward protections is 3 as shown below, it is necessary to set ‘22h’. If the set value is ‘00h’, the number of protections becomes 1 by definition for forward and backward protections. However, the operation becomes the same as for the state without the protection circuit. When the block synchronization flag output (BLOCK) is to be used for determination whether or not there is FM multiplex data, it is recommended to reset the value severer than the initial value. BIC Received data 1 2 3 Reset BIC position of synchronization counter 0 Protection counter 1 2 BLOCK 0 3 2 1 1 2 0 1 0 For the register set value of 22h: the number of both the forward and backward protections become 3. 3h <SYNCF>: Frame synchronization: error protection count <Write Only> Register to set the number of frame synchronization protections for determination of frame synchronization Address Register Name Bit Name 3h SYNCF 7-4 SYNCF_B Description Reset Backward protection value (Register initial value 1: Number of backward protections 2) 0001b Number of backward protections = Backward protection value +1 3-0 SYNCF_F Forward protection value (Register initial value 7: Number of forward protections 8) 0111b Number of forward protections = Forward protection value +1 To change the set value, it is necessary to set the value determined by deducting 1 from the desired number of protections. This LSI detects BIC peculiar change points exist at four points in one frame and increases/decreases the counts of protection counter by determining agreement/disagreement with the timing counter for LSI internal frame synchronization. 20131112V101E 33/42 LC72717PW Application Note 4h <CTL1>: Control register 1 <Write Only> Register to control the block reset ON/OFF, function activation/stop, and the data output method. Address Register Name Bit Name 4h CTL1 7 CRC4_RST Description Reset Layer 4 CRC check circuit reset setting 1: Reset ON 0: Reset OFF 0 To cancel reset, it is necessary to set 0. 6 D O _MOVE Sets the D O pin output method changeover 0: Hi-Z state retained in states other than data output 0 1: Changes in an interlocked manner with the INT signal *6 5 INT_MOVE Sets changeover of corrected data output method *4 0: Outputs only data received at completion of correction & layer 2 CRC completion as well as during synchronization 0 1: Outputs all of data 4 SYNC_RST Synchronization regeneration circuit reset setting *1 1: Reset ON 0: Reset OFF 0 0 to be set to cancel reset 3 EC_STOP Error correction function down setting *2 0: All functions activated 0 1: Only MSK detector circuit and synchronization regeneration circuit activated 2 VEC_HALT Vertical error correction function down function *3 0: Executes vertical error correction and second horizontal correction. 0 1: Does not execute vertical error correction and second horizontal correction. 1 RTIB Real-time information block setting *5 0 0: Real-time information blocks present. 1: No-real-time information block. 0 FRAME Frame setting 0 0: Specifies method B. 1: Specifies method A. *1 With SYNC_RST=1, the synchronization status and the synchronization protection status are cleared, resulting in the unsynchronized state. This function enables rapid pull-in of frame synchronization when the frame synchronization of new tuned and received data is deviated during tuning of a radio receiver. In this case, registers such as the number of allowable BIC errors, the number of block forward/backward protections, and the number of frame forward/backward protections are not initialized. During reset, the INT signal is not output and the DO pin becomes the HI-Z output. *2 With EC_STOP=1, all of operations and data output related to error correction is shut down. MSK demodulation, synchronization circuits, serial data input, and layer 4 CRC circuit remain operative. *3 With VEC_HALT=1 setting, all of LSI operation related to vertical correction and second horizontal correction are shut down. Only the data after first horizontal correction is output. *4 Since the output mode will be modified depending on the setting of the VEC_OUT flag or the result of horizontal error correction, refer to the “List of operation modes” section for detail. *5 In the ITU-R recommended frame structure method A, a total of 12 data blocks can be inserted in the parity data area (the area that consists of 82 consecutive blocks of parity packets). If this IC is used ina system that has no real-time information blocks (RTIB), this flag must be set. Note that if this flag is changed, frame synchronization is retained in the synchronized state for the time corresponding to the forward protection count, and then switches to the unsynchronized state. To quickly reestablish frame synchronization, applications must reset the synchronization circuit using the SYNC_RST flag. *6 About the relationship between INT and DO, refer to the “Output Format with DO_MOVE=1”section in the “Error Correction” chapter. 20131112V101E 34/42 LC72717PW Application Note 5h <CTL2>: Control register 2 <Write Only> Register to control the parallel IF setting, vertically-corrected data output method, etc. Address Register Name Bit Name 5h CTL2 7 Reserved Either keep an initial value or set it to 0. Description 6 BLK_RST Block synchronization circuit reset setting *1 1: Reset ON Reset 0 0: Reset OFF 0 0 to be set to cancel reset 5 DACK DACK signal polarity setting (effective for SP=L only) 0: Negative logic for DACK signal polarity 0 1: Positive logic for DACK signal polarity 4 DREQ DREQ signal polarity setting (effective for SP=L only) 0: Negative logic for DREQ signal polarity 0 1: Positive logic for DREQ signal polarity 3 RDY RDY signal timing setting (effective for SP=L only) 0: Outputs the RDY signal in the timing 1. 0 1: Outputs the RDY signal in the timing 2. 2 VEC_OUT Vertically error corrected data output method changeover setting *2 0: No vertically error corrected output if vertical error correction has not been made 0 1: All data output even when vertical error correction has not been made 1 DMA_RD DMA read control signal selection setting (effective for SP=L only) 0: RD signal used 0 1: DACK signal used 0 DMA DMA transmission function enable setting (effective for SP=L only) 0: DMA transmission not used for reading of corrected data 0 1: DMA transmission used for reading of corrected data *1 With BLK_RST=1, the block synchronization state and block synchronization protection counter value are cleared. But this does not affect the functions related to frame synchronization. *2 With VEC_OUT=1, one frame of data completely free from error. The data similar to the horizontally-corrected data is output in the timing of output of vertically-corrected data even when vertical correction has not been made. (2) Write data for layer 4 CRC check This is a function to detect the error in the data group (Layer 4 CRC), transmitting the data group of specified number of bytes, via the parallel interface, to LSI. The length of data group to be transmitted is on the 8-bit units. Here is not any upper limit (such as N pieces in the figure below) for the length of data to be transmitted at a time. tSAWR tWWRL tHAWR A0 to A3 CS tCYWR WR tWDS tWDH D(n) 20131112V101E 35/42 LC72717PW Application Note 6h <CRC4>: Layer 4 CRC register <Write Only> Register for data group writing to check the layer 4 CRC. Address Register Name Bit Name Description 6h CRC4 7-0 CRCDAT Reset Layer 4 CRC check data setting By writing value consecutively into this register, the layer 4 CRC check of data group comprising multiple bytes can be made. 00h The CRC checked results can be known by checking the CRC4 flag in th e status register or CRC4 pin output. Layer 4 Data Group (N bytes) b1 b8 b9 SOH b24 b8*N Data group header Data group data END CRC Number D7 D6 D5 D4 D3 D2 D1 D0 of writes 20131112V101E 1 SOH (b8 - b1) 2 Data group header (b16 - b9) 3 Data group header (b24 - b17) 4 Data group header (b32 - b25) N-2 END N-1 CRC N CRC 36/42 LC72717PW Application Note (3)Read registers List of read registers Address R/W Register Name Description 0h R PDATO 1h R STAT Status register 2h R BLNO Block number register 3h and beyond - - Error-corrected data Reserved This is to read data from the register in LSI. Only the status register (STAT) and block number register (BLNO) in LSI can be read. For accessing, input the register address in A0 to A3, set the CS pin = L, and then the RD pin = L. This causes the RDY pin to change from “H” to “L”. Then, data is output from the D(n) pin after the RDY pin becomes “H”. It is necessary to keep an interval of tCYRD or more before the next data output. (n: 0-7 for BUSWD=L and 0 – 15 for BUSWD=H.) By setting bit 3 (RDY) = 1 of the control register 2, the RDY pin output method can be changed. In this case, the RDY pin changes from “H” to “L” in the timing enabling output of the acquired data and the pin returns to “H” after the end of data output (shown as Timing 2 in the figure). tSARD tWRDL tHARD A0 to A3 CS tCYRD RD tDRDY tWRDY RDY (Timing1: default) tDRDY2 tDRDY+tWRDY RDY (Timing2) tRDH VALID OUTPUT D(n) tDATON 20131112V101E tDDATn 37/42 LC72717PW Application Note 1h <STAT>: Status register <Read Only> Register to confirm various states Address Register Name Bit Name 1h STAT 7 VH Description Reset Determination on vertically error corrected data 0: Data for which only horizontal correction is performed 1: Data for which vertical and second horizontal correction after horizontal correction 0 are performed 6 BLK Block synchronization state 0: Data that is received when block synchronization is not established 0 1: Data that is received when block synchronization is established 5 FRM Frame synchronization state 0: Data that is received when frame synchronization is not established 0 1: Data that is received when frame synchronization is established 4 ERR Error correction state 0: Data whose correction is completed and for which error is not detected by the layer 2 CRC check 0 1: Data whose correction is impossible or for which error is detected by the layer 2 CRC check. 3 PRI Determination of parity block 0: Data that is estimated to be data block by the frame synchronization circuit 0 1: Data that is estimated to be parity block by the frame synchronization circuit 2 HEAD Frame head determination 1: Data that is estimated to be the frame head block by the frame synchronization circuit 0 0: Data other than above 1 CRC4 Layer 4 CRC check result 0: Error in layer 4 CRC check result 1 1: No error in layer 4 CRC check result 0 RTIB Real-time information block state 0 1: Indicates the data is a real-time information block.(This bit is valid only in method A’.) 0: The others The value in the “Reset” column is the readable value immediately after canceling the reset. 2h <BLNO>: Block Number register <Read Only> Register to confirm the output data block Number Address Register Name Bit Name 2h BLNO 7 BLN7 6 BLN6 Description Indicates the block Number or parity block Number of output data Reset 0 0 Data block Number 0 to 189 Parity block Number 0 to 81 5 BLN5 4 BLN4 0 0 3 BLN3 0 2 BLN2 0 1 BLN1 0 0 BLN0 0 The value in the “Reset” column is the readable value immediately after canceling the reset. The timing for rewriting of read register (STAT, BLNO) data is the timing for changing of INT from H to L. It is possible to read the register in a manner a synchronous with the interrupt signal when INT_MOVE is set to “1”. For example, to check the current receiving state, read the status register to check BLK (data received during block synchronization) and FRM (data received during frame synchronization). In this case, read data is more close to the current receiving state, when VH=0 (data subject to horizontal correction only) information is used. 20131112V101E 38/42 LC72717PW Application Note (4) Read error corrected data This is to output the packet data after correction processing from LSI. The total length of output data is 176 bits (22 Bytes) only, and the Layer 2 CRC data (14 bits) and parity data (82 bits) are not output. The corrected data is output, on either the 8-bit or 16-bit units, sequentially from the leading data among those in one packet. The BIC code is not output. The accessing method is the same as for the register output and the address “0” is input to A0 to A3 pins. Since this is different from the register output in the timing conditions during access, the timing chart is shown here separately from the register output. The RDY signal output method can also be selected similarly. tWDRD tSARD tHARD A0 to A3 CS tCYRD RD tDRDY tWDRDY RDY (Timing1: default) tDRDY+tWRDY tDRDY2 RDY (Timing2) tRDH VALID OUTPUT VALID OUTPUT D(n) tDATON tDDATn * A0 to A3 should be set to 0 during reading of corrected data. 0h <PDATO>: Error-corrected data <Read Only> Register to read the error-corrected data. Address Register Name Bit Name 0h PDATO 7-0 PDATO Description Reset Error-corrected data By reading value consecutively from this register, the error corrected data can be output. 00h With 8-bit mode (BUSWD=L) , 22 times of read access is necessary, With 16-bit mode (BUSWD=H), 11 times of read access is necessary. b1b2 b175b176 Data block (176 bits) Data after error correction Layer 2 CRC (14 bits) Parity (82 bits) Structure of a Single Data Packet (Total length 272 bits: BIC not included) 20131112V101E 39/42 LC72717PW Application Note With 8-bit mode Number of D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 reads 1 Error corrected data (b8 - b1) 2 Error corrected data (b16 - b9) 3 Error corrected data (b24 - b17) 20 Error corrected data (b160 - b153) 21 Error corrected data (b168 - b161) 22 Error corrected data (b176 - b169) With 16-bit mode Number of D15 D14 D13 D12 D7 D6 D5 D4 D3 D2 D1 D0 reads 1 Error corrected data (b16 - b9) Error corrected data (b8 - b1) 2 Error corrected data (b32 - b25) Error corrected data (b24 - b17) 10 Error corrected data (b160 - b153) Error corrected data (b152 - b145) 11 Error corrected data (b176 - b169) Error corrected data (b168 - b161) 20131112V101E 40/42 LC72717PW Application Note Symbol tSARD tHARD *1 Parameter Address and CS to RD setup RD to address and CS hold min typ max unit 20 ns 0 ns tWRDL RD “L” level width 340 ns tCYRD RD cycle wait 150 ns tWRDY RDY width (at register output) tRDH RD data hold 60 210 ns 0 40 ns tSAWR Address and CS to WR setup 20 ns tHAWR WR to address and CS hold 20 ns tCYWR WR cycle wait WR cycle wait(When writing data in Layer 4CRC register) tWWRL WR “L” level width 150 ns 1200 ns 200 ns ns tWDS WR data setup 0 tWDH WR data hold 20 tDRDY RDY output delay 0 40 ns tDRDY2 RDY output delay 2 0 40 ns tWDRD RD width at output of corrected data BUSWD=L (8bit) RD width at output of corrected data BUSWD=H (16bit) tWDRDY RDY width at output of corrected data BUSWD=L (8bit) RDY width at output of corrected data BUSWD=H (16bit) ns 340 ns 620 ns 60 210 ns 300 490 ns tDATON DATn output start time 0 40 ns tDDATn DATn output delay 0 40 ns *1 Specified up to the earliest negating of A0 to A3 and CS 20131112V101E 41/42 LC72717PW Application Note ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any licenseunder its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 20131112V101E 42/42