TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP720 The SP720 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection to sensitive input circuits. The SP720 has 2 protection SCR/Diode device structures per input. A total of 14 available inputs can be used to protect up to 14 external signal or bus lines. Over-voltage protection is from the IN (pins 1-7 and 9-15) to V+ or V-. The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ (Pin 16) or a -VBE diode threshold below V- (Pin 8). From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input. Standard ESD Human Body Model (HBM) Capability is: HBM STANDARD IEC 61000-4-2 MIL-STD-3015.7 MODE R C ESD (V) Air 330Ω 150pF >15kV Direct 330Ω 150pF >4kV Direct, Dual Pins 330Ω 150pF >8kV Direct, In-circuit 1.5kΩ 100pF >15kV Refer to Figure 1 and Table 1 for further detail. Refer to Application Note AN9304 and AN9612 for additional information. Ordering Information PART NO. TEMP. RANGE (oC) PACKAGE PKG. NO. Min. Order SP720AP -40 to 105 16 Ld PDIP E16.3 1500 SP720AB -40 to 105 16 Ld SOIC M16.15 1970 SP720ABT -40 to 105 16 Ld SOIC Tape and Reel M16.15 2500 Features • ESD Interface Capability for HBM Standards - MIL STD 3015.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV - IEC 61000-4-2, Direct Discharge, Single Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2) Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4) - IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . 15kV (Level 4) • High Peak Current Capability - IEC 61000-4-5 (8/20µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A - Single Pulse, 100µs Pulse Width. . . . . . . . . . . . . . . . . . . . . . . ±2A - Single Pulse, 4µs Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . ±5A • Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . +30V - Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime • Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25oC (Typ) • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF (Typ) • An Array of 14 SCR/Diode Pairs • Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40oC to 105oC Pinout SP720 (PDIP, SOIC) Applications • Microprocessor/Logic Input Protection TOP VIEW • Data Bus Protection 228 IN 1 16 V+ IN 2 15 IN IN 3 14 IN IN 4 13 IN IN 5 12 IN IN 6 11 IN IN 7 10 IN V- 8 9 IN • Analog Device Input Protection • Voltage Clamp Functional Block Diagram V+ 16 IN w w w. l i t t e l f u s e . c o m IN 1 V- 8 2 3-7 9 - 15 IN TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP720 Absolute Maximum Ratings Thermal Information Continuous Supply Voltage, (V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . +35V Forward Peak Current, IIN to VCC, IIN to GND (Refer to Figure 6) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2A, 100µs ESD Ratings and Capability (Figure 1, Table 1) Load Dump and Reverse Battery (Note 2) Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . . . . . . θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Storage Temperature Range . . . .. . . . . . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . .. . . . . . .. . . . . . . . . .300oC (SOIC Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = -40oC to 105oC; VIN = 0.5VCC , Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 2 to 30 - V VSUPPLY Forward Voltage Drop: IN to VIN to V+ VFWDL VFWDH - 2 2 - V V Input Leakage Current IIN -20 5 20 nA IQUIESCENT - 50 200 nA Quiescent Supply Current IIN = 1A (Peak Pulse) Equivalent SCR ON Threshold Note 3 - 1.1 - V Equivalent SCR ON Resistance VFWD/IFWD; Note 3 - 1 - Ω Input Capacitance CIN - 3 - pF Input Switching Speed tON - 2 - ns 5 NOTES: 2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here for thumb-rule information to determine peak current and dissipation under EOS conditions. TABLE 1. ESD TEST CONDITIONS ESD Capability ESD capability is dependent on the application and defined test standard. The evaluation results for various test standards and methods based on Figure 1 are shown in Table 1. For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit” method of ESD testing, the V+ and V- pins have a return path to ground and the SP720 ESD capability is typically greater than 15kV from 100pF through 1.5kΩ. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing, the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results were determined from AT&T ESD Test Lab measurements. STANDARD TYPE/MODE RD MIL STD 3015.7 Modified HBM IEC 61000-4-2 EIAJ IC121 The HBM capability to the IEC 61000-4-2 standard is greater than 15kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess of 8kV (Level 4). For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than 1kV from 200pF with no series resistance. CD ±VD 1.5kΩ 100pF 15kV Standard HBM 1.5kΩ 100pF HBM, Air Discharge 330Ω 150pF 15kV HBM, Direct Discharge 330Ω 150pF 4kV HBM, Direct Discharge, Two Parallel Input Pins 330Ω 150pF 8kV Machine Model 0kΩ 1kV R1 200pF 6kV RD CHARGE SWITCH DISCHARGE SWITCH CD H.V. SUPPLY °±VD IN DUT IEC 1000-4-2: R 1 50 to 100MΩ MIL STD 3015.7: R 1 1 to 10MΩ FIGURE 1. ELECTROSTATIC DISCHARGE TEST w w w. l i t t e l f u s e . c o m 229 TVS DIODE ARRAYS PARAMETER Operating Voltage Range, VSUPPLY = [(V+) - (V-)] TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP720 100 2.5 TA = 25oC SINGLE PULSE 2 FORWARD SCR CURRENT (A) FORWARD SCR CURRENT (mA) 80 TA = 25oC SINGLE PULSE 60 40 20 1.5 1 IFWD EQUIV. SAT. ON THRESHOLD ~ 1.1V VFWD 0.5 0 600 800 1000 FORWARD SCR VOLTAGE DROP (mV) 1200 FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP CURVE 0 0 1 2 FORWARD SCR VOLTAGE DROP (V) 3 FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP CURVE +VCC +VCC INPUT DRIVERS OR SIGNAL SOURCES LINEAR OR DIGITAL IC INTERFACE IN 1-7 IN 9-15 TO +VCC V+ SP720 V- SP720 INPUT PROTECTION CIRCUIT (1 OF 14 ON CHIP) FIGURE 4. TYPICAL APPLICATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1VBE ABOVE V+ OR LESS THAN -1V BE BELOW V230 w w w. l i t t e l f u s e . c o m TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP720 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP720’s ability to withstand a wide range of transient current pulses. The circuit used to generate current pulses is shown in Figure 5. The overstress curve is shown in Figure 6 for a 15V supply condition. The dual pins are capable of 10A peak current for a 10µs pulse and 4A peak current for a 1ms pulse. The complete for single pulse peak current vs. pulse width time ranging up to 1 second are shown in Figure 6. + VG - The test circuit of Figure 5 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP720 ‘IN’ input pin and the (+) current pulse input goes to the SP720 V- pin. The V+ to V- supply of the SP720 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 6 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. CURRENT SENSE (-) (+) The maximum peak input current capability is dependent on the V+ to Vvoltage supply level, improving as the supply voltage is reduced. Values of 0, 5, 15 and 30 voltages are shown. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in Figure 6. When adjacent input pins are paralleled, the sustained peak current capability is increased to nearly twice that of a single pin. For comparison, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and 14+15. VARIABLETIME DURATION CURRENT PULSE GENERATOR R1 VOLTAGE PROBE R1 ~ 10Ω TYPICAL VG ADJ. 10V/A TYPICAL C1 ~ 100µF 1 IN V+ 16 2 IN IN 15 3 IN IN 14 4 IN IN 13 + C1 SP720 5 IN IN 12 6 IN IN 11 7 IN IN 10 8 V- IN 9 - 5 FIGURE 5. TYPICAL SP720 PEAK CURRENT TEST CIRCUIT WITH A VARIABLE PULSE WIDTH INPUT 10 9 PEAK CURRENT (A) 8 7 CAUTION: SAFE OPERATING CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EACH CURVE. 6 SINGLE PIN STRESS CURVES DUAL PIN STRESS CURVE 5 4 3 15V 0V 5V 2 15V 30V 1 V+ TO V- SUPPLY 0 0.001 0.01 0.1 1 PULSE WIDTH TIME (ms) 10 100 1000 FIGURE 6. SP720 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVER-STRESS IN AMPERES vs PULSE TIME IN MILLISECONDS (TA = 25 oC) w w w. l i t t e l f u s e . c o m 231 TVS DIODE ARRAYS Peak Transient Current Capability of the SP720 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP720 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001 BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE N E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - 0.558 - B 0.014 0.022 0.356 C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 0.355 - C D 0.735 0.775 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 18.66 19.68 5 e 0.100 BSC 2.54 BSC - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. eA 0.300 BSC 7.62 BSC 6 eB - L 0.115 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. N 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 232 w w w. l i t t e l f u s e . c o m 16 0.430 - 0.150 2.93 16 10.92 7 3.81 4 9 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP720 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M INCHES B M SYMBOL E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MAX A1 e µ MIN MILLIMETERS µ 16 0o 16 8o 0o 7 8o - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. w w w. l i t t e l f u s e . c o m 5 TVS DIODE ARRAYS N 233