AN892 D E S I G N G U ID E F O R I S O L A T E D D C / D C U S I N G S I 882 X X / 8 8 3 X X THE 1. Introduction The Si882xx/Si883xx products have integrated digital isolator channels with an isolated dc-dc controller. This application note provides guidance for selecting external components necessary for the operation of the dc-dc controller. Digital isolation applications with primary side supply voltage 3.0 V VIN 5.5 V and load power requirements of ≤ 2 W can use Si882xx/Si883xx products. These products’ dc-dc controller uses the asymmetric half bridge flyback circuit topology. Figure 1 shows the minimum external components required for the asymmetric half bridge flyback. They are a blocking capacitor C1, input capacitor C2, flyback transformer T1, diode D1, output capacitor C10, voltage sense resistors R5 and R6, and compensation network components R7 and C11. Figure 1. Minimum Required External Components Rev. 0.1 4/15 Copyright © 2015 by Silicon Laboratories AN892 AN892 2. Simplified DC Steady State Analysis Analyzing the asymmetric half bridge behavior in DC steady state provides formulas to assist with selecting values for the components used in Figure 1. For this analysis, it is assumed that components are ideal, 100% efficiency (PIN=POUT), and the circuit has reached equilibrium. Figure 2 shows the critical components of the asymmetric half bridge flyback. The transformer model includes magnetizing inductance Lm and inductance leakage Llkg. RLOAD does not necessarily represent a physical resistor, rather it is an expression of VOUT/IOUT. Figure 2. Asymmetric Half Bridge Flyback Converter To analyze this architecture, a cycle can be divided into eight distinct operating modes. However, for DC steady state analysis, the two modes where the system operates the majority of the cycle are only required: when S1 is closed and S2 is open, and when S1 is open and S2 is closed. Figure 3 depicts the simplified magnetizing and leakage inductance current waveforms. Figure 3. Inductor Currents 2 Rev. 0.1 AN892 2.1. S1 Closed, S2 Open VIN is applied to the series combination of C1 and inductance Lm + Llkg. As a result, current flows through inductance Lm + Llkg in a linear fashion. l m RIPPLE V IN – V C1 = L m + L lkg -------------------------t S1 Equation 1. Where Im,RIPPLEis the magnetizing current ramp during tS1 and tS1 is the time that S1 is closed. 2.2. S1 Open, S2 Closed In this mode, a resonant tank circuit formed by C1, Lm, and Llkg, and -VC1 is applied across Lm + Llkg. The resonant tank causes the current through leakage inductance to rise as a sinusoid while the voltage at the secondary impressed on the primary causes the current through the primary to reduce in a linear fashion. When llkg lm, the difference current (Im-Ilkg) flows out of the dot on the primary side of the ideal transformer. Therefore current must flow into the dot on the secondary side and through the diode. Governing current equations are – V OUT l m RIPPLE -------------------------- = ----------------t S2 Lm N Equation 2. I Llkg t = I m sin r t Equation 3. 1 r = ---------------------------L lkg C1 Equation 4. where N and tS2 are primary to secondary turns ratio and time that S2 is closed respectively. r is the resonance tank frequency in rads/s. The current through the diode in the secondary can be written as the difference of llkg and lm scaled by the transformer turns ratio. l lm – I lkg I D1 = --------------------N Equation 5. As the sinusoidal current returns to match the magnetizing current, the resonance ceases and consequently no current will flow from the dot on the primary or through the secondary into the diode. 2.3. Voltage Transfer Let duty cycle D be defined as the ratio of time S1 is closed over the complete switching period TSW: t S1 D = ---------------------t S1 + t S2 Equation 6. Rev. 0.1 3 AN892 Now tS1 and tS2 can be expressed in terms of D and switching period as: t S1 = DT SW Equation 7. t S2 = 1 – D T SW Equation 8. and assume diode D1 has no voltage drop when conducting, the volt-second balance equation for Llkg can be written as: L lkg V OUT ----------------------- V IN – V C1 DT SW + -------------– V C1 1 – D T SW = 0 L lkg + L m N Equation 9. With the condition that Llkg << Lm, Equation 9 simplifies to: V OUT V C1 -------------N Equation 10. The volt-second balance equation for Lm is: V OUT Lm – -------------- 1 – D T SW + ------------------------ V IN – V C1 DT SW = 0 N L lkg + L m Equation 11. With the condition that Llkg<<Lm, Equation 11 simplifies to: V OUT ------------- 1 – D V IN – V C1 D N Equation 12. Substituting Equation 10 into Equation 12 yields the following relationships: V OUT -------------- V IN D N Equation 13. V C1 V IN D Equation 14. 4 Rev. 0.1 AN892 2.4. Magnetizing Current If during the tS1 portion of the cycle (S1 closed, S2 open), VIN charges C1 in a linear fashion. Rearranging Equation 1 and substituting Equation 7 and Equation 14, ripple magnetizing current is: V IN D 1 – D T SW V IN – V C1 t S1 V IN – V IN D t S1 I m RIPPLE = --------------------------------------- = ------------------------------------------ = -------------------------------------------L m + L lkg L m + L lkg L m + L lkg Equation 15. The average magnetizing current is related to the output current as l m AVE = I LOAD N Equation 16. The peak magnetizing current is given by: V IN D 1 – D T SW l m PK = l m AVE + -------------------------------------------2 L m + L lkg Equation 17. Si882xx/Si883xx controller limited the peak magnetizing current to approximately 3A. If more current than 3A is sensed during S1 on and S2 off mode, the controller immediately switches to the S1 off and S2 on mode. The controller maintains the same switching period, but reduces the duty cycle D to limit peak current. 2.5. Input Capacitor The purpose of C2 input capacitor is to provide current during switching cycles. During S1 closed, S2 open, C2 provides current to C1 in series with Lm + Llkg. l IN = I m AVE D = I LOAD DN Equation 18. During the tS1 portion of the cycle (S1 closed, S2 open), VIN recharges C2. The voltage ripple on C2 can be written as: I C2 1 – D T SW V IN RIPPLE = --------------------------------------C2 Equation 19. Substituting Equation 18 into 19: I LOAD D 1 – D T SW N V IN RIPPLE = -------------------------------------------------------C2 Equation 20. Rev. 0.1 5 AN892 2.6. Diode and Output Capacitor Current flows through D1 only during the (1–D)TSW portion of the steady state cycle. During the DTSW portion of the cycle, lLOAD is sourced solely by the output capacitor C10. Output voltage ripple on C10 can be calculated by I LOAD DT SW V OUT RIPPLE = -------------------------------C10 Equation 21. Applying the charge balance of C10, – I LOAD DT SW + 1 – D T SW = 0 Equation 22. 1 I D1 AVE 1 – D = I LOAD -----------------1 – D Equation 23. When D1 is reversed biased, it must withstand V D1 REV D = V IN 1 – D N + V OUT Equation 24. 6 Rev. 0.1 AN892 2.7. VSNS Voltage Divider For the purpose of selecting sense resistors (R5/R6), the entire dc-dc converter can be modelled as a noninverting amplifier as shown in Figure 4. Notice that the non-inverting input, supply voltage (V+), and output voltage of the amplifier correspond to the internal 1.05V reference, VIN, and VOUT of the dc-dc converter. VIN + - I VSNS 1.05V VREF V+ POWER STAGE VOUT VC10 VSNS RLOAD R5 R6 Figure 4. Simplified VOUT Gain Model Assuming infinite DC gain and applying KCL at the inverting input of the amplifier, VOUT can be expressed as: R5 V OUT = 1.05 -------- + 1 + R5 I VSNS R6 Equation 25. where IVSNS represents the input offset current at VSNS pin. From Equation 25, it can be observed that a very large R5 could reduce the output voltage accuracy. Rev. 0.1 7 AN892 3. Dynamic Response The Si8822xx start-up response consists of three regions of operation: Soft-Start (SS), Proportional-Mode (PMode), and Proportional Integral Mode (PI-mode). Figure 5 shows a typical VOUT response during startup. Figure 5. VOUT during Start Up 3.1. Soft Start In soft start mode, the dc-dc peak current limit is gradually increased to limit the sudden demand of current needed from the primary supply. This mode of operation guarantees that VOUT monotonically increases and minimizes the probability of a voltage overshoot. Once, 90% of the final VOUT is reached, soft start mode ends, and Proportional (P) Mode starts. The total duration of soft start is load dependent as it affects how many switching cycles are required for VOUT to reach 90% of final value. In this mode of operation, the voltage feedback loop is inactive and hence loop stability is not a concern. 3.2. Proportional Mode Once the secondary side senses 90% of VOUT, the control loop begins its P-mode operation. During this mode of operation the dc-dc converter closes the loop (dc-dc converter secondary side communicates with the primary side) and therefore, analyzing the loop stability is required. Figure 6 shows a simplified block diagram of voltage sensed feedback control. gmp represents the equivalent modulator and power stage transconductance of the dc-dc converter and resistors R5 and R6 are the feedback resistors used to sense VOUT. C10 is the output capacitor, and RLOAD represents output load. Parameter gmfb and Ro,gmfb are the effective error amplifier transconductance and the error amplifier output resistance, respectively. During the P-Mode, an integrated resistor RINT is connected to the COMP pin. R7 and C11 are external components connected to the COMP pin used in P-I mode. 8 Rev. 0.1 AN892 Figure 6. Simplified Voltage Sense Feedback Loop For stability analysis, the loop at the input of the error amplifier is broken to obtain the small-signal transfer function from Vfb,in to Vfb,out: V fb out 1 H p s = ------------------ = A DC P ---------------------V fb in s 1 + ----- p Equation 26. 1 pd -------------------------R Load C 10 Equation 27. R6 A DC P = – ---------------------- gm fb R INT ||R o gmfb gm p R LOAD ||R5 + R6 R5 + R6 Equation 28. gm ea gm fb = -------------------------------------------------gm ea R5 R6 + 1 Equation 29. gmea is the error amplifier transconductance. For the Si882xx/883xx, gmea 1x10-3, RINT 50k and Ro,gmfb>>RINT. If R5 and R6 are chosen such that their parallel resistance is sufficiently larger than 1/gmea, Equation 29 simplifies to: 1 gm fb ------------------------- R5 R6 Equation 30. Rev. 0.1 9 AN892 Typically, RLOAD << (R5 + R6) and gmp is approximately 3/N. The DC gain in P-mode simplifies to: 3 A 50x10 3R LOAD – -----------------------------------------------· DC P R5 N Equation 31. Notice that the DC gain of P mode is proportional to RLOAD and inversely proportional to R5. At heavy loads (small RLOAD), a very large R5 could significantly increase the output voltage error as the DC gain reduces. Conversely, a very small R5 increases power consumption and gmfb variability due to higher dependency on gmea, which can significantly vary more than 1/(R5||R6) over temperature or from part to part. The total duration of this mode is approximately 7ms. 3.3. Proportional Integral Mode After P-mode, the controller switches to PI-mode, the steady state and final operation mode. During this mode of operation, the error amplifier drives an impedance that consists of the series combination of resistor R7 and capacitor C11. To achieve a smooth transition between P and PI modes, it is recommended to set R7 to match RINT R7 and C11 are connected to the COMP pin. . R7 = R INT 50x10 3 Equation 32. In PI-mode, the loop transfer is given by: s - 1 + ------- z1 H PI s = A DC PI -------------------------------------------------------s s 1 + -------- 1 + --------- p1 p2 Equation 33. where 1 p1 -------------------------------R o gmfb C11 Equation 34. 1 z1 ------------------R7C11 Equation 35. 1 p2 -----------------------------R LOAD C10 Equation 36. R o gmfb gm p R LOAD A DC PI = – --------------------------------------------------R5 Equation 37. Notice that the loop transfer function in PI-Mode has an additional pole-zero pair when compared with P-Mode. In addition, the loop DC-gain is much higher in PI-Mode than in P-Mode due to Ro,gmfb>>RINT. 10 Rev. 0.1 AN892 Figure 7 shows the magnitude Bode plot of the loop in PI mode. Figure 7. Simplified Transfer Function PI Mode 4. Design Example Consider the desired requirements listed in Table 1. Table 1. Design Requirements Parameter Value Input Voltage 5.0 V 10% Output Voltage 5.0 V Input Voltage Ripple 150 mV Output Voltage Ripple 50 mV Maximum Output Current 400 mA 4.1. Transformer Design The design of a transformer for the asymmetric half bridge flyback is very similar to the design of a flyback transformer operating in continuous current mode. This section provides a starting point for the transformer design which is often an interative process. Equation 13 establishes the relationship between turns ratio n and duty cycle D. For this design, D=0.25 was chosen. The formulas derived in the DC steady state section are based on ideal elements. In practice, a larger duty cycle is expected due to losses in the parasitics. Accounting for forward voltage drop across D1 of 0.5V and solving Equation 13 for turns ratio: Rev. 0.1 11 AN892 V OUT + Vf D1 5 + 0.5 N --------------------------------- --------------------- 4.4 5 0.25 V IN D Equation 38. A 1:4 turns ratio was chosen. The next parameter to choose is the primary inductance. Equation 16 gives the average magnetizing current. Im AVE = NI LOAD = 4 0.4 = 1.6A Equation 39. Equation 15 shows that magnetizing current ripple is inversely proportional to primary inductance. There are considerations for choosing the magnitude of the magnetizing current ripple. Choosing a very small primary inductance leads to a large current ripple. Care must be taken not to approach the cycle-by-cycle current limit of approximately 3A. For this design, peak current was chosen not to exceed 2.5A at specified maximum ILOAD. A ripple current of 1.8A was targeted. Rearranging Equation 15, –6 V IN D 1 – D Tsw 5 0.25 0.75 4x10 L m + L lkg = -------------------------------------------- = --------------------------------------------------------- = 2.08H I m RIPPLE 1.8 Equation 40. The result of Equation 40 suggests the combination of magnetizing current and leakage inductance should be 2.08 H. Leakage inductance is unavoidable in transformer design and it should be minimized for the best energy transfer in an asymmetric half bridge flyback converter. A transformer was designed with primary inductance of 2 H and leakage inductance 100 nH. Figure 8 shows the expected magnetizing current during the portion of the cycle that S1 is closed and S2 is open. Figure 8. Magnetizing Current 12 Rev. 0.1 AN892 4.2. C1 Selection When S2 is closed, a resonant current in the primary is developed with frequency given by Equation 4. To ensure zero current switching of the diode by the time S1 closed, S2 open mode begins, C1 should be chosen so that at least half of the resonant period is completed in (1–D)Tsw time. r --------------------------- 1 – D T sw Equation 41. Combining Equation 4 and Equation 41 and solving for C1: 1 1 – D T sw 2 C1 ---------- ---------------------------- 9.1uF L lkg Equation 42. The next standard size capacitor 10 F was chosen. 4.3. D1 Selection Equations 23 and 24 define the requirements for selecting D1. Substituting into Equation 23, 1 1 I D1 AVE 1 – D = I LOAD ------------- = 0.4 ----------- = 0.533A 0.75 1 – D Equation 43. Diode current capacities are usually specified in rms. Assuming a half wave sinusoid current through D1, consider the translation of average to rms: l D1 RMS 1 – D = I D1 AVE 1 – D ----------- = 0.592A 2 2 Equation 44. Substituting into Equation 24, consider using the maximum expected VIN as the worst case requirement for reverse biasing: V D1 REV D = V IN MAX 1 – D N + V OUT = 5.5 0.75 4 + 5 = 21.5v Equation 45. Equations 24 and 45 do not include the voltage spike due to the interaction of the diode capacitance and leakage inductance and as a result, a diode with a larger withstanding voltage is required in practice. When selecting D1, Schottky diodes are the preferred choice due to their low forward voltage as it minimizes the associated power loss. A 1A, 40V Schottky diode was selected. 4.4. C10 Selection C10 is inversely proportional to output voltage ripple and sets the crossover frequency of control loop gain. It is suggested to use the minimum size capacitor to meet output voltage ripple requirements. Rearranging Equation 21, I LOAD DT sw 0.4 0.25 4x10 – 6 C10 = ----------------------------------- --------------------------------------------------- 8F V OUT RIPPLE 0.05 Equation 46. Rev. 0.1 13 AN892 A 10uF capacitor was chosen. 4.5. C2 Selection In most applications, VIN also supplies the VDDA pin that powers the dc—dc controller and left side digital isolator circuitry. It is recommended to minimize voltage ripple at VDDA. Solving Equation 20: I LOAD D 1 – D T SW N 0.4 0.25 0.75 4x10 4 C2 -------------------------------------------------------- ------------------------------------------------------------------------------- 8F V IN RIPPLE 0.15 –6 Equation 47. A 10F capacitor was chosen. 4.6. R5 and R6 The ratio of R5 and R6 is determined by the 5 V output voltage requirement. To reduce the dependence of feedback gain on the internal error amplifier transconductance, it is recommended to have the parallel combination resistance to be 10 k. Higher values of R5 + R6 reduce power loss through the divider, but at the expense of increasing output voltage error due to lVSNS which varies part to part. So R5 and R6 are chosen to target 10k parallel resistance. 3 R5 R6 10x10 = ---------------------R5 + R6 Equation 48. R5 5 = 1.05 -------- + 1 R6 Equation 49. Substituting Equation 48 into Equation 49 and solving for R6, 3 3.76R6 3 3 10x10 = -------------------- R6 = 12.66x10 R5 = 48.1x10 4.76 Equation 50. The nearest 1% resistor to 12.66 k is 12.7 k. However, setting R5 to either 47.5k or 48.7k does not target exactly 5V as well as other 1% resistor pairs. A better match was found with R6=13.3 k and R5=49.9 k. 4.7. Compensation Network The compensation network is comprised of R7 and C11. R7 is fixed to match RINT and 49.9 k is the nearest 1% resistor value. The C11 places the compensation zero in relationship to the crossover frequency. The equation for crossover frequency can be had by multiplying the P-mode gain (Equation 31) by the frequency of the pole created by RLOAD and C10 (Equation 36): 3 50x10 3R LOAD 1 f c ------------------------------------------------ ------------------------------------- 12.1kHZ R5 N 2R LOAD C10 Equation 51. 14 Rev. 0.1 AN892 To achieve good phase margin, it is suggested to place the zero between 1/4th to 1/10th of the estimated crossover frequency. The zero placement was chosen to lead the crossover frequency by a factor of 6. 6 6 - = 1.58nF C11 = ------------------------- = -------------------------------------------------------------------3 3 2f c R7 2 12.1x10 49.9x10 Equation 52. A 1.5 nF capacitor was chosen. 4.8. Design Summary Table 2 shows the component selection that meet the design requirements. Table 2. Design Summary Part Reference Description Manufacturer Manufacturer Part Number C1 C2 C10 CAP, 10uF, 10V, ±10%, X7R, 1206 Venkel C1206X7R100-106K C11 CAP, 1.5nF, 16V, ±10%, X7R, 0603 Venkel C0603X7R160-152K D1 DIO, FAST, 40V, 1.0A, SOD-128 Panasonic DB2440100L R5 R7 RES, 49.9K, 1/10W, ±1%, ThickFilm, 0603 Venkel CR0603-10W-4992F R6 RES, 13.3K, 1/16W, ±1%, ThickFilm, 0603 Venkel CR0603-16W-1332F T1 TRANSFORMER, POWER, FLYBACK, 2.0uH PRIMARY, 100nH LEAKAGE, 1:4, 1 TAP, SMT UTB02185S Rev. 0.1 UMEC 15 AN892 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 16 Rev. 0.1

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