AN331: Compensating the Feedback Loop for the Si3402

AN331
C O M P E N S A T I N G THE F EEDBACK L O O P FOR THE Si3402
1. Introduction
The Si3402 reference designs are available for many output voltages (e.g., 3.3, 5, 9, 12 V) and output capacitor
types. In general, Silicon Laboratories strongly recommends using these standard designs to minimize risk and
ensure robust performance. Refer to the design databases posted on the Si3402 documentation pages on the
Silicon Labs website for more information.
EVB Data Sheets, Reference Design Databases (Schematics and Layout):


Si3402-EVB
Si3402ISO-EVB
However, some designers may want to consider other cases of output filtering, input filtering, inductors, etc. for a
variety of reasons (cost, footprint, availability, etc.).
While it would be desirable to use circuit simulation to optimize the feedback loop, it is very difficult to get reliable
information about important factors such as capacitor ESR. Also, the stabilizing effect of the input side hot-swap
switch and input filter ESR must be taken into account, which is not straightforward for commonly available SPICE
implementations. For these reasons, the feedback loop must be experimentally optimized if a known reference
design is not used.
The application note outlines the general process for compensating the feedback loop experimentally. In case a
predefined compensation and output filter is not used, it is strongly recommended that this procedure be followed
to ensure robust performance.
1.1. Breaking the Feedback Loop
The feedback loop is broken and a transformer is used to inject an ac signal across the break. Using a transformer
allows the loop stability to be measured in a closed loop system with whatever load a filtering is present. The loop
is broken at the output and at the point sensing the output voltage. The transformer ac and dc impedance must be
small compared to the impedance sensing the output voltage.
Figures 1 and 2 show the recommended transformer placement for the non-isolated and isolated reference
designs.
Rev. 1.0 6/10
Copyright © 2010 by Silicon Laboratories
AN331
K1
LED_K1
A1
9
PWR4
10
L5
RJ-45
330 Ohm
L3
TRD1TRD1+
TRCT1
TRCT4
TRD4+
TRD4-
330 Ohm
L2
330 Ohm
L4
RJ-45
J2
10
11
12
4
5
6
J1
7
8
9
1
2
3
330 Ohm
PWR3
MX1+
CT/MX1MX1-
8
10/100 Connector
Dual Footprint
PWR2
LED_A1
K2
LED_K2
A2
LED_A2
MX0+
CT
MX0TRD2+
TRD2TRCT2
TRCT3
TRD3TRD3+
4
5
6
1
2
3
49.9K
S1B
VC4
16
D15
15
C10
1nF
D11
S1B
PWR5
PWR1
K2
S1B
C14
1nF
11
7
K1
LED_K1
A1
LED_A1
A2
VC3
Alternate
Gigabit Connector
LED_K2
14
D14
VC2
+
SP1
Vposf
CT2
CT1
C18
0.1uF
11
12
13
14
U1
L1 33uH
D1
PDS5100
Si3402
ISOSSFT
Vdd
SSFT
EROUT
4
3
2
C19
150pF
1
C7
3.3nF
FB1
R8
0
30 Ohm
560uF
+ C5
Use Vpos as the ground reference
for loop stability analysis.
Figure 1. Non-Isolated
330
C1
1uF
C2
12uF
C3
15
Vssa
SP2
10
1uF
C4
16
Vposs
Vneg
9
1uF
17
VSS1
RCL
8
LED_A2
VC1
13
C11
D10
1nF
S1B
D13
S1B
C15
1nF
C12
D9
1nF
S1B
D12
S1B
C16
1nF
18
SWO
HSO
7
45.3
C13
D8
S1B
19
6
R3
1nF
C17
1nF
20
FB
VSS2
RDET
PLOSSb
5
25.5K
Rev. 1.0
R4
22uF
R7
30.1K
C8
0.1uF
C6
R2
Vin
C9 0.33uF
R5
2.87K
C20
2
TX1
3.3n
R1
V1
Vout
AN331
RLOAD
8.66K R6
12
1
RDN
TDP
TDN
3
4
5
7
1
CT
2
1
1
1
1
1
300 ohms
1
2
L3
300 ohms
1
2
L2
300 ohms
2
300 ohms
1
L4
L5
7
5
4
3
2
1
RDP
J5
HEADER 1
J6
HEADER 1
J7
HEADER 1
J8
HEADER 1
J9
HEADER 1
49.9K
2
1000p
S1B
2
C14
D10
1
S1B
2
D11
1
MagJack
11
13
12
11
14
13
10
10
15
9
14
9
R2
1000p
S1B
2
C15
D9
1
J1
S1B
2
D15
1
15
8
8
anode
1000p
S1B
2
C10
D14
1
R1
1000p
S1B
2
C11
D13
1
1000p
S1B
2
C16
D8
1
anode
1000p
S1B
2
C12
D12
1
330
1000p
C13
1000p
C17
HEADER 1
J3
1
SP1
Vposf
CT2
CT1
U1
Vssa
Si3402
11
12
13
14
Connect transformer and
input filter caps together
minimizing area of return
loop and then connect
to Vpos plane.
J4
HEADER 1
Figure 2. Isolated
1
D1
ISOSSFT
Vdd
SSFT
EROUT
D2
C2
12uF
15
Vssa
10
SP2
16
1u C3
17
9
VSS1
Vneg
4
3
2
1
1N4148W
12,13 must be isolated from 14,15
C18
HSO
7
1u C1
0.1u
RDET
6
Vposs
RCL
8
18
SWO
1u C4
20
19
VSS2
5
R3
30.9
1000p
C19
2
1
Vssa
FA2805
T2
10:4 secondary
100n
C22
DFLT15A
1u
C23
FB
PLOSSb
R4
25.5K
R12 100
220n
Rev. 1.0
C21
PDS1040
1000p
C20
PS2911
U5
R11
4.99K
R7
1
L1
15n
C9
U4
TLV431
2.05K
Vin
R10
10 C7
9 470p 10
7
8
D3
100u C6
Vpos is a EMI and ESD plane. Use top layer.
10K
R8
TX1
1uH
2
CON1
V1
R9
3.01k
C8
560p
CON1
J12
Vout
R6
12.1K
R5
36.5K
1
CMAX
1000u
C5
1
J11
AN331
3
AN331
A commercially available phase gain meter optimized for power supply analysis is available from Venable Inc. The
Venable meter can be used with an injection transformer from Venable, or an ordinary transformer can be used as
long as it keeps a low ac and dc impedance.
Good results have also been achieved with a Bode 100 phase gain meter from Omicron Labs and using Coilcraft
BU15-7521ROBL common mode choke hooked up as a transformer (input on 1,2 output on 3,4). When terminated
with a 50  resistor on the input side, this transformer gives <100  impedance on the output side from dc to well
over 10 MHz insuring that the transformer itself does not impact the feedback loop.
Other phase gain meters can be used as long as they are capable of operating in the 100 Hz to 40 kHz range of
interest and have a provision for high impedance (1 M) probes.
The phase-gain meter is used to measure the output voltage response to the input voltage that is stimulated by the
transformer (see Figure 3). The magnitude and phase of the voltage (VSTIM) that the transformer produces is not
critical. It should be large enough that the signals can be measured but not so large that there is distortion. In
practice, a signal level of –20 to –30 dBm (50  reference) has been found to be satisfactory.
The magnitude and phase of the ratio of the output voltage the input voltage is what needs to be measured to
examine loop stability. In general it is good practice to have at least 50 degrees of phase margin when the gain is
unity (zero dB) and 10 dB of gain margin when the phase reaches zero degrees.
VIN
VSTIM
VOUT
Figure 3. Phase and Gain of VOUT with Respect to VIN
Experimental results for the standard isolated and non-isolated reference designs are shown in Figures 4 and 5
(see also AN296).
4
Rev. 1.0
AN331
dB
°
60
150
40
100
20
50
0
0
-20
-50
-40
-100
-60
-150
-80
-200
200
500
1000
2000
magnitude(Gain) in dB
5000
10000
20000
f/Hz
phase(Gain) in °
Figure 4. Gain and Phase for Non-Isolated Design
dB
°
60
150
40
100
20
50
0
0
-20
-50
-40
-100
-60
-150
-80
-200
200
500
1000
magnitude(Gain) in dB
2000
5000
10000
20000
f/Hz
phase(Gain) in °
Figure 5. Gain and Phase of Isolated Design
1.2. Optimizing the Feedback Loop
Generally, the feedback loop should be checked over the entire input voltage and load range. In practice, the
maximum input voltage and maximum load is generally the worst case corner. Building in some margin for gain and
phase allows for variation in components and temperature. In the case of the isolated design, a gain sorted optocoupler should be used to avoid a lot of gain variation from the opto-coupler. Also, for designs that operate at very
low (–40 °C) temperature and use electrolytic capacitors in the filter path, it is desirable to check at low temperature
because electrolytic capacitors have substantial variation in ESR at low temperature.
A low or negative gain and phase margin can give power supply output oscillation and the feedback loop crossover
frequency should be reduced. An excessively large gain and phase margin means that better transient response
could be obtained by increasing the crossover frequency.
For the non-isolated design, the dominant pole is set by C7. A zero is introduced by R7-C7, and an optional second
zero is introduced by C20-R6. The zeros in the transfer function are used to compensate for the poles introduced
by the output filter and extend the frequency response of the feedback loop. The R7-C7 zero should be placed at
somewhat less than the desired loop bandwidth in order to contribute the most phase boost. For example, in the
Rev. 1.0
5
AN331
non-isolated reference design the R7-C7 zero is at 1.6 kHz and the loop bandwidth is about 4 kHz. C19 introduces
a final pole which is required to filter noise that can be coupled to the ERout node. If used, the C20-R6 zero is
placed at about the loop bandwidth (not below) so as to maximize the phase boost prior to the pole from C20-R5//
R6.
The below optimization process is greatly aided by the use of a parameter calculation tool, provided in the form of
an Excel spreadsheet. This Switcher Calc tool can be found on the Silicon Labs Si3402 documentation pages.
The optimization process for the non-isolated design is as follows:
1. R5 and R6 are fixed to set the desired output voltage.
2. Vary C7 to move the crossover frequency up and down.
3. R7 is increased to reduce the C7-R7 zero to 1/2 to 1/3 of the loop bandwidth.
4. If used, C20 is set so that C20-R6 is equal to the loop bandwidth.
5. If the phase margin and gain margin are too big or too small go back to step 2 and change C7 up (not enough
margin) or down (too much margin and not enough bandwidth).
For the isolated design, the C21-R11 pole compensates the zero introduced by C9 and R8+R6//R5. Therefore, the
zeros of concern for loop stability are C21-R12 and C8-R5. As in the non-isolated design these zeros (in this case
7.8 kHz and 7.2 kHz) are placed at around the desired loop bandwidth (7 kHz) so as to maximize the phase boost.
In this case both zeros are placed near the loop bandwidth because it is desirable to minimize R12 to reduce noise
at ERout.
The optimization process for the isolated design is as follows:
1. R5 and R6 are fixed to set the desired output voltage. R8 is set to 10 k, R11 is set to 4.99 k and R7 is set
according to the output voltage (1 k at 3.3 V, 2.05 k at 5 V, and 4.99 k at 9 or 12 V, for example). R9 is
generally set to approximately 3.01 k.
2. Vary C9 and C21 to move the crossover frequency up and down. Generally, C9 and C11 are kept as a ratio and
C9 is < 1/4 of C21.
3. R12 is increased so that R12 x C21 is less than or equal to the loop bandwidth subject to the constraint that
R12 <1K to filter any noise at ERout.
4. C8 is increased so that C8 x R5 is approximately equal to the loop bandwidth.
5. If the phase margin and gain margin are too big or too small, go back to step 2 and change C9 and C21 (in the
same ratio) up (not enough margin) or down (too much margin and not enough bandwidth).
2. Conclusions
To ensure robust performance in cases where a predefined compensation and output filter are not used, the
application note outlines the general process required for experimentally compensating the Si3402 feedback loop.
Refer to the Si3402 Evaluation Board User Guides and reference designs for complete schematics for common
output voltages and output filter configurations.
6
Rev. 1.0
AN331
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2

Added Si3402.
Revision 0.2 to Revision 1.0

Removed all references to the Si3400 and Si3401.
The Si3402 replaces these devices.
Rev. 1.0
7
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