PIC16(L)F18324/18344 PIC16(L)F18324/18344 Family Silicon Errata and Data Sheet Clarification The PIC16(L)F18324/18344 family devices that you have received conform functionally to the current Device Data Sheet (DS40001800A), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the PIC16(L)F18324/18344 silicon. 4. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A4). 5. Data Sheet clarifications and corrections start on page 4, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC16(L)F18324/ 18344 silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Device ID(1) Revision ID for Silicon Revision(2) A3 A4 PIC16F18324 303Ah 2003h 2004h PIC16LF18324 303Ch 2003h 2004h PIC16F18344 303Bh 2003h 2004h PIC16LF18344 303Dh 2003h 2004h Note 1: 2: The Device IDs (DEVID and DEVREV) are located at adresses 8006h and 8005h, respectively. They are shown in hexadecimal in the format “DEVID DEVREV”. Refer to the “PIC16(L)F183XX Memory Programming Specification” (DS40001738) for detailed information on Device and Revision IDs for your specific device. 2015 Microchip Technology Inc. DS80000667A-page 1 PIC16(L)F18324/18344 TABLE 2: SILICON ISSUE SUMMARY Module Oscillators Note 1: Feature Fail-Safe Clock Monitor (FSCM) Item Number 1.1 Affected Revisions Issue Summary The FSCM may fail to trigger. A3 A4 X X Only those issues indicated in the last column apply to the current silicon revision. DS80000667A-page 2 2015 Microchip Technology Inc. PIC16(L)F18324/18344 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A4). 1. Module: Oscillators 1.1 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor may fail to trigger with the loss of the external clock signal when the 4x PLL is enabled. This includes all external clock modes, LP, XT, HS, ECL, ECM, and ECH. Work around None. Affected Silicon Revisions A3 A4 X X 2015 Microchip Technology Inc. DS80000667A-page 3 PIC16(L)F18324/18344 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS40001800A): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: CCP In Section 28.3, a note box will be added as follows: Note: When the CCP is configured in Compare mode using the ‘toggle output on match’ setting (CCPxMODE<3:0> bits = 0010) and the reference timer is set for an input clock prescale other than 1:1, the output of the CCP will toggle multiple times until finally settling a ‘0’ logic level. To avoid this, the timer input clock prescale select bits must be set to a 1:1 ratio (TxCKPS = 00). 2. Module: Oscillators In Section 6.5, the HFINTOSC Frequency Selection Register (OSCFRQ) will be modified as follows: REGISTER 6-6: OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 HFFRQ<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’. bit 3-0 HFFRQ<3:0>: HFINTOSC Frequency Selection bits DS80000667A-page 4 HFFRQ<3:0> Nominal Freq. (MHz) (NOSC = 110) 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1 2 Reserved 4 8 12 16 32 32 2xPLL Freq. (MHz) (NOSC = 000) Reserved 16 24 32 Reserved Reserved 2015 Microchip Technology Inc. PIC16(L)F18324/18344 3. Module: Resets In Section 5.12, Bit 6 of the Brown-out Reset Control Register (BORCON) will be modified as follows: REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN(1) Reserved — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit(1) If BOREN <1:0> in Configuration Words 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 Reserved. Bit must be maintained as ‘0’. bit 5-1 Unimplemented: Read as ‘0’. bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2015 Microchip Technology Inc. DS80000667A-page 5 PIC16(L)F18324/18344 4. Module: Power-Saving Operation In Section 8.3, Bit 0 of the Voltage Regulator Control Register (VREGCON) will be modified as follows: REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: 2: PIC16F18324/18344 only. See Section 34.0 “Electrical Specifications”. DS80000667A-page 6 2015 Microchip Technology Inc. PIC16(L)F18324/18344 5. Module: Electrical Specifications In Section 34, Table 34-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brownout Reset Specifications, will be modified as follows: TABLE 8-1: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW POWER BROWN-OUT RESET SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units RST01 TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s RST02 TIOZ I/O high-impedance from Reset detection — — 2 s RST03 TWDT Watchdog Timer Time-out Period 10 16 27 ms RST04* TPWRT Power-up Timer Period 40 65 140 ms RST05 TOST Oscillator Start-up Timer Period(1,2) — 1024 — RST06 VBOR Brown-out Reset Voltage(4) 2.55 2.30 1.80 2.70 2.45 1.90 2.85 2.60 2.10 V V V RST07 VBORHYS Brown-out Reset Hysteresis 0 25 75 mV RST08 TBORDC Brown-out Reset Response Time 1 3 35 s RST09 VLPBOR Low-Power Brown-out Reset Voltage 1.8 2.1 2.5 V * † Note 1: 2: 3: 4: Conditions 16 ms Nominal Reset Time TOSC (Note3) BORV = 0 BORV = 1 (PIC16F18324/18344) BORV = 1 (PIC16LF18324/18344) PIC16LF18324/18344 These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2015 Microchip Technology Inc. DS80000667A-page 7 PIC16(L)F18324/18344 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (09/2015) Initial release of this document. DS80000667A-page 8 2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-827-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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