SiM3L1xx High-Performance, Low-Power, 32-Bit Precision32™ MCU Family with up to 256 kB of Flash 32-bit ARM Cortex-M3 CPU - 50 MHz maximum frequency - Single-cycle multiplication, hardware division support - Nested vectored interrupt control (NVIC) with 8 priority levels Memory - 32–256 kB flash, in-system programmable - 8–32 kB SRAM with configurable low power retention Clock Sources - Internal oscillator with PLL: 23–50 MHz - Low power internal oscillator: 20 MHz - Low frequency internal oscillator (LFO): 16.4 kHz - External real-time clock (RTC) crystal oscillator - External oscillator: Crystal, RC, C, CMOS clock Power Management - Three adjustable low drop-out (LDO) regulators - Power-on reset circuit and brownout detectors - DC-DC buck converter allows dynamic voltage scaling for - maximum efficiency (250 mW output) Multiple power modes supported for low power optimization Low Power Features - 75 nA typical current in Power Mode 8 - Low-current RTC (180 nA from LFO, 300 nA from crystal) - 4 μs wakeup, register state retention and no reset required from - lowest power mode 175 μA/MHz at 3.6 V executing from flash 140 μA/MHz at 3.6 V executing from SRAM Specialized on-chip charge pump reduces power consumption Process/Voltage/Temperature (PVT) Monitor 5 V Tolerant Flexible I/O - Up to 62 contiguous 5 V tolerant GPIO with one priority crossbar providing flexibility in pin assignments Temperature Range: –40 to +85 °C Analog Peripherals - 12-Bit Analog-to-Digital Converter: Up to 250 ksps 12-bit mode - or 1 Msps 10-bit mode 10-Bit Current-mode Digital-to-Analog Converter 2 x Low-current comparators Digital and Communication Peripherals - 1 x USART with IrDA and ISO7816 Smartcard support - 1 x UART that operates in low power mode - 2 x SPIs, 1 x I2C, 16/32-bit CRC - 128/192/256-bit Hardware AES Encryption - Encoder/Decoder: Manchester and Three-out-of-Six - Integrated LCD Controller: up to 160 segments (40x4), autocontrast and low power operation Timers/Counters - 3 x 32-bit or 6 x 16-bit timers with capture/compare - 16-bit, 6-channel counter with capture/compare/PWM and - dead-time controller with differential outputs 16-bit low power timer/advanced capture counter operational in the lowest power mode 32-bit real time clock (RTC) with multiple alarms Watchdog timer Low power mode advanced capture counter (ACCTR) Data Transfer Peripherals - 10-Channel DMA Controller - 3 Channel Data Transfer Manager manages complex DMA transfers without core intervention On-Chip Debugging - Serial wire debug (SWD) with serial wire viewer (SWV) or JTAG - (no boundary scan) allow debug and programming Cortex-M3 embedded trace macrocell (ETM) Package Options - QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm) - TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) Supply Voltage: 1.8 to 3.8 V Rev 1.1 11/14 Copyright © 2013 by Silicon Laboratories SiM3L1xx 2 Rev 1.1 SiM3 L1xx Ta bl e of C o n t e n t s 1. Related Documents and Conventions ...............................................................................5 1.1. Related Documents........................................................................................................5 1.1.1. SiM3L1xx Reference Manual.................................................................................5 1.1.2. Hardware Access Layer (HAL) API Description ....................................................5 1.1.3. ARM Cortex-M3 Reference Manual.......................................................................5 1.2. Conventions ...................................................................................................................5 2. Typical Connection Diagrams ............................................................................................6 2.1. Power .............................................................................................................................6 3. Electrical Specifications......................................................................................................8 3.1. Electrical Characteristics ................................................................................................8 3.2. Thermal Conditions ......................................................................................................30 3.3. Absolute Maximum Ratings..........................................................................................31 4. Precision32™ SiM3L1xx System Overview.....................................................................32 4.1. Power ...........................................................................................................................34 4.1.1. DC-DC Buck Converter (DCDC0)........................................................................34 4.1.2. Three Low Dropout LDO Regulators (LDO0) ......................................................35 4.1.3. Voltage Supply Monitor (VMON0) .......................................................................35 4.1.4. Power Management Unit (PMU)..........................................................................35 4.1.5. Device Power Modes...........................................................................................35 4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0).......................38 4.2. I/O.................................................................................................................................39 4.2.1. General Features.................................................................................................39 4.2.2. Crossbar ..............................................................................................................39 4.3. Clocking........................................................................................................................40 4.3.1. PLL (PLL0)...........................................................................................................41 4.3.2. Low Power Oscillator (LPOSC0) .........................................................................41 4.3.3. Low Frequency Oscillator (LFOSC0)...................................................................41 4.3.4. External Oscillators (EXTOSC0)..........................................................................41 4.4. Integrated LCD Controller (LCD0)................................................................................42 4.5. Data Peripherals...........................................................................................................43 4.5.1. 10-Channel DMA Controller.................................................................................43 4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2) .................................................43 4.5.3. 128/192/256-bit Hardware AES Encryption (AES0) ............................................43 4.5.4. 16/32-bit Enhanced CRC (ECRC0) .....................................................................44 4.5.5. Encoder / Decoder (ENCDEC0) ..........................................................................44 4.6. Counters/Timers...........................................................................................................45 4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2)...........................................................45 4.6.2. Enhanced Programmable Counter Array (EPCA0) .............................................45 4.6.3. Real-Time Clock (RTC0) .....................................................................................46 4.6.4. Low Power Timer (LPTIMER0)............................................................................46 4.6.5. Watchdog Timer (WDTIMER0)............................................................................46 4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0)...................................47 4.7. Communications Peripherals .......................................................................................48 4.7.1. USART (USART0) ...............................................................................................48 Rev 1.1 3 SiM3L1xx 4.7.2. UART (UART0)....................................................................................................48 4.7.3. SPI (SPI0, SPI1) ..................................................................................................49 4.7.4. I2C (I2C0) ............................................................................................................49 4.8. Analog ..........................................................................................................................50 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)...................................................50 4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) .........................................................50 4.8.3. Low Current Comparators (CMP0, CMP1) ..........................................................50 4.9. Reset Sources..............................................................................................................51 4.10.Security ........................................................................................................................52 4.11.On-Chip Debugging .....................................................................................................52 5. Ordering Information .........................................................................................................53 6. Pin Definitions....................................................................................................................55 6.1. SiM3L1x7 Pin Definitions .............................................................................................55 6.2. SiM3L1x6 Pin Definitions .............................................................................................62 6.3. SiM3L1x4 Pin Definitions .............................................................................................69 6.4. TQFP-80 Package Specifications ................................................................................74 6.4.1. TQFP-80 Solder Mask Design.............................................................................77 6.4.2. TQFP-80 Stencil Design ......................................................................................77 6.4.3. TQFP-80 Card Assembly.....................................................................................77 6.5. QFN-64 Package Specifications ..................................................................................78 6.5.1. QFN-64 Solder Mask Design...............................................................................80 6.5.2. QFN-64 Stencil Design ........................................................................................80 6.5.3. QFN-64 Card Assembly.......................................................................................80 6.6. TQFP-64 Package Specifications ................................................................................81 6.6.1. TQFP-64 Solder Mask Design.............................................................................84 6.6.2. TQFP-64 Stencil Design ......................................................................................84 6.6.3. TQFP-64 Card Assembly.....................................................................................84 6.7. QFN-40 Package Specifications ..................................................................................85 6.7.1. QFN-40 Solder Mask Design...............................................................................87 6.7.2. QFN-40 Stencil Design ........................................................................................87 6.7.3. QFN-40 Card Assembly.......................................................................................87 7. Revision Specific Behavior...............................................................................................88 7.1. Revision Identification ..................................................................................................88 Document Change List ...........................................................................................................90 Contact Information ................................................................................................................91 4 Rev 1.1 SiM3 L1xx 1. Related Documents and Conventions 1.1. Related Documents This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices. 1.1.1. SiM3L1xx Reference Manual The Silicon Laboratories SiM3L1xx Reference Manual provides the detailed description for each peripheral on the SiM3L1xx devices. 1.1.2. Hardware Access Layer (HAL) API Description The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual. 1.1.3. ARM Cortex-M3 Reference Manual The ARM-specific features like the Nested Vectored Interrupt Controller are described in the ARM Cortex-M3 reference documentation. The online reference manual can be found here: http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3. 1.2. Conventions The block diagrams in this document use the following formatting conventions: Figure 1.1. Block Diagram Conventions Rev 1.1 5 SiM3L1xx 2. Typical Connection Diagrams This section provides typical connection diagrams for SiM3L1xx devices. 2.1. Power Figure 2.1 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck converter is not used. Figure 2.1. Connection Diagram with DC-DC Converter Unused Figure 2.2 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the internal dc-dc buck converter is in use and I/O are powered directly from the battery. Figure 2.2. Connection Diagram with DC-DC Converter Used and I/O Powered from Battery Figure 2.3 shows a typical connection diagram for the power pins of the SiM3L1xx devices when used with an external radio device like the Silicon Labs EZRadio® or EZRadioPRO® devices. 6 Rev 1.1 SiM3 L1xx Figure 2.3. Connection Diagram with External Radio Device Figure 2.4 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck converter is used and the I/O are powered separately. Figure 2.4. Connection Diagram with DC-DC Converter Used and I/O Powered Separately Rev 1.1 7 SiM3L1xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all Tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Operating Supply Voltage on VBAT/VBATDC VBAT 1.8 — 3.8 V Operating Supply Voltage on VDC VDC 1.25 — 3.8 V Operating Supply Voltage on VDRV VDRV 1.25 — 3.8 V VIO 1.8 — VBAT V Operation Supply Voltage on VIORF VIORF 1.8 — VBAT V Operation Supply Voltage on VLCD VLCD 1.8 — 3.8 V System Clock Frequency (AHB) fAHB 0 — 50 MHz Peripheral Clock Frequency (APB) fAPB 0 — 50 MHz Operating Ambient Temperature TA –40 — +85 °C Operating Junction Temperature TJ –40 — 105 °C Operating Supply Voltage on VIO Note: All voltages with respect to VSS. 8 Rev 1.1 SiM3 L1xx Table 3.2. Power Consumption Parameter Symbol Test Condition Min Typ Max Unit IBAT FAHB = 49 MHz, FAPB = 24.5 MHz — 17.5 18.9 mA FAHB = 20 MHz, FAPB = 10 MHz — 6.7 7.2 mA FAHB = 2.5 MHz, FAPB = 1.25 MHz — 1.15 1.4 mA FAHB = 49 MHz, FAPB = 24.5 MHz — 13.3 14.5 mA FAHB = 20 MHz, FAPB = 10 MHz — 5.4 5.9 mA FAHB = 2.5 MHz, FAPB = 1.25 MHz — 980 1.2 μA FAHB = 49 MHz, FAPB = 24.5 MHz VBAT = 3.3 V — 9.7 — mA FAHB = 49 MHz, FAPB = 24.5 MHz VBAT = 3.8 V — 8.65 — mA FAHB = 20 MHz, FAPB = 10 MHz VBAT = 3.3 V — 4.15 — mA FAHB = 20 MHz, FAPB = 10 MHz VBAT = 3.8 V — 3.9 — mA Digital Core Supply Current Normal Mode1,2,3,4—Full speed with code executing from flash, peripheral clocks ON Normal Mode1,2,3,4—Full speed with code executing from flash, peripheral clocks OFF Normal Mode1,2,3,4—Full speed with code executing from flash, LDOs powered by dc-dc at 1.9 V, peripheral clocks OFF IBAT IBAT Notes: 1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8 production test measurements. Rev 1.1 9 SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter 11,2,3,4—Full Power Mode speed with code executing from RAM, peripheral clocks ON Power Mode 11,2,3,4—Full speed with code executing from RAM, peripheral clocks OFF Power Mode 11,2,3,4—Full speed with code executing from RAM, LDOs powered by dc-dc at 1.9 V, peripheral clocks OFF Power Mode 21,2,3,4,5—Core halted with peripheral clocks ON Symbol Test Condition Min Typ Max Unit IBAT FAHB = 49 MHz, FAPB = 24.5 MHz — 13.4 16.6 mA FAHB = 20 MHz, FAPB = 10 MHz — 4.7 — mA FAHB = 2.5 MHz, FAPB = 1.25 MHz — 810 — μA FAHB = 49 MHz, FAPB = 24.5 MHz — 9.4 12.5 mA FAHB = 20 MHz, FAPB = 10 MHz — 3.3 — mA FAHB = 2.5 MHz, FAPB = 1.25 MHz — 630 — μA FAHB = 49 MHz, FAPB = 24.5 MHz VBAT = 3.3 V — 7.05 — mA FAHB = 49 MHz, FAPB = 24.5 MHz VBAT = 3.8 V — 6.3 — mA FAHB = 20 MHz, FAPB = 10 MHz VBAT = 3.3 V — 2.75 — mA FAHB = 20 MHz, FAPB = 10 MHz VBAT = 3.8 V — 2.6 — mA FAHB = 49 MHz, FAPB = 24.5 MHz — 7.6 11.3 mA FAHB = 20 MHz, FAPB = 10 MHz — 2.75 — mA FAHB = 2.5 MHz, FAPB = 1.25 MHz — 575 — μA IBAT IBAT IBAT Notes: 1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8 production test measurements. 10 Rev 1.1 SiM3 L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Power Mode 21,2,3,4,5—Core halted IBAT FAHB = 49 MHz, FAPB = 24.5 MHz — 4 7.2 mA FAHB = 20 MHz, FAPB = 10 MHz — 1.47 — mA FAHB = 2.5 MHz, FAPB = 1.25 MHz — 430 — μA VBAT = 3.8 V — 320 530 μA VBAT = 1.8 V — 225 — μA FAHB = FAPB = 16 kHz, VBAT = 3.8 V — 385 640 μA FAHB = FAPB = 16 kHz, VBAT = 1.8 V — 330 — μA FAHB = FAPB = 16 kHz, VBAT = 3.8 V — 320 490 μA FAHB = FAPB = 16 kHz, VBAT = 1.8 V — 275 — μA FAHB = FAPB = 16 kHz, VBAT = 3.8 V — 315 490 μA FAHB = FAPB = 16 kHz, VBAT = 1.8 V — 270 — μA RTC Disabled, TA = 25 °C — 75 400 nA RTC w/ 16.4 kHz LFO, TA = 25 °C — 360 — nA RTC w/ 32.768 kHz Crystal, TA = 25 °C — 670 — nA with only Port I/O clocks on (wake from pin). Power Mode 31,2,6—Fast-Wake Mode (PM3CLKEN = 1) 41,2,4,6—Slower IBAT Power Mode clock speed with code executing from flash, peripheral clocks ON IBAT Power Mode 51,2,4,6—Slower clock speed with code executing from RAM, peripheral clocks ON IBAT Power Mode 61,2,4,6—Core halted with peripheral clocks ON IBAT Power Mode 81,2—Low Power Sleep, powered through VBAT, VIO, and VIORF at 2.4 V, 32kB of retention RAM IBAT Notes: 1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8 production test measurements. Rev 1.1 11 SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit 81,2—Low IBAT RTC w/ 16.4 kHz LFO, VBAT = 2.4 V, TA = 25 °C — 180 — nA RTC w/ 32.768 kHz Crystal, VBAT = 2.4 V, TA = 25 °C — 300 — nA RTC w/ 16.4 kHz LFO, VBAT = 3.8 V, TA = 25 °C — 245 — nA RTC w/ 32.768 kHz Crystal, VBAT = 3.8 V, TA = 25 °C — 390 — nA — 2 — nA VBAT = 3.8 V, TA = 25 °C — 195 600 nA VBAT = 2.4 V, TA = 25 °C — 120 — nA VBAT = 3.8 V, TA = 25 °C — 495 660 nA VBAT = 2.4 V, TA = 25 °C — 395 — nA VBAT = 3.8 V, TA = 25 °C — 800 — nA VBAT = 2.4 V, TA = 25 °C — 580 — nA VBAT = 2.4 V, TA = 25 °C, CPMD = 01 — 1.11 — nA/Hz VBAT = 3.8 V, TA = 25 °C, CPMD = 01 — 1.44 — nA/Hz VBAT = 2.4 V, TA = 25 °C, CPMD = 10 — 1.45 — nA/Hz VBAT = 3.8 V, TA = 25 °C, CPMD = 10 — 1.82 — nA/Hz VBAT = 2.4 V, TA = 25 °C, CPMD = 11 — 2.15 — nA/Hz VBAT = 3.8 V, TA = 25 °C, CPMD = 11 — 2.54 — nA/Hz Power Mode Power Sleep, powered by the low power mode charge pump, 32kB of retention RAM Unloaded VIO and VIORF Current10 IVIO Power Mode 8 Peripheral Currents UART0 LCD07, IUART0 No segments active LCD07, All (4 x 40) segments active Advanced Capture Counter (ACCTR0), LC Single-Ended Mode, Relative to Sampling Frequency9 ILCD0 ILCD0 IACCTR Notes: 1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8 production test measurements. 12 Rev 1.1 SiM3 L1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Min Typ Max Unit Advanced Capture Counter (ACCTR0), LC Dual or Quadrature Mode, Relative to Sampling Frequency9 IACCTR VBAT = 2.4 V, TA = 25 °C, CPMD = 01 — 1.39 — nA/Hz VBAT = 3.8 V, TA = 25 °C, CPMD = 01 — 1.89 — nA/Hz VBAT = 2.4 V, TA = 25 °C, CPMD = 10 — 2.08 — nA/Hz VBAT = 3.8 V, TA = 25 °C, CPMD = 10 — 2.59 — nA/Hz VBAT = 2.4 V, TA = 25 °C, CPMD = 11 — 3.47 — nA/Hz VBAT = 3.8 V, TA = 25 °C, CPMD = 11 — 4.03 — nA/Hz Analog Peripheral Supply Currents PLL0 Oscillator (PLL0OSC) IPLLOSC Operating at 49 MHz — 1.4 1.6 mA Low-Power Oscillator (LPOSC0) ILPOSC Operating at 20 MHz — 25 — μA Operating at 2.5 MHz — 25 — μA ILFOSC Operating at 16.4 kHz — 190 310 nA IEXTOSC FREQCN = 111 — 3.8 4.5 mA FREQCN = 110 — 840 960 μA FREQCN = 101 — 185 230 μA FREQCN = 100 — 65 80 μA FREQCN = 011 — 25 30 μA FREQCN = 010 — 10 13 μA FREQCN = 001 — 5 7 μA FREQCN = 000 — 3 5 μA Low-Frequency Oscillator (LFOSC0) External Oscillator (EXTOSC0) Notes: 1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8 production test measurements. Rev 1.1 13 SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter SARADC0 Symbol Test Condition Min Typ Max Unit ISARADC Sampling at 1 Msps, Internal VREF used — 1.2 1.6 mA Sampling at 250 ksps, lowest power mode settings. — 390 540 μA — 75 110 μA Normal Power Mode — 680 — μA Normal Power Mode — 160 — μA — 80 — μA CMPMD = 11 — 0.5 2 μA CMPMD = 10 — 3 8 μA CMPMD = 01 — 10 16 μA CMPMD = 00 — 25 42 μA Temperature Sensor ITSENSE Internal SAR Reference IREFFS VREF0 IREFP Comparator 0 (CMP0), Comparator 1 (CMP1) ICMP IDAC08 IIDAC — 70 100 μA Voltage Supply Monitor (VMON0) IVMON — 10 22 μA Write Operation IFLASH-W — — 8 mA Erase Operation IFLASH-E — — 15 mA Flash Current on VBAT Notes: 1. Currents are additive. For example, where IBAT is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes all peripherals that cannot have clocks gated in the Clock Control module. 3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current. 4. Internal Digital and Memory LDOs scaled to optimal output voltage. 5. Flash AHB clock turned off. 6. Running from internal LFO, Includes LFO supply current. 7. LCD0 current does not include switching currents for external load. 8. IDAC output current not included. 9. Does not include LC tank circuit. 10. Does not include digital drive current or pullup current for active port I/O. Unloaded IVIO is included in all IBAT PM8 production test measurements. 14 Rev 1.1 SiM3 L1xx Table 3.3. Power Mode Wake Up Times Parameter Symbol Test Condition Min Typ Max Unit Power Mode 2 or 6 Wake Time tPM2 4 — 5 clocks Power Mode 3 Fast Wake Time (using LFO as clock source) tPM3FW — 425 — μs tPM8 — 3.8 — μs Power Mode 8 Wake Time Notes: 1. Wake times are specified as the time from the wake source to the execution phase of the first instruction following WFI. This includes latency to recognize the wake event and fetch the first instruction (assuming wait states = 0). Table 3.4. Reset and Supply Monitor Parameter Symbol Test Condition Min Typ Max Unit VBAT High Supply Monitor Threshold (VBATHITHEN = 1) VVBATMH Early Warning — 2.20 — V Reset 1.95 2.05 2.1 V VBAT Low Supply Monitor Threshold (VBATHITHEN = 0) VVBATML Early Warning — 1.85 — V Reset 1.70 1.75 1.77 V Rising Voltage on VBAT — 1.4 — V Falling Voltage on VBAT 0.8 1 1.3 V Power-On Reset (POR) Threshold VPOR VBAT Ramp Time tRMP Time to VBAT > 1.8 V 10 — 3000 μs Reset Delay from POR tPOR Relative to VBAT > VPOR 3 — 100 ms Reset Delay from non-POR source tRST Time between release of reset source and code execution — 10 — μs RESET Low Time to Generate Reset tRSTL 50 — — ns Missing Clock Detector Response Time (final rising edge to reset) tMCD — 0.5 1.5 ms Missing Clock Detector Trigger Frequency FMCD — 2.5 10 kHz VBAT Supply Monitor Turn-On Time tMON — 2 — μs FAHB > 1 MHz Rev 1.1 15 SiM3L1xx Table 3.5. On-Chip Regulators Parameter Symbol Test Condition Min Typ Max Unit VDCIN 1.8 — 3.8 V Input Supply to Output Voltage Differential (for regulation) VDCREG 0.45 — — V Output Voltage Range VDCOUT 1.25 — 3.8 V Output Voltage Accuracy VDCACC — ±25 — mV Output Current IDCOUT — — 90 mA LDC 0.47 0.56 0.68 μH Iload < 50 mA 450 — — mA Iload > 50 mA 550 — — mA CDCOUT 1 2.2 10 μF CDCIN — 4.7 — μF Rload — 0.03 — mV/mA Maximum DC Load Current During Startup IDCMAX — — 5 mA Switching Clock Frequency FDCCLK 1.9 2.9 3.8 MHz Local Oscillator Frequency FDCOSC 2.4 2.9 3.4 MHz Sourced from VBAT 1.8 — 3.8 V Sourced from VDC 1.9 — 3.8 V VLDO 0.8 — 1.9 V VLDOACC — ±25 — mV DC-DC Buck Converter Input Voltage Range Inductor Value 1 Inductor Current Rating Output Capacitor Value Input Capacitor Value2 Load Regulation ILDC LDO Regulators Input Voltage Range3 Output Voltage Range4 LDO Output Voltage Accuracy Output Settings in PM8 (All LDOs) VLDOIN VLDO 1.8 V < VBAT < 2.9 V 1.5 V 1.95 V < VBAT < 3.5 V 1.8 V 2.0 V < VBAT < 3.8 V 1.9 V Notes: 1. See reference manual for recommended inductors. 2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10 m (@ frequency > 1 MHz). 3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure that the LDO output voltage will remain at a valid level as long as VLDOIN is at or above the specified minimum. 4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO. When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO. 5. Output range represents the programmable output range, and does not reflect the minimum voltage under all conditions. Dropout when the input supply is close to the output setting is normal, and accounted for. 6. Analog peripheral specifications assume a 1.8 V output on the analog LDO. 16 Rev 1.1 SiM3 L1xx Table 3.5. On-Chip Regulators (Continued) Parameter Memory LDO Output Setting5 Digital LDO Output Setting Analog LDO Output Setting During Normal Operation6 Symbol Test Condition Min Typ Max Unit VLDOMEM During Programming 1.8 — 1.9 V During Normal Operation 1.5 — 1.9 V FAHB < 20 MHz 1.0 — 1.9 V FAHB > 20 MHz 1.2 — 1.9 V VLDODIG VLDOANA 1.8 V Notes: 1. See reference manual for recommended inductors. 2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10 m (@ frequency > 1 MHz). 3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure that the LDO output voltage will remain at a valid level as long as VLDOIN is at or above the specified minimum. 4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO. When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO. 5. Output range represents the programmable output range, and does not reflect the minimum voltage under all conditions. Dropout when the input supply is close to the output setting is normal, and accounted for. 6. Analog peripheral specifications assume a 1.8 V output on the analog LDO. Rev 1.1 17 SiM3L1xx Table 3.6. Flash Memory Symbol Test Condition Min Typ Max Unit Time1 Parameter tWRITE One 16-bit Half Word 20 21 22 μs Erase Time1 tERASE One Page 20 21 22 ms tERALL Full Device 20 21 22 ms 20k 100k — Cycles 10 100 — Years Write Endurance (Write/Erase Cycles) NWE Retention2 tRET TA = 25 °C, 1k Cycles Notes: 1. Does not include sequencing time before and after the write/erase operation, which may take up to 35 μs. During sequential write operations, this extra time is only taken prior to the first write and after the last write. 2. Additional Data Retention Information is published in the Quarterly Quality and Reliability Report. 18 Rev 1.1 SiM3 L1xx Table 3.7. Internal Oscillators Parameter Symbol Test Condition Min Typ Max Unit fPLL0OSC Full Temperature and Supply Range 48.3 49 49.7 MHz Power Supply Sensitivity (Free-running output mode, RANGE = 2) PSSPLL0OSC TA = 25 °C, Fout = 49 MHz — 300 — ppm/V Temperature Sensitivity (Free-running output mode, RANGE = 2) TSPLL0OSC VBAT = 3.3 V, Fout = 49 MHz — 50 — ppm/°C 23 — 50 MHz fREF = 20 MHz, fPLL0OSC = 50 MHz M=39, N=99, LOCKTH = 0 — 2.75 — μs fREF = 2.5 MHz, fPLL0OSC = 50 MHz M=19, N=399, LOCKTH = 0 — 9.45 — μs fREF = 32.768 kHz, fPLL0OSC = 50 MHz M=0, N=1524, LOCKTH = 0 — 92 — μs Phase-Locked Loop (PLL0OSC) Calibrated Output Frequency (Free-running output mode, RANGE = 2) Adjustable Output Frequency Range fPLL0OSC Lock Time tPLL0LOCK Low Power Oscillator (LPOSC0) Oscillator Frequency fLPOSC Full Temperature and Supply Range 19 20 21 MHz Divided Oscillator Frequency fLPOSCD Full Temperature and Supply Range 2.375 2.5 2.625 MHz Power Supply Sensitivity PSSLPOSC TA = 25 °C — 0.5 — %/V Temperature Sensitivity TSLPOSC VBAT = 3.3 V — 55 — ppm/°C Full Temperature and Supply Range 13.4 16.4 19.7 kHz TA = 25 °C, VBAT = 3.3 V 15.8 16.4 17.3 kHz Low Frequency Oscillator (LFOSC0) Oscillator Frequency fLFOSC Power Supply Sensitivity PSSLFOSC TA = 25 °C — 2.4 — %/V Temperature Sensitivity TSLFOSC VBAT = 3.3 V — 0.2 — %/°C Rev 1.1 19 SiM3L1xx Table 3.7. Internal Oscillators (Continued) Parameter Symbol Test Condition Min Typ Max Unit fRTCMCD — 8 15 kHz fRTCEXTCLK 0 — 40 kHz DCRTC 25 — 55 % Min Typ Max Unit RTC0 Oscillator (RTC0OSC) Missing Clock Detector Trigger Frequency RTC External Input CMOS Clock Frequency RTC Robust Duty Cycle Range Table 3.8. External Oscillator Parameter Symbol Test Condition External Input CMOS Clock Frequency fCMOS 0* — 50 MHz External Crystal Frequency fXTAL 0.01 — 25 MHz External Input CMOS Clock High Time tCMOSH 9 — — ns External Input CMOS Clock Low Time tCMOSL 9 — — ns VBAT 2.4 — 3.8 V Low Power Mode Charge Pump Supply Range (input from VBAT) *Note: Minimum of 10 kHz when debugging. 20 Rev 1.1 SiM3 L1xx Table 3.9. SAR ADC Parameter Resolution Supply Voltage Requirements (VBAT) Symbol Test Condition Nbits 12 Bit Mode 12 Bits 10 Bit Mode 10 Bits VADC Throughput Rate (High Speed Mode) fS Throughput Rate (Low Power Mode) fS Tracking Time SAR Clock Frequency tTRK fSAR Min Typ Max Unit High Speed Mode 2.2 — 3.8 V Low Power Mode 1.8 — 3.8 V 12 Bit Mode — — 250 ksps 10 Bit Mode — — 1 Msps 12 Bit Mode — — 62.5 ksps 10 Bit Mode — — 250 ksps High Speed Mode 230 — — ns Low Power Mode 450 — — ns High Speed Mode — — 16.24 MHz Low Power Mode — — 4 MHz Conversion Time tCNV 10-Bit Conversion, SAR Clock = 16 MHz, APB Clock = 40 MHz Sample/Hold Capacitor CSAR Gain = 1 — 5 — pF Gain = 0.5 — 2.5 — pF High Quality Inputs — 18 — pF Normal Inputs — 20 — pF High Quality Inputs — 300 — Normal Inputs — 550 — 1 — VBAT V Gain = 1 0 — VREF V Gain = 0.5 0 — 2xVREF V — 70 — dB 12 Bit Mode — ±1 ±1.9 LSB 10 Bit Mode — ±0.2 ±0.5 LSB 12 Bit Mode –1 ±0.7 1.8 LSB 10 Bit Mode — ±0.2 ±0.5 LSB 12 Bit Mode, VREF = 2.4 V –2 0 2 LSB 10 Bit Mode, VREF = 2.4 V –1 0 1 LSB Input Pin Capacitance Input Mux Impedance Voltage Reference Range Input Voltage Range* Power Supply Rejection Ratio CIN RMUX VREF VIN PSRRADC 762.5 ns DC Performance Integral Nonlinearity INL Differential Nonlinearity (Guaranteed Monotonic) DNL Offset Error (using VREFGND) EOFF Rev 1.1 21 SiM3L1xx Table 3.9. SAR ADC (Continued) Parameter Offset Temperature Coefficient Slope Error Symbol Test Condition Min Typ Max Unit TCOFF — 0.004 — LSB/°C EM –0.07 –0.02 0.02 % Dynamic Performance (10 kHz Sine Wave Input 1dB below full scale, Max throughput) Signal-to-Noise Signal-to-Noise Plus Distortion SNR SNDR Total Harmonic Distortion (Up to 5th Harmonic) THD Spurious-Free Dynamic Range SFDR 12 Bit Mode 62 66 — dB 10 Bit Mode 58 60 — dB 12 Bit Mode 62 66 — dB 10 Bit Mode 58 60 — dB 12 Bit Mode — 78 — dB 10 Bit Mode — 77 — dB 12 Bit Mode — –79 — dB 10 Bit Mode — –74 — dB *Note: Absolute input pin voltage is limited by the lower of the supply at VBAT and VIO. 22 Rev 1.1 SiM3 L1xx Table 3.10. IDAC Parameter Symbol Test Condition Min Typ Max Unit Static Performance Resolution Nbits Integral Nonlinearity INL — ±0.5 ±2 LSB Differential Nonlinearity (Guaranteed Monotonic) DNL — ±0.5 ±1 LSB Output Compliance Range VOCR — — VBAT – 1.0 V Full Scale Output Current IOUT 2 mA Range, TA = 25 °C 1.98 2.046 2.1 mA 1 mA Range, TA = 25 °C 0.99 1.023 1.05 mA 0.5 mA Range, TA = 25 °C 491 511.5 525 μA — 250 — nA 2 mA Range — 100 — ppm/°C 2 mA Range — –220 — ppm/V — 1 — k — 1.2 — μs — 3 — μs Offset Error EOFF Full Scale Error Tempco TCFS VBAT Power Supply Rejection Ratio Test Load Impedance (to VSS) 10 RTEST Bits Dynamic Performance Output Settling Time to 1/2 LSB min output to max output Startup Time Rev 1.1 23 SiM3L1xx Table 3.11. ACCTR (Advanced Capture Counter) Parameter Symbol Test Condition Min Typ Max Unit LC Comparator Response Time, CMPMD = 11 (Highest Speed) tRESP0 +100 mV Differential — 100 — ns –100 mV Differential — 150 — ns LC Comparator Response Time, CMPMD = 00 (Lowest Power) tRESP3 +100 mV Differential — 1.4 — μs –100 mV Differential — 3.5 — μs CMPHYP = 00 — 0.37 — mV CMPHYP = 01 — 7.9 — mV CMPHYP = 10 — 16.7 — mV CMPHYP = 11 — 32.8 — mV CMPHYN = 00 — 0.37 — mV CMPHYN = 01 — –7.9 — mV CMPHYN = 10 — –16.1 — mV CMPHYN = 11 — –32.7 — mV CMPHYP = 00 — 0.47 — mV CMPHYP = 01 — 5.85 — mV CMPHYP = 10 — 12 — mV CMPHYP = 11 — 24.4 — mV CMPHYN = 00 — 0.47 — mV CMPHYN = 01 — –6.0 — mV CMPHYN = 10 — –12.1 — mV CMPHYN = 11 — –24.6 — mV CMPHYP = 00 — 0.66 — mV CMPHYP = 01 — 4.55 — mV CMPHYP = 10 — 9.3 — mV CMPHYP = 11 — 19 — mV CMPHYN = 00 — 0.6 — mV CMPHYN = 01 — –4.5 — mV CMPHYN = 10 — –9.5 — mV CMPHYN = 11 — –19 — mV LC Comparator Positive Hysteresis Mode 0 (CPMD = 11) LC Comparator Negative Hysteresis Mode 0 (CPMD = 11) LC Comparator Positive Hysteresis Mode 1 (CPMD = 10) LC Comparator Negative Hysteresis Mode 1 (CPMD = 10) LC Comparator Positive Hysteresis Mode 2 (CPMD = 01) LC Comparator Negative Hysteresis Mode 2 (CPMD = 01) 24 HYSCP+ HYSCP- HYSCP+ HYSCP- HYSCP+ HYSCP- Rev 1.1 SiM3 L1xx Table 3.11. ACCTR (Advanced Capture Counter) (Continued) Parameter Symbol Test Condition Min Typ Max Unit HYSCP+ CMPHYP = 00 — 1.37 — mV CMPHYP = 01 — 3.8 — mV CMPHYP = 10 — 7.8 — mV CMPHYP = 11 — 15.6 — mV CMPHYN = 00 — 1.37 — mV CMPHYN = 01 — –3.9 — mV CMPHYN = 10 — –7.9 — mV CMPHYN = 11 — –16 — mV VIN –0.25 — VBAT + 0.25 V LC Comparator Common-Mode Rejection Ratio CMRRCP — 75 — dB LC Comparator Power Supply Rejection Ratio PSRRCP — 72 — dB LC Comparator Input Offset Voltage VOFF –10 0 10 mV LC Comparator Input Offset Tempco TCOFF — 3.5 — μV/°C DACEOFF –1 — 1 LSB Low Range — VIO/8 — V High Range — VIO — V Low Range (48 steps) — VIO/384 — V High Range (64 steps) — VIO/64 — V — 25 — ns — 1 — k — — 2 mA PUVAL[4:2] = 0 to 6 -15 — 15 % PUVAL[4:2] = 7 -10 — 10 % LC Comparator Positive Hysteresis Mode 3 (CPMD = 00) LC Comparator Negative Hysteresis Mode 3 (CPMD = 00) LC Comparator Input Range (ACCTR0_LCIN pin) Reference DAC Offset Error Reference DAC Full Scale Output Reference DAC Step Size HYSCP- DACFS DACLSB LC Oscillator Period TLCOSC LC Bias Output Impedance RLCBIAS LC Bias Drive Strength ILCBIAS Pull-Up Resistor Tolerance RTOL TA = 25 °C 10 μA Load Rev 1.1 25 SiM3L1xx Table 3.12. Voltage Reference Electrical Characteristics Parameter Internal Fast Settling Reference Output Voltage Symbol Test Condition Min Typ Max Unit VREFFS –40 to +85 °C, VBAT = 1.8–3.8 V 1.6 1.65 1.7 V Temperature Coefficient TCREFFS — 50 — ppm/°C tREFFS — — 1.5 μs PSRRREFFS — 400 — ppm/V VREF2X = 0 1.8 — 3.8 V VREF2X = 1 2.7 — 3.8 V 25 °C ambient, VREF2X = 0 1.17 1.2 1.23 V 25 °C ambient, VREF2X = 1 2.35 2.4 2.45 V ISC — — 10 mA Temperature Coefficient TCVREFP — 35 — ppm/°C Load Regulation LRVREFP Load = 0 to 200 μA to VREFGND — 4.5 — ppm/μA Load Capacitor CVREFP Load = 0 to 200 μA to VREFGND 0.1 — — μF tVREFPON 4.7 μF tantalum, 0.1 μF ceramic bypass — 3.8 — ms 0.1 μF ceramic bypass — 200 — μs VREF2X = 0 — 320 — ppm/V VREF2X = 1 — 560 — ppm/V Sample Rate = 250 ksps; VREF = 3.0 V — 5.25 — μA Turn-on Time Power Supply Rejection Internal Precision Reference VBAT Valid Supply Range VREFP Output Voltage Short-Circuit Current Turn-on Time Power Supply Rejection PSRRVREFP External Reference IEXTREF Input Current Table 3.13. Temperature Sensor Parameter Symbol Test Condition Min Typ Max Unit Offset VOFF TA = 0 °C — 760 — mV Offset Error* EOFF TA = 0 °C — ±14 — mV Slope M — 2.77 — mV/°C Slope Error* EM — ±25 — μV/°C Linearity — 1 — °C Turn-on Time — 1.8 — μs *Note: Absolute input pin voltage is limited by the lower of the supply at VBAT and VIO. 26 Rev 1.1 SiM3 L1xx Table 3.14. Comparator Parameter Symbol Test Condition Min Typ Max Unit Response Time, CMPMD = 00 (Highest Speed) tRESP0 +100 mV Differential — 100 — ns –100 mV Differential — 150 — ns Response Time, CMPMD = 11 (Lowest Power) tRESP3 +100 mV Differential — 1.4 — μs –100 mV Differential — 3.5 — μs CMPHYP = 00 — 0.37 — mV CMPHYP = 01 — 7.9 — mV CMPHYP = 10 — 16.7 — mV CMPHYP = 11 — 32.8 — mV CMPHYN = 00 — 0.37 — mV CMPHYN = 01 — –7.9 — mV CMPHYN = 10 — –16.1 — mV CMPHYN = 11 — –32.7 — mV CMPHYP = 00 — 0.47 — mV CMPHYP = 01 — 5.85 — mV CMPHYP = 10 — 12 — mV CMPHYP = 11 — 24.4 — mV CMPHYN = 00 — 0.47 — mV CMPHYN = 01 — –6.0 — mV CMPHYN = 10 — –12.1 — mV CMPHYN = 11 — –24.6 — mV CMPHYP = 00 — 0.66 — mV CMPHYP = 01 — 4.55 — mV CMPHYP = 10 — 9.3 — mV CMPHYP = 11 — 19 — mV CMPHYN = 00 — 0.6 — mV CMPHYN = 01 — –4.5 — mV CMPHYN = 10 — –9.5 — mV CMPHYN = 11 — –19 — mV Positive Hysteresis Mode 0 (CPMD = 00) Negative Hysteresis Mode 0 (CPMD = 00) Positive Hysteresis Mode 1 (CPMD = 01) Negative Hysteresis Mode 1 (CPMD = 01) Positive Hysteresis Mode 2 (CPMD = 10) Negative Hysteresis Mode 2 (CPMD = 10) HYSCP+ HYSCP- HYSCP+ HYSCP- HYSCP+ HYSCP- Rev 1.1 27 SiM3L1xx Table 3.14. Comparator (Continued) Parameter Positive Hysteresis Mode 3 (CPMD = 11) Negative Hysteresis Mode 3 (CPMD = 11) Symbol Test Condition Min Typ Max Unit HYSCP+ CMPHYP = 00 — 1.37 — mV CMPHYP = 01 — 3.8 — mV CMPHYP = 10 — 7.8 — mV CMPHYP = 11 — 15.6 — mV CMPHYN = 00 — 1.37 — mV CMPHYN = 01 — –3.9 — mV CMPHYN = 10 — –7.9 — mV CMPHYN = 11 — –16 — mV HYSCP- Input Range (CP+ or CP–) VIN –0.25 — VBAT + 0.25 V Input Pin Capacitance CCP — 7.5 — pF Common-Mode Rejection Ratio CMRRCP — 75 — dB Power Supply Rejection Ratio PSRRCP — 72 — dB –10 0 10 mV — 3.5 — μV/°C Input Offset Voltage VOFF Input Offset Tempco TCOFF Reference DAC Resolution TA = 25 °C NBits 6 bits Table 3.15. LCD0 Parameter Min Typ Max Unit Charge Pump Output Voltage Error VCPERR — ±50 — mV LCD Clock Frequency 16 — 33 kHz 28 Symbol Test Condition FLCD Rev 1.1 SiM3 L1xx Table 3.16. Port I/O Parameter Output High Voltage (PB0, PB1, PB3, or PB4) Output High Voltage (PB2) Output Low Voltage (any Port I/O pin or RESET1) Symbol Test Condition Min Typ Max Unit VOH Low Drive, IOH = –1 mA VIO – 0.7 — — V Low Drive, IOH = –10 μA VIO – 0.1 — — V High Drive, IOH = –3 mA VIO – 0.7 — — V High Drive, IOH = –10 μA VIO – 0.1 — — V Low Drive, IOH = –1 mA VIORF – 0.7 — — V Low Drive, IOH = –10 μA VIORF – 0.1 — — V High Drive, IOH = –3 mA VIORF – 0.7 — — V High Drive, IOH = –10 μA VIORF – 0.1 — — V Low Drive, IOL = 1.4 mA — — 0.6 V Low Drive, IOL = 10 μA — — 0.1 V High Drive, IOL = 8.5 mA — — 0.6 V High Drive, IOL = 10 μA — — 0.1 V VOH VOL Input High Voltage (PB0, PB1, PB3, PB4 or RESET) VIH VIO – 0.6 — — V Input High Voltage (PB2) VIH VIORF – 0.6 — — V Input Low Voltage any Port I/O pin or RESET) VIL — — 0.6 V Weak Pull-Up Current2 (per pin) IPU VIO or VIORF = 1.8 -6 -3.5 -2 μA VIO or VIORF = 3.8 -32 -20 -10 μA 0 < VIN < VIO or VIORF -1 — 1 μA Input Leakage (Pullups off or Analog) ILK Notes: 1. Specifications for RESET VOL adhere to the low drive setting. 2. On the SiM3L1x6 and SiM3L1x4 devices, the SWV pin will have double the weak pull-up current specified whenever the device is held in reset. Rev 1.1 29 SiM3L1xx 3.2. Thermal Conditions Table 3.17. Thermal Conditions Parameter Thermal Resistance* Symbol Test Condition Min Typ Max Unit JA TQFP-80 Packages — 40 — °C/W QFN-64 Packages — 25 — °C/W TQFP-64 Packages — 30 — °C/W QFN-40 Packages — 30 — °C/W *Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad. 30 Rev 1.1 SiM3 L1xx 3.3. Absolute Maximum Ratings Stresses above those listed under Table 3.18 may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3.18. Absolute Maximum Ratings Parameter Symbol Test Condition Min Max Unit Ambient Temperature Under Bias TBIAS –55 125 °C Storage Temperature TSTG –65 150 °C Voltage on VBAT/VBATDC VBAT VSS–0.3 4.2 V Voltage on VDC VDC VSSDC–0.3 4.2 V Voltage on VDRV VDRV VSS–0.3 4.2 V VIO VSS–0.3 4.2 V Voltage on VIORF VIORF VSS–0.3 4.2 V Voltage on VLCD VLCD VSS–0.3 4.2 V VIO > 3.3 V VSS–0.3 5.8 V VIO < 3.3 V VSS–0.3 VIO+2.5 V VIORF > 3.3 V VSS–0.3 5.8 V VIORF < 3.3 V VSS–0.3 VIORF+2.5 V Voltage on VIO Voltage on I/O (PB0, PB1, PB3, PB4) or RESET1 Voltage on PB2 I/O Pins1 VIN VIN Total Current Sunk into Supply Pins ISUPP VBAT/VBATDC, VIO, VIORF, VDRV, VDC, VLCD — 400 mA Total Current Sourced out of Ground Pins2 IVSS VSS, VSSDC 400 — mA Current Sourced or Sunk by any I/O Pin IPIO All I/O and RESET –100 100 mA Power Dissipation at TA = 85 °C PD TQFP-80 Packages — 500 mW QFN-64 Packages — 800 mW TQFP-64 Packages — 650 mW QFN-40 Packages — 650 mW Notes: 1. Exceeding the minimum VIO voltage may cause current to flow through adjacent device pins. 2. VSS and VSSDC provide separate return current paths for device supplies, but are not isolated. They must always be connected to the same potential on board. Rev 1.1 31 SiM3L1xx 4. Precision32™ SiM3L1xx System Overview The SiM3L1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 5.1 for specific product feature selection and part ordering numbers. Core: 32-bit ARM Cortex-M3 CPU. MHz maximum operating frequency. Branch target cache and prefetch buffers to minimize wait states. 50 32–256 kB flash; in-system programmable, 8–32 kB SRAM configurable to retention mode in 4 kB blocks. Blocks configured to retention mode preserve state in the low power PM8 mode. Power: Memory: Three adjustable low drop-out (LDO) regulators. buck converter allows dynamic voltage scaling for maximum efficiency (250 mW output). Power-on reset circuit and brownout detectors. Power Management Unit (PMU). Specialized charge pump reduces power consumption in low power modes. Process/Voltage/Temperature (PVT) Monitor. Register state retention in lowest power mode. DC-DC Up to 62 contiguous 5 V tolerant I/O pins and one flexible peripheral crossbar. Clock Sources: Internal oscillator with PLL: 23–50 MHz with ± 1.5% accuracy in free-running mode. I/O: Low-power internal oscillator: 20 MHz. internal oscillator: 16.4 kHz. External RTC crystal oscillator: 32.768 kHz. External oscillator: Crystal, RC, C, CMOS clock. Low-frequency Integrated Data LCD Controller (4x40). Peripherals: 10-Channel DMA Controller. x Data Transfer Managers. 128/192/256-bit Hardware AES Encryption. CRC with programmable 16-bit polynomial, one 32-bit polynomial, and bus snooping capability. Encoder / Decoder. 3 Timers/Counters: 3 x 32-bit Timers. x Enhanced Programmable Counter Array (EPCA). Real Time Clock (RTC0). Low Power Timer. Watchdog Timer. Low Power Mode Advanced Capture Counter (ACCTR). 1 Communications Peripherals: 1 x USART with IrDA and ISO7816 SmartCard support. x UART that operates in low power mode (PM8). 2 x SPIs. 1 x I2C. 1 Analog: 1 x 12-Bit Analog-to-Digital Converter (SARADC). x 10-Bit Digital-to-Analog Converter (IDAC). 2 x Low-Current Comparators (CMP). 1 On-Chip Debugging With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillators, the SiM3L1xx devices are truly stand-alone system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing nonvolatile data storage and allowing field upgrades of the firmware. User firmware has complete control of all 32 Rev 1.1 SiM3 L1xx peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings. The on-chip debugging interface (SWJ-DP) allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging. Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (–40 to +85 °C). The SiM3L1xx devices are available in 40-pin or 64-pin QFN and 64-pin or 80-pin TQFP packages. All package options are lead-free and RoHS compliant. See Table 5.1 for ordering information. A block diagram is included in Figure 4.1. Figure 4.1. Precision32™ SiM3L1xx Family Block Diagram Rev 1.1 33 SiM3L1xx 4.1. Power The SiM3L1xx devices include a dc-dc buck converter that can take an input from 1.8–3.8 V and create an output from 1.25–3.8 V. In addition, SiM3L1xx devices include three low dropout regulators as part of the LDO0 module: one LDO powers the analog subsystems, one LDO powers the flash and SRAM memory at 1.8 V, and one LDO powers the digital and core circuitry. Each of these regulators can be independently powered from the dc-dc converter or directly from the battery voltage, and their outputs are adjustable to conserve system power. SiM3L1xx devices also include a low power charge pump in the PMU module for use in low power modes (PM8) to further reduce the power consumption of the device. Figure 4.2 shows the power system configuration of these devices. Figure 4.2. SiM3L1xx Power 4.1.1. DC-DC Buck Converter (DCDC0) SiM3L1xx devices include an on-chip step-down dc-dc converter to efficiently utilize the energy stored in the battery, thus extending the operational life time. The dc-dc converter is a switching buck converter with a programmable output voltage that should be at least 0.45 V lower than the input battery voltage; if this criteria is not met and the converter can no longer operate, the output of the dc-dc converter automatically connects to the battery. The dc-dc converter can supply up to 100 mA and can be used to power the MCU and/or external devices in the system. The dc-dc converter has a built in voltage reference and oscillator and will automatically limit or turn off the switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a secondary power source (when available) in order to preserve battery life. When enabled, the dc-dc converter can source current into the output capacitor, but cannot sink current. The dc-dc converter includes the following features: Efficiently utilizes the energy stored in a battery, extending its operational lifetime. Input range: 1.8 to 3.8 V. Output range: 1.25 to 3.8 V in 50 mV (1.25–1.8 V) or 100 mV (1.8–3.8 V) steps. Supplies up to 100 mA. Includes a voltage reference and an oscillator. 34 Rev 1.1 SiM3 L1xx Supports synchronizing the regulator switching with the system clock. limits the peak inductor current if the load current rises beyond a safe limit. Automatically goes into bypass mode if the battery voltage cannot provide sufficient headroom. Sources current, but cannot sink current. 4.1.2. Three Low Dropout LDO Regulators (LDO0) The SiM3L1xx devices include one LDO0 module with three low dropout regulators. Each of these regulators have independent switches to select the battery voltage or the output of the dc-dc converter as the input to each LDO, and an adjustable output voltage. The LDOs consume little power and provide flexibility in choosing a power supply for the system. Each regulator can be independently adjusted between 0.8 and 1.9 V output. 4.1.3. Voltage Supply Monitor (VMON0) The SiM3L1xx devices include a voltage supply monitor that can monitor the main supply voltage. This module includes the following features: Main supply “VBAT Low” (VBAT below the early warning threshold) notification. Holds the device in reset if the main VBAT supply drops below the VBAT Reset threshold. The voltage supply monitor allows devices to function in known, safe operating conditions without the need for external hardware. Automatically 4.1.4. Power Management Unit (PMU) The Power Management Unit on the SiM3L1xx manages the power systems of the device. It manages the powerup sequence during power on and the wake up sources for PM8. On power-up, the PMU ensures the core voltages are a proper value before core instruction execution begins. The VDRV pin powers external circuitry from either the VBAT battery input voltage or the output of the dc-dc converter on VDC. The PMU includes an internal switch to select one of these sources for the VDRV pin. The PMU has a specialized VBAT-divided-by-2 charge pump that can power some internal modules while in PM8 to save power. The PMU module includes the following features: Provides the enable or disable for the analog power system, including the three LDO regulators. Up to 14 pin wake inputs can wake the device from Power Mode 8. The Low Power Timer, RTC0 (alarms and oscillator failure), Comparator 0, Advanced Capture Counter, LCD0 VBAT monitor, UART0, low power mode charge pump failure, and the RESET pin can also serve as wake sources for Power Mode 8. Controls which 4 kB RAM blocks are retained while in Power Mode 8. Provides a PMU_Asleep signal to a pin as an indicator that the device is in PM8. Specialized charge pump to reduce power consumption in PM8. Provides control for the internal switch between VBAT and VDC to power the VDRV pin for external circuitry. 4.1.5. Device Power Modes The SiM3L1xx devices feature seven low power modes in addition to normal operating mode. Several peripherals provide wake up sources for these low power modes, including the Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator failure notification), Comparator 0 (CMP0), Advanced Capture Counter (ACCTR0), LCD VBAT monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake. In addition, all peripherals can have their clocks disabled to reduce power consumption whenever a peripheral is not being used using the clock control (CLKCTRL) registers. 4.1.5.1. Normal Mode (Power Mode 0) and Power Mode 4 Normal Mode and Power Mode 4 are fully operational modes with code executing from flash memory. PM4 is the same as Normal Mode, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs. Rev 1.1 35 SiM3L1xx 4.1.5.2. Power Mode 1 and Power Mode 5 Power Mode 1 and Power Mode 5 are fully operational modes with code executing from RAM. PM5 is the same as PM1, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs. Compared with the corresponding flash operational mode (Normal or PM4), the active power consumption of the device in these modes is reduced. Additionally, at higher speeds in PM1, the core throughput can also be increased because RAMdoesnot require additional wait states that reduce the instruction fetch speed. 4.1.5.3. Power Mode 2 and Power Mode 6 In Power Mode 2 and Power Mode 6, the core halts and the peripherals continue to run at the selected clock speed. PM6 is the same as PM2, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs. To place the device in PM2 or PM6, the core should execute a wait-for-interrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM2 or PM6 must be of a sufficient priority to be recognized by the core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Syncronization Barrier) operation prior to the WFI to ensure all bus accesses complete. When operating from the LFOSC0, PM6 can achieve similar power consumption to PM3, but with faster wake times and the ability to wake on any interrupt. 4.1.5.4. Power Mode 3 In Power Mode 3 the core and peripheral clocks are halted. The available sources to wake from PM3 are controlled by the Power Management Unit (PMU). A special Fast Wake option allows the core to wake faster by keeping the LFOSC0 or RTC0 clock active. Because the current consumption of these blocks is minimal, it is recommended to use the fast wake option. Before entering PM3, the DMA controller should be disabled, and the desired wake source(s) should be configured in the PMU. The SLEEPDEEP bit in the ARM System Control Register should be set, and the PMSEL bit in the CLKCTRL0_CONFIG register should be cleared to indicate that PM3 is the desired power mode. For fast wake, the core clocks (AHB and APB) should be configured to run from the LPOSC, and the PM3 Fast wake option and clock source should be selected in the PM3CN register. The device will enter PM3 on a WFI or WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must be of a sufficient priority to be recognized by the core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete. 4.1.5.5. Power Mode 8 In Power Mode 8, the core and most peripherals are completely powered down, but all registers and selected RAM blocks retain their state. The LDO regulators are disabled, so all active circuitry operates directly from VBAT. Alternatively, the PMU has a specialized VBAT-divided-by-2 charge pump that can power some internal modules while in PM8 to save power. The fully operational functions in this mode are: LPTIMER0 , RTC0, UART0 running from RTC0TCLK, PMU Pin Wake, the advanced capture counter, and the LCD controller. This mode provides the lowest power consumption for the device, but requires an appropriate wake up source or reset to exit. The available wake up or reset sources to wake from PM8 are controlled by the Power Management Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake. The available reset sources are: RESET pin, VBAT supply monitor, Comparator 0, Comparator 1, low power mode charge pump failure, RTC0 oscillator failure, or a PMU wake event. Before entering PM8, the desired wake source(s) should be configured in the PMU. The SLEEPDEEP bit in the ARM System Control Register should be set, and the PMSEL bit in the CLKCTRL0_CONFIG register should be set to indicate that PM8 is the desired power mode. The device will enter PM8 on a WFI or WFE instruction, and remain in PM8 until a reset configured by the PMU occurs. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete. 36 Rev 1.1 SiM3 L1xx 4.1.5.6. Power Mode Summary The power modes described above are summarized in Table 4.1. Table 3.2 and Table 3.3 provide more information on the power consumption and wake up times for each mode. Table 4.1. SiM3L1xx Power Modes Mode Normal Description Power Mode 1 (PM1) Power Mode 2 (PM2) Power Mode 3 (PM3) Power Mode 4 (PM4) Core operating at full speed Code executing from flash Full device operation Core operating at full speed Code executing from RAM Full device operation Higher CPU bandwidth than PM0 (RAM can operate with zero wait states at any frequency) Core halted AHB, APB and all peripherals operational at full speed Fast wakeup from any interrupt source All clocks to core and peripherals stopped Faster wake enabled by keeping LFOSC0 or RTC0TCLK active Wake on any wake source or reset source defined in the PMU Core operating at low speed Code executing from flash Same capabilities as PM0, operating at lower speed Lower clock speed enables lower LDO output settings to save power Power Mode 5 (PM5) Notes Core operating at low speed Code executing from RAM Core halted AHB, APB and all peripherals operational at low speed Power Mode 6 (PM6) Power Mode 8 (PM8) Low power sleep LDO regulators are disabled and all active circuitry operates directly from VBAT The following functions are available: ACCTR0, RTC0, UART0 running from RTC0TCLK, LPTIMER0, port match, and the LCD controller Register and RAM state retention Rev 1.1 Same capabilities as PM1, operating at lower speed Lower clock speed enables lower LDO output settings to save power Same capabilities as PM2, operating at lower speed Lower clock speed enables lower LDO output settings to save power When running from LFOSC0, power is similar to PM3, but the device wakes much faster Lowest power consumption Wake on any wake source or reset source defined in the PMU 37 SiM3L1xx 4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0) The Process/Voltage/Temperature monitor consists of two modules (TIMER2 and PVTOSC0) designed to monitor the digital circuit performance of the SiM3L1xx device. The PVT oscillator (PVTOSC0) consists of two oscillators, one operating from the memory LDO and one operating from the digital LDO. These oscillators have two independent speed options and provide the clocks for two 16-bit timers in the TIMER2 module using the EX input. By monitoring the resulting counts of the TIMER2 timers, firmware can monitor the current device performance and increase the scalable LDO regulator (LDO0) output voltages as needed or decrease the output voltages to save power. The PVT monitor has the following features: Two separate oscillators and timers for the memory and digital logic voltage domains. Two oscillator output divider settings. Provides a method for monitoring digital performance to allow firmware to adjust the scalable LDO regulator output voltages to the lowest level possible, saving power. 38 Rev 1.1 SiM3 L1xx 4.2. I/O 4.2.1. General Features The SiM3L1xx ports have the following features: 5 V tolerant. Push-pull or open-drain output modes to the VIO or VIORF voltage level. Analog or digital modes. Option for high or low output drive strength. Port Match allows the device to recognize a change on a port pin value. Internal pull-up resistors are enabled or disabled on a port-by-port basis. Two external interrupts with up to 16 inputs each provide monitoring capability for external signals. Internal Pulse Generator Timer (PB0 only) to generate simple square waves and pulses. 4.2.2. Crossbar The SiM3L1xx devices have one crossbar with the following features: Flexible peripheral assignment to port pins. Pins can be individually skipped to move peripherals as needed for design or layout considerations. The crossbar has a fixed priority for each I/O function and assigns these functions to the port pins. When a digital resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. Additionally, the crossbar will skip port pins whose associated bits in the PBSKIPEN registers are set. This provides flexibility when designing a system: pins involved with sensitive analog measurements can be moved away from digital I/O, and peripherals can be moved around the chip as needed to ease layout constraints. Rev 1.1 39 SiM3L1xx 4.3. Clocking The SiM3L1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is derived from one of seven sources: the RTC timer clock (RTC0TCLK), the Low Frequency Oscillator, the Low Power Oscillator, the divided Low Power Oscillator, the External Oscillator, the PLL0 Oscillator, and the VIORFCLK pin input. In addition, a divider for the AHB clock provides flexible clock options for the device. The APB clock services data peripherals and is synchronized with the AHB clock. The APB clock can be equal to the AHB clock or set to the AHB clock divided by two. The Clock Control module on SiM3L1xx devices allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. Most peripherals have clocks off by default after a power-on reset. Figure 4.3. SiM3L1xx Clocking 40 Rev 1.1 SiM3 L1xx 4.3.1. PLL (PLL0) The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in Free-Running mode without a reference frequency, Frequency-Locked to a reference frequency, or Phase-Locked to a reference frequency. The reference frequency for Frequency-Lock and Phase-Lock modes can use one of multiple sources (including the external oscillator) to provide maximum flexibility for different application needs. Because the PLL module generates its own clock, the DCO can be locked to a particular reference frequency and then moved to Free-Running mode to reduce system power and noise. The PLL module includes the following features: Three output ranges with output frequencies ranging from 23 to 50 MHz. Multiple reference frequency inputs, including the RTC0 oscillator, Low Power Oscillator, and external oscillator. Three output modes: Free-Running Digitally-Controlled Oscillator, Frequency-Locked, and Phase-Locked. Able to sense the rising edge or falling edge of the reference source. DCO frequency LSB dithering to provide finer average output frequencies. Spectrum spreading to reduce generated system noise. Low jitter and fast lock times.\ All output frequency updates (including dithering and spectrum spreading) can be temporarily suspended using the STALL bit during noise-sensitive measurements. 4.3.2. Low Power Oscillator (LPOSC0) The Low Power Oscillator is the default AHB oscillator on SiM3L1xx devices and enables or disables automatically, as needed. The default output frequency of this oscillator is factory calibrated to 20 MHz, and a divided 2.5 MHz version of this clock is also available as an AHB clock source. The Low Power Oscillator has the following features: 20 MHz and divided 2.5 MHz frequencies available for the AHB clock. Automatically starts and stops as needed. 4.3.3. Low Frequency Oscillator (LFOSC0) The low frequency oscillator (LFOSC) provides a low power internal clock source for the RTC0 timer and other peripherals on the device. No external components are required to use the low frequency oscillator, and the RTC1 and RTC2 pins do not need to be shorted together. The Low Frequency Oscillator has the following features: 16.4 kHz output frequency. 4.3.4. External Oscillators (EXTOSC0) The EXTOSC0 external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. The external oscillator output may be selected as the AHB clock or used to clock other modules independent of the AHB clock selection. The External Oscillator control has the following features: Support for external crystal, resonator, RC, C, or CMOS oscillators. Support for external CMOS frequencies from 10 kHz to 50 MHz. Support for external crystal frequencies from 10 kHz to 25 MHz. Various drive strengths for flexible crystal oscillator support. Internal frequency divide-by-two option available. Rev 1.1 41 SiM3L1xx 4.4. Integrated LCD Controller (LCD0) SiM3L1xx devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3-mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast control which is independent of the supply voltage. LCD timing is derived from the RTC timer clock (RTC0TCLK) to allow precise control over the refresh rate. The SiM3L1xx devices use registers to store the enabled/disabled state of individual LCD segments. All LCD waveforms are generated on-chip based on the contents of these registers with flexible waveform control to reduce power consumption wherever possible. An LCD blinking function is also supported on a subset of LCD segments. The LCD0 module has the following features: Up to 40 segment pins and 4 common pins. Supports LCDs with 1/2 or 1/3 bias. Includes an on-chip charge pump with programmable output that allows firmware to control the contrast independent of the supply voltage. The RTC timer clock (RTC0TCLK) determines the LCD timing and refresh rate. All LCD waveforms are generated on-chip based on the contents of the LCD0 registers with flexible waveform control. LCD segments can be placed in a discharge state for a configurable number of RTC clock cycles before switching to the next state to reduce power consumption due to display loading. Includes a VBAT monitor that can serve as a wakeup source for Power Mode 8. Supports four hardware auto-contrast modes: bypass, constant, minimum, and auto-bypass. Supports hardware blinking for up to 8 segments. 42 Rev 1.1 SiM3 L1xx 4.5. Data Peripherals 4.5.1. 10-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. The DMA controller has the following features: Utilizes ARM PrimeCell uDMA architecture. Implements 10 channels. DMA crossbar supports DTM0, DTM1, DTM2, SARADC0, IDAC0, I2C0, SPI0, SPI1, USART0, AES0, ENCDEC0, EPCA0, external pin triggers, and timers. Supports primary, alternate, and scatter-gather data structures to implement various types of transfers. Access allowed to all AHB and APB memory space. 4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2) The Data Transfer Manager is a module that collects DMA request signals from various peripherals and generates a series of master DMA requests based on a state-driven configuration. This master request drives a set of DMA channels to perform functions such as assembling and transferring communication packets to external devices. This capability saves power by allowing the core to remain in a low power mode during complex transfer operations. A combination of simple and peripheral scatter-gather DMA configurations can be used to perform complex operations while reducing memory requirements. The DTM acts as a side channel for the peripheral’s DMA control signals. When active, it manages the DMA control signals for the peripherals. When the DTMn module is inactive, the peripherals communicate directly to the DMA module. The DTMn module has the following features: State descriptions stored in RAM with up to 15 states supported per module. Supports up to 15 source peripherals and up to 15 destination peripherals per module, in addition to memory or peripherals that do not require a data request. Includes error detection and an optional transfer timeout. Includes notifications for state transitions. 4.5.3. 128/192/256-bit Hardware AES Encryption (AES0) The basic AES block cipher is implemented in hardware. The integrated hardware support for Cipher Block Chaining (CBC) and Counter (CTR) algorithms results in identical performance, memory bandwidth, and memory footprint between the most basic Electronic Codebook (ECB) algorithm and these more complex algorithms. This hardware accelerator translates to more core bandwidth available for other functions or a power savings for lowpower applications. The AES module includes the following features: Operates on 4-word (16-byte) blocks. Supports key sizes of 128, 192, and 256 bits for both encryption and decryption. Generates the round key for decryption operations. All cipher operations can be performed without any firmware intervention for multiple 4-word blocks (up to 32 kB). Support for various chained and stream-ciphering configurations with XOR paths on both the input and output. Internal 4-word FIFOs to facilitate DMA operations. Integrated key storage. Hardware acceleration for Electronic Codebook (ECB), Cipher-Block Chaining (CBC), and Counter (CTR) algorithms utilizing integrated counterblock generation and previous-block caching. Rev 1.1 43 SiM3L1xx 4.5.4. 16/32-bit Enhanced CRC (ECRC0) The ECRC module is designed to provide hardware calculations for flash memory verification and communications protocols. In addition to calculating a result from direct writes from firmware, the ECRC module can automatically snoop the APB bus and calculate a result from data written to or read from a particular peripheral. This allows for an automatic CRC result without directly feeding data through the ECRC module. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3). The 16-bit polynomial is fully programmable. The ECRC module includes the following features: Support for a programmable 16-bit polynomial and one fixed 32-bit polynomial. Byte-level bit reversal for the CRC input. Byte-order reorientation of words for the CRC input. Word or half-word bit reversal of the CRC result. Ability to configure and seed an operation in a single register write. Support for single-cycle parallel (unrolled) CRC computation for 32-, 16-, or 8-bit blocks. Capability to CRC 32 bits of data per peripheral bus (APB) clock. Automatic APB bus snooping. Support for DMA writes using firmware request mode. 4.5.5. Encoder / Decoder (ENCDEC0) The encoder / decoder module supports Manchester and Three-out-of-Six encoding and decoding from either firmware or DMA operations. This module has the following features: Supports Manchester and Three-out-of-Six encoding and decoding. Automatic flag clearing when writing the input or reading the output data registers. Writing to the input data register automatically initiates an encode or decode operation. Optional output in one’s complement format. Hardware error detection for invalid input data during decode operations, which helps reduce power consumption and packet turn-around time. Flexible byte swapping on the input or output data. 44 Rev 1.1 SiM3 L1xx 4.6. Counters/Timers 4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2) Each timer module is independent, and includes the following features: Operation as a single 32-bit or two independent 16-bit timers. Clocking options include the APB clock, the APB clock scaled using an 8-bit prescaler, the external oscillator, or falling edges on an external input pin (synchronized to the APB clock). Auto-reload functionality in both 32-bit and 16-bit modes. TIMER0 and TIMER1 have the following features: Up/Down count capability, controlled by an external input pin. Rising and falling edge capture modes. Low or high pulse capture modes. Period and duty cycle capture mode. Square wave output mode, which is capable of toggling an external pin at a given rate with 50% duty cycle. 32- or 16-bit pulse-width modulation mode. TIMER2 does not support the standard input/output features of TIMER0 and TIMER1. The TIMER2 EX signal is internally connected to the outputs of the PVTOSC0 oscillators. TIMER2 can use any of the counting modes that use EX as an input, including up/down mode, edge capture mode, and pulse capture mode. The TIMER2 CT signal is disconnected. 4.6.2. Enhanced Programmable Counter Array (EPCA0) The Enhanced Programmable Counter Array (EPCA) module is a timer/counter system allowing for complex timing or waveform generation. Multiple modules run from the same main counter, allowing for synchronous output waveforms. This module includes the following features: Three sets of channel pairs (six channels total) capable of generating complementary waveforms. Center- and edge-aligned waveform generation. Programmable dead times that ensure channel pairs are never active at the same time. Programmable clock divisor and multiple options for clock source selection. Waveform update scheduling. Option to function while the core is inactive. Multiple synchronization triggers. Pulse-Width Modulation (PWM) waveform generation. Rev 1.1 45 SiM3L1xx 4.6.3. Real-Time Clock (RTC0) The RTC module includes a 32-bit timer that allows up to 36 hours of independent time-keeping when used with a 32.768 kHz watch crystal. The RTC provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on SiM3L1xx devices. The RTC module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wide range of crystals. The RTC timer clock can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. The module also includes a low power internal low frequency oscillator that reduces low power mode current and is available for other modules to use as a clock source. The RTC module includes the following features: 32-bit timer (supports up to 36 hours) with three separate alarms. Option for one alarm to automatically reset the RTC timer. Missing clock detector. Can be used with the internal Low Frequency Oscillator or with an external 32.768 kHz crystal (no additional resistors or capacitors necessary). Programmable internal loading capacitors support a wide range of external 32.768 kHz crystals. The RTC timer clock (RTC0CLK) can be buffered and routed to an I/O pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. The RTC module can be powered from the low power mode charge pump for lowest possible power consumption while in PM8. 4.6.4. Low Power Timer (LPTIMER0) The Low Power Timer (LPTIMER) module runs from the RTC timer clock (RTC0CLK), allowing the LPTIMER to operate even if the AHB and APB clocks are disabled. The LPTIMER counter can increment using one of two clock sources: the clock selected by the RTC0 module, or rising or falling edges of an external signal. The Low Power Timer includes the following features: Runs on low-frequency RTC timer clock (RTC0TCLK). The LPTIMER counter can increment using one of two clock sources: the RTC0TCLK or rising or falling edges of an external signal. Overflow and threshold-match detection. Timer reset on threshold-match allows square-wave generation at a variable output frequency. Supports PWM with configurable period and duty cycle. The LPTIMER module can be powered from the low power mode charge pump for lowest possible power consumption while in PM8. 4.6.5. Watchdog Timer (WDTIMER0) The WDTIMER module includes a 16-bit timer, a programmable early warning interrupt, and a programmable reset period. The timer registers are protected from inadvertent access by an independent lock and key interface. The watchdog timer runs from the low frequency oscillator (LFOSC0). The Watchdog Timer has the following features: Programmable timeout interval. Optional interrupt to warn when the Watchdog Timer is nearing the reset trip value. Lock-out feature to prevent any modification until a system reset. 46 Rev 1.1 SiM3 L1xx 4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0) The SiM3L1xx devices contain a low-power Advanced Capture Counter module that runs from the RTC0 clock domain and can be used with digital inputs, switch topology circuits (reed switches), or with LC resonant circuits. For switch topology circuits, the module charges one or two external lines by pulsing internal pull-up resistors and detecting whether the reed switch is open or closed. For LC resonant circuits, the inputs are periodically energized to produce a dampened sine wave and configurable discriminator circuits detect the resulting decay time-constant. The advanced capture counter has the following general features: Single or differential inputs supporting single, dual, and quadrature modes of operation. Variety of interrupt and PM8 wake up sources. Provides feedback of the direction history, current and previous states, and condition flags. The advanced capture counter has the following features for switch circuit topologies: Ultra low power input comparators. Supports a wide range of pull-up resistor values with a self-calibration engine. Asymmetrical integrators for low-pass filtering and switch debounce. Two 24-bit counters and two 24-bit digital threshold comparators. Supports switch flutter detection. For LC resonant circuit topologies, the advanced capture counter includes: Separate minimum and maximum count registers and polarity, pulse, and toggle controls. Zone-based programmable timing. Two input comparators with support for a positive side input bias at VIO divided by 2. Supports a configurable excitation pulse width based on a 40 MHz oscillator and timer or an external digital stop signal. Two 8-bit peak counters that saturate at full scale for detecting the number of LC resonant peaks. Two discriminators with programmable thresholds. Supports a sample and hold mode for Wheatstone bridges. All devices in the SiM3L1xx family include the low power mode advanced capture counter (ACCTR0). Table 4.2 lists the supported inputs and outputs for each of the packages. Table 4.2. SiM3L1xx Supported Advanced Capture Counter Inputs and Outputs Input/Output SiM3L1x7 SiM3L1x6 SiM3L1x4 ACCTR0_IN0 ACCTR0_IN1 ACCTR0_LCIN0 ACCTR0_LCIN1 ACCTR0_STOP0 ACCTR0_STOP1 ACCTR0_LCPUL0 ACCTR0_LCPUL1 ACCTR0_LCBIAS0 ACCTR0_LCBIAS1 ACCTR0_DBG0 ACCTR0_DBG1 Rev 1.1 47 SiM3L1xx 4.7. Communications Peripherals 4.7.1. USART (USART0) The USART uses two signals (TX and RX) to communicate serially with an external device. In addition to these signals, the USART module can optionally use a clock (UCLK) or hardware handshaking (RTS and CTS). The USART module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud rate generators. Synchronous or asynchronous transmissions and receptions. Clock master or slave operation with programmable polarity and edge controls. Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX or RX). Individual enables for generated clocks during start, stop, and idle states. Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from 5 to 9 bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the LIN SYNC byte. Automatic parity generation (with enable). Automatic start and stop generation (with separate enables). Transmit and receive hardware flow-control. Independent inversion correction for TX, RX, RTS, and CTS signals. IrDA modulation and demodulation with programmable pulse widths. Smartcard ACK/NACK support. Parity error, frame error, overrun, and underrun detection. Multi-master and half-duplex support. Multiple loop-back modes supported. Multi-processor communications support. 4.7.2. UART (UART0) The low-power UART uses two signals (TX and RX) to communicate serially with an external device. The UART0 module can operate in PM8 mode by taking the clock directly from the RTC0 time clock (RTC0TCLK) and running from the low power mode charge pump. This will allow the system to conserve power while transmitting or receiving UART traffic. The UART supports standard baud-rates of 9600, 4800, 2400 and 1200 in this low power mode. The UART0 module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud rate generators. Asynchronous transmissions and receptions. Up to 5 Mbaud (TX or RX). Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from 5 to 9 bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the LIN SYNC byte. Automatic parity generation (with enable). Automatic start and stop generation (with separate enables). Independent inversion correction for TX and RX signals. Parity error, frame error, overrun, and underrun detection. Half-duplex support. 48 Rev 1.1 SiM3 L1xx Multiple loop-back modes supported. Multi-processor communications support. Operates at 9600, 4800, 2400, or 1200 baud in Power Mode 8. 4.7.3. SPI (SPI0, SPI1) SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select signal. The SPI0 and SPI1 modules include the following features: Supports 3- or 4-wire master or slave modes. Supports up to 10 MHz clock in master mode and 5 MHz clock in slave mode. Support for all clock phase and slave select (NSS) polarity modes. 16-bit programmable clock rate. Programmable MSB-first or LSB-first shifting. 8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers. Support for multiple masters on the same data lines. In addition, the SPI modules include several features to support autonomous DMA transfers: Hardware NSS control. Programmable FIFO threshold levels. Configurable FIFO data widths. Master or slave hardware flow control for the MISO and MOSI signals. SPI1 is on fixed pins and supports additional flow control options using a fixed input (SPI1CTS). Neither SPI1 nor the flow control input are on the crossbar. 4.7.4. I2C (I2C0) The I2C interface is a two-wire, bi-directional serial bus. The clock and data signals operate in open-drain mode with external pull-ups to support automatic bus arbitration. Reads and writes to the interface are byte oriented with the I2C interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/8th of the APB clock as a master or slave, which can be faster than allowed by the I2C specification, depending on the clock source used. A method of extending the clocklow duration is available to accommodate devices with different speed capabilities on the same bus. The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/ stop control and generation. The I2C0 module includes the following features: Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds. Can operate down to APB clock divided by 32768 or up to APB clock divided by 8. Support for master, slave, and multi-master modes. Hardware synchronization and arbitration for multi-master mode. Clock low extending (clock stretching) to interface with faster masters. Hardware support for 7-bit slave and general call address recognition. Firmware support for 10-bit slave address decoding. Ability to disable all slave states. Programmable clock high and low period. Programmable data setup/hold times. Spike suppression up to 2 times the APB period. Rev 1.1 49 SiM3L1xx 4.8. Analog 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0) The SARADC0 module on SiM3L1xx devices implements the Successive Approximation Register (SAR) ADC architecture. The key features of the module are as follows: Single-ended 12-bit and 10-bit modes. Supports an output update rate of 250 k samples per second in 12-bit mode or 1 M samples per second in 10-bit mode. Operation in low power modes at lower conversion speeds. Selectable asynchronous hardware conversion trigger with hardware channel select. DC offset cancellation. Automatic result notification with multiple programmable thresholds. Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. Non-burst mode operation can also automatically accumulate multiple conversions, but a conversion start is required for each conversion. Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts supported. Flexible output data formatting. Sequencer allows up to eight sources to be automatically scanned using one of four channel characteristic profiles without software intervention. Eight-word conversion data FIFO for DMA operations. Includes two internal references (1.65 V fast-settling, 1.2/2.4 V precision), support for an external reference, and support for an external signal ground. 4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) The IDAC module takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC module includes the following features: 10-bit current DAC with support for four timer, up to seven external I/O and on demand output update triggers. Ability to update on rising, falling, or both edges for any of the external I/O trigger sources. Supports an output update rate greater than 600 k samples per second. Support for three full-scale output modes: 0.5 mA, 1.0 mA and 2.0 mA. Four-word FIFO to aid with high-speed waveform generation or DMA interactions. Individual FIFO overrun, underrun, and went-empty interrupt status sources. Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per word, or four 8-bit samples per word. Support for left- and right-justified data. 4.8.3. Low Current Comparators (CMP0, CMP1) The Comparators take two analog input voltages and output the relationship between these voltages (less than or greater than) as a digital signal. The low power comparator module includes the following features: Multiple sources for the positive and negative inputs, including VBAT, VREF, and 8 I/O pins. Two outputs available: a digital synchronous latched output and a digital asynchronous raw output. Programmable hysteresis and response time. Falling or rising edge interrupt options on the comparator output. 6-bit programmable reference divider. 50 Rev 1.1 SiM3 L1xx 4.9. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: The core halts program execution. Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. External port pins are forced to a known state. Interrupts and timers are disabled. AHB peripheral clocks to flash and RAM are enabled. Clocks to all APB peripherals other than the Watchdog Timer and DMAXBAR are disabled. All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For VBAT Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal lowpower oscillator. The Watchdog Timer is enabled with the low frequency oscillator as its clock source. Program execution begins at location 0x00000000. All RSTSRC0 registers may be locked against writes by setting the CLKRSTL bit in the LOCK0_PERIPHLOCK0 register to 1. The reset sources can also optionally reset individual modules, including the low power mode charge pump, UART0, LCD0, advanced capture counter (ACCTR0), and RTC0. Figure 4.4. SiM3L1xx Reset Sources Block Diagram Rev 1.1 51 SiM3L1xx 4.10. Security The peripherals on the SiM3L1xx devices have a register lock and key mechanism that prevents undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A key sequence must be written to the KEY register to modify bits in PERIPHLOCKx. Any subsequent write to KEY will then inhibit accesses of PERIPHLOCKx until it is unlocked again through KEY. Reading the KEY register indicates the current status of the PERIPHLOCKx lock state. If a peripheral’s registers are locked, all writes will be ignored. The registers can be read, regardless of the peripheral’s lock state. Figure 4.5. SiM3L1xx Security Block Diagram 4.11. On-Chip Debugging The SiM3L1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for instruction trace. The JTAG interface is supported on SiM3L1x7 devices only, and does not include boundary scan capabilites. The ETM interface is supported on SiM3L1x7, and SiM3L1x6 devices only. The JTAG and ETM interfaces can be optionally enabled to provide more visibility while debugging at the cost of using several Port I/O pins. Additionally, if the core is configured for Serial Wire (SW) mode and not JTAG, then the Serial Wire Viewer (SWV) is available to provide a single pin to send out TPIU messages. Serial Wire Viewer is supported on all SiM3Lxxx devices. Most peripherals on SiM3L1xx devices have the option to halt or continue functioning when the core halts in debug mode. 52 Rev 1.1 SiM3 L1xx 5. Ordering Information Figure 5.1. SiM3L1xx Part Numbering All devices in the SiM3L1xx family have the following features: Core: ARM Cortex-M3 with maximum operating frequency of 50 MHz. PLL. 10-Channel DMA Controller. 128/192/256-bit AES. 16/32-bit CRC. Encoder/Decoder. DC-DC Buck Converter. Timers: 3 x 32-bit (6 x 16-bit). Real-Time Clock. Low-Power Timer. PCA: 1 x 6 channels (Enhanced) ADC: 12-bit 250 ksps (10-bit 1 Msps) SAR. DAC: 10-bit IDAC. Temperature Sensor. Internal VREF. Comparator: 2 x low current. Serial Buses: 2 x USART, 2 x SPI, 1 x I2C Additionally, all devices in the SiM3L1xx family include the low power mode advanced capture counter (ACCTR0), though the smaller packages (SiM3L1x4) only support some of the external inputs and outputs. Rev 1.1 53 SiM3L1xx 51 34 23 14/12 11 SiM3L166-C-GQ 256 32 128 (4x32) 51 34 23 14/12 28 26 20 SiM3L164-C-GM 256 32 9/10 Package 128 (4x32) Lead-free (RoHS Compliant) Number of ACCTR0 Inputs and Outputs SiM3L166-C-GM 256 32 Serial Wire Debugging Interface Number of PMU Pin Wake Sources 12 ETM Debugging Interface Number of SARADC0 Channels 24 15/15 14 JTAG Debugging Interface Digital Port I/Os on the Crossbar 38 Number of Comparator 0/1 Inputs (+/-) Digital Port I/Os 62 RAM (kB) 160 (4x40) Flash Memory (kB) SiM3L167-C-GQ 256 32 Ordering Part Number LCD Segments Table 5.1. Product Selection Guide TQFP-80 12 QFN-64 11 12 TQFP-64 11 5 QFN-40 TQFP-80 SiM3L157-C-GQ 128 32 160 (4x40) 62 38 24 15/15 14 12 SiM3L156-C-GM 128 32 128 (4x32) 51 34 23 14/12 11 12 QFN-64 SiM3L156-C-GQ 128 32 128 (4x32) 51 34 23 14/12 11 12 TQFP-64 28 26 20 9/10 11 5 QFN-40 SiM3L154-C-GM 128 32 SiM3L146-C-GM 64 16 128 (4x32) 51 34 23 14/12 11 12 QFN-64 SiM3L146-C-GQ 64 16 128 (4x32) 51 34 23 14/12 11 12 TQFP-64 SiM3L144-C-GM 64 16 28 26 20 9/10 11 5 QFN-40 SiM3L136-C-GM 32 8 128 (4x32) 51 34 23 14/12 11 12 QFN-64 SiM3L136-C-GQ 32 8 128 (4x32) 51 34 23 14/12 11 12 TQFP-64 SiM3L134-C-GM 32 8 28 26 20 11 5 QFN-40 54 Rev 1.1 9/10 SiM3 L1xx 6. Pin Definitions 6.1. SiM3L1x7 Pin Definitions Figure 6.1. SiM3L1x7-GQ Pinout Rev 1.1 55 SiM3L1xx 12 VIO Power (I/O) 7 30 68 VIORF Power (RF I/O) 8 VBAT/ VBATDC 10 VDRV 9 VDC 13 IND Power (LCD Charge Pump) 67 DC-DC Inductor 11 RESET Active-low Reset 72 TCK/ SWCLK JTAG / Serial Wire 6 TMS/ SWDIO JTAG / Serial Wire 5 RTC1 RTC Oscillator Input 70 RTC2 RTC Oscillator Output 69 Rev 1.1 Analog Functions Ground (DCDC) External Trigger Inputs / Digital Functions VSSDC Output Toggle Logic 12 31 52 71 LCD Interface Ground Port Match VSS Crossbar Capability Type I/O Voltage Domain Pin Name VLCD 56 Pin Numbers (TQFP-80) Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 SiM3 L1xx Crossbar Capability Port Match Standard I/O 4 VIO INT0.0 WAKE.0 ADC0.20 VREF CMP0P.0 PB0.1 Standard I/O 3 VIO INT0.1 WAKE.1 ADC0.21 VREFGND CMP0N.0 PB0.2 Standard I/O 2 VIO INT0.2 WAKE.2 ADC0.22 CMP1P.0 XTAL2 PB0.3 Standard I/O 1 VIO INT0.3 WAKE.3 ADC0.23 CMP1N.0 XTAL1 PB0.4 Standard I/O 80 VIO INT0.4 WAKE.4 ADC0.0 CMP0P.1 IDAC0 PB0.5 Standard I/O 79 VIO INT0.5 WAKE.5 ACCTR0_STOP0 ACCTR0_IN0 PB0.6 Standard I/O 78 VIO INT0.6 WAKE.6 ACCTR0_STOP1 ACCTR0_IN1 PB0.7 Standard I/O 77 VIO INT0.7 WAKE.7 ACCTR0_LCIN0 PB0.8 Standard I/O 76 VIO LPT0T0 LPT0OUT0 INT0.8 WAKE.8 ACCTR0_LCIN1 Rev 1.1 Analog Functions I/O Voltage Domain PB0.0 Output Toggle Logic Type LCD Interface Pin Name Pin Numbers (TQFP-80) External Trigger Inputs / Digital Functions Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 57 SiM3L1xx 58 Crossbar Capability Port Match Standard I/O 75 VIO LPT0T1 INT0.9 WAKE.9 ACCTR0_LCPUL0 ADC0.1 CMP0N.1 PB0.10 Standard I/O 74 VIO LPT0T2 INT0.10 WAKE.10 ACCTR0_LCPUL1 ADC0.2 CMP1P.1 PB0.11/ TDO/SWV Standard I/O / JTAG / Serial Wire Viewer 73 VIO LPT0T3 LPT0OUT1 INT0.11 WAKE.11 ADC0.3 CMP1N.1 PB1.0 Standard I/O 66 VIO LCD0.39 LPT0T4 INT0.12 ACCTR0_LCBIAS0 CMP0P.2 PB1.1 Standard I/O 65 VIO LCD0.38 LPT0T5 INT0.13 ACCTR0_LCBIAS1 CMP0N.2 PB1.2 Standard I/O 64 VIO LCD0.37 LPT0T6 INT0.14 UART0_TX CMP1P.2 PB1.3 Standard I/O 63 VIO LCD0.36 LPT0T7 INT0.15 UART0_RX CMP1N.2 PB1.4 Standard I/O 62 VIO LCD0.35 ACCTR0_DBG0 ADC0.4 PB1.5 Standard I/O 61 VIO LCD0.34 ACCTR0_DBG1 ADC0.5 PB1.6/TDI Standard I/O / JTAG 60 VIO LCD0.33 PB1.7 Standard I/O 59 VIO LCD0.32 Rev 1.1 Analog Functions I/O Voltage Domain PB0.9 Output Toggle Logic Type LCD Interface Pin Name Pin Numbers (TQFP-80) External Trigger Inputs / Digital Functions Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) ADC0.6 RTC0TCLK_OUT ADC0.7 SiM3 L1xx Crossbar Capability Port Match Standard I/O 58 VIO LCD0.31 CMP0P.3 PB1.9 Standard I/O 57 VIO LCD0.30 CMP0N.3 PB1.10 Standard I/O 56 VIO LCD0.29 CMP1P.3 PB1.11 Standard I/O 55 VIO LCD0.28 CMP1N.3 PB2.0 Standard I/O 54 VIORF LPT0T8 INT1.0 WAKE.12 SPI1_CTS ADC0.8 CMP0P.4 PB2.1 Standard I/O 53 VIORF LPT0T9 INT1.1 WAKE.13 VIORFCLK ADC0.9 CMP0N.4 PB2.4 Standard I/O 51 VIORF LPT0T12 INT1.4 SPI1_SCLK ADC0.10 CMP0P.5 PB2.5 Standard I/O 50 VIORF LPT0T13 INT1.5 SPI1_MISO ADC0.11 CMP0N.5 PB2.6 Standard I/O 49 VIORF LPT0T14 INT1.6 SPI1_MOSI ADC0.12 CMP1P.5 PB2.7 Standard I/O 48 VIORF INT1.7 SPI1_NSS ADC0.13 CMP1N.5 PB3.0 Standard I/O 47 VIO LCD0.27 INT1.8 ADC0.14 PB3.1 Standard I/O 46 VIO LCD0.26 INT1.9 ADC0.15 PB3.2 Standard I/O 45 VIO LCD0.25 INT1.10 ADC0.16 PB3.3 Standard I/O 44 VIO LCD0.24 INT1.11 ADC0.17 Rev 1.1 Analog Functions I/O Voltage Domain PB1.8 Output Toggle Logic Type LCD Interface Pin Name Pin Numbers (TQFP-80) External Trigger Inputs / Digital Functions Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 59 SiM3L1xx 60 Crossbar Capability Port Match Standard I/O 43 VIO LCD0.23 INT1.12 CMP0P.6 PB3.5 Standard I/O 42 VIO LCD0.22 INT1.13 CMP0N.6 PB3.6 Standard I/O 41 VIO LCD0.21 INT1.14 CMP1P.6 PB3.7 Standard I/O 40 VIO LCD0.20 INT1.15 CMP1N.6 PB3.8 Standard I/O 39 VIO LCD0.19 CMP0P.7 PB3.9 Standard I/O 38 VIO LCD0.18 CMP0N.7 PB3.10 Standard I/O 37 VIO LCD0.17 CMP1P.7 PB3.11 Standard I/O 36 VIO LCD0.16 CMP1N.7 PB3.12 Standard I/O 35 VIO LCD0.15 ADC0.18 PB3.13 Standard I/O 34 VIO LCD0.14 ADC0.19 PB3.14 Standard I/O 33 VIO COM0.3 PB3.15 Standard I/O 32 VIO COM0.2 PB4.0 Standard I/O 29 VIO COM0.1 PB4.1 Standard I/O 28 VIO COM0.0 PB4.2 Standard I/O 27 VIO LCD0.13 PB4.3 Standard I/O 26 VIO LCD0.12 PB4.4 Standard I/O 25 VIO LCD0.11 PB4.5 Standard I/O 24 VIO LCD0.10 PB4.6 Standard I/O 23 VIO LCD0.9 PB4.7 Standard I/O 22 VIO LCD0.8 PB4.8 Standard I/O 21 VIO LCD0.7 Rev 1.1 PMU_Asleep Analog Functions I/O Voltage Domain PB3.4 Output Toggle Logic Type LCD Interface Pin Name Pin Numbers (TQFP-80) External Trigger Inputs / Digital Functions Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) SiM3 L1xx LCD Interface 20 VIO LCD0.6 PB4.10 Standard I/O 19 VIO LCD0.5 PB4.11/ ETM3 Standard I/O / ETM 18 VIO LCD0.4 PB4.12/ ETM2 Standard I/O / ETM 17 VIO LCD0.3 PB4.13/ ETM1 Standard I/O / ETM 16 VIO LCD0.2 PB4.14/ ETM0 Standard I/O / ETM 15 VIO LCD0.1 PB4.15/ TRACECLK Standard I/O / ETM 14 VIO LCD0.0 Rev 1.1 Analog Functions Port Match Standard I/O External Trigger Inputs / Digital Functions I/O Voltage Domain PB4.9 Output Toggle Logic Type Crossbar Capability Pin Name Pin Numbers (TQFP-80) Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) 61 SiM3L1xx 6.2. SiM3L1x6 Pin Definitions Figure 6.2. SiM3L1x6-GQ Pinout 62 Rev 1.1 SiM3 L1xx Figure 6.3. SiM3L1x6-GM Pinout Rev 1.1 63 SiM3L1xx External Trigger Inputs / Digital Functions Serial Wire 4 RTC1 RTC Oscillator Input 56 RTC2 RTC Oscillator Output 55 PB0.0 Standard I/O 3 VIO XBR 0 INT0.0 WAKE.0 ADC0.20 VREF CMP0P.0 PB0.1 Standard I/O 2 VIO XBR 0 INT0.1 WAKE.2 ADC0.22 CMP0N.0 CMP1P.0 XTAL2 VSSDC 10 41 Ground (DC-DC) 10 VIO Power (I/O) 6 VIORF / VDRV Power (RF I/O) 7 VBAT / VBATDC 8 VDC 11 VLCD Power (LCD Charge Pump) 54 IND DC-DC Inductor 9 RESET Analog Functions SWDIO Ground LCD Interface Crossbar Capability 5 VSS Port Match I/O Voltage Domain Serial Wire Type Pin Numbers SWCLK Pin Name 64 Output Toggle Logic Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 Active-low Reset 57 Rev 1.1 SiM3 L1xx Standard I/O 1 VIO XBR 0 INT0.2 WAKE.3 ADC0.23 CMP1N.0 XTAL1 PB0.3 Standard I/O 64 VIO XBR 0 INT0.3 WAKE.4 ADC0.0 CMP0P.1 IDAC0 PB0.4 Standard I/O 63 VIO XBR 0 INT0.4 WAKE.5 ACCTR0_STOP0 ACCTR0_IN0 PB0.5 Standard I/O 62 VIO XBR 0 INT0.5 WAKE.6 ACCTR0_STOP1 ACCTR0_IN1 PB0.6 Standard I/O 61 VIO XBR 0 INT0.6 WAKE.7 ACCTR0_LCIN0 PB0.7 Standard I/O 60 VIO XBR 0 LPT0T0 LPT0OUT0 INT0.7 WAKE.8 ACCTR0_LCIN1 PB0.8 Standard I/O 59 VIO XBR 0 LPT0T1 INT0.8 WAKE.9 ACCTR0_LCPUL0 ADC0.1 CMP0N.1 PB0.9/SWV Standard I/O /Serial Wire Viewer 58 VIO XBR 0 LPT0T2 INT0.9 WAKE.10 LPT0OUT1 ACCTR0_LCPUL1 ADC0.2 CMP1P.1 PB1.0 Standard I/O 53 VIO XBR 0 LPT0T4 INT0.12 ACCTR0_LCBIAS0 CMP0P.2 LCD0.31 Rev 1.1 Analog Functions Crossbar Capability External Trigger Inputs / Digital Functions I/O Voltage Domain PB0.2 LCD Interface Type Port Match Pin Name Pin Numbers Output Toggle Logic Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) 65 SiM3L1xx Crossbar Capability Port Match LCD Interface PB1.1 Standard I/O 52 VIO XBR 0 LCD0.30 LPT0T5 INT0.13 ACCTR0_LCBIAS1 CMP0N.2 PB1.2 Standard I/O 51 VIO XBR 0 LCD0.29 LPT0T6 INT0.14 UART0_TX CMP1P.2 PB1.3 Standard I/O 50 VIO XBR 0 LCD0.28 LPT0T7 INT0.15 UART0_RX CMP1N.2 PB1.4 Standard I/O 49 VIO XBR 0 LCD0.27 ACCTR0_DBG0 ADC0.3 PB1.5 Standard I/O 48 VIO XBR 0 LCD0.26 ACCTR0_DBG1 ADC0.4 PB1.6 Standard I/O 47 VIO XBR 0 LCD0.25 RTC0TCLK_OUT ADC0.5 PB1.7 Standard I/O 46 VIO XBR 0 LCD0.24 CMP0P.3 PB1.8 Standard I/O 45 VIO XBR 0 LCD0.23 CMP0N.3 PB1.9 Standard I/O 44 VIO XBR 0 LCD0.22 CMP1P.3 PB1.10 Standard I/O 43 VIO XBR 0 LCD0.21 CMP1N.3 PB2.0 Standard I/O 42 VIOR F XBR 0 LPT0T8 INT1.0 WAKE.12 SPI1_CTS ADC0.6 CMP0P.4 PB2.4 Standard I/O 40 VIOR F XBR 0 LPT0T12 INT1.4 SPI1_SCLK ADC0.7 CMP0P.5 66 Rev 1.1 Analog Functions Type I/O Voltage Domain External Trigger Inputs / Digital Functions Pin Name Pin Numbers Output Toggle Logic Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) SiM3 L1xx Standard I/O 39 VIOR F XBR 0 LPT0T13 INT1.5 SPI1_MISO ADC0.8 CMP0N.5 PB2.6 Standard I/O 38 VIOR F XBR 0 LPT0T14 INT1.6 SPI1_MOSI ADC0.9 CMP1P.5 PB2.7 Standard I/O 37 VIOR F XBR 0 INT1.7 SPI1_NSS ADC0.10 CMP1N.5 PB3.0 Standard I/O 36 VIO XBR 0 LCD0.20 INT1.8 ADC0.11 PB3.1 Standard I/O 35 VIO XBR 0 LCD0.19 INT1.9 ADC0.12 PB3.2 Standard I/O 34 VIO XBR 0 LCD0.18 INT1.10 CMP0P.6 PB3.3 Standard I/O 33 VIO XBR 0 LCD0.17 INT1.11 CMP0N.6 PB3.4 Standard I/O 32 VIO XBR 0 LCD0.16 INT1.12 CMP0P.7 PB3.5 Standard I/O 31 VIO XBR 0 LCD0.15 INT1.13 CMP0N.7 PB3.6 Standard I/O 30 VIO XBR 0 LCD0.14 INT1.14 CMP1P.7 PB3.7 Standard I/O 29 VIO XBR 0 LCD0.13 INT1.15 CMP1N.7 PB3.8 Standard I/O 28 VIO LCD0.12 ADC0.13 PB3.9 Standard I/O 27 VIO LCD0.11 ADC0.14 PB3.10 Standard I/O 26 VIO COM0.3 PB3.11 Standard I/O 25 VIO COM0.2 Rev 1.1 Analog Functions Crossbar Capability External Trigger Inputs / Digital Functions I/O Voltage Domain PB2.5 LCD Interface Type Port Match Pin Name Pin Numbers Output Toggle Logic Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) 67 SiM3L1xx Port Match LCD Interface Standard I/O 24 VIO COM0.1 PB4.1 Standard I/O 23 VIO COM0.0 PB4.2 Standard I/O 22 VIO LCD0.10 PB4.3 Standard I/O 21 VIO LCD0.9 PB4.4 Standard I/O 20 VIO LCD0.8 PB4.5 Standard I/O 19 VIO LCD0.7 PB4.6 Standard I/O 18 VIO LCD0.6 PB4.7 Standard I/O 17 VIO LCD0.5 PB4.8/ETM3 Standard I/O / ETM 16 VIO LCD0.4 PB4.9/ETM2 Standard I/O / ETM 15 VIO LCD0.3 PB4.10/ ETM1 Standard I/O / ETM 14 VIO LCD0.2 PB4.11/ ETM0 Standard I/O / ETM 13 VIO LCD0.1 PB4.12/ TRACECLK Standard I/O / ETM 12 VIO LCD0.0 68 Rev 1.1 Analog Functions I/O Voltage Domain PB4.0 External Trigger Inputs / Digital Functions Type Output Toggle Logic Pin Name Pin Numbers Crossbar Capability Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) ADC0.19 PMU_Asleep SiM3 L1xx 6.3. SiM3L1x4 Pin Definitions Figure 6.4. SiM3L1x4-GM Pinout Rev 1.1 69 SiM3L1xx Output Toggle Logic Standard I/O 2 VIO XBR0 INT0.0 WAKE.0 ADC0.20 VREF CMP0P.0 PB0.1 Standard I/O 1 VIO XBR0 INT0.1 WAKE.2 ADC0.22 CMP0N.0 CMP1P.0 XTAL2 Ground 9 25 VSSDC Ground (DC-DC) 9 VIO Power (I/O) 5 VIORF / VDRV Power (RF I/O) 6 VBAT / VBATDC 7 VDC 10 IND DC-DC Inductor 8 RESET Active-low Reset 35 SWCLK Serial Wire 4 SWDIO Serial Wire 3 Analog Functions Port Match PB0.0 VSS Crossbar Capability 33 Type I/O Voltage Domain RTC Oscillator Output Pin Numbers RTC2 Pin Name RTC1 70 External Trigger Inputs / Digital Functions Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 RTC Oscillator Input 34 Rev 1.1 SiM3 L1xx I/O Voltage Domain Port Match Output Toggle Logic PB0.2 Standard I/O 40 VIO XBR0 INT0.2 WAKE.3 ADC0.23 CMP0N.1 CMP1N.0 XTAL1 PB0.3 Standard I/O 39 VIO XBR0 INT0.3 WAKE.4 ADC0.0 CMP0P.1 IDAC0 PB0.4 Standard I/O 38 VIO XBR0 INT0.4 WAKE.5 ACCTR0_IN0 PB0.5 Standard I/O 37 VIO XBR0 INT0.5 WAKE.6 ACCTR0_IN1 PB0.6/SWV Standard I/O /Serial Wire Viewer 36 VIO XBR0 LPT0T0 LPT0OUT0 INT0.6 WAKE.8 PB0.7 Standard I/O 32 VIO XBR0 LPT0T6 INT0.7 UART0_TX CMP1P.2 PB0.8 Standard I/O 31 VIO XBR0 LPT0T7 INT0.8 UART0_RX CMP1N.2 PB0.9 Standard I/O 30 VIO XBR0 LPT0T1 INT0.9 RTC0TCLK_OUT ADC0.1 PB2.0 Standard I/O 29 VIORF XBR0 LPT0T8 INT1.0 WAKE.12 SPI1_CTS ADC0.2 CMP0P.4 Rev 1.1 Analog Functions Type Crossbar Capability Pin Name Pin Numbers External Trigger Inputs / Digital Functions Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) 71 SiM3L1xx 72 Analog Functions External Trigger Inputs / Digital Functions Output Toggle Logic Port Match Crossbar Capability I/O Voltage Domain Pin Numbers Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB2.1 Standard I/O 28 VIORF XBR0 LPT0T9 INT1.1 WAKE.13 VIORFCLK ADC0.3 CMP0N.4 PB2.2 Standard I/O 27 VIORF XBR0 LPT0T10 INT1.2 WAKE.14 ADC0.4 CMP1P.4 PB2.3 Standard I/O 26 VIORF XBR0 LPT0T11 INT1.3 WAKE.15 ADC0.5 CMP1N.4 PB2.4 Standard I/O 24 VIORF XBR0 LPT0T12 INT1.4 SPI1_SCLK ADC0.6 CMP0P.5 PB2.5 Standard I/O 23 VIORF XBR0 LPT0T13 INT1.5 SPI1_MISO ADC0.7 CMP0N.5 PB2.6 Standard I/O 22 VIORF XBR0 LPT0T14 INT1.6 SPI1_MOSI ADC0.8 CMP1P.5 PB2.7 Standard I/O 21 VIORF XBR0 INT1.7 SPI1_NSS ADC0.9 CMP1N.5 PB3.0 Standard I/O 20 VIO XBR0 INT1.8 CMP0N.7 PB3.1 Standard I/O 19 VIO XBR0 INT1.9 CMP1P.7 PB3.2 Standard I/O 18 VIO XBR0 INT1.10 CMP1N.7 PB3.3 Standard I/O 17 VIO XBR0 INT1.11 ADC0.10 PB3.4 Standard I/O 16 VIO XBR0 INT1.12 ADC0.11 PB3.5 Standard I/O 15 VIO XBR0 INT1.13 ADC0.12 Rev 1.1 SiM3 L1xx External Trigger Inputs / Digital Functions PB3.6 Standard I/O 14 VIO XBR0 INT1.14 ADC0.13 PB3.7 Standard I/O 13 VIO XBR0 INT1.15 ADC0.14 PB3.8 Standard I/O 12 VIO ADC0.15 PB3.9 Standard I/O 11 VIO ADC0.16 Rev 1.1 Analog Functions I/O Voltage Domain Output Toggle Logic Type Port Match Pin Name Pin Numbers Crossbar Capability Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) 73 SiM3L1xx 6.4. TQFP-80 Package Specifications Figure 6.5. TQFP-80 Package Drawing 74 Rev 1.1 SiM3 L1xx Table 6.4. TQFP-80 Package Dimensions Dimension Min Nominal Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 b 0.17 0.20 0.27 c 0.09 — 0.20 D 14.00 BSC D1 12.00 BSC e 0.50 BSC E 14.00 BSC E1 12.00 BSC L 0.45 0.60 L1 0.75 1.00 Ref 0° 3.5° aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 eee 0.05 7° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ADD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 75 SiM3L1xx Figure 6.6. TQFP-80 Landing Diagram Table 6.5. TQFP-80 Landing Diagram Dimensions Dimension Min Max C1 13.30 13.40 C2 13.30 13.40 E 0.50 BSC X 0.20 0.30 Y 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. 76 Rev 1.1 SiM3 L1xx 6.4.1. TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.4.2. TQFP-80 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.4.3. TQFP-80 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 77 SiM3L1xx 6.5. QFN-64 Package Specifications Figure 6.7. QFN-64 Package Drawing Table 6.6. QFN-64 Package Dimensions Dimension Min Nominal Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 9.00 BSC 3.95 4.10 e 0.50 BSC E 9.00 BSC 4.25 E2 3.95 4.10 4.25 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 78 Rev 1.1 SiM3 L1xx Figure 6.8. QFN-64 Landing Diagram Table 6.7. QFN-64 Landing Diagram Dimensions Dimension mm C1 8.90 C2 8.90 E 0.50 X1 0.30 Y1 0.85 X2 4.25 Y2 4.25 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Rev 1.1 79 SiM3L1xx 6.5.1. QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.5.2. QFN-64 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.0 mm square openings on a 1.5 mm pitch should be used for the center ground pad. 6.5.3. QFN-64 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 80 Rev 1.1 SiM3 L1xx 6.6. TQFP-64 Package Specifications Figure 6.9. TQFP-64 Package Drawing Rev 1.1 81 SiM3L1xx Table 6.8. TQFP-64 Package Dimensions Dimension Min Nominal Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 — 0.20 D 12.00 BSC D1 10.00 BSC e 0.50 BSC E 12.00 BSC E1 10.00 BSC L 0.45 0.60 0.75 0° 3.5° 7° aaa — — 0.20 bbb — — 0.20 ccc — — 0.08 ddd — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ACD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 82 Rev 1.1 SiM3 L1xx Figure 6.10. TQFP-64 Landing Diagram Table 6.9. TQFP-64 Landing Diagram Dimensions Dimension Min Max C1 11.30 11.40 C2 11.30 11.40 E 0.50 BSC X 0.20 0.30 Y 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Rev 1.1 83 SiM3L1xx 6.6.1. TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.6.2. TQFP-64 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.6.3. TQFP-64 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 84 Rev 1.1 SiM3 L1xx 6.7. QFN-40 Package Specifications Figure 6.11. QFN-40 Package Drawing Table 6.10. QFN-40 Package Dimensions Dimension Min Nominal Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 6.00 BSC 4.35 4.50 e 0.50 BSC E 6.00 BSC 4.65 E2 4.35 4.5 4.65 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 85 SiM3L1xx Figure 6.12. QFN-40 Landing Diagram Table 6.11. QFN-40 Landing Diagram Dimensions Dimension mm C1 5.90 C2 5.90 E 0.50 X1 0.30 Y1 0.85 X2 4.65 Y2 4.65 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. 86 Rev 1.1 SiM3 L1xx 6.7.1. QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.7.2. QFN-40 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.1 mm square openings on a 1.6 mm pitch should be used for the center ground pad. 6.7.3. QFN-40 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.1 87 SiM3L1xx 7. Revision Specific Behavior This chapter describes any differences between released revisions of the device. 7.1. Revision Identification The Lot ID Code on the top side of the device package can be used for decoding device revision information. Figures 7.1, 7.2, and 7.3 show how to find the Lot ID Code on the top side of the device package. In addition, firmware can determine the revision of the device by checking the DEVICEID registers. Figure 7.1. SiM3L1x7-GQ Revision Information Figure 7.2. SiM3L1x6-GM and SiM3L1x6-GQ Revision Information 88 Rev 1.1 SiM3 L1xx Figure 7.3. SiM3L1x4-GM Revision Information Rev 1.1 89 SiM3L1xx DOCUMENT CHANGE LIST Revision 0.5 to Revision 1.0 Updated Electrical Specifications Tables with latest characterization data and production test limits. Added missing signal ACCTR0_LCPUL1 to Table 6.2, “Pin Definitions and Alternate Functions for SiM3L1x6,” on page 64. Removed ACCTR0_LCIN1 and ACCTR0_STOP0/1 signals from Table 6.3, “Pin Definitions and Alternate Functions for SiM3L1x4,” on page 70. Updated Figure 6.8, “TFBGA-80 Package Drawing,” on page 79. Revision 1.0 to Revision 1.1 90 Removed all references to BGA-80 and the parts SiM3L167-C-GL and SiM3L157-C-GL. Rev 1.1 SiM3 L1xx CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. Rev 1.1 91