C8051F300-GDI

C8051F300-GDI
8 kB Flash, 8-Bit ADC MCU Die in Wafer Form
Analog Peripherals
- 8-Bit ADC
High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
Up to 500 ksps
Up to 8 external inputs
•
Programmable amplifier gains of 4, 2, 1, & 0.5
•
VREF from external pin or VDD
•
Built-in temperature sensor
•
External conversion start input
Comparator
•
Programmable hysteresis and response time
•
Configurable as interrupt or reset source
•
Low current (0.5 µA)
•
•
On-chip Debug
- On-chip debug circuitry facilitates full speed, non-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.6 mA @ 25 MHz;
-
ports
Three general-purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with three
capture/compare modules
Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
14 µA @ 32 kHz
Typical stop mode current: 0.1 µA
Temperature range: –40 to +85 °C
Full Technical Data Sheet
- C8051F300/1/2/3/4/5
-
supports UART operation
External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
Can switch between clock sources on-the-fly; Useful
in power saving modes
ANALOG
PERIPHERALS
A
M
U
X
PGA
8-bit
500 ksps
ADC
C8051F300/2 only
+
TEMP
SENSOR
-
VOLTAGE COMPARATOR
DIGITAL I/O
UART
SMBus
PCA
Timer 0
Timer 1
I/O Port
-
devices
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
CROSSBAR
-
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- 8 kB Flash; 512 bytes are reserved in the 8 kB
Timer 2
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
ISP Flash
12
INTERRUPTS
Rev. 1.1 4/12
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
Copyright © 2012 by Silicon Laboratories
WDT
C8051F300-GDI
2
MIPS (Peak)
Flash Memory (kB)*
RAM (Bytes)
SMBus/I2C
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
8-bit 500 ksps ADC
Programmable Current Reference
Temperature Sensor
Analog Comparators
Lead-free (RoHS Compliant)
C8051F300-GDI
25
8
256
1
1
3

8



1

*Note: 512 bytes reserved for factory use.
Rev. 1.1
Package
Ordering Part Number
C8051F300-GDI
1. Ordering Information
Table 1.1. Product Selection Guide
Tested Die
in Wafer
Form
C8051F300-GDI
2. Pin Definitions
Table 2.1. Pin Definitions for the C8051F300-GDI
Name
Physical Pad
Number
Type
VREF /
3
A In
P0.0
D I/O or
A In
P0.1
4
VDD
5
XTAL1 /
6
P0.2
XTAL2 /
Description
External Voltage Reference Input.
Port 0.0.
D I/O or A Port 0.1.
In
Power Supply Voltage.
A In
Crystal Input. This pin is the external oscillator circuit return
for a crystal or ceramic resonator.
D I/O or A
In
Port 0.2.
7
P0.3
A Out
Crystal Input/Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input
for CMOS, capacitor, or RC network configurations.
D I/O
Port 0.3.
P0.4
13
D I/O or A Port 0.4.
In
P0.5
14
D I/O or A Port 0.5.
In
C2CK /
15
RST
P0.6 /
16
CNVSTR
C2D /
17
P0.7
GND
D I/O
Clock signal for the C2 Development Interface.
D I/O
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
D I/O or
A In
D I/O
ADC External Convert Start Input Strobe.
D I/O
Data signal for the C2 Development Interface.
D I/O or
A In
18
Port 0.6.
Port 0.7.
Ground.
Rev. 1.1
3
C8051F300-GDI
3. Bonding Instructions
Table 3.1. C8051F300-GDI Pad Connections
Physical Pad
Number
Example Package
Pin Number
(11-QFN)
1
Package Pin
Name
Physical Pad X
(µm)
Physical Pad Y
(µm)
Reserved*
–1001.5
–575
2
Reserved*
–926.5
–575
3
1
VREF/P0.0
–795.5
–575
4
2
P0.1
–615.5
–575
5
3
VDD
346.17
–575
6
4
XTAL1/P0.2
615.5
–575
7
5
XTAL2/P0.3
795.5
–575
8
Reserved*
926.5
–575
9
Reserved*
1001.5
–575
10
Reserved*
1000
–429.57
11
Reserved*
1001.5
575
12
Reserved*
926.5
575
13
6
P0.4
790.5
575
14
7
P0.5
620.5
575
15
8
/RST/C2CK
440.5
575
16
9
P0.6/CNVSTR
–523.5
575
17
10
C2D/P0.7
–703.5
575
18
11
GND
–834.5
575
19
Reserved*
–926.5
575
20
Reserved*
–1001.5
575
*Note: Pins marked “Reserved” should not be connected.
4
Rev. 1.1
C8051F300-GDI
Figure 3.1. Example Die Bonding (QFN-11)
Rev. 1.1
5
C8051F300-GDI
Table 3.2. Wafer and Die Information
C8051F300
Wafer ID
8 in
Wafer Dimensions
Die Dimensions
1.40 mm x 2.2 mm
Wafer Thickness
12 mil ±1 mil
Wafer Identification
Notch
Scribe Line Width
80 µm
Contact Sales for info
Die Per Wafer*
Passivation
Standard
Wafer Packaging Detail
Wafer Jar
Bond Pad Dimensions
60 µm x 60 µm
Maximum Processing Temperature
250 °C
Electronic Die Map Format
.txt
Bond Pad Pitch Minimum
75 µm
*Note: This is the Expected Known Good Die yielded per wafer and represents
the batch order quantity (one wafer).
6
Rev. 1.1
C8051F300-GDI
4. Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.

Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
Wafers must be stored at a temperature of 18–24 °C.
 Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%.
 Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).

Rev. 1.1
7
C8051F300-GDI
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1

8
Changed Wafer Packaging Detail to “Wafer Jar” 
in Table 3.2 on page 6.
Rev. 1.1
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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