EFM32LG900F256G-E-D1I

...the world's most energy friendly microcontrollers
EFM32LG900 DATASHEET
F256
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 63 µA/MHz @ 3 V Sleep Mode
• 211 µA/MHz @ 3 V Run Mode, with code executed from flash
• 256 KB Flash
• 32 KB RAM
• 93 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×36 segments
• Voltage boost, adjustable contrast and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
• External Bus Interface for up to 4×256 MB of external
memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
2
• 2× I C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host & OTG support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Delivered as full wafer
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
...the world's most energy friendly microcontrollers
1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32LG900 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB)
RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32LG900F256G-E-D1I
256
32
48
1.98 - 3.8
-40 - 85
Wafer
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
The EFM32LG900 products are delivered in wafer form, but are otherwise identical to the EFM32LG995
packaged parts. Please refer to the EFM32LG995 datasheet for additional information.
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3 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32LG900.
3.1 Padout
The EFM32LG900 padout is shown in Figure 3.1 (p. 4) and Table 3.1 (p. 5). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pad are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
NC
15
PB3
16
PB4
17
PB5
PB6
18
19
iovss_1
iovdd_1
20
21
PC0
PC1
22
23
PC2
PC3
24
25
PC4
PC5
26
27
PB7
28
PB8
29
usb_vbus
PF3
101
100
PF2
PF1
PF0
iovss_7
PF9
PF8
PF7
PF6
iovdd_5
iovss_5
PF5
PF12
PF4
(X,Y): (2115, 2115)
99
98
97
96
NC
PE8
PB15
PD13
PD12
PD11
PD10
PD9
118
117
116
115
114
113
112
111
PE12
iovss_6
iovdd_6
PE11
PE10
PE9
124
123
122
121
120
119
110
109
108
107
106
105
104
103
102
PA15
PE15
PE14
PE13
(X,Y): (0, 0)
51
52
53
54
55
56
57
58
59
14
43
44
45
46
47
48
49
50
PB2
42
9
10
11
12
13
41
iovss_0
PD14
PD15
PB0
PB1
40
8
39
7
iovdd_0
38
6
PA6
37
5
PA5
36
4
PA4
35
3
30
PA2
PA3
34
2
33
1
PA1
32
PA0
31
(X,Y): (- 2115, 2115)
128
127
126
125
Figure 3.1. EFM32LG900 Padout (top view, not to scale)
95
94
93
92
91
90
89
88
87
86
PF11
PC15
PF10
PC14
usb_vrego_1
usb_vrego_0
usb_vregi_1
usb_vregi_0
PC13
PC12
85
84
83
82
81
80
79
PC11
PC10
PC9
PC8
PE7
PE6
PE5
78
77
76
75
74
73
72
PE4
PE3
PE2
PE1
PE0
iovss_4
NC
71
70
69
68
67
66
65
64
63
62
61
60
dec_2
dec_1
dec_0
iovdd_4
vdd_dreg
vss_dreg
PC7
PC6
PD8
PD7
PD6
PD5
iovss_3
iovdd_3
avss_0
avdd_0
PD0
PD1
PD2
PD3
PD4
PB11
PB12
avss_2
avdd_2
avdd_1
avss_1
PB13
PB14
PB10
PB9
reset
PA14
PA13
PA12
iovss_2
iovdd_2
PA11
PA9
PA10
PA8
(X,Y): (2115, - 2115)
PA7
(X,Y): (- 2115, - 2115)
The pad coordinates represent the center of the pad opening relative to the die center.
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Table 3.1. Device Padout
Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
[µm]
Y
[µm]
Analog
EBI
Timers
Communication
Other
1
PA0
-2065.0
1837.0
LCD_SEG13
EBI_AD09 #0/1/2
TIM0_CC0 #0/1/4
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
2
PA1
-2065.0
1704.6
LCD_SEG14
EBI_AD10 #0/1/2
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
3
PA2
-2065.0
1572.1
LCD_SEG15
EBI_AD11 #0/1/2
TIM0_CC2 #0/1
4
PA3
-2065.0
1439.7
LCD_SEG16
EBI_AD12 #0/1/2
TIM0_CDTI0 #0
U0_TX #2
LES_ALTEX2 #0
ETM_TD1 #3
5
PA4
-2065.0
1307.2
LCD_SEG17
EBI_AD13 #0/1/2
TIM0_CDTI1 #0
U0_RX #2
LES_ALTEX3 #0
ETM_TD2 #3
6
PA5
-2065.0
1174.7
LCD_SEG18
EBI_AD14 #0/1/2
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0
ETM_TD3 #3
7
PA6
-2065.0
1042.3
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
ETM_TCLK #3
GPIO_EM4WU1
8
IOVDD_0
-2065.0
909.8
Digital IO power supply 0.
9
IOVSS_0
-2065.0
630.9
Digital IO ground 0.
10
PD14
-2065.0
550.5
I2C0_SDA #3
11
PD15
-2065.0
451.0
I2C0_SCL #3
12
PB0
-2065.0
352.7
LCD_SEG32
EBI_A16 #0/1/2
TIM1_CC0 #2
13
PB1
-2065.0
249.0
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
14
PB2
-2065.0
107.0
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
15
NC
-2065.0
-40.8
16
PB3
-2065.0
-215.2
LCD_SEG20/
LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
17
PB4
-2065.0
-347.7
LCD_SEG21/
LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
18
PB5
-2065.0
-504.7
LCD_SEG22/
LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
19
PB6
-2065.0
-612.6
LCD_SEG23/
LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
20
IOVSS_1
-2065.0
-745.0
Digital IO ground 1.
21
IOVDD_1
-2065.0
-860.7
Digital IO power supply 1.
22
PC0
-2065.0
-994.8
ACMP0_CH0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4
PCNT0_S0IN #2
US0_TX #5
US1_TX #0
I2C0_SDA #4
LES_CH0 #0
PRS_CH2 #0
23
PC1
-2065.0
-1098.4
ACMP0_CH1
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4
PCNT0_S1IN #2
US0_RX #5
US1_RX #0
I2C0_SCL #4
LES_CH1 #0
PRS_CH3 #0
24
PC2
-2065.0
-1220.4
ACMP0_CH2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
25
PC3
-2065.0
-1322.6
ACMP0_CH3
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
EBI_NANDREn
#0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
26
PC4
-2065.0
-1484.3
ACMP0_CH4
DAC0_P0 /
OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0
LES_CH4 #0
27
PC5
-2065.0
-1586.5
ACMP0_CH5
DAC0_N0 /
OPAMP_N0
EBI_NANDWEn
#0/1/2
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
LES_CH5 #0
Pad #
Pad Name
CMU_CLK0 #0
ETM_TD0 #3
Do not connect.
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
[µm]
Y
[µm]
Analog
Timers
Communication
28
PB7
-2065.0
-1708.6
LFXTAL_P
TIM1_CC0 #3
US0_TX #4
US1_CLK #0
29
PB8
-2065.0
-1830.6
LFXTAL_N
TIM1_CC1 #3
US0_RX #4
US1_CS #0
30
PA7
-1832.5
-2065.0
LCD_SEG35
EBI_CSTFT #0/1/2
31
PA8
-1695.5
-2065.0
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
32
PA9
-1558.5
-2065.0
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
33
PA10
-1421.5
-2065.0
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
34
PA11
-1284.5
-2065.0
LCD_SEG39
EBI_HSNC #0/1/2
35
IOVDD_2
-1147.5
-2065.0
Digital IO power supply 2.
36
IOVSS_2
-1027.4
-2065.0
Digital IO ground 2.
37
PA12
-907.2
-2065.0
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
38
PA13
-780.6
-2065.0
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
39
PA14
-654.0
-2065.0
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
40
RESETn
-527.4
-2065.0
41
PB9
-401.0
-2065.0
EBI_A03 #0/1/2
U1_TX #2
42
PB10
-274.5
-2065.0
EBI_A04 #0/1/2
U1_RX #2
43
PB11
260.7
-2065.0
DAC0_OUT0 /
OPAMP_OUT0
TIM1_CC2 #3
LETIM0_OUT0 #1
I2C1_SDA #1
44
PB12
366.0
-2065.0
DAC0_OUT1 /
OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
45
AVSS_2
464.8
-2065.0
Analog ground 2.
46
AVDD_2
560.5
-2065.0
Analog power supply 2.
47
AVDD_1
661.2
-2065.0
Analog power supply 1.
48
AVSS_1
754.5
-2065.0
Analog ground 1.
49
PB13
833.8
-2065.0
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
50
PB14
919.6
-2065.0
HFXTAL_N
US0_CS #4/5
LEU0_RX #1
51
IOVSS_3
1054.9
-2065.0
Digital IO ground 3.
52
IOVDD_3
1151.7
-2065.0
Digital IO power supply 3.
53
AVSS_0
1254.2
-2065.0
Analog ground 0.
54
AVDD_0
1346.8
-2065.0
Analog power supply 0.
55
PD0
1442.7
-2065.0
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
56
PD1
1559.2
-2065.0
ADC0_CH1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
TIM0_CC0 #3
PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
57
PD2
1646.3
-2065.0
ADC0_CH2
TIM0_CC1 #3
USB_DMPU #0
US1_CLK #1
DBG_SWO #3
58
PD3
1749.3
-2065.0
ADC0_CH3
OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
59
PD4
1851.4
-2065.0
ADC0_CH4
OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
Pad #
Pad Name
EBI
Other
Reset input, active low.
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
2015-03-16 - EFM32LG900FXX - d0328_Rev1.20
EBI_A27 #0/1/2
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
[µm]
Y
[µm]
Analog
60
PD5
2065.0
-1872.9
ADC0_CH5
OPAMP_OUT2 #0
61
PD6
2065.0
-1771.3
ADC0_CH6
DAC0_P1 /
OPAMP_P1
Pad #
Pad Name
EBI
Communication
Other
LEU0_RX #0
ETM_TD3 #0/2
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
US1_RX #2
I2C0_SDA #1
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ETM_TCLK #0
Timers
62
PD7
2065.0
-1669.4
ADC0_CH7
DAC0_N1 /
OPAMP_N1
63
PD8
2065.0
-1561.9
BU_VIN
64
PC6
2065.0
-1470.2
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0
I2C0_SDA #2
LES_CH6 #0
ETM_TCLK #2
65
PC7
2065.0
-1385.2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0
I2C0_SCL #2
LES_CH7 #0
ETM_TD0 #2
66
VSS_DREG
2065.0
-1295.5
Ground for on-chip voltage regulator.
67
VDD_DREG
2065.0
-1218.8
Power supply for on-chip voltage regulator.
68
IOVDD_4
2065.0
-1119.8
Digital IO power supply 4.
69
DEC_0
2065.0
-1018.9
Decouple output for on-chip voltage regulator.
70
DEC_1
2065.0
-925.3
Decouple output for on-chip voltage regulator.
71
DEC_2
2065.0
-847.7
Decouple output for on-chip voltage regulator.
72
NC
2065.0
-356.4
Do not connect.
73
IOVSS_4
2065.0
-265.5
Digital IO ground 4.
74
PE0
2065.0
-181.4
EBI_A07 #0/1/2
TIM3_CC0 #1
PCNT0_S0IN #1
U0_TX #1
I2C1_SDA #2
75
PE1
2065.0
-93.2
EBI_A08 #0/1/2
TIM3_CC1 #1
PCNT0_S1IN #1
U0_RX #1
I2C1_SCL #2
76
PE2
2065.0
-1.1
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
77
PE3
2065.0
91.1
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
78
PE4
2065.0
182.6
LCD_COM0
EBI_A11 #0/1/2
US0_CS #1
79
PE5
2065.0
302.4
LCD_COM1
EBI_A12 #0/1/2
US0_CLK #1
80
PE6
2065.0
406.9
LCD_COM2
EBI_A13 #0/1/2
US0_RX #1
81
PE7
2065.0
519.2
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
82
PC8
2065.0
625.8
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
83
PC9
2065.0
714.3
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0
GPIO_EM4WU2
84
PC10
2065.0
819.1
ACMP1_CH2
EBI_A10 #1/2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
85
PC11
2065.0
905.1
ACMP1_CH3
EBI_ALE #1/2
US0_TX #2
LES_CH11 #0
86
PC12
2065.0
1027.7
ACMP1_CH4
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
U1_TX #0
CMU_CLK0 #1
LES_CH12 #0
87
PC13
2065.0
1131.8
ACMP1_CH5
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
U1_RX #0
LES_CH13 #0
88 USB_VREGI_0
2065.0
1237.6
USB input to internal 3.3 V regulator.
89 USB_VREGI_1
2065.0
1314.6
USB input to internal 3.3 V regulator.
90 USB_VREGO_0
2065.0
1393.0
USB decoupling for internal 3.3 V USB regulator and regulator output.
91 USB_VREGO_1
2065.0
1470.4
USB decoupling for internal 3.3 V USB regulator and regulator output.
2015-03-16 - EFM32LG900FXX - d0328_Rev1.20
CMU_CLK1 #1
TIM0_CDTI0 #1/3
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
[µm]
Y
[µm]
Analog
92
PC14
2065.0
1558.7
ACMP1_CH6
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
93
PF10
2065.0
1673.6
94
PC15
2065.0
1756.6
95
PF11
2065.0
1870.0
96
IOVSS_7
1846.0
2065.0
97
PF0
1739.3
2065.0
TIM0_CC0 #5
LETIM0_OUT0 #2
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK
#0/1/2/3
98
PF1
1626.3
2065.0
TIM0_CC1 #5
LETIM0_OUT1 #2
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO
#0/1/2/3
GPIO_EM4WU3
99
PF2
1513.2
2065.0
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
100
PF3
1389.7
2065.0
LCD_SEG1
EBI_ALE #0
TIM0_CDTI0 #2/5
PRS_CH0 #1
ETM_TD3 #1
101
USB_VBUS
1242.9
2065.0
102
PF4
995.9
2065.0
EBI_WEn #0/2
TIM0_CDTI1 #2/5
PRS_CH1 #1
103
PF12
886.3
2065.0
104
PF5
782.2
2065.0
105
IOVSS_5
672.3
2065.0
Digital IO ground 5.
106
IOVDD_5
576.7
2065.0
Digital IO power supply 5.
107
PF6
488.4
2065.0
108
PF7
380.5
109
PF8
110
Pad #
Pad Name
EBI
Timers
Communication
Other
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
U0_TX #3
LES_CH14 #0
U1_TX #1
USB_DM
ACMP1_CH7
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM0_CDTI2 #1/3
TIM1_CC2 #0
US0_CLK #3
U0_RX #3
LES_CH15 #0
DBG_SWO #1
U1_RX #1
USB_DP
Digital IO ground 7.
USB 5.0 V VBUS input.
LCD_SEG2
USB_ID
LCD_SEG3
EBI_REn #0/2
TIM0_CDTI2 #2/5
USB_VBUSEN #0
PRS_CH2 #1
LCD_SEG24
EBI_BL0 #0/1/2
TIM0_CC0 #2
U0_TX #0
2065.0
LCD_SEG25
EBI_BL1 #0/1/2
TIM0_CC1 #2
U0_RX #0
275.3
2065.0
LCD_SEG26
EBI_WEn #1
TIM0_CC2 #2
PF9
174.3
2065.0
LCD_SEG27
EBI_REn #1
111
NC
43.2
2065.0
112
PD9
-89.5
2065.0
LCD_SEG28
EBI_CS0 #0/1/2
113
PD10
-204.5
2065.0
LCD_SEG29
EBI_CS1 #0/1/2
114
PD11
-313.8
2065.0
LCD_SEG30
EBI_CS2 #0/1/2
115
PD12
-426.2
2065.0
LCD_SEG31
EBI_CS3 #0/1/2
116
PD13
-534.7
2065.0
ETM_TD1 #1
117
PB15
-644.6
2065.0
ETM_TD2 #1
118
PE8
-745.8
2065.0
LCD_SEG4
EBI_AD00 #0/1/2
PCNT2_S0IN #1
119
PE9
-867.9
2065.0
LCD_SEG5
EBI_AD01 #0/1/2
PCNT2_S1IN #1
120
PE10
-976.1
2065.0
LCD_SEG6
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
BOOT_TX
121
PE11
-1085.3
2065.0
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
LES_ALTEX5 #0
BOOT_RX
122
IOVDD_6
-1196.1
2065.0
Digital IO power supply 6.
123
IOVSS_6
-1289.0
2065.0
Digital IO ground 6.
124
PE12
-1385.4
2065.0
TIM1_CC2 #1
US0_RX #3
CMU_CLK1 #2
ETM_TCLK #1
ETM_TD0 #1
Do not connect.
LCD_SEG8
2015-03-16 - EFM32LG900FXX - d0328_Rev1.20
EBI_AD04 #0/1/2
8
PRS_CH3 #1
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Pad #
Wafer Pads and Coordinates
Pad Name
X
[µm]
Pad Alternate Functionality / Description
Y
[µm]
Analog
EBI
Timers
Communication
Other
US0_CLK #0
I2C0_SDA #6
LES_ALTEX6 #0
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
125
PE13
-1518.2
2065.0
LCD_SEG9
EBI_AD05 #0/1/2
126
PE14
-1626.4
2065.0
LCD_SEG10
EBI_AD06 #0/1/2
TIM3_CC0 #0
LEU0_TX #2
127
PE15
-1729.6
2065.0
LCD_SEG11
EBI_AD07 #0/1/2
TIM3_CC1 #0
LEU0_RX #2
128
PA15
-1844.0
2065.0
LCD_SEG12
EBI_AD08 #0/1/2
TIM3_CC2 #0
3.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 3.2 (p. 9). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 3.2. Alternate functionality overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0
PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1
PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2
PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3
PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4
PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5
PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6
PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7
PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
ACMP1_CH0
PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1
PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2
PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3
PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH4
PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5
PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6
PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7
PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
PE2
PE3
PD6
Analog comparator ACMP0, digital output.
PD7
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Analog comparator ACMP1, digital output.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system
is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2
PC12
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1
PD8
PE12
Clock Management Unit, clock output number 1.
DAC0_N0 /
OPAMP_N0
PC5
Operational Amplifier 0 external negative input.
DAC0_N1 /
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
DAC0_OUT0 /
OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
PC0
OPAMP_OUT0ALT
DAC0_OUT1 /
OPAMP_OUT1
PC1
PC2
PC3
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PD0
Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
PB12
DAC0_OUT1ALT /
PC12
OPAMP_OUT1ALT
PC13
OPAMP_OUT2
PD5
PD0
DAC0_P0 /
OPAMP_P0
PC4
Operational Amplifier 0 external positive input.
DAC0_P1 /
OPAMP_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
DBG_SWCLK
PF0
PF0
PF0
PF0
DBG_SWDIO
PF1
PF1
PF1
PF1
DBG_SWO
PF2
PC15
PD1
PD2
EBI_A00
PA12
PA12
PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13
PA13
PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14
PA14
PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9
PB9
PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10
PB10
PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6
PC6
PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7
PC7
PC7
External Bus Interface (EBI) address output pin 06.
PC14
PC15
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PD1
Operational Amplifier 2 output.
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
Debug-interface Serial Wire viewer Output.
2015-03-16 - EFM32LG900FXX - d0328_Rev1.20
Note that this function is not enabled after reset, and must
be enabled by software to be used.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A07
PE0
PE0
PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1
PE1
PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2
PC9
PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3
PC10
PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4
PE4
PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5
PE5
PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6
PE6
PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7
PE7
PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8
PC8
PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0
PB0
PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1
PB1
PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2
PB2
PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3
PB3
PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4
PB4
PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5
PB5
PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6
PB6
PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0
PC0
PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1
PC1
PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2
PC2
PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4
PC4
PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2
PD2
PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8
PE8
PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9
PE9
PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10
PE10
PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11
PE11
PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12
PE12
PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13
PE13
PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14
PE14
PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15
PE15
PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15
PA15
PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0
PA0
PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1
PA1
PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2
PA2
PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3
PA3
PA3
External Bus Interface (EBI) address and data input / output pin 12.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD13
PA4
PA4
PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5
PA5
PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6
PA6
PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3
PC11
PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2
PF2
PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6
PF6
PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7
PF7
PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9
PD9
PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10
PD10
PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11
PD11
PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12
PD12
PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7
PA7
PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8
PA8
PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9
PA9
PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11
PA11
PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn
PC3
PC3
PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5
PC5
PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5
PF9
PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10
PA10
PA10
External Bus Interface (EBI) TFT Vertical Synchronization
pin.
EBI_WEn
PF4
PF8
PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7
PF8
PC6
PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PF9
PC7
PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD13
PD3
PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PB15
PD4
PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PF3
PD5
PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0
PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1
PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2
PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3
PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4
PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5
PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1
PD7
PC7
PD15
PC1
PF1
PE13
I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0
PD6
PC6
PD14
PC0
PF0
PE12
I2C0 Serial Data input / output.
I2C1_SCL
PC5
PB12
PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4
PB11
PE0
I2C1 Serial Data input / output.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_BCAP_N
PA13
LCD voltage booster (optional), boost capacitor, negative
pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P
PA12
LCD voltage booster (optional), boost capacitor, positive
pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the
LCD voltage booster, connect a 1 uF capacitor between
this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if
the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this
pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG1
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG2
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD_SEG20/
LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 4
LCD_SEG21/
LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 5
LCD_SEG22/
LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 6
LCD_SEG23/
LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LES_ALTEX0
PD6
LESENSE alternate exite output 0.
LES_ALTEX1
PD7
LESENSE alternate exite output 1.
LES_ALTEX2
PA3
LESENSE alternate exite output 2.
LES_ALTEX3
PA4
LESENSE alternate exite output 3.
LES_ALTEX4
PA5
LESENSE alternate exite output 4.
LES_ALTEX5
PE11
LESENSE alternate exite output 5.
LES_ALTEX6
PE12
LESENSE alternate exite output 6.
LES_ALTEX7
PE13
LESENSE alternate exite output 7.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0
PD6
PB11
PF0
PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1
PD7
PB12
PF1
PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5
PB14
PE15
PF1
PA0
LEUART0 Receive input.
LEU0_TX
PD4
PB13
PE14
PF0
PF2
LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEU1_RX
PC7
PA6
LEUART1 Receive input.
LEU1_TX
PC6
PA5
LEUART1 Transmit output. Also used as receive input in
half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN
PC13
PE0
PC0
PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PC14
PE1
PC1
PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN
PC4
PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN
PC5
PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN
PD0
PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN
PD1
PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0
PF3
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1
PF4
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PC0
PF5
Peripheral Reflex System PRS, channel 2.
PRS_CH3
PC1
PE8
Peripheral Reflex System PRS, channel 3.
TIM0_CC0
PA0
PA0
PF6
PD1
PA0
PF0
Timer 0 Capture Compare input / output channel 0.
TIM0_CC1
PA1
PA1
PF7
PD2
PC0
PF1
Timer 0 Capture Compare input / output channel 1.
TIM0_CC2
PA2
PA2
PF8
PD3
PC1
PF2
Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0
PA3
PC13
PF3
PC13
PC2
PF3
Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1
PA4
PC14
PF4
PC14
PC3
PF4
Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2
PA5
PC15
PF5
PC15
PC4
PF5
Timer 0 Complimentary Deat Time Insertion channel 2.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
TIM1_CC0
PC13
PE10
PB0
PB7
PD6
Timer 1 Capture Compare input / output channel 0.
TIM1_CC1
PC14
PE11
PB1
PB8
PD7
Timer 1 Capture Compare input / output channel 1.
TIM1_CC2
PC15
PE12
PB2
PB11
PC13
Timer 1 Capture Compare input / output channel 2.
TIM2_CC0
PA8
PA12
PC8
Timer 2 Capture Compare input / output channel 0.
TIM2_CC1
PA9
PA13
PC9
Timer 2 Capture Compare input / output channel 1.
TIM2_CC2
PA10
PA14
PC10
Timer 2 Capture Compare input / output channel 2.
TIM3_CC0
PE14
PE0
Timer 3 Capture Compare input / output channel 0.
TIM3_CC1
PE15
PE1
Timer 3 Capture Compare input / output channel 1.
TIM3_CC2
PA15
PE2
Timer 3 Capture Compare input / output channel 2.
U0_RX
PF7
PE1
PA4
PC15
UART0 Receive input.
U0_TX
PF6
PE0
PA3
PC14
UART0 Transmit output. Also used as receive input in half
duplex communication.
U1_RX
PC13
PF11
PB10
PE3
UART1 Receive input.
U1_TX
PC12
PF10
PB9
PE2
UART1 Transmit output. Also used as receive input in half
duplex communication.
US0_CLK
PE12
PE5
PC9
PC15
PB13
PB13
USART0 clock input / output.
US0_CS
PE13
PE4
PC8
PC14
PB14
PB14
USART0 chip select input / output.
US0_RX
PE11
PE6
PC10
PE12
PB8
PC1
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
US0_TX
PE10
PE7
PC11
PE13
PB7
PC0
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
PB7
PD2
PF0
USART1 clock input / output.
US1_CS
PB8
PD3
PF1
USART1 chip select input / output.
US1_RX
PC1
PD1
PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
US1_TX
PC0
PD0
PD7
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
PC4
PB5
USART2 clock input / output.
US2_CS
PC5
PB6
USART2 chip select input / output.
US2_RX
PC3
PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
US2_TX
PC2
PB3
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_VBUS
USB 5 V VBUS input.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USB_VBUSEN
PF5
USB 5 V VBUS enable.
USB_VREGI
USB_VREGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_VREGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
3.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32LG900 is shown in Table 3.3 (p. 17) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 3.3. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin
9
Pin
8
Pin
7
Pin
6
Pin
5
Pin
4
Pin
3
Pin
2
Pin
1
Pin
0
Port A
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port B
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port C
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Port D
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Port E
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Port F
-
-
-
PF12
PF11
PF10
PF9
PF8
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
3.4 Bonding Instructions
All pads should be bonded out, with the exception of the pads labeled “NC” and listed as “Do not connect”
in Table 3.1 (p. 5) . Gold bond wires are recommended for these devices.
All three voltage regulator output decouple pads (DEC_0, DEC_1, DEC_2) must be bonded out and
electrically connected on the PCB. In the packaged devices, these three pads are all bonded to a single
DECOUPLE pin.
If the USB feature of EFM32LG900 will be used, all of the USB pads must be bonded out, and
• both USB_VREGO_0 and USB_VREGO_1 must be bonded out and electrically connected on the
PCB. In the packaged devices, these two pads are both bonded to a single USB_VREGO pin.
• both USB_VREGI_0 and USB_VREGI_1 must be bonded out and electrically connected on the PCB.
In the packaged devices, these two pads are both bonded to a single USB_VREGI pin.
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3.5 Wafer Description
Table 3.4. Wafer and Die Information
Parameter
Value
Device Family
EFM32LG (Leopard Gecko)
Wafer Diameter
8 in
Die Dimensions (Outer edge of seal ring)
4230 µm × 4230 µm
Wafer Thickness (No backgrind)
725 µm ±15 µm
(28.54 mil ±1 mil)
Wafer Identification
Notch
Scribe Street Width
80 µm × 160 µm
Die Per Wafer
1
Contact sales for information
Passivation
Standard
Wafer Packaging Detail
Wafer Jar
Bond Pad Dimensions
65 µm (parallel to die edge) × 66 µm
Bond Pad Pitch Minimum
76 µm
Maximum Processing Temperature
250°C
Electronic Die Map Format
.txt
1
Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).
3.5.1 Environmental
Bare silicon die are susceptible to mechanical damage and may be sensitive to light. When bare die
must be used in an environment exposed to light, it may be necessary to cover the top and sides with
an opaque material.
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx.
3.6 Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.
•
•
•
•
Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
Wafers must be stored at a temperature of 18 - 24 °C.
Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%
Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
3.7 Failure Analysis (FA) Guidelines
Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in
wafer form.
• In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories
must be provided with die assembled in an industry standard package that is pin compatible with
existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that
meet these requirements will follow the standard FA guidelines for packaged parts.
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• If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer.
Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or are on tape.
Initial response time for FA requests that meet these requirements will be 3 weeks.
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4 Chip Marking, Revision and Errata
4.1 Errata
Please see the errata document for EFM32LG900 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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5 Revision History
5.1 Revision 1.20
March 16th, 2015
Corrected pad numbers and the order of the pads in the padout table so that it matches the drawing.
5.2 Revision 1.10
December 12th, 2014
Added recommendation to use gold bond wire.
5.3 Revision 1.00
October 15th, 2014
Initial release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
3. Pinout and Package .................................................................................................................................. 4
3.1. Padout .......................................................................................................................................... 4
3.2. Alternate Functionality Pinout ............................................................................................................ 9
3.3. GPIO Pinout Overview ................................................................................................................... 17
3.4. Bonding Instructions ...................................................................................................................... 17
3.5. Wafer Description .......................................................................................................................... 18
3.6. Wafer Storage Guidelines ............................................................................................................... 18
3.7. Failure Analysis (FA) Guidelines ...................................................................................................... 18
4. Chip Marking, Revision and Errata .............................................................................................................. 20
4.1. Errata ......................................................................................................................................... 20
5. Revision History ...................................................................................................................................... 21
5.1. Revision 1.20 ............................................................................................................................... 21
5.2. Revision 1.10 ............................................................................................................................... 21
5.3. Revision 1.00 ............................................................................................................................... 21
A. Disclaimer and Trademarks ....................................................................................................................... 22
A.1. Disclaimer ................................................................................................................................... 22
A.2. Trademark Information ................................................................................................................... 22
B. Contact Information ................................................................................................................................. 23
B.1. ................................................................................................................................................. 23
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List of Figures
3.1. EFM32LG900 Padout (top view, not to scale) .............................................................................................. 4
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List of Tables
1.1.
3.1.
3.2.
3.3.
3.4.
Ordering Information ................................................................................................................................ 2
Device Padout ....................................................................................................................................... 5
Alternate functionality overview .................................................................................................................. 9
GPIO Pinout ........................................................................................................................................ 17
Wafer and Die Information ...................................................................................................................... 18
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