AN0948

AN0948: Power Configurations and DC-DC
This application note provides an overview of the integrated DCto-DC converter (DCDC) on the EFM32 Series 2 and EFR32
Wireless Gecko devices. In addition, it describes the available
hardware configurations and programming steps for each.
KEY POINTS
• DC-DC converters can improve overall
system efficiency.
• EFM32 Series 2 and EFR32 Wireless
Gecko devices integrate a DC-DC
converter with flexible configuration
options.
For simplicity, EFR32 Wireless Gecko is used throughout this document to represent
the EFR32 portfolio devices (Mighty Gecko, Flex Gecko, Blue Gecko, etc.) and EFM32
Series 2 Gecko is used to represent the next-generation Gecko MCUs (Pearl Gecko,
Jade Gecko, etc.).
• emlib fully supports the DC-DC converter
and provides the optimal configuration for
most cases.
VDD
Main
Supply
+
–
VREGVDD
VDCDC
CDVDD
0.1 µF
CDEC
1 µF
VREGSW
DC-DC
Driver
FLASH
OFF
0
DC-DC
VREGVSS
1
ANASW
Analog
Blocks
DVDD
Digital
LDO
Digital
Logic
RF
Power
Amplifier
RF
Analog
DECOUPLE
RFVDD
CRFVDD
220 nF
LPAVDD
22 nH
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IOVDD
AVDD
Bypass
Switch
LDCDC
4.7 µH
CDCDC
1 µF
CIOVDD CIOVDD1
1 µF 0.1 µF
CAVDD CAVDD1
10 µF 10 nF
CVDD CVDD1
10 µF 0.1 µF
PAVDD
CRFVDD1
10 pF
CPAVDD
220 nF
CPAVDD1
10 pF
Rev. 0.3
AN0948: Power Configurations and DC-DC
DC-DC Buck Converter Theory
1. DC-DC Buck Converter Theory
A DC-DC buck converter is a type of switching regulator that efficiently converts a high input voltage to a lower output voltage. A DCDC converter is generally much more efficient than a low-dropout (LDO) regulator. For an LDO regulator, the input current generally
equals the output current. As the difference between the input voltage and output voltage increases, the power efficiency decreases as
more power is dissipated as heat. For the DC-DC converter, power output is proportional to power input based on an efficiency rating
determined by the load current and switching losses. A DC-DC converter's efficiency may typically reach 90% under normal operating
conditions, whereas the LDO peak efficiency is directly proportional to the output voltage over the input voltage (i.e., if the input is 3.3 V
and output is 1.8 V, then the LDO efficiency is approximately 1.8 V/ 3.3 V, or 54%).
A basic block diagram of a generic DC-DC buck converter is shown below:
IIND
VDD
VSW
VDCDC
L
PFET
Main
Supply
+
–
ILOAD
C
NFET
Figure 1.1. Basic DC-DC Buck Converter Block Diagram
DC-DC converters will typically use one of two modulation schemes: PWM (pulse width modulation) or PFM (pulse frequency modulation). A PWM DC-DC converter modulates the on-time of the PFET switch with a constant switching frequency. This method concentrates the noise from the DC-DC converter into a single, filterable band. A PFM DC-DC converter modulates the switching frequency.
While this can be more efficient, it spreads out the noise spectrum, making it harder to filter. Continuous Conduction Mode (CCM)
Continuous Conduction Mode (CCM)
Continuous Conduction Mode (CCM) occurs when the DC-DC converter's PFET and NFET switches are turned on complimentarily. In
this mode, the power transfer occurs in two phases by first storing energy in the inductor, and then transferring the stored energy to the
load.
IIND
ILOAD
0
t
Figure 1.2. DC-DC Converter Current in Continuous Conduction Mode (CCM)
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AN0948: Power Configurations and DC-DC
DC-DC Buck Converter Theory
Forced Continuous Conduction Mode (FCCM)
Forced Continuous Conduction Mode (FCCM) occurs when the DC-DC converter's PFET and NFET switches are turned on complimentarily, but the current to the load can be negative.
IIND
ILOAD
0
t
Figure 1.3. DC-DC Converter Current in Forced Continuous Conduction Mode (FCCM)
Discontinuous Conduction Mode (DCM)
Discontinuous Conduction Mode (DCM) is similar to CCM except the charge stored in the inductor is allowed to be depleted. A third
phase of operation then occurs when the inductor current is depleted before the next switching cycle starts. DCM can occur when the
peak-to-peak inductor-current ripple (IIND_pp) exceeds twice the average load current (ILOAD):
I IND_pp > 2 × I LOAD
(
I IND_pp = 1 –
V DCDC
V DD
)
×
V DCDC
f SW × L
Where fSW is the controller's switching frequency.
To ensure that the current to the load remains positive or zero, the hardware uses a comparator on the output to turn off the NFET
switch when the current to the load starts to go negative. This ensures that charge is not being pushed back into the main supply (e.g.,
battery), as some supplies cannot tolerate this condition.
IIND
ILOAD
0
t
Figure 1.4. DC-DC Converter Current in Discontinuous Conduction Mode (DCM)
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
2. DC-DC Converter Module Overview
The EFM32 Series 2 and EFR32 Wireless Gecko devices feature a DC-to-DC buck converter which requires a single external inductor
and a single external capacitor. The converter takes the VREGVDD input voltage and converts it down to an output voltage between
VREGVDD and 1.8 V with a peak efficiency of approximately 90% in Low Noise (LN) mode and 85% in Low Power (LP) mode. Refer to
datasheet for full DC-DC specifications.
The DC-DC converter operates in either Low Noise (LN) or Low Power (LP) mode. LN mode is intended for higher current operation
(e.g., EM0), whereas LP mode is intended for very low current operation (e.g., EM2 and below). The DC-DC may be configured to automatically transition from LN mode in EM0/EM1 to LP mode in EM2, EM3, or EM4.
In addition, the DC-DC converter supports an unregulated Bypass mode, in which the input voltage is directly shorted to the DC-DC
output.
2.1 Bypass Mode
In Bypass mode, the VREGVDD input voltage is directly shorted to the DC-DC converter output through an internal switch. Out of reset,
the DC-DC converter defaults to Bypass mode.
Consult the datasheet for the Bypass switch impedance specification.
2.2 Low Power (LP) Mode
The Low Power (LP) controller operates in a hysteretic mode to keep the output voltage within a defined voltage band. Once the DCDC output voltage drops below a programmable internal reference, the LP controller generates a pulse train to control the powertrain
PFET switch, which charges up the DC-DC output capacitor. When the output voltage is at the programmed upper level, the powertrain
PFET is turned off. The output ripple voltage may be quite large (>100 mV) in LP mode.
The LP controller supports load currents up to approximately 10 mA, making it suitable for EM2, EM3, or EM4 low energy modes.
2.3 Low Noise (LN) Mode
The Low Noise (LN) controller continuously switches the powertrain NFET and PFET switches to maintain a constant programmed voltage at the DVDD pin. The LN controller supports load current from sub-mA up to 200 mA.
The LN controller switching frequency is programmable using the RCOBAND bitfield in the EMU_DCDCLNFREQCTRL register. See
below for recommended RCOBAND settings for each mode.
The DC-DC Low Noise controller operates in one of two modes:
1. Continuous Conduction Mode (CCM)
2. Discontinuous Conduction Mode (DCM)
2.3.1 Low Noise (LN) Continuous Conduction Mode (CCM)
CCM operation is configured by setting the LNFORCECCM bit in the EMU_DCDCMISCCTRL register. CCM can be used to improve
the DC-DC converter's output transient response time to quick load current changes, which minimizes voltage transients on the DC-DC
output.
Note that all references to CCM in the documentation actually refer to Forced Continuous Conduction Mode (FCCM) - that is, if the
LNFORCECCM bit is set and the output load current is very low, the DC-DC will be forced to operated in CCM. In this case, the current
through the inductor may be negative and current may flow back into the battery.
CCM is required for radio or Wireless Gecko systems because, unlike DCM, it allows use of the radio's interference minimization features.
In CCM, the recommended DC-DC converter switching frequency is 6.4 MHz (RCOBAND = 4) . Note that when the radio's interference
minimization features are enabled, RCOBAND = 4 corresponds to a DC-DC converter switching frequency of 7 MHz.
.
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
2.3.2 Low Noise (LN) Discontinuous Conduction Mode (DCM)
To enable DCM, the LNFORCECCM bit in EMU_DCDCMISCCTRL must be cleared before entering LN. Typically, this configuration
would occur while the part was in Bypass mode. Once DCM is enabled, the DC-DC should operate in DCM at light load currents. However, as the load current increases, the DC-DC will automatically transition into CCM without software intervention.
The advantage of DCM is improved efficiency for light load currents. However, the disadvantage is that DCM increases the potential RF
switching interference, because in DCM the DC-DC switching events are load dependent and can no longer be synchronized with radio
operation. In addition, in DCM the DC-DC has poorer dynamic response to changes in load current, leading to potentially larger
changes in the regulated output voltage. For these reasons, DCM is not recommended for radio applications, or for non-radio applications that expect large instantaneous load current steps. For example, if the DC-DC is in DCM, firmware may need to increment the
core clock frequency in small steps to prevent a large sudden load increase.
In DCM, the recommended DC-DC converter switching frequency is 3 MHz (RCOBAND = 0).
2.4 Analog Peripheral Power Selection
The analog peripherals (e.g., ULFRCO, LFRCO, LFXO, HFRCO, AUXHFRCO, VMON, IDAC, ADC) may be powered from one of two
supply pins, depending on the configuration of the ANASW bit in the EMU_PWRCTRL register: Changes to the ANASW setting should
be made immediately out of reset (i.e., in the Startup Configuration) before all clocks (with the exception of HFRCO and ULFRCO) are
enabled. Once ANASW is configured it should not be changed.
Table 2.1. Analog Peripheral Power Configuration
ANASW
Analog Peripheral Power Source
Comments
0 (default)
AVDD pin
This configuration may provide a quieter supply to the analog modules, but is less efficient as AVDD is typically at a higher voltage than
DVDD.
1
DVDD pin
This configuration may provide a noisier supply to the analog modules, but is more efficient.
Note that the flash is always powered from the AVDD pin, regardless of the state of the ANASW bit.
2.5 Maximum Output Current and Minimum Input Voltage
The DC-DC converter is designed to operate efficiently over a very wide range of current loads (<75 uA up to 200 mA). However, consideration must be given to both the maximum load current and the minimum input voltage. In addition, certain parameters of the DCDC converter will need to be adjusted based on the load current for optimal efficiency.
As the DC-DC input supply voltage nears its minimum voltage, the DC-DC converter performance is impacted in two ways:
1. The DC-DC converter efficiency decreases to a point where it provides limited benefit compared to Bypass mode
2. The DC-DC converter eventually loses the ability to maintain a constant output voltage, and enters dropout. When dropout occurs,
the DC-DC will no longer be in regulation and significant overshoot/undershoot will occur, which may cause the brown-out detectors to trip and reset the device.
To avoid dropout, the system should switch the DC-DC to Bypass mode when the input supply voltage drops to the minimum. Some
hysteresis (e.g., 100 mV~200 mV) should be used to prevent the DC-DC from toggling back into switching mode due to small input
supply voltage variations. Note that the DC-DC module doesn’t provide a means to directly monitor the input supply voltage; however,
input supply voltage monitoring may be implemented through other means, for example using the on-chip VMON supply monitor, the
on-chip ADC, or using an off-chip voltage supervisor IC.
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
Low Noise Mode
Note: The guidelines below must be followed. Not following these guidelines may result in inefficient DC-DC operation or DC-DC output
supply brownouts and unintended resets.
The minimum input voltage in LN mode depends on both the DC-DC load current as well as the ambient temperature (Tamb), because
the maximum DC-DC load current is limited to 100 mA above Tamb=85°C. Consult the table below for the recommended minimum
VREGVDD input supply voltage to prevent dropout for particular conditions.
The powertrain NFET and PFET switches are optimized based on load current by configuring the NFETCNT and PFETCNT bitfields in
the EMU_DCDCMISCCTRL register.
Table 2.2. DC-DC Configuration, Maximum Load Current, and Minimum Input Voltage in Low Noise Mode
Maximum Load Current,
ILOAD
Drive
Minimum VREGVDD In- Maximum Ambient
put Voltage
Temperature, Tamb
PFETCNT/NFETCNT
Configuration
50 mA
Light
2.4 V
125°C
3
100 mA
Medium
2.4 V
125°C
7
200 mA
Heavy
2.6 V
85°C
15
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
The plots below show the DCM Light Drive and CCM Light/Medium/Heavy Drive efficiencies vs load currents, for input voltages of 3.8
V, 3.3 V, and 2.4 V.
Figure 2.1. DCM Light Drive/CCM Light/Medium/Heavy Drive Efficiency vs Load Current
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
Low Power Mode
Note: The guidelines below must be followed. Not following these guidelines may result in inefficient DC-DC operation or DC-DC output
supply brownouts and unintended resets.
The DC-DC Low Power controller comparator bias may be adjusted based on load current using the LPCMPBIAS bitfield in the
EMU_DCDCMISCCTRL register. The powertrain switches are always recommended to be set to 7 in Low Power mode (i.e., PFETCNT
= NFETCNT = 7).
Table 2.3. DC-DC Configuration, Maximum Load Current, and Minimum Input Voltage in Low Power Mode
Maximum Load Current,
ILOAD
Minimum
VREGVDD Input
Voltage
Maximum Ambient Temperature, Tamb
LPCMPBIAS Configu- PFETCNT/NFETCNT
ration
Configuration
75 µA
2.4 V
125°C
0
7
500 µA
2.4 V
125°C
1
7
2.5 mA
2.4 V
125°C
2
7
10 mA
2.4 V
125°C
3
7
Bypass Mode
After the DC-DC is switched to bypass mode, it has the ability to operate with a VREGVDD input as low as 1.85 V. However, because
the internal bypass switch has a finite on-resistance (RBYP, consult the datasheet specification for the maximum value), the voltage at
the DVDD pin may be below DVDDmin, depending on the load current.
The minimum VREGVDD input supply voltage may be determined using the following equation:
× R
+ RPCB )
VREGVDD MIN = DVDD MIN + I
LOAD ( BYP
Some margin should be applied to this equation to account for variations in ILOAD, RBYP, and RPCB. In addition, effort should be made
to reduce the parasitic trace resistance as much as possible on the power supply trace routing, as these will increase RPCB.
2.6 DC-DC Efficiency Threshold
A DC-DC's efficiency peaks at high current loads, and drops off as the load current is reduced. Once the DC-DC converter efficiency
drops below a certain threshold, not only is there no benefit to using it, but it will actually be less efficient than turning off the DC-DC
and powering the output directly from the main supply.
This efficiency threshold may be calculated by simply dividing the DC-DC output voltage by the DC-DC input voltage. For example,
when the main supply is at 3.0 V and the DC-DC output is configured for 1.8 V, the DC-DC efficiency threshold is 60%. When the DCDC converter is operating below the threshold, the firmware should put the device into bypass mode.
The table below shows the efficiency threshold for both DCM and CCM over a range of input voltages.
Table 2.4. DC-DC Converter Efficiency Threshold: Low Noise Mode, Light Drive
VREGVDD Input Voltage
VDCDC Output Voltage
Efficiency
Threshold
DCM, 3 MHz Load Current at
Efficiency Threshold
CCM, 7 MHz Load Current at
Efficiency Threshold
3.8 V
1.8 V
47.4%
1.0 mA
2.5 mA
3.3 V
1.8 V
54.5%
1.0 mA
2.5 mA
2.4 V
1.8 V
69.2%
1.3 mA
2.0 mA
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
The plots below show the DCM and CCM Light Drive efficiencies vs load currents, for input voltages of 3.8 V, 3.3 V, and 2.4 V.
Figure 2.2. DCM/CCM Light Drive Efficiency vs Load Current
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AN0948: Power Configurations and DC-DC
DC-DC Converter Module Overview
2.7 Using the DC-DC Converter to Power External Loads
While the DC-DC converter is primarily intended to power the internal, on-chip loads (e.g., radio and core), it may be used to power
external devices as well. However, systems using the DC-DC converter to power external devices should consider:
1. The total worst-case maximum static DC-DC load currents, including both internal and external devices, for active and low energy
modes. This maximum total load current should be used when calling the emlib configuration and optimization functions (refer to
section 2.5 Maximum Output Current and Minimum Input Voltage).
2. The worst-case maximum transient load current, including both internal and external devices, for active and low energy modes.
3. The maximum load current drawn in Bypass mode (refer to section 2.5 Maximum Output Current and Minimum Input Voltage)
4. The required voltage-regulation accuracy and ripple voltage tolerance of the external devices
5. The power-up / down timing requirements for external devices
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AN0948: Power Configurations and DC-DC
DC-DC Power Configurations
3. DC-DC Power Configurations
EFM32 Series 2 and EFR32 Wireless Gecko devices have a default startup configuration and three selectable power configurations. A
power configuration is defined as a combination of hardware (i.e., PCB and schematic) connections and firmware (i.e., emlib).
EFM32 Series 2 and EFR32 Wireless Gecko Supply Pin Overview
Below is an overview of the supply pins. Consult the datasheet for restrictions for minimum and maximum values for each supply, as
well as other supply constraints
• VREGVDD — DC-DC input voltage
• AVDD — Analog power supply
• VREGSW — DC-DC powertrain switching node
• DVDD — Input to the internal Digital LDO & DC-DC feedback input
• DECOUPLE — Output of the internal Digital LDO & Digital logic power supply
• RFVDD (Wireless Gecko only) — RF analog power supply
• PAVDD (Wireless Gecko only) — Power amplifier power supply
3.1 Startup Configuration
During power-on reset (POR), the system boots up in a safe Startup Configuration that supports all of the available Power Configurations. The Startup Configuration is shown in the simplified diagram below.
In the Startup Configuration:
• The DC-DC converter's Bypass switch is On (i.e., the VREGVDD pin is shorted internally to the DVDD pin).
• The analog blocks are powered from the AVDD supply pin (i.e., ANASW=0).
VDD
Main
Supply
+
–
VREGVDD
IOVDD
AVDD
Bypass
Switch
VREGSW
DC-DC
Driver
FLASH
ON
0
DC-DC
VREGVSS
1
ANASW
Analog
Blocks
DVDD
Digital
LDO
Digital
Logic
DECOUPLE
Figure 3.1. Startup Configuration
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AN0948: Power Configurations and DC-DC
DC-DC Power Configurations
3.2 Power Configuration 1: No DC-DC
In certain applications, use of the integrated DC-DC converter isn't attractive. For example:
• the application is extremely space-sensitive or cost-sensitive
• the application's power efficiency isn't important
• the application's expected EM0/EM1 currents are very low (i.e., ~3 mA or less). Refer to section 2.6 DC-DC Efficiency Threshold.
In Power Configuration 1:
• The DC-DC converter is programmed in Off mode (see section 4.2 To initialize the DC-DC converter to OFF), and the Bypass switch
is Off. The DVDD pin must be powered externally - typically, DVDD is connected to the main supply.
• RFVDD and PAVDD (Wireless Gecko), which power the radio, are shorted to the main supply as well.
• IOVDD and AVDD are powered from the main supply as well.
• VREGSW should be left disconnected in this configuration.
VDD
Main
Supply
CVDD CVDD1
10 µF 0.1 µF
+
–
CIOVDD CIOVDD1
1 µF 0.1 µF
CAVDD CAVDD1
10 µF 10 nF
VREGVDD
IOVDD
AVDD
Bypass
Switch
VREGSW
DC-DC
Driver
CDEC
1 µF
0
DC-DC
VREGVSS
CDVDD
0.1 µF
FLASH
OFF
1
ANASW
Analog
Blocks
DVDD
Digital
LDO
Digital
Logic
RF
Power
Amplifier
RF
Analog
DECOUPLE
RFVDD
CRFVDD
220 nF
LPAVDD
22 nH
PAVDD
CRFVDD1
10 pF
CPAVDD1
10 pF
CPAVDD
220 nF
Figure 3.2. Power Configuration 1 — No DC-DC
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AN0948: Power Configurations and DC-DC
DC-DC Power Configurations
3.3 Power Configuration 2: DC-DC
For the lowest power applications, the DC-DC converter can be used to power the DVDD supply, as well as RFVDD and PAVDD (on
Wireless Gecko).
In Power Configuration 2:
• The DC-DC Output (VDCDC) is connected to DVDD. DVDD powers the internal Digital LDO which powers the digital circuits.
• RFVDD (Wireless Gecko) is also powered from the DC-DC Output. RFVDD powers the radio analog.
• PAVDD (Wireless Gecko only) is connected to the DC-DC output through a filter. PAVDD powers the power amplifier used for the
radio.
• AVDD is connected to the main supply voltage. The internal analog blocks may be powered from AVDD or DVDD, depending on the
ANASW configuration. Flash is always powered from the AVDD pin.
• IOVDD could be connected to either the main supply (as shown below) or to VDCDC, depending on the system IO requirements.
VDD
Main
Supply
+
–
VREGVDD
VDCDC
CDVDD
0.1 µF
CDEC
1 µF
IOVDD
AVDD
Bypass
Switch
LDCDC
4.7 µH
CDCDC
1 µF
CIOVDD CIOVDD1
1 µF 0.1 µF
CAVDD CAVDD1
10 µF 10 nF
CVDD CVDD1
10 µF 0.1 µF
VREGSW
DC-DC
Driver
FLASH
OFF
0
DC-DC
VREGVSS
1
ANASW
Analog
Blocks
DVDD
Digital
LDO
Digital
Logic
RF
Power
Amplifier
RF
Analog
DECOUPLE
RFVDD
CRFVDD
220 nF
LPAVDD
22 nH
PAVDD
CRFVDD1
10 pF
CPAVDD
220 nF
CPAVDD1
10 pF
Figure 3.3. Power Configuration 2 — DC-DC Powers DVDD
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AN0948: Power Configurations and DC-DC
DC-DC Power Configurations
3.4 Power Configuration 3: DC-DC (High Power RF)
For the high-power radio applications (i.e., >13 dBm transmit power), it is necessary to power the radio power amplifier (PAVDD) from
the main supply. In this configuration, the DC-DC converter can be used to power the DVDD supply and RFVDD.
In Power Configuration 3:
• The DC-DC Output (VDCDC) is connected to DVDD. DVDD powers the internal Digital LDO which powers the digital circuits.
• RFVDD (Wireless Gecko) is also powered from the DC-DC Output. RFVDD powers the radio analog.
• PAVDD (Wireless Gecko only) is connected to the main supply through a filter. PAVDD powers the power amplifier used for the
radio.
• AVDD is connected to the main supply voltage. The internal analog blocks may be powered from AVDD or DVDD, depending on the
ANASW configuration. Flash is always powered from the AVDD pin.
• IOVDD could be connected to either the main supply (as shown below) or to VDCDC, depending on the system IO requirements.
VDD
Main
Supply
+
–
CVDD CVDD1
10 µF 0.1 µF
VREGVDD
VDCDC
CDVDD
0.1 µF
CDEC
1 µF
IOVDD
AVDD
Bypass
Switch
LDCDC
4.7 µH
CDCDC
1 µF
CIOVDD CIOVDD1
1 µF 0.1 µF
CAVDD CAVDD1
10 µF 10 nF
VREGSW
DC-DC
Driver
FLASH
OFF
0
DC-DC
VREGVSS
1
ANASW
Analog
Blocks
DVDD
Digital
LDO
Digital
Logic
RF
Power
Amplifier
RF
Analog
DECOUPLE
RFVDD
CRFVDD
220 nF
LPAVDD
22 nH
PAVDD
CRFVDD1
10 pF
CPAVDD1
10 pF
CPAVDD
220 nF
Figure 3.4. Power Configuration 3 — DC-DC powers DVDD, Main Supply powers PAVDD
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AN0948: Power Configurations and DC-DC
DC-DC Programming Using emlib
4. DC-DC Programming Using emlib
To simplify use of the DC-DC converter, emlib contains functions which will properly configure the DC-DC for efficient operation. It is
strongly recommended to take advantage of these functions. These emlib functions will also avoid or workaround any errata issues
affecting the DC-DC converter. More information on the EMU emlib library can be found using the [Software Documentation] tile in
Simplicity Studio.
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AN0948: Power Configurations and DC-DC
DC-DC Programming Using emlib
4.1 To initialize the DC-DC converter to Low Noise or Bypass mode
1. Define a structure of type EMU_DCDCInit_TypeDef
typedef struct
{
EMU_PowerConfig_TypeDef powerConfig;
EMU_DcdcMode_TypeDef dcdcMode;
uint16_t mVout;
uint16_t em01LoadCurrent_mA;
uint16_t em234LoadCurrent_uA;
uint16_t maxCurrent_mA;
EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower;
EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl;
} EMU_DCDCInit_TypeDef;
Description of parameters:
• powerConfig: Should always be set to emuPowerConfig_DcdcToDvdd
• dcdcMode: May be set to
• emuDcdcMode_Bypass — Enables Bypass mode (i.e., the DC-DC is not switching and the VREGVDD pin is shorted internally
to the DVDD pin)
• emuDcdcMode_LowNoise — Configures the DC-DC converter for Low Noise mode
• mVout: Target output voltage in mV's. To prevent risk of triggering the brown-out protection on the DVDD supply pin, mVout
should not be set lower than "1800" . Consult the datasheet DC-DC Regulation DC Accuracy specifications to ensure sufficient
margin is allowed in the actual DC-DC output voltage.
• em01LoadCurrent_mA: Highest average load current in mA expected in either EM0 or EM1 modes. Used to optimize the DC-DC
settings (e.g., PFETCNT and NFETCNT) for efficiency. The total must be less than "200", and should include both the internal
current required by the EFM32 Series 2 or EFR32 Wireless Gecko device as well as current for any other devices attached to
the DC-DC converter output. The default em01LoadCurrent_mA value for Wireless Gecko is "15", and the default for Jade
Gecko and Pearl Gecko is "5".
• em234LoadCurrent_uA: Highest average load current in µA expected in EM2, EM3, or EM4. Used to optimize the DC-DC settings (e.g. LPCMPBIAS) for efficiency. The total must be less than "1000", and should include both the EFM32 Series 2 or
EFR32 Wireless Gecko device current, as well as current for any other devices attached to the DC-DC converter output.
• maxCurrent_mA: Maximum peak load current in mA for any energy mode. The total must be less than "200", and should include
both the internal current required by the EFM32 Series 2 or EFR32 Wireless Gecko device as well as current for any other devices attached to the DC-DC converter output.
• anaPeripheralPower: Changes to the anaPeripheralPower selection should be made immediately out of reset, before all
clocks are enabled (with the exception of HFRCO and ULFRCO), and once set it should not be changed. May be set to:
• emuDcdcAnaPeripheralPower_AVDD — Selects the AVDD pin as analog power supply. Typically lower noise, but less energy efficient.
• emuDcdcAnaPeripheralPower_DCDC — Selects the DVDD pin (i.e., DC-DC output) as analog power supply. Typically more
energy efficient, but more noise.
• reverseCurrentControl: This parameter uses special encoding, defined as follows:
• Set to "-1" to configure the DC-DC for Low Noise DCM.
• Set to a value of 0 or greater to configure the DC-DC for Low Noise forced CCM, where the value of reverseCurrentContro
l is the reverse current limit in mA (see section 5.8 Low-Side (Zero Detector) Current Limiter for further details on the reverse current limit).
2. Call EMU_DCDCInit(), passing the EMU_DCDCInit_TypeDef structure created in step 1 as an argument. At the completion of this
function call, the DC-DC should be in regulation. This function does the following:
• Configures the PWRCFG register
• Loads the production calibration register values into the respective registers.
• Configures the powertrain switches for optimal efficiency based on the em01LoadCurrent_mA and em234LoadCurrent_uA values
• Configures the High-Side Current Limits for both LN and LP modes (i.e., LNCLIMILIMSEL, LPCLIMILIMSEL)
• Configures the DC-DC output target voltage, interpolating, if necessary, between the production-calibrated reference voltage
levels.
• Configures the analog power switch to either AVDD or DVDD, based on the anaPeripheralPower value. Once set, the analog
power setting should not be changed.
• Sets the DCDCMode bitfield to select either Low Noise (which initiates regulation) or Bypass.
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AN0948: Power Configurations and DC-DC
DC-DC Programming Using emlib
4.2 To initialize the DC-DC converter to OFF
To power off the DC-DC, and set the internal Bypass switch to Off, call the EMU_DCDCPowerOff() function. This function should only be
called when using Power Configuration 1 (see section 3.2 Power Configuration 1: No DC-DC).
Note: Before calling this function, it is critical to ensure that the hardware provides an external power supply to DVDD. The internal
bypass switch cannot be used when the DC-DC is powered off, so if the DC-DC is powered off without DVDD powered externally, there
is a risk the device could be put into an unrecoverable state.
4.3 To enter EM2, EM3, or EM4 low energy modes from Low Noise mode
To enter the low energy modes, call EMU_EnterEM2(), EMU_EnterEM3(), or EMU_EnterEM4(). The DC-DC converter will automatically
transition to Low Power mode while the core is in low energy mode.
Note: The ARM CortexTM SLEEPONEXIT functionality is not currently compatible with the emlib low energy mode functions. The
SLEEPONEXIT feature allows the MCU to wakeup on an interrupt, service an interrupt routine, then immediately (and autonomously)
go back to sleep. The SLEEPONEXIT interrupt routines are typically written only for the functional requirements of the module interrupt
(e.g. LEUART) with no knowledge about the DC-DC or other power management systems. Because the integrated DC-DC converter
requires firmware reprogramming before exiting or entering the low energy modes, it is not straightforward to use it in conjunction with
SLEEPONEXIT.
4.4 To optimize the powertrain switches in Low Noise mode
Once the DC-DC is configured and running, firmware may call EMU_DCDCOptimizeSlice(loadCurrent) to update the NFETCNT and
PFETCNT settings for optimal efficiency, where the loadCurrent argument is the highest average expected EM0 / EM1 load current in
mA.
This function might be called whenever there is a substantial expected change in load current (e.g., between low-current radio receive
and high-current radio transmit operations).
4.5 To enter Bypass mode from Low Noise mode
After the DC-DC has already been initialized to Low Noise mode as described in section 4.1 To initialize the DC-DC converter to Low
Noise or Bypass mode, firmware can call EMU_DCDCModeSet(emuDcdcMode_Bypass) to enter Bypass mode.
Firmware may switch to Bypass mode for several reasons:
1. The VREGVDD input supply voltage is nearing the minimum input voltage for the DC-DC (see section 2.5 Maximum Output Current and Minimum Input Voltage)
2. The DC-DC output load current has decreased to a point (e.g., ~2.5 mA < ILOAD < ~ 18 mA) that the DC-DC should switch from
CCM to DCM to improve efficiency (see section 4.7 To switch from Low Noise CCM mode to Low Noise DCM mode). Switching to
Bypass mode is an intermediate step in the CCM to DCM transition.
3. The DC-DC output load current has decreased to a point (e.g., ILOAD < ~2.5 mA) that the DC-DC is now operating below its efficiency threshold (see section 2.6 DC-DC Efficiency Threshold)
4.6 To re-enter Low Noise mode from Bypass mode
If DC-DC has already been initialized, but is currently in Bypass mode, firmware can call EMU_DCDCModeSet(emuDcdcMode_LowNoise)
to re-enter Low Noise mode.
Note: This command should only be used after the DC-DC has already been initialized as described in section 4.1 To initialize the DCDC converter to Low Noise or Bypass mode
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AN0948: Power Configurations and DC-DC
DC-DC Programming Using emlib
4.7 To switch from Low Noise CCM mode to Low Noise DCM mode
When the DC-DC output load current is less than ~18 mA, the DC-DC can switch from CCM to DCM to improve efficiency (see figure
Figure 2.1 DCM Light Drive/CCM Light/Medium/Heavy Drive Efficiency vs Load Current on page 6).
There is no method to directly switch between CCM and DCM (or vice-versa). If the DC-DC converter is operating in CCM, firmware
must configure the DC-DC to Bypass mode before it can be configured for DCM. Note that this may result in a large and undesirable
transient voltage on the DC-DC output, as the DC-DC output will be momentarily shorted to the VREGVDD input supply.
Here is the recommended sequence to perform this switch:
1. Define a structure of type EMU_DCDCInit_TypeDef with reverseCurrentControl set to -1 (i.e., DCM).
2. Call EMU_DCDCModeSet(emuDcdcMode_Bypass) to enter Bypass mode.
3. Call EMU_DCDCInit(), passing the new DCM DCDCInit structure created in step 1 as an argument.
To switch from DCM to CCM instead, change the reverseCurrentControl parameter in step 1 to a value greater than 0 (i.e., CCM),
instead.
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AN0948: Power Configurations and DC-DC
DC-DC Configuration Reference
5. DC-DC Configuration Reference
Note: emlib contains functions which will properly configure the DC-DC for efficient operation. It is strongly recommended to take advantage of these functions. These emlib functions will also avoid or workaround any errata issues affecting this block.
5.1 DC-DC Module Register Locks
The DC-DC module has several locks that can be used to prevent accidental changes to the EMU and DC-DC configuration registers.
Note that these locks are unlocked by default, and are not used by any of the emlib DC-DC configuration functions.
1. EMU_LOCK — All non-DC-DC, EMU registers may be unlocked by writing 0xADE8 to LOCKKEY, or locked by writing any other
value to LOCKKEY.
2. EMU_PWRLOCK — All DC-DC registers may be unlocked by writing 0xADE8 to LOCKKEY, or locked by writing any other value to
LOCKKEY.
5.2 DC-DC Mode Selection
The DC-DC Mode has multiple mode configurations depending on which energy mode the device is in. Note that the below details are
provided for reference only, as the DC-DC Mode is configured automatically for all energy modes in the emlib DC-DC functions.
In EM0/EM1, the DC-DC mode may be configured by the DCDCMODE bitfield in the EMU_DCDCCTRL register to one of the following
settings:
• BYPASS — Bypass switch is ON (i.e., VREGVDD is shorted internally to the DVDD pin).
• LOWNOISE — Bypass switch is OFF. The Low Noise controller is enabled.
• LOWPOWER — Bypass switch is OFF. The Low Power controller is enabled. Because the low power mode is limited to a maximum
load current of 10 mA, it should only be enabled in low energy modes EM2, EM3, or EM4.
• OFF — Bypass switch is OFF. The DC-DC converter is disabled. This mode should only be used in Power Configuration 1 (see
section 3.2 Power Configuration 1: No DC-DC). Because the bypass switch is off, hardware MUST supply DVDD externally if this
configuration is selected. Selecting this mode without an external connection supplying DVDD may put the device into an unrecoverable state.
In EM2/EM3, the DC-DC mode may be configured by the DCDCMODEEM23 bitfield in the EMU_DCDCCTRL register to one of the
following settings:
• EM23SW — DC-DC Mode is set according to the DCDCMODE configuration.
• EM23LOWPOWER — DC-DC Mode is set to Low Power.
In EM4, the DC-DC mode may be configured by the DCDCMODEEM4 bitfield in the EMU_DCDCCTRL register to one of the following
settings:
• EM4SW — DC-DC Mode is set according to the DCDCMODE configuration.
• EM4LOWPOWER — DC-DC Mode is set to Low Power.
5.3 DC-DC Output Voltage Configuration
Note the below details are provided for reference only, as the output voltage settings are configured automatically in the emlib DC-DC
functions.
In Low Noise Mode, the output voltage is controlled by the LNVREF and LNATT bitfields in the EMU_DCDCLNVCTRL register.
LNVREF controls the voltage reference level and LNATT controls the attenuation . For 1.8 V output and greater, LNATT should always
be set to 1. During production, each device has LNVREF calibration values stored in internal flash that correspond to a DC-DC output
of 1.8 V and 3.0 V. For output voltages between 1.8 V and 3.0 V, the firmware should interpolate between calibration values.
In Low Power Mode, the output voltage is controlled by the LPVREF and LPATT bitfields in the EMU_DCDCLPVCTRL register.
LPVREF controls the voltage reference level and LPATT controls the attenuation . For 1.8 V output and greater, LPATT should always
be set to 1. During production, each device has multiple LPVREF calibration values (one per LPCMPBIAS setting) stored in internal
flash that correspond to a DC-DC output of 1.8 V and 3.0 V. For output voltages between 1.8 V and 3.0 V, the firmware should interpolate between the calibration values corresponding to the desired LPCMPBIAS configuration.
5.4 Low Power Mode Duty Cycling
Firmware should set LPREFDUTYEN in EMU_DCDCLPCTRL to enable Duty Cycling for optimal efficiency in Low Power mode. Note
that this configuration is handled automatically in the emlib DC-DC functions.
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AN0948: Power Configurations and DC-DC
DC-DC Configuration Reference
5.5 Low Power Mode Hysteresis
The LPCMPHYSSEL bitfield in EMU_DCDCLPCTRL configures the hysteresis in Low Power mode. During production, each device
has four calibration values (one for each LPCMPBIAS setting) stored in internal flash which correspond to ~100 mV of hysteresis . The
calibration values corresponding to the desired LPCMPBIAS configuration should be written to the LPCMPPHYSSEL bitfield during initialization. Note that this configuration is handled automatically in the emlib DC-DC functions.
5.6 Bypass Current Limiter
The DC-DC Bypass Current Limit limits the maximum current drawn from the main supply in Bypass mode. This current limit is enabled
by setting the BYPLIMEN bit in the EMU_DCDCCLIMCTRL register, and the limit value may be adjusted between 20 mA and 320 mA
using the BYPLIMSEL bitfield in the EMU_DCDCMISCCTRL register.
5.7 High-Side Current Limiter
The DCDC High-Side Current Limiter includes two different programmable current limits (LNCLIMILIMSEL and LPCLIMILIMSEL) in the
EMU_DCDCMISCCTRL register. An overlimit condition generates a PFETOVERCURRENTLIMIT interrupt in the EMU_IF register.
Depending on the DC-DC mode, these programmable current limits may serve different functions:
1. In LP mode, LPCLIMILIMSEL is used to adjust the DC-DC pumping current to optimize efficiency.
2. In LN modes, LNCLIMILIMSEL prevents the DC-DC from building up substantial current which would burn out the DC-DC switch in
the unlikely event the DC-DC output or switching node were accidentally connected to ground or to a lower voltage power supply.
3. In LN modes, LNCLIMILIMSEL limits the magnitude of current the DC-DC will draw. Some batteries have a high internal impedance, and the battery output voltage may droop severely under high transient current load.
Low Power
In LP mode, the current limiter is used to adjust the average pumping current to optimize the power efficiency. In LP mode, constant
configuration of PFETCNT=7 and LPCLIMILIMSEL=1 is recommended, which corresponds to a nominal 80 mA peak current.
Firmware may safely ignore the PFETOVERCURRENTLIMIT flag in the EMU_IF register in LP mode, because this interrupt will trigger
during normal LP operation.
Low Noise CCM/DCM
In LN modes, the High-Side Current Limiter is used to limit the maximum current drawn from the main supply. For example, if the main
supply is a battery with a non-negligible output impedance, the current should be limited to prevent voltage droops at the DC-DC's input
pin (VREGVDD). Otherwise, the High-Side Current Limiter is configured to protect the DC-DC powertrain switch from damage due to
excessive current.
The following equation may be used to determine the appropriate LNCLIMILSEL setting:
LNCLIMILIMSEL =
(I MAX + 40mA) × 1.5
5mA × (PFETCNT + 1)
−1
Where:
• IMAX is the lower of a) the maximum current the main supply can provide or b) 200 mA.
• 40 mA is an empirical value that represents the expected output current ripple with some margin
• The 1.5 factor accounts for errors from input and output voltage variation, switching frequency variation, inductance variation, detection error, etc..
For example, when PFETCNT=3, and IMAX=20 mA, setting LNCLIMILIMSEL=3 equates to a peak current limit of 80 mA. Note that the
actual expected load current should be lower than the current limit setting.
When the High-Side Current Limiter is triggered, it will turn off the power train PFET and turn on the powertrain NFET earlier, which
may result in sub-harmonics. Severe sub-harmonics could reduce the maximum average current. In normal Low Noise mode operation,
the High-Side Current Limiter is not expected to trigger assuming it is configured to a level higher than necessary, with margin. However, significant changes in load current (e.g., entering LN mode from LP or bypass modes), may cause the current limiter to trigger occasionally even in normal operation. When the high side current limiter is triggered, the PFETOVERCURRENTLIMIT flag in the EMU_IF
register will be set.
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AN0948: Power Configurations and DC-DC
DC-DC Configuration Reference
5.8 Low-Side (Zero Detector) Current Limiter
The DC-DC Low-Side Current Limiter is also referred to as the Zero Detector, and serves multiple purposes depending on the DC-DC
configuration. The current limit value is programmed by the ZDETILIMSEL bitfield in the EMU_DCDCZDETCTRL register and an overlimit condition generates a NFETOVERCURRENTLIMIT interrupt in the EMU_IF register.
Low Power
In LP mode, the Zero Detector is used to detect the end of each pumping process to turn off the powertrain NFET, so that all energy in
the inductor is delivered to the load capacitor.
Firmware may safely ignore the NFETOVERCURRENTLIMIT flag in the EMU_IF register in LP mode.
Low Noise DCM
In LN DCM mode, the Zero Detector turns the powertrain NFET off when it detects the inductor current has dropped to zero.
Firmware may safely ignore the NFETOVERCURRENTLIMIT flag in the EMU_IF register in LN DCM.
Low Noise CCM
In LN CCM, the Zero Detector is reconfigured as a reverse current limiter to prevent current flowing back into the battery or main supply. The reverse current limit is set by the ZDETILIMSEL bitfield in EMU_DCDCZDETCTRL.
If the battery or main supply can safely tolerate reverse current, the reverse current limiter is simply configured to its maximum value
(i.e., ZDETILIMSEL=7) to protect the DC-DC powertrain switch from damage due to excessive current. For example, in the unlikely
event the DC-DC supply output were accidentally shorted to another higher voltage power supply, the DC-DC may sink large amounts
of current in its attempt to regulate to its target.
The recommended ZDETILIMSEL setting may be determined by the following equation:
ZDETILIMSEL =
(I RMAX + 40mA) × 1.5
2.5mA × (NFETCNT + 1)
Where:
• IRMAX is the lower of a) the maximum reverse current the main supply can tolerate or b) 280 mA.
• 40 mA is an empirical value that represents the expected output current ripple with some margin
• The 1.5 factor accounts for errors from input and output voltage variation, switching frequency variation, inductance variation, detection error, etc..
So, for example, if NFETCNT=3 and IR_MAX = 0 mA, ZDETILIMSEL=6. Note, the reverse current limit isn’t very accurate and may have
>10 mA error.
In normal Low Noise CCM operation, the Zero Detector interrupt is not expected to trigger. However, significant changes in load current
(e.g., entering LN mode from LP or bypass modes), may cause the current limiter to trigger occasionally even in normal operation.
When the Zero Detector is triggered, the NFETOVERCURRENTLIMIT flag in the EMU_IF register will be set. If firmware sees this flag
triggering frequently in LN CCM, this likely indicates that the ZDETLIMSEL threshold is set too low and should be raised; otherwise,
DC-DC efficiency may be impacted.
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AN0948: Power Configurations and DC-DC
DC-DC Recommended Components
6. DC-DC Recommended Components
6.1 DC-DC Output Capacitor
Note that the Murata GRM188R71A105KA61D capacitor was used for all of the DC-DC validation and characterization testing.
Table 6.1. Recommended DC-DC Output Capacitor
Manufacturer
Part Number
Value
(μF)
Voltage
Rating (V)
Dielectric
Operating Temperature (°C)
Package
Murata
GRM188R71A105KA61D
1±10%
10
X7R
-55 to +125
0603/1608
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AN0948: Power Configurations and DC-DC
DC-DC Recommended Components
6.2 DC-DC Inductor
Below are some recommended inductor part numbers and LN CCM efficiency curves for each. Note that the Murata
LQH3NPN4R7MM0L inductor was used for all of the DC-DC validation and characterization testing.
Table 6.2. Recommended DC-DC Inductors
Manufacturer
Part Number
Value
(μH)
Isaturation
(mA)
DCR (Ω)
Operating Temperature (°C)
Package
Murata
LQH3NPN4R7MM0L
4.7±20%
880
0.13±20%
-40 to +125
1212/3030
Murata
LQH2HPN4R7MGRL
4.7±20%
1090
0.30±20%
-40 to +105
1008/2520
Murata
LQM21FN4R7M80L
4.7±20%
120
0.18±30%
-55 to +125
0805/2012
Murata
LQM18FN4R7M00D
4.7±20%
80
0.60±30%
-55 to +125
0603/1608
Murata
LQH2HPN4R7MGRL
4.7±20%
1090
0.30±20%
-40 to +105
1008/2520
Murata
LQM21PN4R7MGRD
4.7±20%
800
0.23±20%
-55 to +125
0805/2012
Murata
LQM18PN4R7MFRL
4.7±20%
Unspecified
0.44±25%
-40 to +85
0603/1608
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AN0948: Power Configurations and DC-DC
DC-DC Recommended Components
Figure 6.1. Inductor Efficiency Curves
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AN0948: Power Configurations and DC-DC
DC-DC Layout Considerations
7. DC-DC Layout Considerations
Because the DC-DC converter is a high-frequency, high-current module, some special layout considerations are required for optimal
operation:
• The following connections should be made on the PCB using minimum trace length and resistance
• • Between the VREGSW pin and the LDCDC inductor
• Between the LDCDC inductor and the CDCDC capacitor
• Between the CDCDC capacitor and the DVDD pin
• Between the Main Supply and the VREGVDD pin
• Between the VREGVSS pin and ground
• The LDCDC inductor should be placed far away from any noise-sensitive circuitry (e.g., a radio antenna). The inductor should ideally
be on the opposite side of the PCB, so that there is a solid ground plane shielding the noisy inductor from the sensitive circuitry.
• For more detailed radio-specific layout guidelines, consultAN928: EFR32 Layout Design Guide .
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AN0948: Power Configurations and DC-DC
DC-DC Software Examples
8. DC-DC Software Examples
8.1 Software Example 1 — Bypass
This example enables the bypass switch, which shorts the VREGVDD pin to the DVDD pin internally within the DC-DC module. This
mode is functionally compatible with the EFM32 Series 1 Gecko power configuration.
8.2 Software Example 2 — DC-DC to DVDD 1.8V
This example enables the DC-DC converter and sets the nominal output voltage to 1.8 V. This example requires an external inductor
and capacitor (see section 3.3 Power Configuration 2: DC-DC).
The DC-DC is configured for Low Noise mode in EM0/1 and Low Power mode in EM2/EM3/EM4, and the example assumes the following load currents:
• EM0/1 load current — 5 mA
• EM2/EM3/EM4 load current — 10 uA
• Max Current — 160 mA
Analog peripherals are powered from the AVDD supply.
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AN0948: Power Configurations and DC-DC
Revision History
9. Revision History
9.1 Revision 0.3
2016-6-15
Overhaul of all Power Configuration diagrams
Added "Efficiency Threshold" section
Added "Maximum Output Current" section
Added "Programming using emlib" section
Added "Recommend Components" section
Added "Layout Considerations" section
Added "Configuration Reference" section
9.2 Revision 0.2
2015-11-13
Added support for EFR32 Wireless Gecko portfolio
Updated recommendations for NFETCNT in EM2/EM3/EM4 LP mode in the Load Current Selection table.
9.3 Revision 0.1
2015-11-6
Initial revision.
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