PIC16(L)F170X/171X Cost Effective 8-Bit Intelligent Analog Flash Microcontrollers Description: PIC16F(L)170X/171X microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP) to suit a variety of general purpose applications. These 14 to 44-pin devices deliver on-chip Op Amps, Core Independent Peripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased design flexibility. Core Features: Digital Peripherals: • C Compiler Optimized RISC Architecture • Only 49 Instructions • Operating Speed: - 0-32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Up to Four 8-bit Timers • One 16-bit Timer • Power-on Reset (POR) • Power-up Timer (PWRT) • Low-Power Brown-Out Reset (LPBOR) • Programmable Watchdog Timer (WDT) up to 256s • Programmable Code Protection • Configurable Logic Cell (CLC): - Integrated combinational and sequential logic • Complementary Output Generator (COG): - Rising/falling edge dead-band control/blanking • Numerically Controlled Oscillator (NCO): - Generates true linear frequency control and increased frequency resolution - Input Clock: 0Hz < FNCO < 32 MHz - Resolution: FNCO/220 • Capture/Compare/PWM (CCP) module Memory: • Up to 16 Kwords Flash Program Memory • Up to 2048 Bytes Data SRAM Memory • Direct, Indirect and Relative Addressing modes Operating Characteristics: • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF170X/171X) - 2.3V to 5.5V (PIC16F170X/171X) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features: • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical 2013 Microchip Technology Inc. • PWM: Two 10-bit Pulse-Width Modulators • Serial Communications: - SPI, I2C™, RS-232, RS-485, LIN compatible - Auto-Baud Detect, auto-wake-up on start • Up to 35 I/O Pins and One Input Pin: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O Intelligent Analog Peripherals: • Operational Amplifiers: - Two configurable rail-to-rail op amps - Selectable internal and external channels - 2 MHz gain bandwidth product • High-Speed Comparators: - Up to two comparators - 50 ns response time - Rail-to-rail inputs • 10-Bit Analog-to-Digital Converter (ADC): - Up to 28 external channels - Conversion available during Sleep - Temperature indicator • Zero-Cross Detector (ZCD): - Detect when AC signal on pin crosses ground • 8-Bit Digital-to-Analog Converter (DAC): - Output available externally - Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC • Internal Voltage Reference module Advance Information DS40001708A-page 1 PIC16(L)F170X/171X Clocking Structure: Programming/Debug Features: • 16 MHz Internal Oscillator Block: - ±1% at calibration - Selectable frequency range from 0 to 32 MHz • 31 kHz Low-Power Internal Oscillator • External Oscillator Block with: - Three crystal/resonator modes up to 20 MHz - Two external clock modes up to 32 MHz • Fail-Safe Clock Monitor • Two-Speed Oscillator Start-up • Oscillator Start-up Timer (OST) • In-Circuit Debug Integrated On-Chip • Emulation Header for Advanced Debug: - Provides trace, background debug and up to 32 hardware break points • In-Circuit Serial Programming™ (ICSP™) via Two Pins Program Memory Flash (words) Data SRAM (bytes) I/O Pins 8-bit/16-bit Timers High-Speed Comparators Op Amp 10-bit ADC (ch) 5-/8-bit DAC Zero Cross CCP/PWM COG EUSART I2C™/SPI CLC NCO Debug(1) PIC16(L)F170X/171X FAMILY TYPES PIC16(L)F1703 2k 256 12 2/1 0 2 8 0/0 1 2/0 0 0 1 0 0 I/E PIC16(L)F1704 4k 512 12 4/1 2 2 8 0/1 1 2/2 1 1 1 3 0 I/E PIC16(L)F1705 8k 1024 12 4/1 2 2 8 0/1 1 2/2 1 1 1 3 0 I/E PIC16(L)F1707 2k 256 18 2/1 0 2 8 0/0 1 2/0 0 0 1 0 0 I/E PIC16(L)F1708 4k 512 18 4/1 2 2 12 0/1 1 2/2 1 1 1 3 0 I/E PIC16(L)F1709 8k 1024 18 4/1 2 2 12 0/1 1 2/2 1 1 1 3 0 I/E PIC16(L)F1713 4k 512 25 4/1 2 2 17 1/1 1 2/2 1 1 1 4 1 I/E PIC16(L)F1716 8k 1024 25 4/1 2 2 17 1/1 1 2/2 1 1 1 4 1 I/E Device PIC16(L)F1717 8k 1024 36 4/1 2 2 28 1/1 1 2/2 1 1 1 4 1 I/E PIC16(L)F1718 16k 2048 25 4/1 2 2 17 1/1 1 2/2 1 1 1 4 1 I/E PIC16(L)F1719 16k 2048 36 4/1 2 2 28 1/1 1 2/2 1 1 1 4 1 I/E Note 1: I – Debugging integrated on chip; H – Debugging via ICD header; E – Debugging via Emulation header. PACKAGES Device PDIP TSSOP QFN (4x4x0.9) SOIC PIC16F1703 x x x x PIC16F1704 x x x x PIC16F1705 x x x x PIC16F1707 x x x x PIC16F1708 x x x x PIC16F1709 x x x x x x x x x x x x x x PIC16F1713 PIC16F1716 PIC16F1717 SPDIP QFN UQFN (6x6x0.9) (4x4x0.5) x PIC16F1718 PIC16F1719 SSOP x x x x DS40001708A-page 2 Advance Information x TQFP UQFN (5x5x0.5) x x x x x 2013 Microchip Technology Inc. PIC16(L)F170X/171X VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 Note: 1 2 3 4 5 6 7 PIC16(L)F1703 PIC16(L)F1704 PIC16(L)F1705 PIN DIAGRAM – 14-PIN PDIP, SOIC, SSOP 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 See Table 1 and Table 2 for the pin allocation tables. NC VSS 16 15 14 13 VDD NC PIN DIAGRAM – 16-PIN QFN 1 12 RA0/ICSPDAT PIC16(L)F1703 2 11 RA1/ICSPCLK PIC16(L)F1704 3 PIC16(L)F1705 10 RA2 4 9 RC0 RC4 RC3 RC2 RC1 5 6 7 8 RA5 RA4 RA3/MCLR/VPP RC5 Note: See Table 1 and Table 2 or the pin allocation tables. 2013 Microchip Technology Inc. Advance Information DS40001708A-page 3 PIC16(L)F170X/171X PIN DIAGRAM – 20-PIN PDIP, SOIC, SSOP Note: 1 20 VSS 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK VPP/MCLR/RA3 4 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 7 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 PIC16(L)F1707 PIC16(L)F1708 PIC16(L)F1709 VDD RA5 See Table 3 and Table 4 for the pin allocation tables. 20 19 18 17 16 RA4 RA5 VDD VSS RA0/ICSPDAT PIN DIAGRAM – 20-PIN QFN 1 15 RA1/ICSPCLK 2 PIC16(L)F1707 14 RA2 3 PIC16(L)F1708 13 RC0 4 PIC16(L)F1709 12 RC1 5 11 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 VPP/MCLR/RA3 RC5 RC4 RC3 RC6 Note: See Table 3 and Table 4 for the pin allocation tables. DS40001708A-page 4 Advance Information 2013 Microchip Technology Inc. PIC16(L)F170X/171X PIN DIAGRAM – 28-PIN PDIP, SOIC, SSOP VPP/MCLR/RE3 1 28 RB7 RA0 27 RB6 3 26 RB5 RA2 4 25 RB4 RA3 5 24 RB3 23 RB2 22 RB1 RB0 RA4 Note: 6 RA5 VSS 7 RA7 9 8 PIC16L(F)1713/6/8 2 RA1 21 20 VDD 19 VSS 18 RC7 RA6 10 RC0 11 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 See Table 5 and Table 6 for the pin allocation table. 28 27 26 25 24 23 22 RA1 RA0 RE3/MCLR/VPP RB7 RB6 RB5 RB4 PIN DIAGRAM – 28-PIN (U)QFN 1 2 3 PIC16L(F)1713/6/8 4 5 6 7 Note: 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC1 RC2 RC3 RC4 RC5 RC6 RC0 8 9 10 11 12 13 14 RA2 RA3 RA4 RA5 VSS RA7 RA6 See Table 5 and Table 6 for the pin allocation table. 2013 Microchip Technology Inc. Advance Information DS40001708A-page 5 PIC16(L)F170X/171X PIN DIAGRAM – 40-PIN PDIP VPP/MCLR/RE3 Note: 1 40 RB7/ICSPDAT 2 39 RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 RE0 7 34 8 33 RB1 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 PIC16L(F)1717/9 RA0 RB6/ICSPCLK 15 26 RC7 RC1 16 25 RC6 RC2 RC3 17 RC5 18 24 23 RD0 19 22 RC4 RD3 RD1 20 21 RD2 See Table 7 and Table 8 for the pin allocation table. DS40001708A-page 6 Advance Information 2013 Microchip Technology Inc. PIC16(L)F170X/171X 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC PIN DIAGRAM – 44-PIN TQFP (10x10) PIC16L(F)1717/9 NC RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 Note: 33 32 31 30 29 28 27 26 25 24 23 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RC7 RD4 See Table 7 and Table 8 for the pin allocation table. 31 32 34 33 35 36 37 38 39 40 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 PIN DIAGRAM – 40-PIN UQFN (5x5) RC7 RD4 1 2 30 RD5 RD6 RD7 3 29 4 28 27 VSS VDD RB0 RB1 RB2 6 5 PIC16L(F)1717/9 26 7 25 8 24 23 9 20 19 18 17 16 15 14 13 12 22 21 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 10 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 Note: See Table 7 and Table 8 for the pin allocation table. 2013 Microchip Technology Inc. Advance Information DS40001708A-page 7 MSSP CLC Interrupt Pull-up Basic VREF- — — — — — — IOC Y ICSPDAT AN1 VREF+ — — — — — — IOC Y ICSPCLK RA2 11 10 AN2 — — ZCD T0CKI(1) — — — INT(1) IOC Y — RA3 4 3 — — — — — — — — IOC Y MCLR VPP RA4 3 2 AN3 — — — T1G(1) — — — IOC Y CLKOUT RA5 2 1 — — — — T1CKI(1) — — — IOC Y CLKIN RC0 10 9 AN4 — OPA1IN+ — — — SCK(1) SCL(3) — IOC Y — RC1 9 8 AN5 — OPA1IN- — — — SDI(1) SDA(3) — IOC Y — RC2 8 7 AN6 — OPA1OUT — — — — — IOC Y — RC3 7 6 AN7 — OPA2OUT — — CCP2(1) SS(1) — IOC Y — RC4 6 5 — — OPA2IN- — — — — — IOC Y — RC5 5 4 — — OPA2IN+ — — CCP1(1) — — IOC Y — VDD 1 16 — — — — — — — — — — VDD VSS 14 13 — — — — — — — — VSS OUT(2) Note 2013 Microchip Technology Inc. 1: 2: 3: CCP AN0 11 Timers 12 12 Zero Cross ADC 13 RA1 Op Amp QFN RA0 Reference PDIP/SOIC/SSOP Advance Information I/O(2) 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1703) — — (3) — — — — — — — CPP1 SDA — — — — — — — — — — — CPP2 SCL(3) SCK — — — — — — — — — — — — SDO — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F170X/171X DS40001708A-page 8 TABLE 1: Timers CCP CLC Interrupt Pull-up — DAC1OUT — — — — — — — IOC Y ICSPDAT C1IN0C2IN0- — — — — — — — — — IOC Y ICSPCLK RA2 11 10 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — COGIN(1) — — — INT(1) IOC Y — RA3 4 3 — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 2 AN3 — — — — — T1G(1) SOSCO — — — — — IOC Y CLKOUT OSC2 RA5 2 1 — — — — — — T1CKI(1) SOSCI — — — — CLCIN3(1) IOC Y CLKIN OSC1 RC0 10 9 AN4 — C2IN+ OPA1IN+ — — — — — SCK(1) SCL(3) — — IOC Y — RC1 9 8 AN5 — C1IN1C2IN1- OPA1IN- — — — — — SDI(1) SDA(3) — CLCIN2(1) IOC Y — RC2 8 7 AN6 — C1IN2C2IN2- OPA1OUT — — — — — — — — IOC Y — RC3 7 6 AN7 — C1IN3C2IN3- OPA2OUT — — — CCP2(1) — SS(1) — CLCIN0(1) IOC Y — RC4 6 5 — — — OPA2IN- — — — — — — CK(1) CLCIN1(1) IOC Y — — — RX (3) — IOC Y — — — — — VDD — — — — VSS — (1) RC5 5 4 — — — OPA2IN+ — — — VDD 1 16 — — — — — — — — — — VSS 14 13 — — — — — — — — — — (2) OUT DS40001708A-page 9 1: 2: 3: (3) — — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA CK CLC1OUT — — — — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — COGC SDO TX CLC3OUT — — — — — — — — — — — — — COGD SCK — — — — — — Note CCP1 Basic Zero Cross C1IN+ VREF+ EUSART DAC VREF- AN1 MSSP Op Amp AN0 11 COG Comparator 12 12 PWM ADC 13 RA1 Reference QFN RA0 Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F170X/171X Advance Information PDIP/SOIC/SSOP 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1704/5) I/O(2) 2013 Microchip Technology Inc. TABLE 2: ADC Op Amp Zero Cross Timers CCP MSSP Interrupt Pull-up 19 16 AN0 VREF- — — — — — IOC Y ICSPDAT RA1 18 15 AN1 VREF+ — — — — — IOC Y ICSPCLK RA2 17 14 AN2 — — ZCD T0CKI(1) — — INT(1) IOC Y — RA3 4 1 — — — — — — — IOC Y MCLR VPP RA4 3 20 AN3 — — — T1G(1) — — IOC Y CLKOUT RA5 2 19 — — — — T1CKI — — IOC Y CLKIN RB4 13 10 AN10 — OPA1IN- — — — SCK(1) SDA(3) IOC Y — RB5 12 9 AN11 — OPA1IN+ — — — — IOC Y — RB6 11 8 — — — — — — SDI(1) SCL(3) IOC Y — Basic QFN RA0 Reference PDIP/SOIC/ SSOP Advance Information I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F1707) 2013 Microchip Technology Inc. RB7 10 7 — — — — — — — IOC Y — RC0 16 13 AN4 — — — — — — IOC Y — RC1 15 12 AN5 — — — — — — IOC Y — RC2 14 11 AN6 — OPA1OUT — — — — IOC Y — RC3 7 4 AN7 — OPA2OUT — — CCP2(1) — IOC Y — RC4 6 3 — — OPA2IN- — — — — IOC Y — RC5 5 2 — — OPA2IN+ — — CCP1(1) — IOC Y — RC6 8 5 AN8 — — SS(1) IOC Y — RC7 9 6 AN9 — — — — — — IOC Y — VDD 1 18 — — — — — — — — — VDD VSS 20 17 — — — — — — — — — VSS — — — — — — — CPP1 SDA(3) — — — — — — — — — — CPP2 SCL(3) SCK — — — — — — — — — — — SDO — — — OUT(2) Note 1: 2: 3: — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F170X/171X DS40001708A-page 10 TABLE 3: Comparator Op Amp DAC Zero Cross Timers CCP PWM COG MSSP EUSART CLC Interrupt Pull-up 16 AN0 VREF- C1IN+ — DAC1OUT — — — — — — — — IOC Y ICSPDAT 18 15 AN1 VREF+ C1IN0C2IN0- — — — — — — — — — — IOC Y ICSPCLK RA2 17 14 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) IOC Y — RA3 4 1 — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 20 AN3 — — — — — T1G(1) SOSCO — — — — — — IOC Y CLKOUT OSC2 RA5 2 19 — — — — — — T1CKI SOSCI — — — — — CLCIN3(1) IOC Y CLKIN OSC1 RB4 13 10 AN10 — — OPA1IN- — — — — — — SCK(1) SDA(3) — — IOC Y — RB5 12 9 AN11 — — OPA1IN+ — — — — — — — RX(1) IOC Y — RB6 11 8 — — — — — — — — — — SDI(1) SCL(3) — — IOC Y — RB7 10 7 — — — — — — — — — — — CK(1) — IOC Y — RC0 16 13 AN4 — C2IN+ — — — — — — — — — — IOC Y — IOC Y — (3) (3) (1) CLCIN2 Basic ADC 19 RA1 Reference QFN RA0 RC1 15 12 AN5 — C1IN1C2IN1- — — — — — — — — — RC2 14 11 AN6 — C1IN2C2IN2- OPA1OUT — — — — — — — — — IOC Y — RC3 7 4 AN7 — C1IN3C2IN3- OPA2OUT — — — CCP2(1) — — — — CLCIN0(1) IOC Y — RC4 6 3 — — — OPA2IN- — — — — — — — — CLCIN1(1) IOC Y — — — — — — IOC Y — — DS40001708A-page 11 RC5 5 2 — — — OPA2IN+ — — — CCP1(1) RC6 8 5 AN8 — — — — — — — — — SS(1) — — IOC Y RC7 9 6 AN9 — — — — — — — — — — — — IOC Y — VDD 1 18 — — — — — — — — — — — — — — — VDD 20 17 — — — — — — — — — — — — — — — VSS VSS Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F170X/171X Advance Information PDIP/SOIC/ SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F1708/9) I/O(2) 2013 Microchip Technology Inc. TABLE 4: 1: 2: 3: PDIP/SOIC/ SSOP QFN ADC Reference Comparator Op Amp DAC Zero Cross Timers CCP PWM COG MSSP EUSART CLC Interrupt Pull-up Basic I/O(2) Note — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — — — — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT CLC2OUT — — — — — — — — — — — — — — COGC SDO TX CLC3OUT — — — — — — — — — — — — — — COGD — — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. Advance Information PIC16(L)F170X/171X DS40001708A-page 12 OUT(2) — 2013 Microchip Technology Inc. C1IN0+ C2IN0+ RA3 RA4 RA5 5 6 7 2 3 4 AN3 Vref+ C1IN1+ RA6 10 7 RA7 9 6 RB0 21 18 AN12 C2IN1+ RB1 22 19 AN10 C1IN3C2IN3- RB2 23 20 AN8 CLCIN1(1) IOC Y IOC Y IOC IOC IOC Y Y Y T0CKI(1) nSS(1) DAC2OUT1 NCOCLK 24 21 AN9 RB4 RB5 25 26 22 23 AN11 AN13 RB6 27 24 28 Y OSC2 CLKOUT OSC1 CLKIN IOC RB3 RB7 IOC DAC1OUT1 OPA1IN+ OPA1IN- AN4 CLCIN0(1) C1IN2C2IN2- IOC INT(1) IOC COGIN(1) ZCD OPA2OUT IOC OPA2IN- IOC OPA2IN+ IOC DAC1OUT2 DAC2OUT2 RC0 11 8 T1CKI SOSCO RC1 12 9 SOSCI DS40001708A-page 13 13 10 AN14 RC3 14 11 AN15 CCP2(1) CCP1 (1) SCK(1) Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. Note 4: Alternate outputs are excluded from solid shaded areas. Note 5: Alternate inputs are excluded from dot shaded areas. Y Y CLCIN2(1) IOC Y ICSPCLK (1) IOC Y IOC Y IOC Y CLCIN3 (1) RC2 IOC IOC T1G(1) SCL(1) 25 Basic Vref- Pull-up AN2 Interrupt 1 OPA1OUT CLC 4 EUSART RA2 MSSP C1IN1C2IN1- COG AN1 PWM 28 NCO 3 CCP RA1 Timers C1IN0C2IN0- Zero Cross AN0 DAC 27 Op Amp ADC 2 Reference QFN, UQFN RA0 IOC Y IOC Y ICSPDAT PIC16(L)F170X/171X Advance Information PDIP,SOIC, SSOP Comparator 28-PIN ALLOCATION TABLE (PIC16L(F)1713/6/8) (PART 1) I/O(2) 2013 Microchip Technology Inc. TABLE 5: Pull-up IOC IOC IOC Y Y Y Basic Interrupt CLC EUSART MSSP COG NCO CCP PWM TX/CK DT(3) CLC1OUT CLC2OUT CLC3OUT CLC4OUT RX(3) CK CLCIN0 CLCIN1 CLCIN2 CLCIN3 SCK/SCL Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. Note 4: Alternate outputs are excluded from solid shaded areas. Note 5: Alternate inputs are excluded from dot shaded areas. INT SDO SS SCK/SCL(3) SDA(3) SDI (3) COGD COGC COGA PWM4OUT PWM3OUT COGB COGIN IN(5) NCOOUT Advance Information OUT(4) NCOCLK Vss CCP2 17 5 16 CCP2 20 8 19 Y MCLR Vpp Vdd Vss CCP1 Vdd RX(3) CCP1 26 Timers 1 CK(3) T0CKI RE3 IOC SDA(1) T1G AN17 AN18 AN19 SDI(1) T1CKI 13 14 15 Zero Cross 16 17 18 DAC RC5 RC6 RC7 Op Amp AN16 Comparator ADC 12 C2OUT QFN, UQFN 15 C1OUT PDIP,SOIC, SSOP RC4 Reference I/O(2) 28-PIN ALLOCATION TABLE (PIC16L(F)1713/6/8) (PART 2) PIC16(L)F170X/171X DS40001708A-page 14 TABLE 6: 2013 Microchip Technology Inc. 3 20 18 AN1 C1IN1OPA1OUT C2IN1- CLCIN1(1) IOC Y RA2 4 21 19 AN2 IOC Y RA3 RA4 RA5 5 6 7 22 23 24 20 AN3 Vref+ C1IN1+ 21 22 AN4 IOC IOC IOC Y Y Y RA6 14 31 29 RA7 13 30 28 RB0 33 8 8 AN12 C2IN1+ RB1 34 9 9 AN10 C1IN3OPA2OUT C2IN3- RB2 35 10 10 AN8 DS40001708A-page 15 11 11 AN9 RB4 RB5 37 38 14 15 12 AN11 13 AN13 RB6 39 16 14 RB7 40 17 15 RC0 15 32 30 RC1 16 35 31 RC2 17 36 32 AN14 RC3 18 37 33 AN15 42 COG DAC DAC1OUT1 T0CKI(1) OPA1IN+ OPA1IN- DAC2OUT1 nSS(1) NCOCLK 36 23 C1IN0+ C2IN0+ OSC2 CLKOUT OSC1 CLKIN IOC RB3 RC4 Vref- C1IN2C2IN2- IOC INT(1) IOC COGIN(1) ZCD Basic Pullup RA1 CLC Y MSSP IOC PWM CLCIN0(1) NCO C1IN0C2IN0- CCP 17 AN0 Timers 19 Op Amp Interrupt EUSART Zero Cross Comparator UQFN 2 ADC TQFP RA0 IOC OPA2IN- IOC OPA2IN+ IOC IOC IOC Y Y CLCIN2(1) IOC Y ICSPCLK CLCIN3(1) IOC Y ICSPDAT IOC Y SOSCI CCP2(1) IOC Y CCP1(1) IOC Y SCK(1) IOC Y SDI(1) IOC Y T1G(1) SCL(1) DAC1OUT2 DAC2OUT2 T1CKI(1) SOSCO 38 AN16 SDA(1) Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. Note 4: Alternate outputs are excluded from solid shaded areas. PIC16(L)F170X/171X Advance Information PDIP Reference PIN ALLOCATION TABLE (PIC16L(F)1717/9) (PART 1) I/O(2) 2013 Microchip Technology Inc. TABLE 7: Pullup Y Y Y Basic Interrupt IOC IOC IOC AN5 AN6 AN7 MCLR Vpp Vdd TX/CK DT (3) CLC1OUT CLC2OUT CLC3OUT CLC4OUT RX (3) CK CLCIN0 CLCIN1 CLCIN2 CLCIN3 SCK/SCL Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. Note 4: Alternate outputs are excluded from solid shaded areas. Note 5: Alternate inputs are excluded from dot shaded areas. INT SDO SS SCK/SCL(3) SDA(3) (3) SDI COGD COGC COGB COGIN COGA PWM4OUT NCOOUT NCOCLK PWM3OUT CCP2 CCP2 2013 Microchip Technology Inc. CCP1 T0CKI T1CKI T1G IN(5) CCP1 Vss C2OUT OUT(4) CK (3) RX(3) C1OUT Vss CLC 7 26 6 27 EUSART 7 28 6 29 MSSP 11 32 12 31 Vdd COG 16 PWM 18 NCO 1 CCP RE3 Timers AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 Zero Cross 39 40 1 34 35 36 37 2 3 4 5 23 24 25 DAC ADC 43 44 1 38 39 40 41 2 3 4 5 25 26 27 Op Amp UQFN 24 25 26 19 20 21 22 27 28 29 30 8 9 10 Comparator TQFP RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 Reference PDIP Advance Information I/O(2) PIN ALLOCATION TABLE (PIC16L(F)1717/9) (PART 2 PIC16(L)F170X/171X DS40001708A-page 16 TABLE 8: Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620772942 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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