Si 5 3 3 0 1 / 4 - E VB Si53301/4 E VALUATION B OARD U SER ’ S G U ID E Description EVB Features The Si53301/4-EVB is used for evaluation of the Si533xx family of low-jitter clock buffers/level translators. As shipped from the factory, this evaluation board has the Si53301 device installed. The entire Si533xx family of buffers use the same input circuits and output drivers, and all have the same jitter specifications. Thus, this evaluation board can be used to evaluate any Si533xx device. The Si53301 provides pin-selectable clock output signal format, drive strength control, optional clock division, and per-bank output enable. The Si53304 provides pin-selectable clock output signal format, drive strength control, and individual output enable pins for each clock output. Features of this evaluation board include: Power supply connections for VDD, VDDOA and VDDOB, GND Jumpers for selection of output signal format, output enable, input clock select and output divider Jumpers to allow self biasing of CMOS single-ended inputs SMA connectors for easy access to test and evaluate the Si53301 Figure 1. Si53301/4 Evaluation Board Rev. 0.3 10/12 Copyright © 2012 by Silicon Labs Si53301/4-EVB Si53301/4-EVB 1. Supply Voltage Three supply voltages are required: VDD, VDDOA, and VDDOB. These supply voltages are applied at the two bottom corners of the evaluation board via J18 and J20, which are located on the bottom side of the evaluation board and function as standoffs as well as inputs for the supply voltages. Note that the J18 and J20 have silkscreen on the top side of the evaluation board that identifies the J18 and J20 inputs. VDD powers the input buffers, mux, and dividers. VDDOA and VDDOB provide power for the output drivers on CLK0,1,2 and CLK3,4,5, respectively. The three input power supply voltages should all have a common external ground. A separate ground wire should be run from the common power ground to the ground on both J18 and J20. VDD, VDDOA, and VDDOB can be 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±10%. VDDOA,B need to be set according to the output driver format as shown in Table 1. 2. Clock Inputs This evaluation board accepts differential clock inputs on SMA connectors labeled CLK0,CLK0B as well as CLK1,CLK1B. A single-ended CMOS input with the same voltage swing as the VDD voltage may also be applied to either CLK0 and/or CLK1. See “4.4. Jumpers P1 and P2” for more information. The clock input that is active is selected by JP1, which controls the CLK_SEL input pin 8. 3. Clock Outputs Six clock outputs are present at the SMA connectors labeled Q0, 1, 2, 3, 4, 5. As built and delivered, the evaluation board will support differential outputs that are LVDS, CML, or low-power LVPECL without any component changes. Standard LVPECL and HCSL outputs require output resistor and/or capacitor changes. See the table in Figure 3 for these changes. 4. Jumpers This evaluation board can be used to evaluate a Si53301 or Si53304; however, the Si53301 is installed on the evaluation board. Refer to Figures 1, 2, and 3 and Tables 1 and 2 as needed for the following discussion about the jumpers. Many of the inputs are shown on the evaluation board silkscreen and schematic with dual names, such as name1(name2), where name1 is the input pin name for the Si53301 and name2 is the input pin name for the Si53304. In two cases, the input pin of the Si53301 is a no-connect (NC) when the Si53304 is a functional input. 4.1. Jumpers JP2 and JP3 Jumpers JP2 and JP3 set the level to SFOUTA1 and SFOUTA0 on input pins 2 and 3, respectively. Jumpers JP4 and JP5 set the level to SFOUTB1 and SFOUTB0 on input pins 22 and 23, respectively. These inputs have three valid input levels: Ground, VDD, and Open. See Table 1. 4.2. Jumpers JP1 and JP6 For the Si53301 device, Jumpers JP1 and JP6 control the output dividers for bank A (Q0,1,2) and bank B (Q3,4,5), respectively. For the Si53304 device, Jumpers JP1 and JP6 control the enabling of output clocks Q1 and Q5, respectively. See Table 2 for the settings of these jumpers. 4.3. Jumpers P3, P4, P5, P6, and P7 For the Si53301, these jumpers control CLK_SEL, OEA, and OEB. OEA is the enable for output clocks Q0,1,2, and OEB is the enable for output clocks Q3,4,5. For the Si53304, these jumpers control CLK_SEL, OE1, OE2, OE3, and OE4. See Table 3 for more information. 4.4. Jumpers P1 and P2 Jumpers P1 and P2 should be left open unless a single-ended input is applied to the CLK0 or CLK1 input. When a jumper is placed across P1 (P2), the voltage from the VREF pin 17 is applied to the CLK0B (CLK1B) input pin so that a CMOS input with a voltage swing of VDD (pin7) volts can be applied to the CLK0 (CLK1) pin. In addition, some resistor and capacitor changes (described in the Figure 3 schematic near P1 and P2) must be made to the evaluation board. 2 Rev. 0.3 Si53301/4-EVB Table 1. JP2, JP3, JP4, and JP5 Output Signal Format SFOUTX11 SFOUTX01 VDDOX = 3.3 V VDDOX = 2.5 V VDDOX = 1.8 V Open2 Open2 LVPECL LVPECL N/A Ground Ground LVDS LVDS LVDS Ground VDD LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive VDD Ground LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive VDD VDD LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive Open2 Ground LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive Open2 VDD LVPECL Low power LVPECL Low power N/A Ground Open2 CML CML CML VDD Open2 HCSL HCSL HCSL Notes: 1. Ground means short center pin to ground pin. VDD means short center pin to VDD pin. Open means leave center pin open. 2. SFOUTX are three-level input pins. Table 2. Jumper Selections for JP1,6 Signal* Jumper Si53301 Si53304 Jumper Position Jumper Position Ground Open VDD Ground Open VDD DIVA(OE1) JP1 /2 /1 /4 Q1 Disabled Q1 Enabled Q1 Enabled DIVB(OE5) JP6 /2 /1 /4 Q5 Disabled Q5 Enabled Q5 Enabled *Note: The signal name in parentheses applies to the Si53304 device, which is not installed from the factory. Table 3. Jumper Selections for P3,4,5,6,7 Signal* Jumper Si53301 Si53304 Jumper Position Jumper Position Shorted Open Shorted Open CLK_SEL P3 CLK0 Selected CLK1 Selected CLK0 Selected CLK1 Selected NC(OE1) P4 NA NA Q1 Disabled Q1 Enabled OEA(OE2) P5 Q0,1,2 Disabled Q0,1,2 Enabled Q2 Disabled Q2 Enabled OEB(OE3) P6 Q3,4,5 Disabled Q3,4,5 Enabled Q3 Disabled Q3 Enabled NC(OE4) P7 NA NA Q4 Disabled Q4 Enabled *Note: The signal name in parentheses applies to the Si53304 device, which is not installed from the factory. Rev. 0.3 3 J18 2 1 VDD GND J20 2 1 CONN TRBLK 2 VDDOB VDDOA CONN TRBLK 2 J16 SMA J15 SMA C14 49.9 R27 R26 CLK0B 1K 1 49.9 R30 49.9 R28 CLK1B 1K R29 CLK1 1 JUMPER VREF P2 JUMPER VREF P1 C25 10uF J21 HEADER 1x1 C24 10uF J19 HEADER 1x1 C23 10uF J17 HEADER 1x1 330 Ohm FB3 330 Ohm FB2 330 Ohm FB1 VDD VDDOB VDDOA Short pin 1 to pin 2 of P2 Remove R28 For CMOS input on CLK1/J15 Replace C19 with a short 0.1uF C21 0.1uF C20 C19 0.1uF Short pin 1 to pin 2 of P1 Remove R25 For CMOS input on CLK0/J13 Replace C13 with a short 0.1uF C15 0.1uF 49.9 CLK0 2 2 VREF VREF 1 1 1 1 1 2 2 2 2 2 NC(OE4) OEB(OE3) OEA(OE2) NC(OE1) CLK_SEL VDD VDD VDD VDD 1K NI R35 1K NI R34 1K NI R33 1K NI R32 1K R31 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 1 2 3 1 2 3 VDD HEADER 1x3 SFOUTB1 JP5 HEADER 1x3 SFOUTB0 JP4 SFOUTB1 SFOUTB0 SFOUTA0 SFOUTA1 DIVB(OE5) VDD DIVA(OE0) VDD VDD HEADER 1x3 SFOUTA0 JP3 HEADER 1x3 SFOUTA1 JP2 HEADER 1x3 DIVB(OE5) JP6 HEADER 1x3 DIVA(OE0) 1 2 3 Figure 2. Schematic Main JUMPER NC(OE4) P7 JUMPER OEB(OE3) P6 JUMPER OEA(OE2) P5 JUMPER NC(OE1) P4 JUMPER CLK_SEL P3 VDD JP1 VDD 1K NI R37 1K NI R36 CLK_SEL SFOUTB0 SFOUTB1 SFOUTA0 SFOUTA1 DIVA(OE0) NC(OE1) OEA(OE2) OEB(OE3) NC(OE4) DIVB(OE5) CLK1B CLK1 CLK0B CLK0 8 22 23 3 2 1 9 12 13 16 24 15 14 11 10 CLK_SEL SFOUTB0 SFOUTB1 SFOUTA0 SFOUTA1 DIVA(OE0) NC(OE1) OEA(OE2) OEB(OE3) NC(OE4) DIVB(OE5) CLK1B CLK1 CLK0B CLK0 C17 1.0uF VDD 7 VDDOA Q5 Q5B Q4 Q4B Q3 Q3B Q2 Q2B Q1 Q1B Q0 Q0B 17 21 20 26 25 28 27 30 29 32 31 5 4 U1 C18 1.0uF VREF VDDOB C16 1.0uF Si53301(Si53304) VDD R25 EPAD 33 0.1uF C13 18 VDDOA J14 SMA 1 1 Rev. 0.3 1 19 VDDOB GND 4 6 J13 SMA VREF C22 0.1uF Q5 Q4 Q4B Q3 Q3B Q2 Q2B Q1 Q1B Q0 Q0B Si53301/4-EVB Rev. 0.3 Q5 Q4 Q3 Q2 Q1 Q0 R21 R17 R14 R9 R5 R2 0 0 0 0 0 0 R23 120 NI R19 120 NI R15 120 NI R11 120 NI R7 120 NI R3 120 NI 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C11 0.1uF C9 C8 C5 C3 C2 J11 SMA J9 SMA J7 SMA J5 SMA J3 SMA J1 SMA Q5 Q4 Q3 Q2 Q1 Q0 Q5B Q4B Q3B Q2B Q1B Q0B 0 0 0 0 0 0 R24 120 NI R20 120 NI R16 120 NI R12 120 NI R8 120 NI R4 120 NI 0.1uF 0.1uF 0.1uF 0.1uF C12 0.1uF C10 0.1uF C7 C6 C4 C1 J12 SMA J10 SMA J8 SMA J6 SMA J4 SMA J2 SMA /Q5 /Q4 /Q3 /Q2 /Q1 /Q0 Figure 3. Schematic Outputs R22 R18 R13 R10 R6 R1 CMOS 0 0 0 0 0 42.2 0 R1, R2, R6, R9, R13,R14, R18,R21, R5, R10, R17, R22 NP NP NP See note NP 86.6 NP R3, R4, R7, R8, R11,R12, R15,R16,R19, R20,R23,R24 Note : 90 for VDD = 2.5V; 120 for VDD = 3.3V 0 OHMS 0.1 uF 0.1 uF/0 ohms LVDS AC/DC CML 0.1 uF 0.1 uF 0 OHMS 0 OHMS STANDARD LVPECL LOW POWER LVPECL HCSL ADD-IN HCSL SAME BD Output Format C1, C2, C3, C4, C5, C6, C7, C8, C9, C10,C11,C12 Component Configurations For Various Output Formats All resistors on this page are located very close to the Si533xx device, caps are located very close to the SMA's Si53301/4-EVB 5 Si53301/4-EVB 5. Bill of Materials Table 4. Si53301/4-EVB Bill of Materials Qty Ref Value 19 C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C19, C20, C21, C22 3 6 Rating Voltage Tol Type PCB Footprint Mfr Part # Mfr 0.1 µF 10 V ±10% X7R C0402 C0402X7R100-104K Venkel C16, C17, C18 1.0 µF 6.3 V ±10% X5R C0402 C0402X5R6R3-105K Venkel 3 C23, C24, C25 10 µF 10 V ±20% X7R C1206 C1206X7R100-106M Venkel 3 FB1, FB2, FB3 330 SMT L0805 BLM21PG331SN1 MuRata 16 J1, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, J12, J13, J14, J15, J16 SMA SMA SMA-EDGE-3 142-0701-801 Johnson Components 3 J17, J19, J21 Header 1x1 Header CONN-1X1 TSW-101-14-T-S Samtec 2 J18, J20 CONN TRBLK 2 Term Blk CONN-TB1711026 1711026 Phoenix Contact 6 JP1, JP2, JP3, JP4, JP5, JP6 Header 1x3 Header CONN-1X3 TSW-103-07-T-S Samtec 9 JS1, JS2, JS3, JS4, JS5, JS6, JS7, JS8, JS9 Jumper Shunt Shunt N/A SNT-100-BK-T Samtec 2 MH1, MH2 Screw/ Standoff HDW MH-125NP NSS-4-4-01/2399 Various 7 P1, P2, P3, P4, P5, P6, P7 Jumper Header CONN1X2 TSW-102-07-L-S Samtec 12 R1, R2, R5, R6, R9, R10, R13, R14, R17, R18, R21, R22 0 1A ThickFilm R0402 CR0402-16W-000 Venkel 4 R25, R27, R28, R30 49.9 1/16 W ±1% ThickFilm R0402 CR0402-16W-49R9F Venkel 3 R26, R29, R31 1 k 1/16 W ±5% ThickFilm R0402 CR0402-16W-102J Venkel 1 U1 Si53301 Timing QFN32M5X5 P0.5 Si53301-A-GM SiLabs 1500 mA 24 A Rev. 0.3 Si53301/4-EVB Table 4. Si53301/4-EVB Bill of Materials (Continued) Qty Ref Value Rating Voltage Tol Type PCB Footprint Mfr Part # Mfr Not-Installed Components 12 R3, R4, R7, R8, R11, R12, R15, R16, R19, R20, R23, R24 120 1/16 W ±1% ThickFilm R0402 CR0402-16W-1200F Venkel 6 R32, R33, R34, R35, R36, R37 1 k 1/16 W ±5% ThickFilm R0402 CR0402-16W-102J Venkel Rev. 0.3 7 Si53301/4-EVB DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.3 8 Comprehensive rewrite of previous revision. Rev. 0.3 Si53301/4-EVB NOTES: Rev. 0.3 9 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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