S i 5 3 1 5 4 - E VB Si53154 E VALUATION B OARD U SER ’ S G UIDE Description EVB Features The Si53154 is a four port PCIe clock buffer compliant to the PCIe Gen1, Gen2 and Gen3 standards. The Si53154 is a 24-pin QFN device that operates on a 3.3 V power supply and can be controlled using SMBus signals along with hardware control input pins. The device is spread aware and accepts a frequency spread differential clock frequency range from 100 to 210 MHz. The connections are described in this document. This document is intended to be used in conjunction with the Si53154 device and data sheet for the following tests: GND PCIe Gen1, Gen2, Gen3 compliancy Power consumption test Jitter performance Testing out I2C code for signal tuning In-system validation where SMA connectors are present VDD = 3.3V power supply Power connectors Differential Clock Input DIFF3 Output Enable SDATA SRC3 connection for application SCLK Si53154 DIFF1 Output Enable SRC2 connection for application DIFF2 Output Enable DIFF0 Output Enable SRC0 connection for application Rev. 0.1 1/12 Copyright © 2012 by Silicon Labs SRC1 connection for application Si53154-EVB Si53154-EVB 1. Front Panel Differential Buffer Input for on Si53154-EVB only I2C connect -For I2C read and write. In sequence SData, Gnd, SCLK from left to right. 3.3V Power Supply Connector GND Connector OE_DIFF3 hardware input control for DIFF3 output VDD Connectors DIFF3 Differential output OE1 hardware input control for DIFF1 output No Connect OE2 hardware input control for DIFF2 output DIFF2 Differential output OE0 hardware input control for DIFF0 output DIFF1 Differential output Si53154 device mount DIFF0 Differential output Figure 1. Evaluation Module Front Panel Table 1. Input Jumper Settings 2 Jumper Label Type Description OE0 I OE0, 3.3 V Input for Enabling DIFF0 Clock Output. 1 = DIFF0 enabled, 0 = DIFF0 disabled. OE1 I OE1, 3.3 V Input for Enabling DIFF1 Clock Output. 1 = DIFF1 enabled, 0 = DIFF1 disabled. OE2 I OE2, 3.3 V Input for Enabling DIFF2 Clock Output. 1 = DIFF2 enabled, 0 = DIFF2 disabled. OE3 I OE3, 3.3 V Input for Enabling DIFF3 Clock Output. 1 = DIFF3 enabled, 0 = DIFF3 disabled. SDATA I/O SCLK I SMBus-Compatible SDATA. SMBus-Compatible SCLOCK. Rev. 0.1 Si53154-EVB 1.1. Generating DIFF Outputs from the Si53154 Upon power-on of the device if the differential input is applied and input pins are left floating, by default all DIFF outputs DIFF[0:3] are ON. The input pin headers have clear indication of jumper settings for setting logic low (0) and high (1) as shown in the figure below, the jumper placed on middle and left pin will set input OE0 to low; and jumper placed on middle and right pin will set input OE0 to high. The output enable pins can be changed on the fly to observe outputs stopped cleanly. Input functionality is explained in detail below. 1.1.1. OE [0:3] Inputs The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high) results in corresponding output that was stopped are to resume normal operation in a glitch-free manner. Each of the hardware OE [0:3] pins are mapped via I2C to control bit in Control register. The hardware pin and the Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or enable the DIFF output. Both of these form an “AND” function to disable or enable the DIFF output. The DIFF outputs and their corresponding I2C control bits and hardware pins are listed in Table 2. Table 2. Output Enable Control I2C Control Bit Output Hardware Control Input Byte1 [bit 2] DIFF0 OE0 Byte1 [bit 0] DIFF1 OE1 Byte2 [bit 7] DIFF2 OE2 Byte2 [bit 6] DIFF3 OE3 Rev. 0.1 3 Si53154-EVB 2. Schematics R1 XOUT_DIFFIN U1 5 OE2 For Si52144,R10 open For Si53154,R11 open 7 OE0 XOUT/DIFFIN OE0 18 OE3 0 OE2 22 R2 NI OE3 YC1 NI XTL P/N: ECS-250-20-5PXDU-F-TR Use SMD footprint VDD1 R10 OE1 0 R11 NI 2 OE1 3 SSON VDD XIN/DIFFIN# Y1 NI 23 YC2 NI Si53154 19 SCLK SCLK 20 SDATA DUTGND R3 NI R4 SDA XIN_DIFFIN# 0 1 6 12 17 21 VDD1 VDD6 VDD12 VDD17 VDD21 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF VDD1 VDD6 VDD12 VDD17 VDD21 DIFF0 DIFF0# DIFF1 DIFF1# DIFF2 DIFF2# 4 24 25 VSS4 VSS24 EPAD DIFF3 DIFF3# 8 9 10 11 14 13 16 15 DIFF0 DIFF0# DIFF1 DIFF1# DIFF2 DIFF2# DIFF3 DIFF3# DUTGND DUTGND Figure 2. QFN-24 Device Connection VCC_3.3V + C6 10uF C7 0.1uF L1 HEADER 1x1 VDD_3.3V1 VCC_3.3V 1 HEADER 1x1 JP1 JP2 JP3 JP4 JP5 JUMPER JUMPER JUMPER JUMPER JUMPER L2 L3 L4 L5 L6 TP1 TP2 TP3 TP4 TP5 + C8 10uF R5 0 C13 + 1uF C9 10uF R6 0 + C17 1uF C10 10uF R7 0 + C14 1uF C11 10uF R8 0 + C15 1uF C12 10uF C16 1uF R9 0 VDD1 VDD21 VDD6 VDD12 VDD17 Figure 3. Device Power Supply 4 Rev. 0.1 GND1 1 Si53154-EVB SCLK/SDATA OE2 VDD_3.3V OE2 VDD_3.3V XIN_DIFFIN#1 VDD HEADER 1x3 3 2 1 GND P2 XIN_DIFFIN# R16 3 2 1 DUTGND SMA R15 10K HEADER 1x3 10K SCLK DUTGND VDD_3.3V P1 XOUT_DIFFIN1 XOUT_DIFFIN DUTGND SMA R17 10K OE0 SDATA DUTGND VDD_3.3V OE0 VDD HEADER 1x3 3 2 1 R20 10K GND P3 DUTGND OE3 VDD_3.3V OE3 VDD HEADER 1x3 3 2 1 R23 10K GND P4 DUTGND VDD_3.3V OE1 VDD HEADER 1x3 3 2 1 P5 R24 10K GND DUTGND OE1 SSON VDD_3.3V SSON VDD HEADER 1x3 3 2 1 P6 GND DUTGND Figure 4. Clock and Control Signals DIFF0_1 DUTGND DIFF2_1 SMA SMA C27 2.0pF DIFF0 DIFF2 C28 2.0pF DIFF2# C30 2.0pF DUTGND DIFF0# C29 2.0pF L1 SHOULD BE SHORT AS POSSIBLE DUTGND DIFF0#_1 L1 SHOULD BE SHORT AS POSSIBLE SMA DIFF2#_1 SMA DUTGND DUTGND DUTGND DIFF1_1 DUTGND DUTGND SMA SMA C32 2.0pF DIFF1 C31 2.0pF DIFF3 DUTGND DIFF1# L1 SHOULD BE SHORT AS POSSIBLE C34 2.0pF DIFF3_1 DUTGND DIFF3# DIFF1#_1 C33 2.0pF L1 SHOULD BE SHORT AS POSSIBLE SMA DIFF3#_1 SMA DUTGND DUTGND DUTGND Figure 5. Differential Clock Signals Rev. 0.1 5 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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