S i 5 3 1 5 9 - E VB Si53159 E VALUATION B OARD U SER ’ S G UIDE Description EVB Features The Si53159 is a nine port PCIe clock buffer compliant to the PCIe Gen1, Gen2 and Gen3 standards. The Si53159 is a 48-pin QFN device that operates on a 3.3 V power supply and can be controlled using SMBus signals along with hardware control input pins. The device is spread aware and accepts frequency spread differential clock frequency range from 100 to 210 MHz. The connections are described in this document. This document is intended to be used in conjunction with the Si53159 device and data sheet for the following tests: Power connectors PCIe Gen1, Gen2, Gen3 compliancy Power consumption test Jitter performance Testing out I2C code for signal tuning In-system validation where SMA connectors are present Differential Clock Input DIFF8 connection for application DIFF7 connection for application VDD = 3.3 V power supply GND CKPWRGD/Power down enable SDATA DIFF6 connection for application SCLK GND DIFF0 Output Enable DIFF5 connection for application Si53159 DIFF1 Output Enable DIFF2 Output Enable DIFF3 Output Enable DIFF4/DIFF5 Output Enable DIFF6/DIFF8 Output Enable DIFF4 connection for application DIFF0 connection for application DIFF1 connection for application Rev. 0.1 1/12 DIFF2 connection for application Copyright © 2012 by Silicon Labs DIFF3 connection for application Si53159-EVB Si53159-EVB 1. Front Panel DIFF8 Differential output Differential Buffer Input for on Si53159-EVB only DIFF7 Differential output CKPWRGD/ Power down input control Power Connectors I2C connect -For I2C read and write. In sequence SData, Gnd, SCLK from left to right. DIFF6 Differential output OE0 and OE1 hardware input control for DIFF0 and DIFF1 respectively t t GND Connector DIFF5 Differential output 3.3V Power Supply Connector OE2, OE3, OE4/5 and OE6/8 hardware inputs control for DIFF2, DIFF3, DIFF4 though DIFF5 and DIFF6 through DIFF8 outputs respectively DIFF4 Differential output DIFF1 Differential output DIFF0 Differential output DIFF3 Differential output Si53159 device mount DIFF2 Differential output Figure 1. Evaluation Module Front Panel Table 1. Input Jumper Settings Jumper Label Type Description OE0 I OE0, 3.3 V Input for Enabling DIFF0 Clock Output. 1 = DIFF0 enabled, 0 = DIFF0 disabled. OE1 I OE1, 3.3 V Input for Enabling DIFF1 Clock Output. 1 = DIFF1 enabled, 0 = DIFF1 disabled. OE2 I OE2, 3.3 V Input for Enabling DIFF2 Clock Output. 1 = DIFF2 enabled, 0 = DIFF2 disabled. OE3 I OE3, 3.3 V Input for Enabling DIFF3 Clock Output. 1 = DIFF3 enabled, 0 = DIFF3 disabled. OE4/5 I OE4/5, 3.3 V Input for Enabling DIFF4 and DIFF5 Clock Outputs. 1 = DIFF4 & DIFF5 enabled, 0 = DIFF4 & DIFF5 disabled. OE6/8 I OE6/8, 3.3 V Input for Enabling DIFF6, DIFF7 and DIFF8 Clock Outputs. 1 = DIFF6, DIFF7 & DIFF8 enabled, 0 = DIFF6, DIFF7 & DIFF8 disabled. CLKPWGD/PD I 3.3 V LVTTL Input. After CLKPWGD (active high) assertion, this pin becomes a real-time input for asserting power down (active low). 2 SDATA I/O SCLK I SMBus-Compatible SDATA. SMBus-Compatible SCLOCK. Rev. 0.1 Si53159-EVB 1.1. Generating DIFF Outputs from the Si53159 Upon power-on of the device if the differential input is applied and input pins are left floating, by default all DIFF outputs DIFF[0:8] are ON. The input pin headers have clear indication of jumper settings for setting logic low (0) and high (1) as shown in the figure below, the jumper placed on the middle and left pin will set input OE0 to low; and jumper placed on the middle and right pin will set input OE0 to high. The output enable pins can be changed on the fly to observe outputs stopped cleanly. Input functionality is explained in detail below. 1.1.1. OE [0:8] Inputs The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high) results in corresponding output that was stopped are to resume normal operation in a glitch-free manner. Each of the hardware OE [0:8] pins are mapped via I2C to control bit in Control register. The hardware pin and the Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or enable the DIFF output. The DIFF outputs and their corresponding I2C control bits and hardware pins are listed in Table 2. Table 2. Output Enable Control I2C Control Bit Output Hardware Control Input Byte1 [bit 4] DIFF0 OE0 Byte1 [bit 2] DIFF1 OE1 Byte2 [bit 1] DIFF2 OE2 Byte2 [bit 0] DIFF3 OE3 Byte1 [bit 7] DIFF4 OE4/5 Byte1 [bit 6] DIFF5 OE4/5 Byte2 [bit 5] DIFF6 OE6/8 Byte2 [bit 4] DIFF7 OE6/8 Byte2 [bit 3] DIFF8 OE6/8 Rev. 0.1 3 Si53159-EVB 2. Schematics VDD1 VDD2 VDD12 VDD13 VDD23 VDD34 VDD40 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF C60 0.1uF C61 0.1uF 11 OE6/8 0 5 SSON 39 CKPWRGD_PD# 37 SCLK 38 40 VDD_REF 23 13 12 34 VDD_PLL1 VDD_SRC VDD_PLL2 OE4/5 OE6/8 SRC5# SRC5 SSON SRC6# SRC6 CKPWRGD_PDB SRC7# SRC7 SRC8# SRC8 SCLK SDATA 6 VSS_PLL3 SDATA SRC4# SRC4 VSS_PCI 10 OE4/5 R10 OE3 NC_43 NC_44 NC_47 NC_48 14 15 DIFF0_14 DIFF0#_15 17 18 DIFF1_17 DIFF1#_18 19 20 DIFF2_19 DIFF2#_20 21 22 DIFF3_21 DIFF3#_22 25 26 DIFF4#_25 DIFF4_26 27 28 DIFF5#_27 DIFF5_28 30 31 DIFF6#_30 DIFF6_31 32 33 DIFF7#_32 DIFF7_33 35 36 DIFF8#_35 DIFF8_36 43 44 47 48 NC_43 NC_44 NC_47 NC_48 46 VDD1 OE2 VSS_REF 0 SRC3 SRC3# 45 9 OE3 Si53159 OE1 VSS_PLL1 OE2 XIN_DIFFIN# SRC2 SRC2# 29 R4 8 SRC1 SRC1# OE0 VSS_SRC 4 OE1 R3 NI XIN/CLKIN VSS_PLL2 3 OE0 YC2 NI SRC0 SRC0# 24 Y1 NI DUTGND XOUT 16 42 VSS_PLL4 41 7 R2 NI YC1 NI XTL P/N: ECS-250-20-5PXDU-F-TR Use SMD footprint VDD_PLL4 1 VDD_PCI 0 VDD_PLL3 R1 XOUT_DIFFIN 2 DUTGND U1 DUTGND Figure 2. QFN-48 Device Connection VCC_3.3V + C6 10uF C7 0.1uF L1 HEADER 1x1 VDD_3.3V1 VCC_3.3V 1 HEADER 1x1 JP1 JP2 JP3 JP4 JP5 JP7 JP8 JUMPER JUMPER JUMPER JUMPER JUMPER JUMPER JUMPER L2 L3 L4 L5 L6 L8 L9 TP1 TP2 TP3 TP4 TP5 + C8 10uF R5 0 C13 + 1uF C9 10uF R6 0 + C17 1uF C10 10uF R7 0 + C14 1uF C11 10uF R8 0 + C15 1uF C12 10uF R9 0 + C16 1uF C35 10uF R34 0 + C36 1uF C37 10uF C38 1uF R35 0 VDD1 VDD2 VDD12 VDD13 VDD23 VDD34 VDD40 Figure 3. Device Power Supply 4 Rev. 0.1 GND1 1 Si53159-EVB SCLK/SDATA NC_47 SSON VDD_3.3V VDD_3.3V VDD_3.3V HEADER 1x3 HEADER 1x3 3 2 1 P2 R15 10K HEADER 1x3 3 2 1 R16 NI 3 2 1 R57 10K P7 DUTGND DUTGND SCLK VDD_3.3V P1 DUTGND R17 10K SDATA NC_48 NC_43 VDD_3.3V VDD_3.3V HEADER 1x3 HEADER 1x3 3 2 1 3 2 1 R20 10K P3 R60 10K P8 XIN_DIFFIN#1 DUTGND XIN_DIFFIN# DUTGND SMA DUTGND XOUT_DIFFIN1 CKPWRGD_PD# NC_44 XOUT_DIFFIN SMA VDD_3.3V VDD_3.3V HEADER 1x3 HEADER 1x3 3 2 1 P9 DUTGND VDD_3.3V VDD_3.3V HEADER 1x3 HEADER 1x3 3 2 1 3 2 1 R24 10K DUTGND 3 2 1 R36 10K P10 DUTGND OE4/5 OE2 OE1 OE6/8 OE3 VDD_3.3V VDD_3.3V VDD_3.3V HEADER 1x3 HEADER 1x3 HEADER 1x3 3 2 1 R46 10K P12 DUTGND OE0 P6 R63 10K DUTGND VDD_3.3V HEADER 1x3 P5 DUTGND 3 2 1 R23 10K P4 3 2 1 R33 10K DUTGND 3 2 1 R38 10K P11 R48 10K P13 DUTGND DUTGND Figure 4. Clock and Control Signals DIFF0 DUTGND DIFF0_14 C29 2.0pF L1 SHOULD BE SHORT AS POSSIBLE SMA SMA DIFF3_21 C54 2.0pF DIFF6_31 C28 2.0pF DUTGND DIFF0#_15 DIFF6 DIFF3 SMA C27 2.0pF DUTGND DUTGND DIFF3#_22 DIFF0#_1 C30 2.0pF L1 SHOULD BE SHORT AS POSSIBLE SMA DIFF6#_30 L1 SHOULD BE SHORT AS POSSIBLE DIFF3#_1 C55 2.0pF DIFF6#_1 SMA SMA DUTGND DUTGND DIFF1 DUTGND C32 2.0pF L1 SHOULD BE SHORT AS POSSIBLE C34 2.0pF SMA SMA C56 2.0pF DIFF7_33 C31 2.0pF DIFF4_26 DUTGND DIFF1#_18 DIFF7 DUTGND DIFF4 DUTGND SMA DIFF1_17 DUTGND DUTGND DUTGND DUTGND DIFF4#_25 DIFF1#_1 C33 2.0pF L1 SHOULD BE SHORT AS POSSIBLE SMA DIFF7#_32 C57 2.0pF L1 SHOULD BE SHORT AS POSSIBLE DIFF4#_1 DUTGND DUTGND DUTGND DUTGND DUTGND DIFF2 DUTGND SMA C50 2.0pF DIFF2_19 L1 SHOULD BE SHORT AS POSSIBLE C51 2.0pF C53 2.0pF L1 SHOULD BE SHORT AS POSSIBLE SMA DUTGND SMA DUTGND DUTGND DIFF5#_27 DIFF2#_1 DIFF8 C58 2.0pF DIFF8_36 C52 2.0pF DUTGND DIFF2#_20 DUTGND DIFF5 SMA DIFF5_28 DIFF7#_1 SMA SMA DUTGND DIFF8#_35 DIFF5#_1 C59 2.0pF L1 SHOULD BE SHORT AS POSSIBLE DIFF8#_1 SMA SMA DUTGND DUTGND DUTGND DUTGND Figure 5. Differential Clock Signals Rev. 0.1 5 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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