EFM32ZG210 Data Sheet

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EFM32ZG210 DATASHEET
F32/F16/F8/F4
• ARM Cortex-M0+ CPU platform
• High Performance 32-bit processor @ up to 24 MHz
• Wake-up Interrupt Controller
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.5 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 48 µA/MHz @ 3 V Sleep Mode
• 114 µA/MHz @ 3 V Run Mode, with code executed from flash
• 32/16/8/4 KB Flash
• 4/4/2/2 KB RAM
• 24 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 14 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 4 Channel DMA Controller
• 4 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128-bit keys in 54 cycles
• Timers/Counters
• 2× 16-bit Timer/Counter
• 2×3 Compare/Capture/PWM channels
• 1× 24-bit Real-Time Counter
• 1× 16-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Communication interfaces
• Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
2
• I C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 4 single ended channels/ differential channels
• On-chip temperature sensor
• Current Digital to Analog Converter
• Selectable current range between 0.05 and 64 uA
• 1× Analog Comparator
• Capacitive sensing with up to 2 inputs
• Supply Voltage Comparator
• Ultra efficient Power-on Reset and Brown-Out Detector
• 2-pin Serial Wire Debug interface
• Pre-Programmed UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• QFN32 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32ZG210 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB)
RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32ZG210F4-QFN32
4
2
24
1.98 - 3.8
-40 - 85
QFN32
EFM32ZG210F8-QFN32
8
2
24
1.98 - 3.8
-40 - 85
QFN32
EFM32ZG210F16-QFN32
16
4
24
1.98 - 3.8
-40 - 85
QFN32
EFM32ZG210F32-QFN32
32
4
24
1.98 - 3.8
-40 - 85
QFN32
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination
of the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time from
energy saving modes, and a wide selection of peripherals, the EFM32ZG microcontroller is well suited
for any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32ZG210 devices. For a complete feature set and indepth information on the modules, the reader is referred to the EFM32ZG Reference Manual.
A block diagram of the EFM32ZG210 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
ZG210F32/ 16/ 8/ 4
Clock Managem ent
Core and Mem ory
ARM Cortex ™ M0+ processor
Flash
Program
Mem ory
RAM
Mem ory
Debug
Interface
DMA
Controller
Energy Managem ent
High Freq
Crystal
Oscillator
High Freq
RC
Oscillator
Voltage
Regulator
Voltage
Com parator
Aux High Freq
RC
Oscillator
Low Freq
RC
Oscillator
Brown- out
Detector
Power- on
Reset
Low Freq
Crystal
Oscillator
Ultra Low Freq
RC
Oscillator
32- bit bus
Peripheral Ref lex Syst em
Serial Interfaces
USART
Low
Energy
Uart™
2
IC
I/ O Ports
Tim ers and Triggers
Analog Interfaces
Ex ternal
Interrupts
General
Purpose
I/ O
Tim er/
Counter
Real Tim e
Counter
ADC
Pin
Reset
Pin
Wakeup
Pulse
Counter
Watchdog
Tim er
Current
DAC
Analog
Com parator
Security
Hardware
AES
2.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 Dhrystone
MIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is included as well. The EFM32 implementation of the Cortex-M0+ is described in detail in ARM Cortex-M0+
Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface .
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32ZG microcontroller.
The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory is
divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
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2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32ZG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32ZG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board
the EFM32ZG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Inter-Integrated Circuit Interface (I2C)
2
2
The I C module provides an interface between the MCU and a serial I C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
2
The interface provided to software by the I C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
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2.1.12 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.13 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
TM
The unique LEUART , the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/PulseWidth Modulation (PWM) output.
2.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.16 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 - EM3.
2.1.17 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.18 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.19 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 4 external
pins and 6 internal signals.
2.1.20 Current Digital to Analog Converter (IDAC)
The current digital to analog converter can source or sink a configurable constant current, which can
be output on, or sinked from pin or ADC. The current is configurable with several ranges of various
step sizes.
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2.1.21 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one
128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must
be 32-bit operations, i.e. 8- or 16-bit operations are not supported.
2.1.22 General Purpose Input/Output (GPIO)
In the EFM32ZG210, there are 24 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 14 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32ZG210 is a subset of the feature set described in the EFM32ZG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Configuration
Pin Connections
Cortex-M0+
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO,
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
USART1
Full configuration with I2S and IrDA
US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
TIMER0
Full configuration
TIM0_CC[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
RTC
Full configuration
NA
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
ACMP0
Full configuration
ACMP0_CH[1:0], ACMP0_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[3:0]
IDAC0
Full configuration
IDAC0_OUT
AES
Full configuration
NA
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Module
Configuration
Pin Connections
GPIO
24 pins
Available pins are shown in
Table 4.3 (p. 54)
2.3 Memory Map
The EFM32ZG210 memory map is shown in Figure 2.2 (p. 7) , with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32ZG210 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 8) , by simulation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in Table 3.2 (p. 8), by simulation and/or technology characterisation unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 8) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
8) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Typ
Max
-40
Unit
150
1
TSTG
Storage temperature range
TS
Maximum soldering
temperature
VDDMAX
External main supply voltage
0
3.8 V
VIOPIN
Voltage on any I/O
pin
-0.3
VDD+0.3 V
Latest IPC/JEDEC J-STD-020
Standard
°C
260 °C
1
Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed calibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data retention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
Parameter
TAMB
Ambient temperature range
VDDOP
Operating supply voltage
fAPB
Internal APB clock frequency
24 MHz
fAHB
Internal AHB clock frequency
24 MHz
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Min
Typ
-40
1.98
8
Max
Unit
85 °C
3.8 V
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3.4 Current Consumption
Table 3.3. Current Consumption
Symbol
IEM0
IEM1
Parameter
EM0 current. No
prescaling. Running
prime number calculation code from
Flash. (Production
test condition = 14
MHz)
EM1 current (Production test condition = 14 MHz)
Condition
Min
Typ
Max
Unit
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
115
132 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
117
136 µA/
MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
114
128 µA/
MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
116
132 µA/
MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
117
131 µA/
MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
118
133 µA/
MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
118
133 µA/
MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
120
135 µA/
MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
124
139 µA/
MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
125
142 µA/
MHz
1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
155
177 µA/
MHz
1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
162
181 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
48
57 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
49
59 µA/
MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
48
52 µA/
MHz
21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
49
53 µA/
MHz
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Symbol
IEM2
IEM3
IEM4
Parameter
Condition
Min
Typ
Max
Unit
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
50
54 µA/
MHz
14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
51
56 µA/
MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
52
56 µA/
MHz
11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
53
58 µA/
MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
57
63 µA/
MHz
6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
59
66 µA/
MHz
1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V,
TAMB=25°C
89
99 µA/
MHz
1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V,
TAMB=85°C
92
103 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
0.9
1.25 µA
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
1.7
2.35 µA
EM3 current (ULFRCO enabled, LFRCO/LFXO disabled),
VDD= 3.0 V, TAMB=25°C
0.5
0.9 µA
EM3 current (ULFRCO enabled, LFRCO/LFXO disabled),
VDD= 3.0 V, TAMB=85°C
1.3
2.0 µA
VDD= 3.0 V, TAMB=25°C
0.02
0.035 µA
VDD= 3.0 V, TAMB=85°C
0.29
0.700 µA
EM2 current
EM3 current
EM4 current
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3.4.1 EM0 Current Consumption
Figure 3.1. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 24 MHz
2.84
2.80
Idd [m A]
2.78
2.82
2.80
2.78
Idd [m A]
2.82
2.84
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.76
2.76
2.74
2.74
2.72
2.72
2.70
2.70
2.68
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.68
–40
3.8
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
–15
5
25
Tem perature [°C]
45
65
85
Figure 3.2. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 21 MHz
2.40
2.40
Idd [m A]
2.45
Idd [m A]
2.45
2.35
2.35
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.30
2.0
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
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3.4
3.6
2.30
3.8
–40
11
–15
5
25
Tem perature [°C]
45
65
85
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1.68
1.68
1.66
1.66
1.64
1.64
1.62
1.62
Idd [m A]
Idd [m A]
Figure 3.3. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 14 MHz
1.60
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
1.58
1.56
1.54
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
1.60
1.58
1.56
1.54
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
1.34
1.34
1.32
1.32
1.30
1.30
Idd [m A]
Idd [m A]
Figure 3.4. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 11 MHz
1.28
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
1.26
1.24
1.22
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
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3.4
3.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
1.28
1.26
1.24
1.22
–40
3.8
12
–15
5
25
Tem perature [°C]
45
65
85
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0.84
0.84
0.83
0.83
0.82
0.82
0.81
0.81
Idd [m A]
Idd [m A]
Figure 3.5. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 6.6 MHz
0.80
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.79
0.78
0.77
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
0.80
0.79
0.78
0.77
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
3.4.2 EM1 Current Consumption
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 24 MHz
1.20
1.18
1.20
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
1.18
Idd [m A]
1.16
Idd [m A]
1.16
1.14
1.14
1.12
1.12
1.10
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
3.4
3.6
1.10
–40
3.8
13
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
–15
5
25
Tem perature [°C]
45
65
85
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1.04
1.04
1.03
1.03
1.02
1.02
1.01
1.01
Idd [m A]
Idd [m A]
Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 21 MHz
1.00
0.99
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.98
0.97
0.96
0.95
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
1.00
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
0.99
0.98
0.97
0.96
0.95
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
0.73
0.73
0.72
0.72
0.71
0.71
0.70
0.70
Idd [m A]
Idd [m A]
Figure 3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 14 MHz
0.69
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.68
0.67
0.66
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
3.4
3.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
0.69
0.68
0.67
0.66
–40
3.8
14
–15
5
25
Tem perature [°C]
45
65
85
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0.59
0.59
0.58
0.58
0.57
0.57
Idd [m A]
Idd [m A]
Figure 3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 11 MHz
0.56
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.55
0.54
0.53
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
0.56
0.55
0.54
0.53
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
0.395
0.395
0.390
0.390
0.385
0.385
0.380
0.380
Idd [m A]
Idd [m A]
Figure 3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 6.6 MHz
0.375
0.370
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.365
0.360
0.355
0.350
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
3.4
3.6
0.375
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
0.370
0.365
0.360
0.355
0.350
–40
3.8
15
–15
5
25
Tem perature [°C]
45
65
85
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3.4.3 EM2 Current Consumption
Figure 3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
2.0
2.0
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
1.8
1.6
1.4
Idd [uA]
Idd [uA]
1.6
1.8
1.2
1.4
1.2
1.0
1.0
0.8
0.8
0.6
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
0.6
–40
3.8
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
–15
5
25
Tem perature [°C]
45
65
85
5
25
Tem perature [°C]
45
65
85
3.4.4 EM3 Current Consumption
Figure 3.12. EM3 current consumption.
1.6
1.6
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
1.4
1.2
Idd [uA]
Idd [uA]
1.2
1.4
1.0
1.0
0.8
0.8
0.6
0.6
0.4
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
3.4
3.6
0.4
–40
3.8
16
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
–15
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3.4.5 EM4 Current Consumption
Figure 3.13. EM4 current consumption.
0.5
Idd [uA]
0.3
0.4
0.3
Idd [uA]
0.4
0.5
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
0.2
0.2
0.1
0.1
0.0
0.0
–0.1
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
–0.1
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
0
HFCORECLK
cycles
tEM20
Transition time from EM2 to EM0
2
µs
tEM30
Transition time from EM3 to EM0
2
µs
tEM40
Transition time from EM4 to EM0
163
µs
3.6 Power Management
The EFM32ZG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
17
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Table 3.5. Power Management
Symbol
Parameter
VBODextthr-
BOD threshold on
falling external supply voltage
VBODextthr+
BOD threshold on
rising external supply voltage
tRESET
Delay from reset
is released until
program execution
starts
CDECOUPLE
Voltage regulator
decoupling capacitor.
Condition
Min
Typ
Max
1.74
Unit
1.96 V
1.85
V
Applies to Power-on Reset,
Brown-out Reset and pin reset.
163
µs
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1
µF
3.7 Flash
Table 3.6. Flash
Symbol
Parameter
ECFLASH
Flash erase cycles
before failure
Condition
Min
TAMB<150°C
RETFLASH
Flash data retention
Typ
Max
Unit
20000
cycles
10000
h
TAMB<85°C
10
years
TAMB<70°C
20
years
µs
tW_PROG
Word (32-bit) programming time
20
tP_ERASE
Page erase time
20
20.4
20.8 ms
tD_ERASE
Device erase time
40
40.8
41.6 ms
IERASE
Erase current
7
1
mA
IWRITE
Write current
7
1
mA
VFLASH
Supply voltage during flash erase and
write
1.98
3.8 V
1
Measured at 25°C
3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol
Parameter
VIOIL
Input low voltage
VIOIH
Input high voltage
VIOOH
Output high voltage (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Condition
Min
Typ
Max
Unit
0.30VDD V
0.70VDD
V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.90VDD
V
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Symbol
VIOOL
Parameter
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Condition
Min
Typ
Max
Unit
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.85VDD
V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.90VDD
V
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD
V
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85VDD
V
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.60VDD
V
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.80VDD
V
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD
V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.10VDD
V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.10VDD
V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.05VDD
V
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD V
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD V
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.35VDD V
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.25VDD V
IIOLEAK
Input leakage current
High Impedance IO connected
to GROUND or Vdd
RPU
I/O pin pull-up resistor
40
kOhm
RPD
I/O pin pull-down resistor
40
kOhm
RIOESD
Internal ESD series
resistor
200
Ohm
tIOGLITCH
Pulse width of pulses to be removed
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
±0.1
10
19
±100 nA
50 ns
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
by the glitch suppression filter
tIOOF
VIOHYST
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capacitance CL=12.5-25pF.
20+0.1CL
250 ns
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
20+0.1CL
250 ns
Output fall time
I/O pin hysteresis
(VIOTHR+ - VIOTHR-)
VDD = 1.98 - 3.8 V
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
0.1VDD
20
V
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Figure 3.14. Typical Low-Level Output Current, 2V Supply Voltage
5
0.20
4
Low- Level Output Current [m A]
Low- Level Output Current [m A]
0.15
0.10
3
2
0.05
1
- 40°C
25°C
85°C
0.00
0.0
0.5
1.5
1.0
Low- Level Output Voltage [V]
- 40°C
25°C
85°C
0
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
1.5
1.0
Low- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = LOW
45
20
40
35
Low- Level Output Current [m A]
Low- Level Output Current [m A]
15
10
30
25
20
15
5
10
5
- 40°C
25°C
85°C
0
0.0
0.5
1.5
1.0
Low- Level Output Voltage [V]
0
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
- 40°C
25°C
85°C
0.5
1.5
1.0
Low- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = HIGH
21
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Figure 3.15. Typical High-Level Output Current, 2V Supply Voltage
0.00
0.0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–0.5
High- Level Output Current [m A]
High- Level Output Current [m A]
–0.05
–0.10
–1.0
–1.5
–0.15
–2.0
–0.20
0.0
1.5
0.5
1.0
High- Level Output Voltage [V]
–2.5
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
1.5
0.5
1.0
High- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–10
High- Level Output Current [m A]
High- Level Output Current [m A]
–5
–10
–20
–30
–15
–40
–20
0.0
1.5
0.5
1.0
High- Level Output Voltage [V]
–50
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
1.5
0.5
1.0
High- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = HIGH
22
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0.5
10
0.4
8
Low- Level Output Current [m A]
Low- Level Output Current [m A]
Figure 3.16. Typical Low-Level Output Current, 3V Supply Voltage
0.3
0.2
0.1
6
4
2
- 40°C
25°C
85°C
0.0
0.0
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
- 40°C
25°C
85°C
0
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = LOW
40
50
35
40
Low- Level Output Current [m A]
Low- Level Output Current [m A]
30
25
20
15
30
20
10
10
5
0
0.0
- 40°C
25°C
85°C
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
- 40°C
25°C
85°C
0
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = HIGH
23
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Figure 3.17. Typical High-Level Output Current, 3V Supply Voltage
0.0
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
High- Level Output Current [m A]
High- Level Output Current [m A]
–0.1
–0.2
–0.3
–2
–3
–4
–0.4
–5
–0.5
0.0
0.5
1.5
1.0
2.0
High- Level Output Voltage [V]
2.5
–6
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
2.5
3.0
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–10
High- Level Output Current [m A]
–10
High- Level Output Current [m A]
1.5
1.0
2.0
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOW
0
–20
–30
–40
–50
0.0
0.5
–20
–30
–40
0.5
1.5
1.0
2.0
High- Level Output Voltage [V]
2.5
–50
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
0.5
1.5
1.0
2.0
High- Level Output Voltage [V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = HIGH
24
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Figure 3.18. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
14
0.7
12
Low- Level Output Current [m A]
Low- Level Output Current [m A]
0.6
0.5
0.4
0.3
10
8
6
4
0.2
2
0.1
0.0
0.0
- 40°C
25°C
85°C
0.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
- 40°C
25°C
85°C
0
0.0
3.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
50
50
40
40
30
20
10
30
20
10
- 40°C
25°C
85°C
0
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = LOW
Low- Level Output Current [m A]
Low- Level Output Current [m A]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
0.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
- 40°C
25°C
85°C
0
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = STANDARD
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
0.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
3.5
GPIO_Px_CTRL DRIVEMODE = HIGH
25
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Figure 3.19. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
0
- 40°C
25°C
85°C
–1
- 40°C
25°C
85°C
–2
High- Level Output Current [m A]
High- Level Output Current [m A]
–0.2
–0.3
–0.4
–0.5
–3
–4
–5
–6
–0.6
–7
–0.7
–0.8
0.0
–8
0.5
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
3.0
–9
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = LOWEST
3.0
3.5
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–10
High- Level Output Current [m A]
–10
High- Level Output Current [m A]
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOW
0
–20
–30
–40
–50
0.0
0.5
–20
–30
–40
0.5
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
3.0
–50
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = STANDARD
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
0.5
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
3.0
3.5
GPIO_Px_CTRL DRIVEMODE = HIGH
26
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
fLFXO
Supported nominal
crystal frequency
ESRLFXO
Supported crystal
equivalent series resistance (ESR)
CLFXOL
Supported crystal
external load range
ILFXO
Current consumption for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190
nA
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
1100
ms
32.768
Unit
kHz
30
120 kOhm
5
25 pF
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
3.9.2 HFXO
Table 3.9. HFXO
Symbol
Parameter
fHFXO
Supported nominal
crystal Frequency
ESRHFXO
The transconductance of the HFXO
input transistor at
crystal startup
CHFXOL
Supported crystal
external load range
tHFXO
Min
Typ
Current consumption for HFXO after
startup
Startup time
Max
4
Supported crystal
Crystal frequency 24 MHz
equivalent series reCrystal frequency 4 MHz
sistance (ESR)
gmHFXO
IHFXO
Condition
HFXOBOOST in CMU_CTRL
equals 0b11
Unit
24 MHz
30
100 Ohm
400
1500 Ohm
20
mS
5
25 pF
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
µA
24 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165
µA
24 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
785
µs
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3.9.3 LFRCO
Table 3.10. LFRCO
Symbol
Parameter
fLFRCO
Oscillation frequency , VDD= 3.0 V,
TAMB=25°C
tLFRCO
Startup time not including software
calibration
150
µs
ILFRCO
Current consumption
190
nA
TUNESTEPL-
Frequency step
for LSB change in
TUNING value
1.5
%
FRCO
Condition
Min
Typ
31.29
Max
32.768
Unit
34.28 kHz
42
42
40
40
38
38
Frequency [MHz]
Frequency [MHz]
Figure 3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
- 40°C
25°C
85°C
36
34
34
32
32
30
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
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3.4
3.6
30
–40
3.8
28
2.0 V
3.0 V
3.8 V
36
–15
5
25
Tem perature [°C]
45
65
85
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3.9.4 HFRCO
Table 3.11. HFRCO
Symbol
Parameter
Oscillation frequency, VDD= 3.0 V,
TAMB=25°C
fHFRCO
tHFRCO_settling
Settling time after
start-up
Current consumption (Production test
condition = 14 MHz)
IHFRCO
TUNESTEPHFRCO
Condition
Min
Typ
Max
Unit
21 MHz frequency band
20.37
21.0
21.63 MHz
14 MHz frequency band
13.58
14.0
14.42 MHz
11 MHz frequency band
10.67
11.0
11.33 MHz
7 MHz frequency band
6.40
6.60
6.80 MHz
1 MHz frequency band
1.15
1.20
1.25 MHz
fHFRCO = 14 MHz
0.6
Cycles
fHFRCO = 21 MHz
93
175 µA
fHFRCO = 14 MHz
77
140 µA
fHFRCO = 11 MHz
72
125 µA
fHFRCO = 6.6 MHz
63
105 µA
fHFRCO = 1.2 MHz
22
40 µA
1
Frequency step
for LSB change in
TUNING value
0.3
%
1
The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
1.45
1.45
1.40
1.40
1.35
1.35
Frequency [MHz]
Frequency [MHz]
Figure 3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
1.30
- 40°C
25°C
85°C
1.25
1.20
1.30
1.25
1.20
1.15
1.15
1.10
1.10
1.05
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
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3.4
3.6
1.05
–40
3.8
29
2.0 V
3.0 V
3.8 V
–15
5
25
Tem perature [°C]
45
65
85
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6.70
6.70
6.65
6.65
6.60
6.60
Frequency [MHz]
Frequency [MHz]
Figure 3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
6.55
6.50
6.45
6.40
6.50
6.45
6.40
- 40°C
25°C
85°C
6.35
6.30
2.0
6.55
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0 V
3.0 V
3.8 V
6.35
6.30
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
11.2
11.2
11.1
11.1
11.0
11.0
Frequency [MHz]
Frequency [MHz]
Figure 3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
10.9
10.8
10.8
10.7
10.6
2.0
10.9
10.7
- 40°C
25°C
85°C
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
10.6
–40
3.8
2.0 V
3.0 V
3.8 V
–15
5
25
Tem perature [°C]
45
65
85
14.2
14.2
14.1
14.1
14.0
14.0
Frequency [MHz]
Frequency [MHz]
Figure 3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
13.9
13.8
13.7
13.6
13.8
13.7
13.6
- 40°C
25°C
85°C
13.5
13.4
2.0
13.9
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
3.4
3.6
2.0 V
3.0 V
3.8 V
13.5
13.4
–40
3.8
30
–15
5
25
Tem perature [°C]
45
65
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21.2
21.2
21.0
21.0
Frequency [MHz]
Frequency [MHz]
Figure 3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
20.8
20.6
20.4
20.8
20.6
20.4
- 40°C
25°C
85°C
20.2
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0 V
3.0 V
3.8 V
20.2
–40
3.8
–15
5
25
Tem perature [°C]
45
Typ
Max
65
85
3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol
fAUXHFRCO
Parameter
Oscillation frequency, VDD= 3.0 V,
TAMB=25°C
tAUXHFRCO_settlingSettling time after
start-up
Condition
Min
Unit
fAUXHFRCO = 21 MHz
20.37
21.0
21.63 MHz
fAUXHFRCO = 14 MHz
13.58
14.0
14.42 MHz
fAUXHFRCO = 11 MHz
10.67
11.0
11.33 MHz
fAUXHFRCO = 6.6 MHz
6.40
6.60
6.80 MHz
fAUXHFRCO = 1.2 MHz
1.15
1.20
1.25 MHz
fAUXHFRCO = 14 MHz
TUNESTEPAUX- Frequency step
for LSB change in
HFRCO
TUNING value
0.6
Cycles
0.3
%
3.9.6 ULFRCO
Table 3.13. ULFRCO
Symbol
Parameter
Condition
Min
Typ
Max
fULFRCO
Oscillation frequency
25°C, 3V
TCULFRCO
Temperature coefficient
0.05
%/°C
VCULFRCO
Supply voltage coefficient
-18.2
%/V
0.70
Unit
1.75 kHz
3.10 Analog Digital Converter (ADC)
Table 3.14. ADC
Symbol
Parameter
Condition
VADCIN
Input voltage range
Single ended
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Min
Typ
0
31
Max
Unit
VREF V
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Symbol
Parameter
Condition
Min
Differential
VADCREFIN
Input range of external reference voltage, single ended
and differential
Typ
Max
Unit
-VREF/2
VREF/2 V
1.25
VDD V
VADCREFIN_CH7 Input range of external negative reference voltage on
channel 7
See VADCREFIN
0
VDD - 1.1 V
VADCREFIN_CH6 Input range of external positive reference voltage on
channel 6
See VADCREFIN
0.625
VDD V
0
VDD V
VADCCMIN
Common mode input range
IADCIN
Input current
CMRRADC
Analog input common mode rejection
ratio
IADC
Average active current
IADCREF
Current consumption of internal voltage reference
CADCIN
Input capacitance
RADCIN
Input ON resistance
RADCFILT
Input RC filter resistance
CADCFILT
Input RC filter/decoupling capacitance
fADCCLK
ADC Clock Frequency
tADCCONV
Conversion time
2pF sampling capacitors
<100
nA
65
dB
1 MSamples/s, 12 bit, external
reference
351
500 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b00
67
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b01
63
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b10
64
µA
Internal voltage reference
65
127 µA
2
pF
1
MOhm
10
250
kOhm
fF
13 MHz
6 bit
7
ADCCLK
Cycles
8 bit
11
ADCCLK
Cycles
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Symbol
Parameter
Condition
Min
12 bit
tADCACQ
Acquisition time
tADCACQVDD3
Required acquisition time for VDD/3
reference
tADCSTART
SNRADC
Programmable
Typ
Max
Unit
13
ADCCLK
Cycles
1
256 ADCCLK
Cycles
2
µs
Startup time of reference generator
and ADC core in
NORMAL mode
5
µs
Startup time of reference generator
and ADC core in
KEEPADCWARM
mode
1
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
59
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
65
dB
1 MSamples/s, 12 bit, differential, internal 1.25V reference
60
dB
1 MSamples/s, 12 bit, differential, internal 2.5V reference
65
dB
1 MSamples/s, 12 bit, differential, 5V reference
54
dB
1 MSamples/s, 12 bit, differential, VDD reference
67
dB
1 MSamples/s, 12 bit, differential, 2xVDD reference
69
dB
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
62
dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
63
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
67
dB
200 kSamples/s, 12 bit, differential, internal 1.25V reference
63
dB
200 kSamples/s, 12 bit, differential, internal 2.5V reference
66
dB
200 kSamples/s, 12 bit, differential, 5V reference
66
dB
66
dB
Signal to Noise Ratio (SNR)
200 kSamples/s, 12 bit, differential, VDD reference
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Symbol
SINADADC
Parameter
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
Condition
Min
SFDRADC
Max
Unit
200 kSamples/s, 12 bit, differential, 2xVDD reference
70
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
58
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
64
dB
1 MSamples/s, 12 bit, differential, internal 1.25V reference
60
dB
1 MSamples/s, 12 bit, differential, internal 2.5V reference
64
dB
1 MSamples/s, 12 bit, differential, 5V reference
54
dB
1 MSamples/s, 12 bit, differential, VDD reference
66
dB
1 MSamples/s, 12 bit, differential, 2xVDD reference
68
dB
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
61
dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
65
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
66
dB
200 kSamples/s, 12 bit, differential, internal 1.25V reference
63
dB
200 kSamples/s, 12 bit, differential, internal 2.5V reference
66
dB
200 kSamples/s, 12 bit, differential, 5V reference
66
dB
66
dB
200 kSamples/s, 12 bit, differential, 2xVDD reference
69
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
64
dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
73
dBc
1 MSamples/s, 12 bit, differential, internal 1.25V reference
66
dBc
1 MSamples/s, 12 bit, differential, internal 2.5V reference
77
dBc
1 MSamples/s, 12 bit, differential, VDD reference
76
dBc
200 kSamples/s, 12 bit, differential, VDD reference
Spurious-Free Dynamic Range (SFDR)
Typ
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Symbol
Parameter
Condition
Min
Typ
75
dBc
1 MSamples/s, 12 bit, differential, 5V reference
69
dBc
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
75
dBc
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
75
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
76
dBc
200 kSamples/s, 12 bit, differential, internal 1.25V reference
79
dBc
200 kSamples/s, 12 bit, differential, internal 2.5V reference
79
dBc
200 kSamples/s, 12 bit, differential, 5V reference
78
dBc
79
dBc
79
dBc
0.3
4 mV
0.3
mV
68
200 kSamples/s, 12 bit, differential, 2xVDD reference
After calibration, single ended
-4
Offset voltage
After calibration, differential
TGRADADCTH
Unit
1 MSamples/s, 12 bit, differential, 2xVDD reference
200 kSamples/s, 12 bit, differential, VDD reference
VADCOFFSET
Max
Thermometer output gradient
DNLADC
Differential non-linearity (DNL)
VDD= 3.0 V, external 2.5V reference
INLADC
Integral non-linearity (INL), End point
method
VDD= 3.0 V, external 2.5V reference
MCADC
No missing codes
-1
11.999
1
-1.92
mV/°C
-6.3
ADC
Codes/
°C
±0.7
4 LSB
±1.2
±3 LSB
12
bits
1
On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.26 (p.
36) and Figure 3.27 (p. 36) , respectively.
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Figure 3.26. Integral Non-Linearity (INL)
Digital ouput code
INL= | [(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2 N - 1
4095
4094
Actual ADC
tranfer function
before offset and
gain correction
4093
4092
Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
VOFFSET
0
Analog Input
Figure 3.27. Differential Non-Linearity (DNL)
Digital
ouput
code
DNL= | [(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2 N - 2
Full Scale Range
4095
4094
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
4093
4092
Actual transfer
function with one
m issing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
5
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
4
3
2
1
Ideal 50%
Transition Point
Ideal Code Center
0
Analog Input
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3.10.1 Typical performance
Figure 3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.31. ADC Absolute Offset, Common Mode = Vdd /2
5
2.0
Vref= 1V25
Vref= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
4
1.5
2
Actual Offset [LSB]
Actual Offset [LSB]
3
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1
0
–1
1.0
0.5
0.0
–2
–0.5
–3
–4
2.0
2.2
2.4
2.6
2.8
3.0
Vdd (V)
3.2
3.4
3.6
–1.0
–40
3.8
Offset vs Supply Voltage, Temp = 25°C
–15
5
25
Tem p (C)
45
65
85
Offset vs Temperature, Vdd = 3V
Figure 3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
79.4
71
2XVDDVSS
70
1V25
79.2
Vdd
69
79.0
67
5VDIFF
2V5
66
SFDR [dB]
SNR [dB]
68
Vdd
2V5
78.8
78.6
2XVDDVSS
78.4
65
78.2
64
63
–40
–15
5
25
Tem perature [°C]
45
65
5VDIFF
1V25
85
78.0
–40
Signal to Noise Ratio (SNR)
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
–15
5
25
Tem perature [°C]
45
65
85
Spurious-Free Dynamic Range (SFDR)
40
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Figure 3.33. ADC Temperature sensor readout
2800
Vdd = 2.0
Vdd = 3.0
Vdd = 3.8
2700
2600
Sensor readout
2500
2400
2300
2200
2100
2000
1900
–40
–15
5
25
Tem perature [°C]
45
65
85
3.11 Current Digital Analog Converter (IDAC)
Table 3.15. IDAC Range 0 Source
Symbol
Parameter
Condition
Min
Active current with
STEPSEL=0x10
EM0, default settings
IIDAC
Typ
Duty-cycled
I0x10
Nominal IDAC output current with
STEPSEL=0x10
ISTEP
Step size
ID
Current drop at high
impedance load
VIDAC_OUT = VDD - 100mV
TCIDAC
Temperature coefficient
VDD = 3.0V, STEPSEL=0x10
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
Max
Unit
11.7
µA
10
nA
0.84
µA
0.049
µA
0.73
%
0.3
nA/°C
11.7
nA/V
Table 3.16. IDAC Range 0 Sink
Symbol
Parameter
Condition
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
I0x10
Nominal IDAC output current with
STEPSEL=0x10
ISTEP
Step size
ID
Current drop at high
impedance load
VIDAC_OUT = 200 mV
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
Min
41
Typ
Max
Unit
13.7
µA
0.84
µA
0.050
µA
0.16
%
0.2
nA/°C
12.5
nA/V
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Table 3.17. IDAC Range 1 Source
Symbol
Parameter
Condition
Min
Active current with
STEPSEL=0x10
EM0, default settings
IIDAC
Typ
Duty-cycled
I0x10
Nominal IDAC output current with
STEPSEL=0x10
ISTEP
Step size
ID
Current drop at high
impedance load
VIDAC_OUT = VDD - 100mV
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
Max
Unit
13.0
µA
10
nA
3.17
µA
0.097
µA
0.79
%
0.7
nA/°C
38.4
nA/V
Table 3.18. IDAC Range 1 Sink
Symbol
Parameter
Condition
Min
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
I0x10
Nominal IDAC output current with
STEPSEL=0x10
ISTEP
Step size
ID
Current drop at high
impedance load
VIDAC_OUT = 200 mV
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
Typ
Max
Unit
17.9
µA
3.18
µA
0.098
µA
0.20
%
0.7
nA/°C
40.9
nA/V
Table 3.19. IDAC Range 2 Source
Symbol
Parameter
Condition
Min
Active current with
STEPSEL=0x10
EM0, default settings
IIDAC
Typ
Duty-cycled
I0x10
Nominal IDAC output current with
STEPSEL=0x10
ISTEP
Step size
ID
Current drop at high
impedance load
VIDAC_OUT = VDD - 100mV
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
Max
Unit
16.2
µA
10
nA
8.40
µA
0.493
µA
1.26
%
2.8
nA/°C
96.6
nA/V
Table 3.20. IDAC Range 2 Sink
Symbol
Parameter
Condition
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
Min
42
Typ
Max
28.4
Unit
µA
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Symbol
Parameter
Condition
Min
I0x10
Nominal IDAC output current with
STEPSEL=0x10
ISTEP
Step size
ID
Current drop at high
impedance load
VIDAC_OUT = 200 mV
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
Typ
Max
Unit
8.44
µA
0.495
µA
0.55
%
2.8
nA/°C
94.4
nA/V
Table 3.21. IDAC Range 3 Source
Symbol
Parameter
Condition
Min
Active current with
STEPSEL=0x10
EM0, default settings
IIDAC
Typ
Duty-cycled
Max
Unit
18.3
µA
10
nA
I0x10
Nominal IDAC output current with
STEPSEL=0x10
34.03
µA
ISTEP
Step size
1.996
µA
ID
Current drop at high
impedance load
VIDAC_OUT = VDD - 100 mV
3.18
%
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
10.9
nA/°C
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
159.5
nA/V
Table 3.22. IDAC Range 3 Sink
Symbol
Parameter
Condition
Min
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
I0x10
Typ
Max
Unit
62.9
µA
Nominal IDAC output current with
STEPSEL=0x10
34.16
µA
ISTEP
Step size
2.003
µA
ID
Current drop at high
impedance load
VIDAC_OUT = 200 mV
1.65
%
TCIDAC
Temperature coefficient
VDD = 3.0 V, STEPSEL=0x10
10.9
nA/°C
VCIDAC
Voltage coefficient
T = 25 °C, STEPSEL=0x10
148.6
nA/V
Table 3.23. IDAC
Symbol
Parameter
tIDACSTART
Start-up time, from enabled to output settled
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
Min
43
Typ
Max
40
Unit
µs
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Figure 3.34. IDAC Source Current as a function of voltage on IDAC_OUT
101
101
100
100
99
Percentage of nom inal current [%]
Percentage of nom inal current [%]
99
98
97
96
95
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
94
93
92
98
97
96
95
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
94
93
92
91
91
90
–2.0
90
–2.0
–1.5
–1.0
V(IDAC_OUT) - Vdd [V]
–0.5
0.0
–1.5
101
101
100
100
99
99
98
97
96
95
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
94
93
96
95
0.0
93
91
–0.5
90
–2.0
0.0
Range 2
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
94
91
–1.0
V(IDAC_OUT) - Vdd [V]
–0.5
97
92
–1.5
0.0
98
92
90
–2.0
–0.5
Range 1
Percentage of nom inal current [%]
Percentage of nom inal current [%]
Range 0
–1.0
V(IDAC_OUT) - Vdd [V]
–1.5
–1.0
V(IDAC_OUT) - Vdd [V]
Range 3
44
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101
101
100
100
Percentage of nom inal current [%]
Percentage of nom inal current [%]
Figure 3.35. IDAC Sink Current as a function of voltage from IDAC_OUT
99
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
98
97
99
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
98
97
96
96
95
0.0
0.5
1.0
V(IDAC_OUT) [V]
1.5
95
0.0
2.0
0.5
1.0
V(IDAC_OUT) [V]
2.0
Range 1
101
101
100
100
Percentage of nom inal current [%]
Percentage of nom inal current [%]
Range 0
1.5
99
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
98
97
96
99
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
98
97
96
95
0.0
0.5
1.0
V(IDAC_OUT) [V]
1.5
95
0.0
2.0
0.5
1.0
V(IDAC_OUT) [V]
Range 2
1.5
2.0
Range 3
Figure 3.36. IDAC linearity
5
70
60
4
50
Idd [uA]
Idd [uA]
3
Range 0
Range 1
2
40
Range 2
Range 3
30
20
1
10
0
0
5
10
15
Step
20
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
25
0
30
45
0
5
10
15
Step
20
25
30
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3.12 Analog Comparator (ACMP)
Table 3.24. ACMP
Symbol
Parameter
VACMPIN
Input voltage range
0
VDD V
VACMPCM
ACMP Common
Mode voltage range
0
VDD V
IACMP
IACMPREF
Active current
Current consumption of internal voltage reference
Condition
Min
Typ
Max
Unit
BIASPROG=0b0000, FULLBIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
0.4 µA
BIASPROG=0b1111, FULLBIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
2.87
15 µA
BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
195
520 µA
Internal voltage reference off.
Using external voltage reference
0
µA
Internal voltage reference
5
µA
0
12 mV
VACMPOFFSET
Offset voltage
BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
VACMPHYST
ACMP hysteresis
Programmable
17
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
39
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
kOhm
CSRESSEL=0b10 in
ACMPn_INPUTSEL
104
kOhm
CSRESSEL=0b11 in
ACMPn_INPUTSEL
136
kOhm
RCSRES
tACMPSTART
Capacitive Sense
Internal Resistance
Startup time
-12
10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 46) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
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46
(3.1)
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Figure 3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
20
2.5
HYSTSEL= 0
HYSTSEL= 2
HYSTSEL= 4
HYSTSEL= 6
2.0
Response Tim e [us]
Current [uA]
15
1.5
1.0
10
5
0.5
0.0
4
8
ACMP_CTRL_BIASPROG
0
0
12
Current consumption, HYSTSEL = 4
0
2
4
6
8
10
ACMP_CTRL_BIASPROG
12
14
Response time , Vcm =
1.25V, CP+ to CP- = 100mV
100
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hysteresis [m V]
80
60
40
20
0
0
1
2
4
3
ACMP_CTRL_HYSTSEL
5
6
7
Hysteresis
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3.13 Voltage Comparator (VCMP)
Table 3.25. VCMP
Symbol
Parameter
VVCMPIN
Input voltage range
VDD
V
VVCMPCM
VCMP Common
Mode voltage range
VDD
V
IVCMP
Condition
Min
Typ
Max
Unit
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.1
0.8 µA
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
14.7
35 µA
NORMAL
10
µs
Single ended
10
mV
Differential
10
mV
17
mV
Active current
tVCMPREF
Startup time reference generator
VVCMPOFFSET
Offset voltage
VVCMPHYST
VCMP hysteresis
tVCMPSTART
Startup time
10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.14 I2C
Table 3.26. I2C Standard-mode (Sm)
Symbol
Parameter
Min
Typ
0
Max
Unit
fSCL
SCL clock frequency
tLOW
SCL clock low time
4.7
µs
tHIGH
SCL clock high time
4.0
µs
tSU,DAT
SDA set-up time
250
ns
tHD,DAT
SDA hold time
tSU,STA
Repeated START condition set-up time
4.7
µs
tHD,STA
(Repeated) START condition hold time
4.0
µs
tSU,STO
STOP condition set-up time
4.0
µs
tBUF
Bus free time between a STOP and START condition
4.7
µs
8
100
1
2,3
3450
kHz
ns
1
For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32ZG Reference Manual.
The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3
-9
When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10 [s] * fHFPERCLK [Hz]) - 5).
2
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Table 3.27. I2C Fast-mode (Fm)
Symbol
Parameter
Min
Typ
Max
fSCL
SCL clock frequency
tLOW
SCL clock low time
1.3
µs
tHIGH
SCL clock high time
0.6
µs
tSU,DAT
SDA set-up time
100
ns
tHD,DAT
SDA hold time
tSU,STA
Repeated START condition set-up time
0.6
µs
tHD,STA
(Repeated) START condition hold time
0.6
µs
tSU,STO
STOP condition set-up time
0.6
µs
tBUF
Bus free time between a STOP and START condition
1.3
µs
0
Unit
1
400
2,3
8
900
kHz
ns
1
For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32ZG Reference Manual.
The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3
-9
When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10 [s] * fHFPERCLK [Hz]) - 5).
2
Table 3.28. I2C Fast-mode Plus (Fm+)
Symbol
Parameter
Min
Typ
Max
Unit
fSCL
SCL clock frequency
tLOW
SCL clock low time
0.5
µs
tHIGH
SCL clock high time
0.26
µs
tSU,DAT
SDA set-up time
50
ns
tHD,DAT
SDA hold time
8
ns
tSU,STA
Repeated START condition set-up time
0.26
µs
tHD,STA
(Repeated) START condition hold time
0.26
µs
tSU,STO
STOP condition set-up time
0.26
µs
tBUF
Bus free time between a STOP and START condition
0.5
µs
1
0
1000
kHz
1
For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32ZG Reference Manual.
3.15 Digital Peripherals
Table 3.29. Digital Peripherals
Symbol
Parameter
Condition
IUSART
USART current
USART idle current, clock enabled
7.5
µA/
MHz
ILEUART
LEUART current
LEUART idle current, clock enabled
150
nA
II2C
I2C current
I2C idle current, clock enabled
6.25
µA/
MHz
ITIMER
TIMER current
TIMER_0 idle current, clock
enabled
8.75
µA/
MHz
IPCNT
PCNT current
PCNT idle current, clock enabled
100
nA
IRTC
RTC current
RTC idle current, clock enabled
100
nA
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
Min
49
Typ
Max
Unit
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Symbol
Parameter
Condition
Min
IAES
AES current
AES idle current, clock enabled
IGPIO
GPIO current
IPRS
IDMA
Typ
Max
Unit
2.5
µA/
MHz
GPIO idle current, clock enabled
5.31
µA/
MHz
PRS current
PRS idle current
2.81
µA/
MHz
DMA current
Clock enable
8.12
µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32ZG210.
4.1 Pinout
The EFM32ZG210 pinout is shown in Figure 4.1 (p. 51) and Table 4.1 (p. 51). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32ZG210 Pinout (top view, not to scale)
Table 4.1. Device Pinout
Pin Alternate Functionality / Description
Pin #
QFN32 Pin#
and Name
Pin Name
Analog
Timers
Communication
Other
0
VSS
1
PA0
TIM0_CC0 #0/1/4
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
2
PA1
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
Ground.
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Pin Alternate Functionality / Description
Pin #
QFN32 Pin#
and Name
Pin Name
Analog
Timers
Communication
3
PA2
4
IOVDD_0
5
PC0
ACMP0_CH0
TIM0_CC1 #4
PCNT0_S0IN #2
US1_TX #0
I2C0_SDA #4
PRS_CH2 #0
6
PC1
ACMP0_CH1
TIM0_CC2 #4
PCNT0_S1IN #2
US1_RX #0
I2C0_SCL #4
PRS_CH3 #0
7
PB7
LFXTAL_P
TIM1_CC0 #3
US1_CLK #0
8
PB8
LFXTAL_N
TIM1_CC1 #3
US1_CS #0
9
RESETn
10
PB11
11
AVDD_2
12
PB13
HFXTAL_P
LEU0_TX #1
13
PB14
HFXTAL_N
LEU0_RX #1
14
IOVDD_3
Digital IO power supply 3.
15
AVDD_0
Analog power supply 0.
16
PD4
ADC0_CH4
LEU0_TX #0
17
PD5
ADC0_CH5
LEU0_RX #0
18
PD6
ADC0_CH6
TIM1_CC0 #4
PCNT0_S0IN #3
US1_RX #2/3
I2C0_SDA #1
ACMP0_O #2
19
PD7
ADC0_CH7
TIM1_CC1 #4
PCNT0_S1IN #3
US1_TX #2/3
I2C0_SCL #1
CMU_CLK0 #2
20
VDD_DREG
Power supply for on-chip voltage regulator.
21
DECOUPLE
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
22
PC13
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
23
PC14
TIM1_CC1 #0
PCNT0_S1IN #0
US1_CS #3
PRS_CH0 #2
24
PC15
TIM1_CC2 #0
US1_CLK #3
PRS_CH1 #2
25
PF0
TIM0_CC0 #5
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK #0
BOOT_TX
26
PF1
TIM0_CC1 #5
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0
GPIO_EM4WU3
BOOT_RX
27
PF2
TIM0_CC2 #5
LEU0_TX #4
GPIO_EM4WU4
28
IOVDD_5
29
PE10
TIM1_CC0 #1
PRS_CH2 #2
30
PE11
TIM1_CC1 #1
PRS_CH3 #2
31
PE12
TIM1_CC2 #1
32
PE13
TIM0_CC2 #0/1
Other
CMU_CLK0 #0
Digital IO power supply 0.
Reset input, active low.
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up
ensure that reset is released.
IDAC0_OUT
TIM1_CC2 #3
Analog power supply 2.
Digital IO power supply 5.
2015-03-06 - EFM32ZG210FXX - d0065_Rev1.10
52
I2C0_SDA #6
CMU_CLK1 #2
I2C0_SCL #6
ACMP0_O #0
GPIO_EM4WU5
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4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 53) . The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 4.2. Alternate functionality overview
Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
ACMP0_CH0
PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1
PC1
Analog comparator ACMP0, channel 1.
ACMP0_O
PE13
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PF1
Bootloader RX.
BOOT_TX
PF0
Bootloader TX.
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1
PE12
Clock Management Unit, clock output number 1.
DBG_SWCLK
PF0
DBG_SWDIO
PF1
GPIO_EM4WU0
PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU3
PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4
PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5
PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1
PD7
PC1
PF1
PE13
I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0
PD6
PC0
PF0
PE12
I2C0 Serial Data input / output.
IDAC0_OUT
PB11
LEU0_RX
PD5
PB14
PF1
PA0
LEUART0 Receive input.
LEU0_TX
PD4
PB13
PF0
PF2
LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin.
Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN
PC13
PD6
Analog comparator ACMP0, digital output.
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has
a built-in pull down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has
a built-in pull up.
IDAC0 output.
PC0
PD6
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Alternate
LOCATION
Functionality
0
1
2
3
PD7
4
5
6
Description
PCNT0_S1IN
PC14
PC1
Pulse Counter PCNT0 input number 1.
PRS_CH0
PA0
PC14
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1
PC15
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PC0
PE10
Peripheral Reflex System PRS, channel 2.
PRS_CH3
PC1
PE11
Peripheral Reflex System PRS, channel 3.
TIM0_CC0
PA0
PA0
PA0
PF0
Timer 0 Capture Compare input / output channel 0.
TIM0_CC1
PA1
PA1
PC0
PF1
Timer 0 Capture Compare input / output channel 1.
TIM0_CC2
PA2
PA2
PC1
PF2
Timer 0 Capture Compare input / output channel 2.
TIM1_CC0
PC13
PE10
PB7
PD6
Timer 1 Capture Compare input / output channel 0.
TIM1_CC1
PC14
PE11
PB8
PD7
Timer 1 Capture Compare input / output channel 1.
TIM1_CC2
PC15
PE12
PB11
PC13
Timer 1 Capture Compare input / output channel 2.
US1_CLK
PB7
PF0
PC15
USART1 clock input / output.
US1_CS
PB8
PF1
PC14
USART1 chip select input / output.
US1_RX
PC1
PD6
PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
US1_TX
PC0
PD7
PD7
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32ZG210 is shown in Table 4.3 (p. 54) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin
9
Pin
8
Pin
7
Pin
6
Pin
5
Pin
4
Pin
3
Pin
2
Pin
1
Pin
0
Port A
-
-
-
-
-
-
-
-
-
-
-
-
-
PA2
PA1
PA0
Port B
-
PB14
PB13
-
PB11
-
-
PB8
PB7
-
-
-
-
-
-
-
Port C
PC15
PC14
PC13
-
-
-
-
-
-
-
-
-
-
-
PC1
PC0
Port D
-
-
-
-
-
-
-
-
PD7
PD6
PD5
PD4
-
-
-
-
Port E
-
-
PE13
PE12
PE11
PE10
-
-
-
-
-
-
-
-
-
-
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
PF2
PF1
PF0
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4.4 QFN32 Package
Figure 4.2. QFN32
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from
the terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm is
acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional
Table 4.4. QFN32 (Dimensions in mm)
Symbol
A
A1
Min
0.80
0.00
Nom
0.85
-
Max
0.90
0.05
A3
b
D
E
0.25
0.203
0.30
REF
6.00 6.00
BSC BSC
0.35
D2
E2
4.30
4.30
4.40
4.40
4.50
4.50
e
0.65
BSC
L
L1
0.35
0.00
0.40
0.45
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.05
0.08
0.10
The QFN32 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. QFN32 PCB Land Pattern
a
p8
b
p7
p1
p6
e
g
p9
c
p2
p5
p3
p4
f
d
Table 5.1. QFN32 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
Symbol
Pin number
Symbol
Pin number
a
0.80
P1
1
P6
24
b
0.35
P2
8
P7
25
c
0.65
P3
26
P8
32
d
6.00
P4
16
P9
33
e
6.00
P5
17
-
-
f
4.40
-
-
-
-
g
4.40
-
-
-
-
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Figure 5.2. QFN32 PCB Solder Mask
a
b
e
g
c
f
d
Table 5.2. QFN32 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
0.92
b
0.47
c
0.65
d
6.00
e
6.00
f
4.52
g
4.52
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Figure 5.3. QFN32 PCB Stencil Design
a
b
x
y
e
z
c
d
Table 5.3. QFN32 PCB Stencil Design Dimensions (Dimensions in mm)
1.
2.
3.
4.
5.
6.
Symbol
Dim. (mm)
a
0.70
b
0.25
c
0.65
d
6.00
e
6.00
x
1.30
y
1.30
z
0.50
The drawings are not to scale.
All dimensions are in millimeters.
All drawings are subject to change without notice.
The PCB Land Pattern drawing is in compliance with IPC-7351B.
Stencil thickness 0.125 mm.
For detailed pin-positioning, see Figure 4.2 (p. 55) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions. Place as many and as small as possible vias
underneath each of the solder patches under the ground pad.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 59) .
6.3 Errata
Please see the errata document for EFM32ZG210 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.10
March 6th, 2015
Updated ADC data, updated temperature sensor graph and added clarification on conditions for INLADC
and DNLADC parameters.
Updated Max ESRHFXO value for Crystal Frequency of 24 MHz.
Updated current consumption.
Updated LFXO and HFXO data.
Updated LFRCO and HFRCO data.
Updated ACMP data.
Updated VCMP data.
Updated Memory Map.
Added DMA current in Digital Peripherals section.
Added AUXHFRCO to block diagram and Electrical Characteristics.
Updated Package dimensions table.
Updated block diagram.
7.2 Revision 1.00
July 2nd, 2014
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Removed "Preliminary" markings.
Updated current consumption.
Updated transition between energy modes.
Updated power management data.
Updated GPIO data.
Updated LFXO, HFXO, HFRCO and ULFRCO data.
Updated LFRCO and HFRCO plots.
Updated ADC data.
Updated ACMP data.
7.3 Revision 0.61
November 21st, 2013
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Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
7.4 Revision 0.60
October 9th, 2013
Added I2C characterization data.
Added IDAC characterization data.
Updated current consumption table and figures in Electrical characteristics section.
Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
Removed Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.5 Revision 0.50
April 22nd, 2013
Updated HFCORE max frequency from 32 MHz to 24 MHz.
Updated pinout.
Other minor corrections.
7.6 Revision 0.40
September 11th, 2012
Updated CPU core from Cortex M0 to Cortex M0+.
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Corrected operating voltage from 1.8 V to 1.85 V.
Other minor corrections.
7.7 Revision 0.30
July 16th, 2011
Updated the Electrical Characteristics section.
7.8 Revision 0.20
June 8th, 2011
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Corrected all current values in Electrical Characteristics section.
Updated Cortex M0 related items in the memory map.
7.9 Revision 0.10
June 7th, 2011
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 6
2.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 8
3.1. Test Conditions .............................................................................................................................. 8
3.2. Absolute Maximum Ratings .............................................................................................................. 8
3.3. General Operating Conditions ........................................................................................................... 8
3.4. Current Consumption ....................................................................................................................... 9
3.5. Transition between Energy Modes .................................................................................................... 17
3.6. Power Management ....................................................................................................................... 17
3.7. Flash .......................................................................................................................................... 18
3.8. General Purpose Input Output ......................................................................................................... 18
3.9. Oscillators .................................................................................................................................... 27
3.10. Analog Digital Converter (ADC) ...................................................................................................... 31
3.11. Current Digital Analog Converter (IDAC) .......................................................................................... 41
3.12. Analog Comparator (ACMP) .......................................................................................................... 46
3.13. Voltage Comparator (VCMP) ......................................................................................................... 48
3.14. I2C ........................................................................................................................................... 48
3.15. Digital Peripherals ....................................................................................................................... 49
4. Pinout and Package ................................................................................................................................. 51
4.1. Pinout ......................................................................................................................................... 51
4.2. Alternate Functionality Pinout .......................................................................................................... 53
4.3. GPIO Pinout Overview ................................................................................................................... 54
4.4. QFN32 Package ........................................................................................................................... 55
5. PCB Layout and Soldering ........................................................................................................................ 56
5.1. Recommended PCB Layout ............................................................................................................ 56
5.2. Soldering Information ..................................................................................................................... 58
6. Chip Marking, Revision and Errata .............................................................................................................. 59
6.1. Chip Marking ................................................................................................................................ 59
6.2. Revision ...................................................................................................................................... 59
6.3. Errata ......................................................................................................................................... 59
7. Revision History ...................................................................................................................................... 60
7.1. Revision 1.10 ............................................................................................................................... 60
7.2. Revision 1.00 ............................................................................................................................... 60
7.3. Revision 0.61 ............................................................................................................................... 60
7.4. Revision 0.60 ............................................................................................................................... 61
7.5. Revision 0.50 ............................................................................................................................... 61
7.6. Revision 0.40 ............................................................................................................................... 61
7.7. Revision 0.30 ............................................................................................................................... 61
7.8. Revision 0.20 ............................................................................................................................... 61
7.9. Revision 0.10 ............................................................................................................................... 62
A. Disclaimer and Trademarks ....................................................................................................................... 63
A.1. Disclaimer ................................................................................................................................... 63
A.2. Trademark Information ................................................................................................................... 63
B. Contact Information ................................................................................................................................. 64
B.1. ................................................................................................................................................. 64
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32ZG210 Memory Map with largest RAM and Flash sizes ........................................................................ 7
3.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 24
MHz ........................................................................................................................................................ 11
3.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21
MHz ........................................................................................................................................................ 11
3.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14
MHz ........................................................................................................................................................ 12
3.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11
MHz ........................................................................................................................................................ 12
3.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 6.6
MHz ........................................................................................................................................................ 13
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 24 MHz .............................. 13
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 14
3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 14
3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 15
3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6 MHz ........................... 15
3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 16
3.12. EM3 current consumption. ................................................................................................................... 16
3.13. EM4 current consumption. ................................................................................................................... 17
3.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22
3.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24
3.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25
3.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26
3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 28
3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 29
3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.26. Integral Non-Linearity (INL) ................................................................................................................... 36
3.27. Differential Non-Linearity (DNL) .............................................................................................................. 36
3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 37
3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 38
3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 39
3.31. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 40
3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 40
3.33. ADC Temperature sensor readout ......................................................................................................... 41
3.34. IDAC Source Current as a function of voltage on IDAC_OUT ....................................................................... 44
3.35. IDAC Sink Current as a function of voltage from IDAC_OUT ........................................................................ 45
3.36. IDAC linearity .................................................................................................................................... 45
3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 47
4.1. EFM32ZG210 Pinout (top view, not to scale) .............................................................................................. 51
4.2. QFN32 ................................................................................................................................................ 55
5.1. QFN32 PCB Land Pattern ...................................................................................................................... 56
5.2. QFN32 PCB Solder Mask ....................................................................................................................... 57
5.3. QFN32 PCB Stencil Design .................................................................................................................... 58
6.1. Example Chip Marking (top view) ............................................................................................................. 59
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 6
3.1. Absolute Maximum Ratings ...................................................................................................................... 8
3.2. General Operating Conditions ................................................................................................................... 8
3.3. Current Consumption ............................................................................................................................... 9
3.4. Energy Modes Transitions ...................................................................................................................... 17
3.5. Power Management ............................................................................................................................... 18
3.6. Flash .................................................................................................................................................. 18
3.7. GPIO .................................................................................................................................................. 18
3.8. LFXO .................................................................................................................................................. 27
3.9. HFXO ................................................................................................................................................. 27
3.10. LFRCO .............................................................................................................................................. 28
3.11. HFRCO ............................................................................................................................................. 29
3.12. AUXHFRCO ....................................................................................................................................... 31
3.13. ULFRCO ............................................................................................................................................ 31
3.14. ADC .................................................................................................................................................. 31
3.15. IDAC Range 0 Source ......................................................................................................................... 41
3.16. IDAC Range 0 Sink ............................................................................................................................. 41
3.17. IDAC Range 1 Source ......................................................................................................................... 42
3.18. IDAC Range 1 Sink ............................................................................................................................. 42
3.19. IDAC Range 2 Source ......................................................................................................................... 42
3.20. IDAC Range 2 Sink ............................................................................................................................. 42
3.21. IDAC Range 3 Source ......................................................................................................................... 43
3.22. IDAC Range 3 Sink ............................................................................................................................. 43
3.23. IDAC ................................................................................................................................................. 43
3.24. ACMP ............................................................................................................................................... 46
3.25. VCMP ............................................................................................................................................... 48
3.26. I2C Standard-mode (Sm) ...................................................................................................................... 48
3.27. I2C Fast-mode (Fm) ............................................................................................................................ 49
3.28. I2C Fast-mode Plus (Fm+) .................................................................................................................... 49
3.29. Digital Peripherals ............................................................................................................................... 49
4.1. Device Pinout ....................................................................................................................................... 51
4.2. Alternate functionality overview ................................................................................................................ 53
4.3. GPIO Pinout ........................................................................................................................................ 54
4.4. QFN32 (Dimensions in mm) .................................................................................................................... 55
5.1. QFN32 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 56
5.2. QFN32 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 57
5.3. QFN32 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 58
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 46
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 48
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