EFM32GG230 Rev D Errata

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EFM32GG230 Errata, Chip Rev. E
F1024/F512
This document describes errata for the latest revision of EFM32GG230 devices.
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1 Errata
This document contains information on the errata of the latest revision of this device. For errata on older revisions, please refer to the errata history for the
device. The device data sheet explains how to identify chip revisions, either from package markings or electronically.
In addition to the errata noted below, the errata for the ARM Cortex-M3 r2p1 (www.arm.com) also applies to this device.
1.1 Chip revision E
Table 1.1. Erratas
ID
Title/Problem
Effect
Fix/Workaround
ADC_E116
Offset in ADC Temperature Sensor
Calibration DataData
For devices with PROD_REV values of 16 or 17, the
ADC0_TEMP_0_READ_1V25 register of the Device Information Page has an offset of 112. Using this value for calculating the absolute temperature gives an approximately 18 degrees too high value. Relative temperature measurements
(temperature changes) are not affected by this offset.
For devices with PROD_REV values of 16 or 17,
use ADC0_TEMP_0_READ_1V25 - 112 instead of
ADC0_TEMP_0_READ_1V25 when calculating the temperature.
For ADC warm-up, the user is required to set the
ADC_CTRL_TIMEBASE to the number of ADC clock cycles
in 1 µs. As this register is only 5 bits wide, it does not support
frequencies above 32 MHz.
If an ADC clock above 32 MHz is required, the acquistion time should be increased to also account for too short
warmup-time.
If BYTEORDER is used in combination with DATASTART
or XORSTART, the AES data and key are interpreted in the
wrong order.
Do not use BYTEORDER in combination with DATASTART
or XORSTART.
If BYTEORDER is used, it will take one cycle for the
AES_STATUS_RUNNING flag to be set. This means that
polling this status flag should be postponed at least one cycle
after starting encryption/decryption.
If polling the AES_STATUS_RUNNING is preferred, insert a
No Operation assembly instruction (NOP()) before starting to
poll the status flag.
Counting error occurs if overflow on 7 LSBs happens when
entering LPMODE with LPCOMP=7. This results in the
Avoid using LPMODE with LPCOMP=7.
The ADC temperature sensor calibration value stored in the Device Information (DI) Page has an offset.
ADC_E117
TIMEBASE not wide enough
For 48 MHz ADC clock, the
ADC_CTRL_TIMEBASE is not wide
enough.
AES_E101
BYTEORDER does not work
in combination with DATASTART/XORSTART
When the BYTEORDER bit in
AES_CTRL is set, an encryption or decryption should not be started through
DATASTART or XORSTART.
AES_E102
AES_STATUS_RUNNING set one
cycle late with BYTEORDER set
When the BYTEORDER
bit in AES_CTRL is set,
AES_STATUS_RUNNING is set one
cycle late.
BURTC_E101
BURTC LPMODE entry
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ID
BU_E105
Title/Problem
Effect
Fix/Workaround
Entering LPMODE with LPCOMP=7
causes counter error.
counter value being 256 less than it should be after the error.
The error accumulates.
LFXO missing cycles during IOVDD
ramping
When IOVDD is ramped, the dc-level of the XTAL signal
changes, resulting in missed LFXO cycles and possible
glitches on the LFXO clock.
Set PRESC in BURTC_CTRL to greater then 0 when ramping IOVDD in combination with Backup mode to avoid glitches on the LFXO clock.
LFXO will not work properly with LFXOBUFCUR in
CMU_CTRL set.
Do not set LFXOBUFCUR in CMU_CTRL.
For devices with PROD_REV = 16, LFXO may have startup
issues with low capacitance crystals when using the default
LFXO configuration.
Make this line of code part of your starup code, typically
in the start of main(): *((volatile uint32_t*) 0x400c80C0) =
(*((volatile uint32_t*) 0x400c80C0) & ~(1<<6)) | (1<<4);.
When the device is powered and the DAC is disabled, stress
on an internal circuit node can cause the output voltage of
the DAC to drift over time, and in some cases may violate the
VDACOFFSET specification. If the DAC is always enabled while
the device is powered, this condition cannot occur.
Both in the startup initialization code and prior to disabling
the DAC in application code, set the OPAnSHORT bit in
DACn_OPACTRL to a '1' for the corresponding DAC(s) used
by the application. This will prevent the output voltage drift
over time effect.
In EM2, when sleeping with WFE (Wait for Event), an interrupt from the DMA will not wake up the system.
Use WFI (Wait for Interrupt) or EM1 instead.
LFXO missing cycles during IOVDD
ramping when used in combination
with Backup mode.
CMU_E112
LFXO boost buffer current setting
LFXO boost buffer current must be
disabled
CMU_E113
LFXO startup at high temperature
LFXO does not start at high temperature with default configuration.
DAC_E109
DAC output drift over lifetime
The voltage output of the DAC might
drift over time.
DMA_E101
EM2 with WFE and DMA
WFE does not work for the DMA in
EM2.
PCNT_E102
PCNT Pulse Width Filtering does
not work
The PCNT Pulse Width Filter does not work as intended.
Do not use the pulse width filter, i.e. ensure FILT = 0 in
PCNTn_CTRL.
PRS_E101
Edge detect on GPIO/ACMP
When using edge detect in PRS on signals from ACMP,
GPIO, RTC, LETIMER, LESENSE, VCMP and BURTC
edges can be missed.
Do not use edge detect on ACMP, GPIO, RTC, LETIMER,
LESENSE, VCMP and BURTC.
When RSSCOIST is set and PRESC > 0 in TIMERn_CTRL,
the capture/compare output value is not reliable.
Do not use a prescaled clock, i.e. ensure PRESC = 0 in
TIMERn_CTRL when RSSCOIST is enabled.
Edge detect on peripherals with asynchronous edges might be missed.
TIMER_E103
Capture/compare output is unreliable with RSSCOIST enabled
The TIMER capture/compare output is
unreliable when RSSCOIST is enabled
and the clock is prescaled.
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ID
Title/Problem
USART_E112
USART AUTOTX continues to transmit even with full RX buffer
Effect
Fix/Workaround
When AUTOTX in USARTn_CTRL or AUTOTXEN in
USARTn_TRIGCTRL is set, the USART will continue to
transmit data even after the RX buffer is full. This may cause
USART AUTOTX continues to transmit the RX buffer to overflow if the data is not read out in time.
even with full RX buffer.
No known workaround.
1.2 Older Revisions
Erratas for older revisions can be found at the Silicon Laboratories homepage:
www.silabs.com/32bit-errata
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2 Revision History
2.1 Revision 1.20
April 8th, 2016
Updated the latest revision to revision E.
Removed BURTC_E102, BU_E106, CMU_E114, DI_E101, EMU_107, and LES_E103 from revision E.
2.2 Revision 1.10
February 20th, 2015
Added DAC_E109.
Added EMU_E107.
Added TIMER_E103.
Added PCNT_E102.
Updated link to errata for older revisions.
Corrected typos.
Updated Trademark Information.
2.3 Revision 0.80
August 21st, 2013
Added ADC_E117.
Added AES_E102.
Updated disclaimer, trademark and contact information.
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2.4 Revision 0.70
July 30th, 2013
Added AES_E101.
Added BURTC_E102.
Added CMU_E114.
Added DMA_E101.
Updated errata naming convention.
2.5 Revision 0.60
June 5th, 2012
Added ADC1.
Added DI1.
2.6 Revision 0.50
April 24th, 2012
Added BU6.
Added CMU4.
Added CMU5.
Added LES3.
Removed Erratas not valid for chip revision.
2.7 Revision 0.40
January 19th, 2012
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Updated CUR5.
2.8 Revision 0.30
January 13th, 2012
Added USART1.
2.9 Revision 0.20
January 6th, 2012
Added CMU3.
Added CUR3.
Added CUR5.
Added MSC1.
Updated PRS1.
Removed Erratas not valid for chip revision.
2.10 Revision 0.10
November 4th, 2011
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system
and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples
described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon
Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications.
Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or
chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro
logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®,
ISOmodem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM,
CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other
products or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Errata .......................................................................................................................................................................................................................................
1.1. Chip revision E .................................................................................................................................................................................................................
1.2. Older Revisions ................................................................................................................................................................................................................
2. Revision History ..........................................................................................................................................................................................................................
2.1. Revision 1.20 ...................................................................................................................................................................................................................
2.2. Revision 1.10 ...................................................................................................................................................................................................................
2.3. Revision 0.80 ...................................................................................................................................................................................................................
2.4. Revision 0.70 ...................................................................................................................................................................................................................
2.5. Revision 0.60 ...................................................................................................................................................................................................................
2.6. Revision 0.50 ...................................................................................................................................................................................................................
2.7. Revision 0.40 ...................................................................................................................................................................................................................
2.8. Revision 0.30 ...................................................................................................................................................................................................................
2.9. Revision 0.20 ...................................................................................................................................................................................................................
2.10. Revision 0.10 .................................................................................................................................................................................................................
A. Disclaimer and Trademarks ..........................................................................................................................................................................................................
A.1. Disclaimer .......................................................................................................................................................................................................................
A.2. Trademark Information .......................................................................................................................................................................................................
B. Contact Information .....................................................................................................................................................................................................................
B.1. .....................................................................................................................................................................................................................................
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List of Tables
1.1. Erratas .................................................................................................................................................................................................................................... 2
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