EFM32GG332 Errata History

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EFM32GG332 Errata History
F1024/F512
This document describes known errata for all revisions of EFM32GG332 devices.
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1 Errata History
1.1 Errata Overview
Table 1.1 (p. 2) shows which erratum is applicable for each revision. The device datasheet explains how to identify chip revision, either from package
marking or electronically.
In addition to the errata noted below, the errata for the ARM Cortex-M3 r2p1 (www.arm.com) also applies to all revisions of this device.
Table 1.1. Errata Overview
Erratum ID
Rev. Rev.
E
D
Rev. Rev.
C
B
ADC_E116
X
X
ADC_E117
X
X
X
X
AES_E101
X
X
X
X
AES_E102
X
X
X
X
BU_E101
X
BU_E102
X
BU_E104
X
BU_E105
X
BU_E106
BURTC_E101
X
X
X
X
X
X
X
X
X
X
X
BURTC_E102
CMU_E108
X
CMU_E110
X
CMU_E111
CMU_E112
X
X
CMU_E113
X
X
CMU_E114
X
X
X
X
X
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Erratum ID
Rev. Rev.
E
D
Rev. Rev.
C
B
CUR_E103
X
CUR_E104
X
X
X
X
X
X
X
X
X
X
X
DAC_E109
X
DI_E101
DMA_E101
X
EMU_E105
X
EMU_E107
X
X
X
ETM_E101
X
GPIO_E101
X
LES_E101
X
LES_E102
X
LES_E103
X
MSC_E101
X
OPA_E101
X
X
PCNT_E102
X
X
X
X
PRS_E101
X
X
X
X
TIMER_E103
X
X
X
X
USART_E112
X
X
X
X
USB_E101
X
USB_E102
X
USB_E103
X
X
X
X
USB_E104
X
X
X
X
USB_E105
X
X
X
X
USB_E106
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X
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Erratum ID
Rev. Rev.
E
D
Rev. Rev.
C
B
USB_E107
X
X
USB_E108
X
X
USB_E109
X
X
X
X
USB_E110
X
X
X
X
1.2 EFM32GG332 Errata Descriptions
Table 1.2. EFM32GG332 Errata Descriptions
ID
Title/Problem
Effect
Fix/Workaround
ADC_E116
Offset in ADC Temperature Sensor
Calibration DataData
For devices with PROD_REV values of 16 or 17, the
ADC0_TEMP_0_READ_1V25 register of the Device Information Page has an offset of 112. Using this value for calculating the absolute temperature gives an approximately 18 degrees too high value. Relative temperature measurements
(temperature changes) are not affected by this offset.
For devices with PROD_REV values of 16 or 17,
use ADC0_TEMP_0_READ_1V25 - 112 instead of
ADC0_TEMP_0_READ_1V25 when calculating the temperature.
For ADC warm-up, the user is required to set the
ADC_CTRL_TIMEBASE to the number of ADC clock cycles
in 1 µs. As this register is only 5 bits wide, it does not support
frequencies above 32 MHz.
If an ADC clock above 32 MHz is required, the acquistion time should be increased to also account for too short
warmup-time.
If BYTEORDER is used in combination with DATASTART
or XORSTART, the AES data and key are interpreted in the
wrong order.
Do not use BYTEORDER in combination with DATASTART
or XORSTART.
If BYTEORDER is used, it will take one cycle for the
AES_STATUS_RUNNING flag to be set. This means that
polling this status flag should be postponed at least one cycle
after starting encryption/decryption.
If polling the AES_STATUS_RUNNING is preferred, insert a
No Operation assembly instruction (NOP()) before starting to
poll the status flag.
The ADC temperature sensor calibration value stored in the Device Information (DI) Page has an offset.
ADC_E117
TIMEBASE not wide enough
For 48 MHz ADC clock, the
ADC_CTRL_TIMEBASE is not wide
enough.
AES_E101
BYTEORDER does not work
in combination with DATASTART/XORSTART
When the BYTEORDER bit in
AES_CTRL is set, an encryption or decryption should not be started through
DATASTART or XORSTART.
AES_E102
AES_STATUS_RUNNING set one
cycle late with BYTEORDER set
When the BYTEORDER
bit in AES_CTRL is set,
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ID
Title/Problem
Effect
Fix/Workaround
Additional current consumption on BU_VIN approximately 100uA when VDD_DREG is between 0.3 BU_VIN to 0.7
BU_VIN.
Avoid having VDD_DREG in between 0.3 BU_VIN to 0.7
BU_VIN.
With GPIO retention enabled, GPIO pins will still drive in
backup mode.
Do not use EM4 GPIO retention in combination with backup
mode.
EM4 with backup BODs does not trigger reset.
Avoid using backup BODs when entering EM4.
When IOVDD is ramped, the dc-level of the XTAL signal
changes, resulting in missed LFXO cycles and possible
glitches on the LFXO clock.
Set PRESC in BURTC_CTRL to greater then 0 when ramping IOVDD in combination with Backup mode to avoid glitches on the LFXO clock.
AES_STATUS_RUNNING is set one
cycle late.
BU_E101
Backup power increased power
consumtion
Additional current consumption on
BU_VIN approximately 100uA when
VDD_DREG is between 0.3 BU_VIN
to 0.7 BU_VIN.
BU_E102
EM4 GPIO retention in backup
mode
EM4 GPIO retention not shut off in
backup mode.
BU_E104
EM4 with backup BODs
EM4 with backup BODs does not trigger reset.
BU_E105
LFXO missing cycles during IOVDD
ramping
LFXO missing cycles during IOVDD
ramping when used in combination
with Backup mode.
BU_E106
Current leakage in Backup mode
In Backup mode, when VDD > BU_VIN + 0.7, current will
leak from VDD.
To avoid leakage, exit Backup mode before VDD exceeds
the voltage where the leakage start by configuring the threshold in EMU_BUACT.
BURTC_E101
BURTC LPMODE entry
Counting error occurs if overflow on 7 LSBs happens when
entering LPMODE with LPCOMP=7. This results in the
counter value being 256 less than it should be after the error.
The error accumulates.
Avoid using LPMODE with LPCOMP=7.
When LPMODE is active (i.e.
BURTC_STATUS_LPMODEACT is high), software reads
might result in wrong value being read from BURTC_CNT.
Before reading BURTC_CNT, disable LPMODE and wait for
BURTC_STATUS_LPMODEACT to be cleared before reading BURTC_CNT.
For devices with PROD_REV < 15, enabling the clock for
LFA/LFB after reset and then immediately writing LFACLKEN/LFBCLKEN, may cause the write to miss its effect.
For devices with PROD_REV < 15, make sure
CMU_SYNCBUSY is not set before writing LFACLKEN/LFB-
Entering LPMODE with LPCOMP=7
causes counter error.
BURTC_E102
BURTC_CNT read error
Software reads from BURTC_CNT
might fail when LPMODE is activated
CMU_E108
LFxCLKEN write
First write to LFxCLKEN can be
missed.
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ID
Title/Problem
Effect
Fix/Workaround
CLKEN. Can temporarily switch to HFCORECLKLEDIV2 to
speed up clearing synchbusy.
CMU_E110
LFXO phase shift
Transients on pin D8 can give a temporary phase shift on
LFXO. Frequency is unchanged.
No known workaround.
For devices with PROD_REV < 15, LFXOBUFCUR in
CMU_CTRL is default 0 and LFXOBOOST in CMU_CTRL is
default 1. However, these values are incorrect.
On devices with PROD_REV < 15, change LFXOBUFCUR to
1 and LFXOBOOST to 0.
LFXO will not work properly with LFXOBUFCUR in
CMU_CTRL set.
Do not set LFXOBUFCUR in CMU_CTRL.
For devices with PROD_REV = 16, LFXO may have startup
issues with low capacitance crystals when using the default
LFXO configuration.
Make this line of code part of your starup code, typically
in the start of main(): *((volatile uint32_t*) 0x400c80C0) =
(*((volatile uint32_t*) 0x400c80C0) & ~(1<<6)) | (1<<4);.
Transients on pin D8 cause LFXO
phase shift.
CMU_E111
LFXO configuration incorrect
LFXO configuration incorrect.
CMU_E112
LFXO boost buffer current setting
LFXO boost buffer current must be
disabled
CMU_E113
LFXO startup at high temperature
LFXO does not start at high temperature with default configuration.
CMU_E114
Device not waking up from EM2
when using prescaled non-HFRCO
oscillator as HFCLK
If the device is running from any prescaled oscillator other
than HFRCO as HFCLK and HFRCO is disabled, the device
will not wake up from EM2.
Before entering EM2, clear CMU_CTRL_HFCLKDIV.
Alternatively, enable HFRCO by setting
CMU_OSCENCMD_HFRCOEN and wait until
CMU_STATUS_HFRCORDY is set.
CUR_E103
Increased EM2 current
Current consumption in EM2 and EM3 has two stable states,
the normal state (1200 nA and 900 nA for EM2 and EM3
respectively) and an error state. In the error state the current consumption in EM2 and EM3 is typically 4.5 uA at 25C
(manufacturing test limits is set to 7 uA) but will increase with
increased temperature. At 85C the error state EM2 and EM3
current consumption is typically 25 uA. It is unpredictable
which state the device will go into on EM2/EM3 entry and it
can also change state during operation.
No known workaround.
Increased consumption in EM2
CUR_E104
Increased current on AVDD2
When VREGO is floating or 0 V, a leakage can appear on
AVDD2. This leakage is typically less than 10 uA, but can alIncreased current on AVDD2 related to so rise to around 300 uA.
VREGO
Make sure VREGO is always defined high when there is
power on AVDD2. For bus-powered devices this is always
the case, but for devices where the power on VREGO can
be lost during operation, e.g. a USB device where the USB
phy is powered from VBUS when a master is attached, a 5
MOhm to VDD can help keep VREGO defined.
DAC_E109
DAC output drift over lifetime
Both in the startup initialization code and prior to disabling
the DAC in application code, set the OPAnSHORT bit in
2016-04-08 - EFM32GG332FXX - d0169_Rev1.20
When the device is powered and the DAC is disabled, stress
on an internal circuit node can cause the output voltage of
6
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ID
DI_E101
Title/Problem
Effect
Fix/Workaround
The voltage output of the DAC might
drift over time.
the DAC to drift over time, and in some cases may violate the
VDACOFFSET specification. If the DAC is always enabled while
the device is powered, this condition cannot occur.
DACn_OPACTRL to a '1' for the corresponding DAC(s) used
by the application. This will prevent the output voltage drift
over time effect.
Flash Page Size
For devices with PROD_REV values lower than 18, the
MEM_INFO_PAGE_SIZE register value in the Device Information Page is incorrect.
Use fixed flash page size of 4k bytes.
In EM2, when sleeping with WFE (Wait for Event), an interrupt from the DMA will not wake up the system.
Use WFI (Wait for Interrupt) or EM1 instead.
DMA requests from the LEUART can trigger a DMA operation from EM2. While waiting for the DMA to fetch data from
the respective peripheral, the debugger cannot access the
system. If such a DMA request is not handled by the DMA
controller, the system will keep waiting for it while denying
debug access.
Make sure DMA requests triggered from EM2 are handled.
During EM2 entry, the high frequency clocks that are disabled during EM2 will run for some clock cycles after WFI is
issued to allow safe shutdown of the peripherals. If an enabled interrupt is requested from one of these non-EM2 peripherals during this shutdown period, the attempt to enter
EM2 will fail, and the device will enter EM1 instead. As a result the pending interrupt will immediately wake the device to
EM0.
Before entering EM2, disable all high frequency peripheral interrupts in the core.
ETM trace clock is out of phase making the data transition
occur at the same time as the ETM trace clock transitions.
ETM trace clock needs to be delayed between 10 ns and 1/4
of the trace clock period.
All EM4 wakeup cause bits for EM4 wakeup pins with high
polarity are set on wakeup.
Use low polarity if possible. For active high, slow changing inputs, a solution is to sample the inputs on wakeup.
The MEM_INFO_PAGE_SIZE value
stored in Device Information (DI) Page
is incorrect.
DMA_E101
EM2 with WFE and DMA
WFE does not work for the DMA in
EM2.
EMU_E105
Debug unavailable during DMA processing from EM2
The debugger cannot access the system processing DMA request from
EM2.
EMU_E107
Interrupts during EM2 entry
An interrupt from a peripheral running from the high frequency clock
that is received during EM2 entry will
cause the EMU to ignore the SLEEPDEEP-flag.
ETM_E101
ETM Trace Clock
ETM Trace Clock needs to be delayed.
GPIO_E101
GPIO wakeup from EM4
On GPIO wakeup from EM4 all cause
bits for high-polarity wakeup pins are
set.
LES_E101
LESENSE and Schmitt trigger
Schmitt trigger cannot be disabled on
pins used for sensor excitation
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When using LESENSE to excite a pin, the pin has to be con- Keep the input voltage to pins configured as push-pull outfigured in push-pull mode, which also enables the Schmitt
side the range 0.3*VDD to 0.7*VDD when LESENSE is not
trigger. If this pin has an input voltage somewhere in between interacting with the connected sensor.
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ID
Title/Problem
Effect
Fix/Workaround
0.3*VDD and 0.7*VDD, the Schmitt trigger will consume a
considerable ammount of current.
LES_E102
LESENSE and DAC CH1 configuration
LESENSE control of DAC CH1 cannot be enabled if
DACCH0CONV in LESENSE_PERCTRL is set to DISABLE.
Configure DACCH0CONV in LESENSE_PERCTRL to anything but DISABLE, this enables DAC CH1 to be controlled
properly. If DAC CH0 is not to be used, set DACCH0OUT
in LESENSE_PERCTRL to DISABLE. This will disable
LESENSE control of DAC CH0, but still allow LESENSE to
control DAC CH1.
LESENSE will not work properly when used with the AUXHFRCO running at the 1 or 7 MHz band.
Do not use a AUXHFRCO frequency band of 1 or 7 MHz
when used in combination with LESENSE.
When prefetch is enabled, i.e. the PREFETCH bit (bit 8)
is set in MSC_READCTRL, wrong instruction data can be
prefetched causing system failure.
Do not enable prefetch. Prefetching is disabled by default.
When OPA2 is started the output rampup is constant independent of bias setting.
No known workaround.
LESENSE cannot control
DAC CH1 if DACCH0CONV in
LESENSE_PERCTRL is set to DISABLE.
LES_E103
AUXHFRCO and LESENSE
LESENSE will not work properly at low
AUXHFRCO frequencies.
MSC_E101
Prefetch unreliable
Prefetch unreliable.
OPA_E101
Opamp 2 startup rampup
When OPA2 is started the output rampup is constant independent of bias
setting.
PCNT_E102
PCNT Pulse Width Filtering does
not work
The PCNT Pulse Width Filter does not work as intended.
Do not use the pulse width filter, i.e. ensure FILT = 0 in
PCNTn_CTRL.
PRS_E101
Edge detect on GPIO/ACMP
When using edge detect in PRS on signals from ACMP,
GPIO, RTC, LETIMER, LESENSE, VCMP and BURTC
edges can be missed.
Do not use edge detect on ACMP, GPIO, RTC, LETIMER,
LESENSE, VCMP and BURTC.
When RSSCOIST is set and PRESC > 0 in TIMERn_CTRL,
the capture/compare output value is not reliable.
Do not use a prescaled clock, i.e. ensure PRESC = 0 in
TIMERn_CTRL when RSSCOIST is enabled.
When AUTOTX in USARTn_CTRL or AUTOTXEN in
USARTn_TRIGCTRL is set, the USART will continue to
transmit data even after the RX buffer is full. This may cause
the RX buffer to overflow if the data is not read out in time.
No known workaround.
Edge detect on peripherals with asynchronous edges might be missed.
TIMER_E103
Capture/compare output is unreliable with RSSCOIST enabled
The TIMER capture/compare output is
unreliable when RSSCOIST is enabled
and the clock is prescaled.
USART_E112
USART AUTOTX continues to transmit even with full RX buffer
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ID
Title/Problem
Effect
Fix/Workaround
USB DMA transfers to flash may fail when prescaling HFCLK.
Do not prescale HFCLK when using USB-DMA transfers to
read from flash.
USART AUTOTX continues to transmit
even with full RX buffer.
USB_E101
USB DMA transfers with prescaled
HFCLK
USB DMA transfers to flash fail when
prescaling HFCLK.
USB_E102
USB datalines
USB datalines rise and fall time are
slightly outside specification.
USB datalines rise and fall time are slightly outside specifica- No known workaround.
tion under worst case conditions. They may fail USB certification eye test depending on PCB layout.
USB_E103
HNP Sequence fails if A-Device con- The B-Device core only waits for up to 3.4ms before signects after 3.4ms
nalling HNP fail and reverting back to Peripheral mode.
Therefore, the HNP sequence fails if the A-Device connects
after 3.4ms.
No known workaround.
USB_E104
USB A-Device delays the HNP
switch back process
The A-Device core delays the HNP switch back process. As
per the USB-OTG 2.0 specification, the B-Device on the other side of the USB pipe either should wait for disconnect from
the A-Device or should switch to Peripheral mode and wait
for the A-Device to issue a USB reset. Hence, there is no significant impact on actual operation.
No known workaround.
If the B-Device as Host on the other side of the USB pipe
drives K-J pairs for more than 200 ms during USB reset, the
A-Device core exits peripheral state, causing the HNP process to fail. There is no significant impact since normally the
host drives USB reset for a shorter time than 200 ms.
No known workaround.
USB inteerrupts are now trigggered by signal edge rather
then signal level.
Make sure to handle edge triggered interrupt, rather then signal level interrupts.
On transition from EM0 to EM4 a current leakage from
VREGO of up to 1 mA lasting a few seconds can occur.
No known workaround.
When the USB_DM or USB_DP pins are floating while the
USB PHY is disabled, a current in the order of a couple hun-
If there is no intention to use the USB module, e.g. the USB
PHY is disabled, but there is still a voltage on USB_VREGO,
The D+ line disconnects after 200 ms,
delaying the HNP switch back process.
USB_E105
B-Device as Host driving K-J pairs
during reset
The A-Device misinterprets the K-J
pairs as Suspend after switching to
High Speed mode.
USB_E106
USB interrupts
USB interrupts have changed from being level triggered to edge triggered.
USB_E107
Entry to EM4 causes temporary
leakage from VREGO
Entry to EM4 causes temporary leakage from VREGO.
USB_E108
Floating DM/DP pins cause leakage
when USB is disabled
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ID
USB_E109
Title/Problem
Effect
Fix/Workaround
Floating DM/DP pins cause leakage
when USB is disabled.
dred uA may leak from USB_VREGO to VSS. This will not be
an issue if there is no voltage applied to USB_VREGO, either
externally or through the USB regulator.
make sure the USB_DM and USB_DP pins are defined. This
can be done using GPIO or by defining them externally.
Missing
USB_GINTSTS.SESSREQINT
Interrupt with
USB_PCGCCTL.STOPPCLK = 1
When USB_PCGCCTL.STOPPCLK is set and the device is
acting as a B-peripheral, a Host-initated Suspend, followed
by a Host Disconnect and Host Connect will not result in a
SessReq interrupt.
If this is an expected use-case, USB_PCGCCTL.STOPPCLK
should not be set. USB_PCGCCTL.GATEHCLK can still be
used to save power.
In some cases, an unexpected USB_HCx_INT.CHHLTD
interrupt might be received from another endpoint
that does not have the USB_HCx_CHAR.CHDIS,
USB_HCx_INT.XACTERR, USB_HCx_INT.BBLERR,
USB_HCx_INT.DATATGLERR or
USB_HCx_INT.XFERCOMPL interrupts enabled.
If such an interrupt is received, the application must reenable the channel for which it received the unexpected
USB_HCx_INT.CHHLTD interrupt.
A Host-initiated Suspend, followed by
a Host Disconnect and Host Connect
will not result in a SessReq interrupt.
USB_E110
Unexpected USB_HCx_INT.CHHLTD
interrupt
In some cases the
USB_HCx_INT.CHHLTD interrupt
might be incorrectly set.
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2 Revision History
2.1 Revision 1.20
April 8th, 2016
Updated the latest revision to revision E.
Removed BURTC_E102, BU_E106, CMU_E114, DI_E101, EMU_107, and LES_E103 from revision E.
2.2 Revision 1.10
February 20th, 2015
Added DAC_E109.
Added EMU_E107.
Added TIMER_E103.
Added PCNT_E102.
Updated link to errata for older revisions.
Corrected typos.
2.3 Revision 0.70
March 26th, 2014
Corrected typos in document.
2.4 Revision 0.60
August 21st, 2013
Added ADC_E117.
Added AES_E102.
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Added USB_E109.
Added USB_E110.
Updated disclaimer, trademark and contact information.
2.5 Revision 0.50
July 30th, 2013
Added AES_E101.
Added BURTC_E102.
Added CMU_E114.
Added DMA_E101.
Updated errata naming convention.
2.6 Revision 0.40
June 5th, 2012
Added ADC1.
Added DI1.
2.7 Revision 0.30
April 24th, 2012
Added BU6.
Added CMU4.
Added CMU5.
Added LES3.
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Updated CMU3.
2.8 Revision 0.10
January 9th, 2012
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system
and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples
described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon
Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications.
Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or
chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro
logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®,
ISOmodem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM,
CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other
products or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Errata History ............................................................................................................................................................................................................................. 2
1.1. Errata Overview ................................................................................................................................................................................................................ 2
1.2. EFM32GG332 Errata Descriptions ....................................................................................................................................................................................... 4
2. Revision History ........................................................................................................................................................................................................................ 11
2.1. Revision 1.20 ................................................................................................................................................................................................................. 11
2.2. Revision 1.10 ................................................................................................................................................................................................................. 11
2.3. Revision 0.70 ................................................................................................................................................................................................................. 11
2.4. Revision 0.60 ................................................................................................................................................................................................................. 11
2.5. Revision 0.50 ................................................................................................................................................................................................................. 12
2.6. Revision 0.40 ................................................................................................................................................................................................................. 12
2.7. Revision 0.30 ................................................................................................................................................................................................................. 12
2.8. Revision 0.10 ................................................................................................................................................................................................................. 13
A. Disclaimer and Trademarks ......................................................................................................................................................................................................... 14
A.1. Disclaimer ..................................................................................................................................................................................................................... 14
A.2. Trademark Information ..................................................................................................................................................................................................... 14
B. Contact Information ................................................................................................................................................................................................................... 15
B.1. ................................................................................................................................................................................................................................... 15
2016-04-08 - EFM32GG332FXX - d0169_Rev1.20
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...the world's most energy friendly microcontrollers
List of Tables
1.1. Errata Overview ........................................................................................................................................................................................................................ 2
1.2. EFM32GG332 Errata Descriptions ............................................................................................................................................................................................... 4
2016-04-08 - EFM32GG332FXX - d0169_Rev1.20
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