EFM32JG1 Reference Manual

EFM32 Jade Gecko Family
EFM32JG1 Reference Manual
The EFM32 Jade Gecko MCUs are the world’s most energyfriendly microcontrollers.
ENERGY FRIENDLY FEATURES
EFM32JG1 features a powerful 32-bit ARM® Cortex-M3 and a wide selection of peripherals, including a unique cryptographic hardware engine supporting AES, ECC, and
SHA. These features, combined with ultra-low current active mode and short wake-up
time from energy-saving modes, make EFM32JG1 microcontrollers well suited for any
battery-powered application, as well as other systems requiring high performance and
low-energy consumption.
• Home automation and security
• Industrial and factory automation
• 1.4 μA EM2 DeepSleep current (RTCC
running with state and RAM retention)
• 60 μA/MHz in Energy Mode 0 (EM0)
• Integrated dc-dc converter
• CRYOTIMER operates down to EM4
• 5 V tolerant I/O
Core / Memory
ARM CortexTM M4 processor
with DSP extensions and FPU
Flash Program
Memory
• Ultra low energy operation:
• 1.1 μA EM3 Stop current (CRYOTIMER
running with state/RAM retention)
• Hardware cryptographic engine supports
AES, ECC, and SHA
Example applications:
• IoT devices and sensors
• Health and fitness
• Smart accessories
• ARM Cortex-M3 at 40 MHz
Clock Management
Memory
Protection Unit
RAM Memory
Debug Interface
DMA Controller
Energy Management
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
Regulator
Voltage Monitor
Low Frequency
RC Oscillator
Auxiliary High
Frequency RC
Oscillator
DC-DC
Converter
Power-On Reset
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Brown-Out
Detector
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
USART
External Interrupts
Timers and Triggers
Low Energy Timer
ADC
CRYPTO
Pulse Counter
Real Time Counter
and Calendar
Analog Comparator
CRC
Watchdog Timer
CRYOTIMER
IDAC
Pin Reset
I2C
Pin Wakeup
Other
Timer/Counter
General Purpose I/O
Low Energy UARTTM
Analog Interfaces
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 – Deep Sleep
EM3 - Stop
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
EM4 - Hibernate
EM4 - Shutoff
Preliminary Rev. 0.2
EFM32JG1 Reference Manual
About This Document
1. About This Document
1.1 Introduction
This document contains reference material for the EFM32 Jade Gecko devices. All modules and peripherals in the EFM32 Jade Gecko
devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such
differences, including pinout, are covered in the device data sheets.
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About This Document
1.2 Conventions
Register Names
Register names are given with a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the module number for modules which can exist in more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register
The "x" denotes the different ports.
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Bit fields wider than 1 bit are given with start (x) and stop (y) bit
[y:x].
Bit fields containing more than one bit are unsigned integers unless otherwise is specified.
Unspecified bit field settings must not be used, as this may lead to unpredictable behaviour.
Address
The address for each register can be found by adding the base address of the module found in the Memory Map (see ), and the offset
address for the register (found in module Register Map).
Access Type
The register access types used in the register descriptions are explained in Table 1.1 Register Access Types on page 2.
Table 1.1. Register Access Types
Access Type
Description
R
Read only. Writes are ignored
RW
Readable and writable
RW1
Readable and writable. Only writes to 1 have effect
(R)W1
Sometimes readable. Only writes to 1 have effect. Currently only
used for IFC registers (see 3.3.1.2 IFC Read-clear Operation)
W1
Read value undefined. Only writes to 1 have effect
W
Write only. Read value undefined.
RWH
Readable, writable, and updated by hardware
RW(nB), RWH(nB), etc.
"(nB)" suffix indicates that register explicitly does not support peripheral bit set or clear (see 4.2.2 Peripheral Bit Set and Clear)
RW(a), R(a), etc.
"(a)" suffix indicates that register has actionable reads (see
5.3.6 Debugger reads of actionable registers)
Number format
0x prefix is used for hexadecimal numbers
0b prefix is used for binary numbers
Numbers without prefix are in decimal representation.
Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the
Register Description. Reserved bits might be read as 1 in future devices.
Reset Value
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The reset value denotes the value after reset.
Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations
on these registers before they are initialized results in undefined register values.
Pin Connections
Pin connections are given with a module prefix followed by a short pin name:
CMU_CLKOUT1 (Clock management unit, clock output pin number 1)
The location for the pin names given in the module documentation can be found in the device-specific datasheet.
1.3 Related Documentation
Further documentation on the EFM32 Jade Gecko family and the ARM Cortex-M3 can be found at the Silicon Labs and ARM web pages:
www.silabs.com
www.arm.com
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System Overview
2. System Overview
Quick Facts
What?
0 1 2 3
4
The EFM32 Jade Gecko is a highly integrated, configurable and low power MCU with a complete set of
peripherals.
Why?
EFM32 Jade Gecko features an Cortex-M3 core, a
unique cryptographic hardware engine supporting
AES, ECC, and SHA, ultra-low current active mode,
and short wake-up time from energy-saving modes.
How?
EFM32 Jade Gecko microcontrollers are well suited
for any batter-powered application, as well as other
systems requiring high performance and low-energy
consumption
2.1 Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM CortexM3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32
Jade Gecko microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption.
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System Overview
2.2 Block Diagrams
The block diagram for the EFM32 Jade Gecko MCU series is shown in (Figure 2.1 EFM32 Jade Gecko System-On-Chip Block Diagram
on page 5).
Core / Memory
TM
ARM Cortex M4 processor
with DSP extensions and FPU
Flash Program
Memory
Clock Management
Memory
Protection Unit
RAM Memory
Debug Interface
DMA Controller
Energy Management
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
Regulator
Voltage Monitor
Low Frequency
RC Oscillator
Auxiliary High
Frequency RC
Oscillator
DC-DC
Converter
Power-On Reset
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Brown-Out
Detector
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
USART
External Interrupts
Timers and Triggers
Low Energy Timer
ADC
CRYPTO
Pulse Counter
Real Time Counter
and Calendar
Analog Comparator
CRC
Watchdog Timer
CRYOTIMER
IDAC
Pin Reset
I2C
Pin Wakeup
Other
Timer/Counter
General Purpose I/O
Low Energy UARTTM
Analog Interfaces
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 – Deep Sleep
EM3 - Stop
EM4 - Hibernate
EM4 - Shutoff
Figure 2.1 EFM32 Jade Gecko System-On-Chip Block Diagram
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System Overview
2.3 MCU Features overview
• ARMCortex-M3 CPU platform
• High Performance 32-bit processor @ up to 40 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
• Flexible Energy Management System
• Power routing configurations including DCDC control
• Voltage Monitoring and Brown Out Detection
• State Retention
• 256 KB Flash
• 32 KB RAM
• Up to 28 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
• 12 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
• CRYPTO Advanced Encryption Standard Accelerator
• AES encryption / decryption, with 128 or 256 bit keys
• Multiple AES modes of operation, including Counter (CTR), Galois/Counter Mode (GCM), Cipher Block Chaining (CBC), Cipher
Feedback (CFB) and Output Feedback (OFB).
• Accelerated SHA-1 and SHA-2
• Accelerated Elliptic Curve Cryptography (ECC), with binary or prime fields
• Flexible 256-bit ALU and sequencer
• General Purpose Cyclic Redundancy Check
• Programmable 16-bit polynomial, fixed 32-bit polynomial
• Communication interfaces
• 2∙Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Hardware flow control
• 4-16 data bits
• 1∙ Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 1∙I2C Interface with SMBus support
• Address recognition in Stop Mode
• Timers/Counters
• 2∙ 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 32-bit Ultra Low Energy Timer/Counter (CRYOTIMER) for periodic wake-up from any Energy Mode
• 32-bit Real-Time Counter and Calendar
• 16+16+32 bit Protocol Timer
• 16-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 input channels and on-chip temperature sensor
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System Overview
• Single ended or differential operation
• Conversion tailgating for predictable latency
• Current Digital to Analog Converter
• Source or sink a configurable constant current
• 2∙ Analog Comparator
• Programmable speed/current
• Capacitive sensing with up to 8 inputs
• Analog Port
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 4-pin Joint Test Action Group (JTAG) interface
• 2-pin serial-wire debug (SWD) interface
• 1.62 V to 3.8 V single power supply
2.4 Oscillators and Clocks
EFM32 Jade Gecko has six different oscillators integrated, as shown in Table 2.1 EFM32 Jade Gecko Oscillators on page 7
Table 2.1. EFM32 Jade Gecko Oscillators
Oscillator
Frequency
Optional?
External
components
Description
HFXO
38 MHz - 40 MHz
No
Crystal
High accuracy, low jitter high frequency crystal oscillator. Tunable crystal loading capacitors are fully integrated.
HFRCO
1 MHz - 38 MHz
No
-
Medium accuracy RC oscillator, typically used for timing during startup of the HFXO or if a precise oscillator is not required.
AUXHFRCO
1 MHz - 38 MHz
No
-
Medium accuracy RC oscillator, typically used as alternative
clock source for Analog to Digital Converter or Debug Trace.
LFRCO
32768 Hz
No
-
Medium accuracy frequency reference typically used for medium accuracy RTCC timing.
LFXO
32768 Hz
Yes
Crystal
High accuracy frequency reference typically used for high accuracy RTCC timing. Tunable crystal loading capacitors are
fully integrated.
ULFRCO
1000 Hz
No
-
Ultra low frequency oscillator typically used for the watchdog
timer.
The RC oscillators can be calibrated against either of the crystal oscillators in order to compensate for temperature and voltage supply
variations. Hardware support is included to measure the frequency of various oscillators against each other.
Oscillator and clock management is available through the Clock Management Unit (CMU), see section 10. CMU - Clock Management
Unit for details.
2.5 Hardware CRC Support
EFM32 Jade Gecko supports a configurable CRC generation:
•
•
•
•
•
8, 16, 24 or 32 bit CRC value
Configurable polynomial and initialization value
Optional inversion of CRC value over air
Configurable CRC byte ordering
Support for multiple CRC values calculated and verified per transmitted or received frame
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System Overview
2.6 Data Encryption and Authentication
EFM32 Jade Gecko has hardware support for AES encryption, decryption and authentication modes. These security operations can be
performed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits.
AES modes of operations directly supported by the EFM32 Jade Gecko hardware are listed in Table 2.2 AES modes of operation with
hardware support on page 8. In addition to these modes, other modes can also be implemented by using combinations of modes.
For example, the CCM mode can be implemented using the CTR and CBC-MAC modes in combination.
Table 2.2. AES modes of operation with hardware support
AES Mode
Encryption / Decryption
Authentication
Comment
ECB
Yes
-
Electronic Code Book
CTR
Yes
-
Counter mode
CCM
Yes
Yes
Counter with CBC-MAC
CCM*
Yes
Yes
CCM with encryption-only and
integrity-only capabilities
GCM
Yes
Yes
Galois Counter Mode
CBC
Yes
-
Cipher Block Chaining
CBC-MAC
-
Yes
Cipher Block Chaining, Message Authentication Code
CMAC
-
Yes
Cipher-basec MAC
CFB
Yes
-
Cipher Feedback
OFB
Yes
-
Output Feedback
The CRYPTO module can provide data directly from the embedded Cortex-M3 or via DMA.
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System Overview
2.7 Timers
EFM32 Jade Gecko includes multiple timers, as can be seen from Table 2.3 EFM32 Jade Gecko Timers Overview on page 9.
Table 2.3. EFM32 Jade Gecko Timers Overview
Timer
Number of instances
Typical clock source
Overview
RTCC
1
Low frequency (LFXO or
LFRCO)
32 bit Real Time Counter and
Calendar, typically used to accurately time inactive periods
and enable wakeup on compare
match.
TIMER
2
High frequency (HFXO or
HFRCO)
16 bit general purpose timer.
Systick timer
1
High frequency (HFXO or
HFRCO)
32 bit systick timer integrated in
the Cortex-M3. Typically used
as an Operating System timer.
WDOG
1
Low frequency (LFXO, LFRCO
or ULFRCO)
Watch dog timer. Once enabled,
this module must be periodically
accessed. If not, this is considered an error and the EFM32
Jade Gecko is reset in order to
recover the system.
LETIMER
1
Low frequency (LFXO, LFRCO
or ULFRCO)
Low energy general purpose
timer.
Advanced interconnect features allows synchronization between timers. This includes:
• Start / stop any high frequency timer synchronized with the RTCC
• Trigger RSM state transitions based on compare timer compare match, for instance to provide clock cycle accuracy on frame transmit timing
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System Processor
3. System Processor
Quick Facts
What?
0 1 2 3
4
The industry leading Cortex-M3 processor from
ARM is the CPU in the EFM32 Jade Gecko devices.
Why?
The ARM Cortex-M3 is designed for exceptionally
short response time, high code density, and high 32bit throughput while maintaining a strict cost and
power consumption budget.
CM3Core
How?
32-bit ALU
Hardware divider
Single cycle
32-bit multiplier
Control Logic
Thumb & Thumb-2
Decode
Instruction Interface
Data Interface
NVIC Interface
Memory Protection Unit
Combined with the ultra low energy peripherals
available in EFM32 Jade Gecko devices, the CortexM3 processor's Harvard architecture, 3 stage pipeline, single cycle instructions, Thumb-2 instruction
set support, and fast interrupt handling make it perfect for 8-bit, 16-bit, and 32-bit applications.
3.1 Introduction
The ARM Cortex-M3 32-bit RISC processor provides outstanding computational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption.
The ARM Cortex-M3 implemented is revision r0p1.
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System Processor
3.2 Features
• Harvard architecture
• Separate data and program memory buses (No memory bottleneck as in a single bus system)
• 3-stage pipeline
• Thumb-2 instruction set
• Enhanced levels of performance, energy efficiency, and code density
• Single cycle multiply and hardware divide instructions
• 32-bit multiplication in a single cycle
• Signed and unsigned divide operations between 2 and 12 cycles
• Atomic bit manipulation with bit banding
• Direct access to single bits of data
• Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions
• Atomic operation, cannot be interrupted by other bus activities
• 1.25 DMIPS/MHz
• Memory Protection Unit
• Up to 8 protected memory regions
• 24 bits System Tick Timer for Real Time OS
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplicity of legacy 8-bit and 16-bit architectures
• Alligned or unaligned data storage and access
• Contiguous storage of data requiring different byte lengths
• Data access in a single core access cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
3.3 Functional Description
For a full functional description of the ARM Cortex-M3 implementation in the EFM32 Jade Gecko family, the reader is referred to the
ARM Cortex-M3 documentation.
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System Processor
3.3.1 Interrupt Operation
Module
Cortex-M4 NVIC
IFS[n]
IFC[n]
IEN[n]
SETENA[n]/CLRENA[n]
Active interrupt
Interrupt
condition
set
clear
IF[n]
IRQ
set
clear
Interrupt
request
SETPEND[n]/CLRPEND[n]
Software generated interrupt
Figure 3.1 Interrupt Operation
The interrupt request (IRQ) lines are connected to the Cortex-M3. Each of these lines (shown in Table 3.1 Interrupt Request Lines (IRQ)
on page 13) is connected to one or more interrupt flags in one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its
own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the
corresponding pending bit (can also be set/cleared with the SETPEND/CLRPEND bits in ISPR0/ICPR0) in the Cortex-M3 NVIC. The
pending bit is then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt
request to the core. Figure 3.1 Interrupt Operation on page 12 illustrates the interrupt system. For more information on how the interrupts are handled inside the Cortex-M3, the reader is referred to the EFM32 Cortex-M3 Reference Manual.
3.3.1.1 Avoiding Extraneous Interrupts
There can be latencies in the system such that clearing an interrupt flag could take longer than leaving an Interrupt Service Routine
(ISR). This can lead to the ISR being re-entered as the interrupt flag has yet to clear immediately after leaving the ISR. To avoid this,
when clearing an interrupt flag at the end of an ISR, the user should execute ARM's Data Synchronization Barrier (DSB) instruction.
Another approach is to clear the interrupt flag immediately after identifying the interrupt source and then service the interrupt as shown
in the pseudo-code below. The ISR typically is sufficiently long to more than cover the few cycles it may take to clear the interrupt status, and also allows the status to be checked for further interrupts before exiting the ISR.
irqXServiceRoutine() {
do {
clearIrqXStatus();
serviceIrqX();
} while(irqXStatusIsActive());
}
3.3.1.2 IFC Read-clear Operation
In addition to the normal interrupt setting and clearing operations via the IFS/IFC registers, there is an additional atomic Read-clear
operation that can be enabled by setting IFCREADCLEAR=1 in the MSC_CTRL register. When enabled, reads of peripheral IFC registers will return the interrupt vector (mirroring the IF register), while at the same time clearing whichever interrupt flags are set. This operation is functionally equivalent to reading the IF register and then writing the result immediately back to the IFC register.
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System Processor
3.3.2 Interrupt Request Lines (IRQ)
Table 3.1. Interrupt Request Lines (IRQ)
IRQ #
Source
0
EMU
2
WDOG0
8
LDMA
9
GPIO_EVEN
10
TIMER0
11
USART0_RX
12
USART0_TX
13
ACMP0
14
ADC0
15
IDAC0
16
I2C0
17
GPIO_ODD
18
TIMER1
19
USART1_RX
20
USART1_TX
21
LEUART0
22
PCNT0
23
CMU
24
MSC
25
CRYPTO
26
LETIMER0
29
RTCC
31
CRYOTIMER
33
FPUEH
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Memory and Bus System
4. Memory and Bus System
Quick Facts
What?
0 1 2 3
4
A low latency memory system including low energy
Flash and RAM with data retention which makes the
energy modes attractive.
Why?
Flash
ARM Cortex-M
RAM retention reduces the need for storing data in
Flash and enables frequent use of the ultra low energy modes EM2 DeepSleep and EM3 Stop with as
little as 700 nA current consumption.
How?
RAM
DMA Controller
Peripherals
Low energy and non-volatile Flash memory stores
program and application data in all energy modes
and can easily be reprogrammed in system. Low
leakage RAM with data retention in EM0 Active to
EM3 Stop removes the data restore time penalty,
and the DMA ensures fast autonomous transfers
with predictable response time.
4.1 Introduction
The EFM32 Jade Gecko contains an AMBA AHB Bus system to allow bus masters to access the memory mapped address space. A
multilayer AHB bus matrix connects the 4 master bus interfaces to the AHB slaves (Figure 4.1 EFM32 Jade Gecko Bus System on
page 14). The bus matrix allows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The 4 AHB bus masters are:
• Cortex-M3 ICode: Used for instruction fetches from Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
• Cortex-M3 DCode: Used for debug and data access to Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
• Cortex-M3 System: Used for data and debug access to system space. It can access entire memory space except Code memory
(valid address range: 0x20000000 - 0xFFFFFFFF)
• DMA: Can access entire memory space except internal core memory region and Code memory (valid address range: 0x20000000 0xDFFFFFFF)
ARM
Cortex-M
ICode
AHB Multilayer
Bus Matrix
Flash
RAM
DCode
CRYPTO
System
AHB/
APB
Bridge
Peripheral 0
DMA
Peripheral n
Figure 4.1 EFM32 Jade Gecko Bus System
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Memory and Bus System
4.2 Functional Description
The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Figure 4.2 System Address Space with Core and Code Space Listing on page 15.
Figure 4.2 System Address Space with Core and Code Space Listing
Additionally, the peripheral address map is detailed by Figure 4.3 System Address Space with Peripheral Listing on page 16.
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Memory and Bus System
Figure 4.3 System Address Space with Peripheral Listing
The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32 Jade Gecko. When running code located in
SRAM starting at this address, the Cortex-M3 uses the System bus interface to fetch instructions. This results in reduced performance
as the Cortex-M3 accesses stack, other data in SRAM and peripherals using the System bus interface. To be able to run code from
SRAM efficiently, the SRAM is also mapped in the code space at address 0x10000000. When running code from this space, the CortexM3 fetches instructions through the I/D-Code bus interface, leaving the System bus interface for data access. The SRAM mapped into
the code space can however only be accessed by the CPU, i.e. not the DMA.
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Memory and Bus System
4.2.1 Bit-banding
The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and
write operations to these regions are converted into masked single-bit reads and atomic single-bit writes to the embedded SRAM and
peripherals of the EFM32 Jade Gecko.
Note: Bit-banding is only available through the CPU. No other AHB masters (e.g., DMA) can perform Bit-banding operations.
Using a standard approach to modify a single register or SRAM bit in the aliased regions, would require software to read the value of
the byte, half-word or word containing the bit, modify the bit, and then write the byte, half-word or word back to the register or SRAM
address. Using bit-banding, this can be done in a single operation, consuming only two bus cycles. As read-writeback, bit-masking and
bit-shift operations are not necessary in software, code size is reduced and execution speed improved.
The bit-band regions allow each bit in the SRAM and Peripheral areas of the memory map to be addressed. To set or clear a bit in the
embedded SRAM, write a 1 or a 0 to the following address:
bit_address = 0x22000000 + (address – 0x20000000) ∙ 32 + bit ∙ 4
where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.
To modify a bit in the Peripheral area, use the following address:
bit_address = 0x42000000 + (address – 0x40000000) ∙ 32 + bit ∙ 4
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Memory and Bus System
4.2.2 Peripheral Bit Set and Clear
The EFM32 Jade Gecko supports bit set and bit clear access to all peripherals except those listed in Table 4.1 Peripherals that Do Not
Support Bit Set and Bit Clear on page 18. The bit set and bit clear functionality (also called Bit Access) enables modification of bit
fields (single bit or multiple bit wide) without the need to perform a read-modify-write (though it is functionally equivalent). Also, the operation is contained within a single bus access (for HF peripherals), unlike the Bit-banding operation described in section 4.2.1 Bitbanding which consumes two bus accesses per operation. All AHB masters can utilize this feature.
The bit clear aliasing region starts at 0x44000000 and the bit set aliasing region starts at 0x46000000. Thus, to apply a bit set or clear
operation, write the bit set or clear mask the following addresses:
bit_clear_address = address + 0x04000000
bit_set_address = address + 0x06000000
For bit set operations, bit locations that are 1 in the bit mask will be set in the destination register:
register = (register OR mask)
For bit clear operations, bit locations that are 1 in the bit mask will be cleared in the destination register:
register = (register AND (NOT mask))
Note: It is possible to combine bit clear and bit set operations in order to arbitrarily modify multi-bit register fields, without affecting other
fields in the same register. In this case, care should be taken to ensure that the field does not have intermediate values that can lead to
erroneous behavior. For example, if bit clear and bit set operations are used to change an analog tuning register field from 25 to 26, the
field would initially take on a value of zero. If the analog module is active at the time, this could lead to undesired behavior.
The peripherals listed in 4.2.2 Peripheral Bit Set and Clear do not support Bit Access for any registers. All other peripherals do support
Bit Access, however, there may be cases of certain registers that do not support it. Such registers have a note regarding this lack of
support.
Table 4.1. Peripherals that Do Not Support Bit Set and Bit Clear
Module
EMU
RMU
CRYOTIMER
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4.2.3 Peripherals
The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 4.2 Peripherals on page 19, Table 4.3 Low Energy Peripherals on page 19 , and Table 4.4 Core Peripherals on page 19.
Table 4.2. Peripherals
Address Range
Module Name
0x400E6000 - 0x400E6400
PRS
0x4001E000 - 0x4001E400
CRYOTIMER
0x4001C000 - 0x4001C400
GPCRC
0x40018400 - 0x40018800
TIMER1
0x40018000 - 0x40018400
TIMER0
0x40010400 - 0x40010800
USART1
0x40010000 - 0x40010400
USART0
0x4000C000 - 0x4000C400
I2C0
0x4000A000 - 0x4000B000
GPIO
0x40006000 - 0x40006400
IDAC0
0x40002000 - 0x40002400
ADC0
0x40000400 - 0x40000800
ACMP1
0x40000000 - 0x40000400
ACMP0
Table 4.3. Low Energy Peripherals
Address Range
Module Name
0x40052000 - 0x40052400
WDOG0
0x4004E000 - 0x4004E400
PCNT0
0x4004A000 - 0x4004A400
LEUART0
0x40046000 - 0x40046400
LETIMER0
0x40042000 - 0x40042400
RTCC
Table 4.4. Core Peripherals
Address Range
Module Name
0x400F0000 - 0x400F0400
CRYPTO
0x400E2000 - 0x400E3000
LDMA
0x400E1000 - 0x400E1400
FPUEH
0x400E0000 - 0x400E0800
MSC
4.2.4 Bus Matrix
The Bus Matrix connects the memory segments to the bus masters as detailed in 4.1 Introduction.
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4.2.4.1 Arbitration
The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency, while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does
not insert any bus wait-states during peak interaction. However, one wait state is inserted for master accesses occurring after a prolonged inactive time. This wait state allows for increased power efficiency during master idle time.
4.2.4.2 Access Performance
The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth of 4x a single AHB interface.
The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any wait-states. However, the
slaves may insert wait-states depending on their internal throughput and the clock frequency.
The Cortex-M3, DMA Controller, and peripherals (not peripherals in the low frequency clock domain) run on clocks which can be prescaled separately. Clocks and prescaling are described in more detail in 10. CMU - Clock Management Unit .
In general, when accessing a peripheral, the latency in number of HFBUSCLK cycles, not including master arbitration, is given by:
Nbus cycles = Nslave cycles ∙ fHFBUSCLK/fHFPERCLK, best-case write accesses
Nbus cycles = Nslave cycles ∙ fHFBUSCLK/fHFPERCLK + 1, best-case read accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFBUSCLK/fHFPERCLK - 1, worst-case write accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFBUSCLK/fHFPERCLK, worst-case read accesses
where Nslave cycles is the number of cycles required to access the particular slave, including any wait cycles introduced by the slave.
Equation: Bus Access Latency (General Case)
Note that a latency of 1 cycle corresponds to 0 wait states.
Additionally, for back-to-back accesses to the same peripheral, the throughput in number of cycles per transfer is given by:
Nbus cycles = Nslave cycles ∙ fHFBUSCLK/fHFPERCLK, write accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFBUSCLK/fHFPERCLK, read accesses
Equation: Bus Access Throughput (Back-to-Back Transfers)
Lastly, in the highest performing case, where HFPERCLK equals HFBUSCLK and the slave doesn't introduce any additional wait
states, the access latency in number of cycles is given by:
Nbus cycles = 1, write accesses
Nbus cycles = 2, read accesses
Equation: Bus Access Latency (Max Performance)
Note that the cycle counts in the equations above is in terms of the HFBUSCLK. When the core is prescaled from the bus clock, the
core will see a reduced number of latency cycles given by:
Ncore cycles = ceiling( Nbus cycles ∙ fHFCORECLK/fHFBUSCLK )
where master arbitration is not included.
Equation: Core Access Latency
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4.2.4.3 Bus Faults
System accesses from the core can receive a bus fault in the following condition(s):
• The core attempts to access an address that is not assigned to any peripheral or other system device. These faults can be enabled
or disabled by setting the ADDRFAULTEN bit appropriately in MSC_CTRL.
• The core attempts to access a peripheral or system device that has its clock disabled. These faults can be enabled or disabled by
setting the CLKDISFAULTEN bit appropriately in MSC_CTRL.
In addition to any condition-specific bus fault control bits, the bus fault interrupt itself can be enabled or disabled in the same way as all
other internal core interrupts.
4.3 Access to Low Energy Peripherals (Asynchronous Registers)
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy
mode EM2 DeepSleep and in some cases also EM3 Stop. This enables the peripherals to perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are listed in Table 4.3 Low Energy Peripherals on page 19.
All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low Energy Peripherals are running on clocks asynchronous to the high frequency system clock, there are some constraints on how register accesses are performed,
as described in the following sections.
4.3.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to
maintain data consistency and predictable operation. There are two different synchronization mechanisms on the EFM32JG1, immediate synchronization, and delayed synchronization. Immediate synchronization is available for the RTCC and LETIMER, and results in
an immediate update of the target registers. Delayed synchronization is used for the remaining Low Energy Peripherals, and for these
peripherals, a write operation requires 3 positive edges of the clock on the Low Energy Peripheral being accessed. Registers requiring
synchronization are marked "Async Reg" in their description header.
Note: On the Gecko series of devices, all LE peripherals are subject to delayed synchronization.
High Frequency Clock Domain
Write request 1
Write request n
Low Frequency Clock Domain
Low Frequency Clock
Low Frequency Clock
Register 0
Synchronizer 0
Register 0 Sync
Register 1
.
.
.
Register n
Synchronizer 1
.
.
.
Synchronizer n
Register 1 Sync
.
.
.
Register n Sync
High Frequency Clock
Write request 0
Freeze
Synchronization Done
Write request [0:n]
Set 0
Syncbusy Register 0
Clear 0
Set 1
Syncbusy Register 1
.
.
.
Syncbusy Register n
Clear 1
Set n
Clear n
Figure 4.8 Write operation to Low Energy Peripherals
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4.3.1.1 Delayed Synchronization
After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corresponding busy flag in the <module_name>_SYNCBUSY register (e.g. LETIMER_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon completion.
Note: Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag
is cleared may result in undefined behavior. In general the SYNCBUSY register only needs to be observed if there is a risk of multiple
write access to a register (which must be prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is
cleared after writing a register. E.g., EM2 DeepSleep can be entered directly after writing a register.
See Figure 4.9 Write operation to Low Energy Peripherals on page 22 for an overview of the writing mechanism operation.
High Frequency Clock Domain
Write request 1
Write request n
Low Frequency Clock Domain
Low Frequency Clock
Low Frequency Clock
Register 0
Synchronizer 0
Register 0 Sync
Register 1
.
.
.
Register n
Synchronizer 1
.
.
.
Synchronizer n
Register 1 Sync
.
.
.
Register n Sync
High Frequency Clock
Write request 0
Freeze
Synchronization Done
Write request [0:n]
Set 0
Syncbusy Register 0
Clear 0
Set 1
Syncbusy Register 1
.
.
.
Syncbusy Register n
Clear 1
Set n
Clear n
Figure 4.9 Write operation to Low Energy Peripherals
4.3.1.2 Immediate Synchronization
In contrast to the peripherals with delayed synchronization, peripherals with immediate synchronization don't experience a delay from a
value is written to it takes effect in the peripheral. They are updated immediately on the peripheral write access. If such a write is done
close to an edge on the clock of the peripheral, the write is delayed to after the clock edge. This will introduce wait-states on the peripheral access.
Peripherals with immediate synchronization each have a SYNCBUSY register. Commands written to a peripheral with immediate synchronization are not executed before the first peripheral clock after the write. In this period, the SYNCBUSY flag for the command register is set, indicating that the command has not yet been performed. Secondly, to maintain compatibility with the Gecko series, the rest
of the SYNCBUSY registers are also present, but these are always 0, indicating that register writes are always safe.
Note: If compatibility with the Gecko series is a requirement for a given application, the rules that apply to delayed synchronization with
respect to SYNCBUSY should also be followed for the peripherals that support immediate synchronization.
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4.3.2 Reading
When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates in the Low Energy clock domain
or High Frequency clock domain. See Figure 4.10 Read operation from Low Energy Peripherals on page 23 for an overview of the
reading operation.
Note: Writing a register and then immediately reading the new value of the register may give the impression that the write operation is
complete. This may not be the case. Please refer to the SYNCBUSY register for correct status of the write operation to the Low Energy
Peripheral.
High Frequency Clock Domain
Freeze
Low Frequency Clock Domain
Low Frequency Clock
Low Frequency Clock
Register 0
Synchronizer 0
Register 0 Sync
Register 1
.
.
.
Register n
Synchronizer 1
.
.
.
Synchronizer n
Register 1 Sync
.
.
.
Register n Sync
High Frequency Clock
HW Status Register 0
Read
Synchronizer
HW Status Register 1
.
.
.
HW Status Register m
Low Energy
Peripheral
Main
Function
Read Data
Figure 4.10 Read operation from Low Energy Peripherals
4.3.3 FREEZE Register
In all Low Energy Peripheral with delayed synchronization there is a <module_name>_FREEZE register (e.g. RTCC_FREEZE). The
register contains a bit named REGFREEZE. If precise control of the synchronization process is required, this bit may be utilized. When
REGFREEZE is set, the synchronization process is halted allowing the software to write multiple Low Energy registers before starting
the synchronization process, thus providing precise control of the module update process. The synchronization process is started by
clearing the REGFREEZE bit.
Note: The FREEZE register is also present on peripherals with immediate synchronization, but there it has no effect
4.4 Flash
The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash
memory is typically programmed through the debug interface, but can also be erased and written to from software.
• Up to 256 KB of memory
• Page size of 2048 bytes (minimum erase unit)
• Minimum 10K erase cycles endurance
• Greater than 10 years data retention at 85°C
• Lock-bits for memory protection
• Data retention in any state
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Memory and Bus System
4.5 SRAM
The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and
the DMA may be set up to transfer data between the SRAM, Flash and peripherals.
• Up to 32 KB of memory
• Bit-band access support
• Set of RAM blocks may be powered down when not in use
• Data retention of the entire memory in EM0 Active to EM3 Stop
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4.6 DI Page Entry Map
The DI page contains production calibration data as well as device identification information. See the peripheral chapters for how each
calibration value is to be used with the associated peripheral.
The offset address is relative to the start address of the DI page.(see 6.3 Functional Description)
Offset
Name
Type
Description
0x000
CAL
RO
CRC of DI-page and calibration temperature
0x028
EUI48L
RO
EUI48 OUI and Unique identifier
0x02C
EUI48H
RO
OUI
0x030
CUSTOMINFO
RO
Custom information
0x034
MEMINFO
RO
Flash page size and misc. chip information
0x040
UNIQUEL
RO
Low 32 bits of device unique number
0x044
UNIQUEH
RO
High 32 bits of device unique number
0x048
MSIZE
RO
Flash and SRAM Memory size in kB
0x04C
PART
RO
Part description
0x050
DEVINFOREV
RO
Device information page revision
0x054
EMUTEMP
RO
EMU Temperature Calibration Information
0x060
ADC0CAL0
RO
ADC0 calibration register 0
0x064
ADC0CAL1
RO
ADC0 calibration register 1
0x068
ADC0CAL2
RO
ADC0 calibration register 2
0x06C
ADC0CAL3
RO
ADC0 calibration register 3
0x080
HFRCOCAL0
RO
HFRCO Calibration Register (4 MHz)
0x08C
HFRCOCAL3
RO
HFRCO Calibration Register (7 MHz)
0x098
HFRCOCAL6
RO
HFRCO Calibration Register (13 MHz)
0x09C
HFRCOCAL7
RO
HFRCO Calibration Register (16 MHz)
0x0A0
HFRCOCAL8
RO
HFRCO Calibration Register (19 MHz)
0x0A8
HFRCOCAL10
RO
HFRCO Calibration Register (26 MHz)
0x0AC
HFRCOCAL11
RO
HFRCO Calibration Register (32 MHz)
0x0B0
HFRCOCAL12
RO
HFRCO Calibration Register (38 MHz)
0x0E0
AUXHFRCOCAL0
RO
AUXHFRCO Calibration Register (4 MHz)
0x0EC
AUXHFRCOCAL3
RO
AUXHFRCO Calibration Register (7 MHz)
0x0F8
AUXHFRCOCAL6
RO
AUXHFRCO Calibration Register (13 MHz)
0x0FC
AUXHFRCOCAL7
RO
AUXHFRCO Calibration Register (16 MHz)
0x100
AUXHFRCOCAL8
RO
AUXHFRCO Calibration Register (19 MHz)
0x108
AUXHFRCOCAL10
RO
AUXHFRCO Calibration Register (26 MHz)
0x10C
AUXHFRCOCAL11
RO
AUXHFRCO Calibration Register (32 MHz)
0x110
AUXHFRCOCAL12
RO
AUXHFRCO Calibration Register (38 MHz)
0x140
VMONCAL0
RO
VMON Calibration Register 0
0x144
VMONCAL1
RO
VMON Calibration Register 1
0x148
VMONCAL2
RO
VMON Calibration Register 2
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Offset
Name
Type
Description
0x158
IDAC0CAL0
RO
IDAC0 Calibration Register 0
0x15C
IDAC0CAL1
RO
IDAC0 Calibration Register 1
0x168
DCDCLNVCTRL0
RO
DCDC Low-noise VREF Trim Register 0
0x16C
DCDCLPVCTRL0
RO
DCDC Low-power VREF Trim Register 0
0x170
DCDCLPVCTRL1
RO
DCDC Low-power VREF Trim Register 1
0x174
DCDCLPVCTRL2
RO
DCDC Low-power VREF Trim Register 2
0x178
DCDCLPVCTRL3
RO
DCDC Low-power VREF Trim Register 3
0x17C
DCDCLPCMPHYSSEL0 RO
DCDC LPCMPHYSSEL Trim Register 0
0x180
DCDCLPCMPHYSSEL1 RO
DCDC LPCMPHYSSEL Trim Register 1
4.7 DI Page Entry Description
4.7.1 CAL - CRC of DI-page and calibration temperature
3
2
1
0
2
1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
3
Name
CRC
Access
RO
17
18
19
20
21
22
23
24
25
26
27
28
TEMP RO
29
30
0x000
Bit Position
31
Offset
Bit
Name
Access
Description
23:16
TEMP
RO
Calibration temperature as an usigned int in DegC
(25 = 25DegC)
15:0
CRC
RO
CRC of DI-page (CRC-16-CCITT)
4.7.2 EUI48L - EUI48 OUI and Unique identifier
OUI48L
Access
Name
4
5
6
7
8
9
10
11
12
UNIQUEID RO
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RO
29
30
0x028
Bit Position
31
Offset
Bit
Name
Access
Description
31:24
OUI48L
RO
Lower Octet of EUI48 Organizationally Unique Identifier
23:0
UNIQUEID
RO
Unique identifier
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Memory and Bus System
4.7.3 EUI48H - OUI
3
2
1
0
3
2
1
0
4
5
6
7
8
OUI48H RO
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
Access
Name
Bit
Name
Access
Description
31:16
Reserved
Reserved for future use
15:0
OUI48H
RO
Upper two Octets of EUI48 Organizationally Unique
Identifier
4.7.4 CUSTOMINFO - Custom information
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PARTNO RO
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Access
Name
Bit
Name
Access
Description
31:16
PARTNO
RO
Custom part identifier as unsigned integer (e.g. 903)
65535 for standard product
15:0
Reserved
Reserved for future use
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4.7.5 MEMINFO - Flash page size and misc. chip information
Bit
Name
Access
Description
31:24
FLASH_PAGE_SIZE
RO
A signed integer. FlashPageSize = 2 ^
(FLASH_PAGE_SIZE + 10). Ie. the value 0xFF (-1)
results in a page size of 2^(-1 + 10) = 512 bytes.
23:16
PINCOUNT
RO
Device pin count as unsigned integer (eg. 48)
15:8
PKGTYPE
RO
Package Identifier as character
Value
Mode
Description
74
WLCSP
WLCSP package
77
QFN
QFN package
81
QFP
QFP package
TEMPGRADE
RO
Temperature Grade of product as unsigned integer enumeration
Value
Mode
Description
0
N40TO85
-40 to 85degC
1
N40TO125
-40 to 125degC
2
N40TO105
-40 to 105degC
3
N0TO70
0 to 70degC
7:0
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0
1
2
3
4
TEMPGRADE
RO
5
6
7
8
9
10
11
12
RO
13
14
15
16
17
18
20
19
PKGTYPE
Name
PINCOUNT
Access
RO
21
22
23
24
25
26
27
28
FLASH_PAGE_SIZE RO
29
30
0x034
Bit Position
31
Offset
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EFM32JG1 Reference Manual
Memory and Bus System
4.7.6 UNIQUEL - Low 32 bits of device unique number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UNIQUEL RO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
Access
Name
Bit
Name
Access
Description
31:0
UNIQUEL
RO
Low 32 bits of device unique number
4.7.7 UNIQUEH - High 32 bits of device unique number
5
4
3
2
1
0
5
4
3
2
1
0
6
7
8
9
10
11
12
13
14
15
16
UNIQUEH RO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Access
Name
Bit
Name
Access
Description
31:0
UNIQUEH
RO
High 32 bits of device unique number
4.7.8 MSIZE - Flash and SRAM Memory size in kB
Name
6
7
8
9
10
11
12
FLASH RO
SRAM
Access
13
14
15
16
17
18
19
20
21
22
23
24
RO
25
26
27
28
29
30
0x048
Bit Position
31
Offset
Bit
Name
Access
Description
31:16
SRAM
RO
Ram size, kbyte count as unsigned integer (eg. 16)
15:0
FLASH
RO
Flash size, kbyte count as unsigned integer (eg. 128)
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4.7.9 PART - Part description
Bit
Name
Access
Description
31:24
PROD_REV
RO
Production revision as unsigned integer
23:16
DEVICE_FAMILY
RO
Device Family
Value
Mode
Description
16
EFR32MG1P
EFR32 Mighty Gecko Device Family
17
EFR32MG1B
EFR32 Mighty Gecko Device Family
18
EFR32MG1V
EFR32 Mighty Gecko Device Family
19
EFR32BG1P
EFR32 Blue Gecko Device Family
20
EFR32BG1B
EFR32 Blue Gecko Device Family
21
EFR32BG1V
EFR32 Blue Gecko Device Family
22
EFR32ZG1P
EFR32 Zappy Gecko Device Family
23
EFR32ZG1B
EFR32 Zappy Gecko Device Family
24
EFR32ZG1V
EFR32 Zappy Gecko Device Family
25
EFR32FG1P
EFR32 Flex Gecko Device Family
26
EFR32FG1B
EFR32 Flex Gecko Device Family
27
EFR32FG1V
EFR32 Flex Gecko Device Family
71
G
EFM32 Gecko Device Family
71
EFM32G
EFM32 Gecko Device Family
72
EFM32GG
EFM32 Giant Gecko Device Family
72
GG
EFM32 Giant Gecko Device Family
73
TG
EFM32 Tiny Gecko Device Family
73
EFM32TG
EFM32 Tiny Gecko Device Family
74
EFM32LG
EFM32 Leopard Gecko Device Family
74
LG
EFM32 Leopard Gecko Device Family
75
EFM32WG
EFM32 Wonder Gecko Device Family
75
WG
EFM32 Wonder Gecko Device Family
76
ZG
EFM32 Zero Gecko Device Family
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DEVICE_NUMBER RO
Name
19
20
DEVICE_FAMILY
PROD_REV
Access
RO
21
22
23
24
25
26
27
28
RO
29
30
0x04C
Bit Position
31
Offset
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EFM32JG1 Reference Manual
Memory and Bus System
Bit
15:0
Name
Access
Description
76
EFM32ZG
EFM32 Zero Gecko Device Family
77
HG
EFM32 Happy Gecko Device Family
77
EFM32HG
EFM32 Happy Gecko Device Family
81
EFM32PG1B
EFM32 Pearl Gecko Device Family
83
EFM32JG1B
EFM32 Jade Gecko Device Family
120
EZR32LG
EZR32 Leopard Gecko Device Family
121
EZR32WG
EZR32 Wonder Gecko Device Family
122
EZR32HG
EZR32 Happy Gecko Device Family
DEVICE_NUMBER
RO
Part number as unsigned integer (e.g. 233 for
EFR32BG1P233F256GM48-B0)
4.7.10 DEVINFOREV - Device information page revision
0
1
2
3
4
DEVINFOREV RO
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x050
Bit Position
31
Offset
Access
Name
Bit
Name
Access
31:8
Reserved
Reserved for future use
7:0
DEVINFOREV
RO
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Description
DEVINFO layout revision as unsigned integer (initially 1)
Preliminary Rev. 0.2 | 31
EFM32JG1 Reference Manual
Memory and Bus System
4.7.11 EMUTEMP - EMU Temperature Calibration Information
2
1
0
1
0
3
2
4
EMUTEMPROOM RO
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x054
Bit Position
31
Offset
Access
Name
Bit
Name
Access
Description
31:8
Reserved
Reserved for future use
7:0
EMUTEMPROOM
RO
EMU_TEMP temperature reading at room (durring
calibration)
4.7.12 ADC0CAL0 - ADC0 calibration register 0
Bit
Name
Access
31
Reserved
Reserved for future use
30:24
GAIN2V5
RO
Gain for 2.5V reference
23:20
NEGSEOFFSET2V5
RO
Negative single ended offset for 2.5V reference
19:16
OFFSET2V5
RO
Offset for 2.5V reference
15
Reserved
Reserved for future use
14:8
GAIN1V25
RO
Gain for 1.25V reference
7:4
NEGSEOFFSET1V25
RO
Negative single ended offset for 1.25V reference
3:0
OFFSET1V25
RO
Offset for 1.25V reference
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RO
OFFSET1V25
3
4
5
6
NEGSEOFFSET1V25 RO
7
8
9
10
12
RO 11
GAIN1V25
13
14
15
16
17
18
RO
OFFSET2V5
19
20
21
22
RO
23
24
25
26
GAIN2V5
Name
NEGSEOFFSET2V5
Access
RO 27
28
29
30
0x060
Bit Position
31
Offset
Description
Preliminary Rev. 0.2 | 32
EFM32JG1 Reference Manual
Memory and Bus System
4.7.13 ADC0CAL1 - ADC0 calibration register 1
Bit
Name
Access
31
Reserved
Reserved for future use
30:24
GAIN5VDIFF
RO
Gain for for 5V differential reference
23:20
NEGSEOFFSET5VDIFF
RO
Negative single ended offset with for 5V differential
reference
19:16
OFFSET5VDIFF
RO
Offset for 5V differential reference
15
Reserved
Reserved for future use
14:8
GAINVDD
RO
Gain for VDD reference
7:4
NEGSEOFFSETVDD
RO
Negative single ended offset for VDD reference
3:0
OFFSETVDD
RO
Offset for VDD reference
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0
1
2
RO
OFFSETVDD
3
4
5
6
RO
NEGSEOFFSETVDD
7
8
9
10
12
RO 11
GAINVDD
13
14
15
16
17
18
RO
OFFSET5VDIFF
19
20
21
22
23
24
25
26
GAIN5VDIFF
Name
NEGSEOFFSET5VDIFF RO
Access
RO 27
28
29
30
0x064
Bit Position
31
Offset
Description
Preliminary Rev. 0.2 | 33
EFM32JG1 Reference Manual
Memory and Bus System
4.7.14 ADC0CAL2 - ADC0 calibration register 2
0
OFFSET2XVDD
Name
1
2
2
Access
RO
3
3
4
5
6
NEGSEOFFSET2XVDD RO
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x068
Bit Position
31
Offset
Bit
Name
Access
Description
31
Reserved
Reserved for future use
30:24
Reserved
Reserved for future use
23:20
Reserved
Reserved for future use
19:16
Reserved
Reserved for future use
15:8
Reserved
Reserved for future use
7:4
NEGSEOFFSET2XVDD
RO
Negative single ended offset for 2XVDD reference
3:0
OFFSET2XVDD
RO
Offset for 2XVDD reference
4.7.15 ADC0CAL3 - ADC0 calibration register 3
Access
Name
Bit
Name
Access
28:13
Reserved
Reserved for future use
15:4
TEMPREAD1V25
RO
3:0
Reserved
Reserved for future use
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0
1
4
5
6
7
8
9
10
11
12
13
14
TEMPREAD1V25 RO 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x06C
Bit Position
31
Offset
Description
Temperature reading at 1.25V reference (durring calibration)
Preliminary Rev. 0.2 | 34
EFM32JG1 Reference Manual
Memory and Bus System
4.7.16 HFRCOCAL0 - HFRCO Calibration Register (4 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x080
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 35
EFM32JG1 Reference Manual
Memory and Bus System
4.7.17 HFRCOCAL3 - HFRCO Calibration Register (7 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x08C
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 36
EFM32JG1 Reference Manual
Memory and Bus System
4.7.18 HFRCOCAL6 - HFRCO Calibration Register (13 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x098
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 37
EFM32JG1 Reference Manual
Memory and Bus System
4.7.19 HFRCOCAL7 - HFRCO Calibration Register (16 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x09C
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 38
EFM32JG1 Reference Manual
Memory and Bus System
4.7.20 HFRCOCAL8 - HFRCO Calibration Register (19 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0A0
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 39
EFM32JG1 Reference Manual
Memory and Bus System
4.7.21 HFRCOCAL10 - HFRCO Calibration Register (26 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0A8
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 40
EFM32JG1 Reference Manual
Memory and Bus System
4.7.22 HFRCOCAL11 - HFRCO Calibration Register (32 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0AC
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 41
EFM32JG1 Reference Manual
Memory and Bus System
4.7.23 HFRCOCAL12 - HFRCO Calibration Register (38 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
HFRCO Temperature Coefficient Trim on Comparator
Reference
27
FINETUNINGEN
RO
HFRCO enable reference for fine tuning
26:25
CLKDIV
RO
HFRCO Clock Output Divide
24
LDOHP
RO
HFRCO LDO High Power Mode
23:21
CMPBIAS
RO
HFRCO Comparator Bias Current
20:16
FREQRANGE
RO
HFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
RO
4
5
TUNING
FINETUNING
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0B0
Bit Position
31
Offset
HFRCO Fine Tuning Value
HFRCO Tuning Value
Preliminary Rev. 0.2 | 42
EFM32JG1 Reference Manual
Memory and Bus System
4.7.24 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0E0
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 43
EFM32JG1 Reference Manual
Memory and Bus System
4.7.25 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0EC
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 44
EFM32JG1 Reference Manual
Memory and Bus System
4.7.26 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
silabs.com | Smart. Connected. Energy-friendly.
0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0F8
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 45
EFM32JG1 Reference Manual
Memory and Bus System
4.7.27 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x0FC
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 46
EFM32JG1 Reference Manual
Memory and Bus System
4.7.28 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
silabs.com | Smart. Connected. Energy-friendly.
0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x100
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 47
EFM32JG1 Reference Manual
Memory and Bus System
4.7.29 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x108
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 48
EFM32JG1 Reference Manual
Memory and Bus System
4.7.30 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x10C
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 49
EFM32JG1 Reference Manual
Memory and Bus System
4.7.31 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz)
Bit
Name
Access
Description
31:28
VREFTC
RO
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
27
FINETUNINGEN
RO
AUXHFRCO enable reference for fine tuning
26:25
CLKDIV
RO
AUXHFRCO Clock Output Divide
24
LDOHP
RO
AUXHFRCO LDO High Power Mode
23:21
CMPBIAS
RO
AUXHFRCO Comparator Bias Current
20:16
FREQRANGE
RO
AUXHFRCO Frequency Range
15:14
Reserved
Reserved for future use
13:8
FINETUNING
RO
7
Reserved
Reserved for future use
6:0
TUNING
RO
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0
1
2
3
TUNING
FINETUNING
RO
4
5
6
7
8
9
10
11
RO
12
13
14
15
16
17
RO 18
FREQRANGE
19
20
21
RO 22
CMPBIAS
23
RO 24
LDOHP
25
26
RO
CLKDIV
28
29
30
FINETUNINGEN RO 27
Name
RO
Access
VREFTC
0x110
Bit Position
31
Offset
AUXHFRCO Fine Tuning Value
AUXHFRCO Tuning Value
Preliminary Rev. 0.2 | 50
EFM32JG1 Reference Manual
Memory and Bus System
4.7.32 VMONCAL0 - VMON Calibration Register 0
Name
Access
Description
31:28
ALTAVDD2V98THRESCOARSE
RO
ALTAVDD 2.98 V Coarse Threshold Adjust
27:24
ALTAVDD2V98THRESFINE
RO
ALTAVDD 2.98 V Fine Threshold Adjust
23:20
ALTAVDD1V86THRESCOARSE
RO
ALTAVDD 1.86 V Coarse Threshold Adjust
19:16
ALTAVDD1V86THRESFINE
RO
ALTAVDD 1.86 V Fine Threshold Adjust
15:12
AVDD2V98THRESCOARSE
RO
AVDD 2.98 V Coarse Threshold Adjust
11:8
AVDD2V98THRESFINE
RO
AVDD 2.98 V Fine Threshold Adjust
7:4
AVDD1V86THRESCOARSE
RO
AVDD 1.86 V Coarse Threshold Adjust
3:0
AVDD1V86THRESFINE
RO
AVDD 1.86 V Fine Threshold Adjust
0
1
2
RO
3
4
AVDD1V86THRESFINE
Bit
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5
6
RO
AVDD1V86THRESCOARSE
7
8
9
10
RO
AVDD2V98THRESFINE
11
12
13
14
RO
AVDD2V98THRESCOARSE
15
16
17
18
RO
ALTAVDD1V86THRESFINE
19
20
21
22
23
24
25
27
28
29
30
26
RO
ALTAVDD1V86THRESCOARSE RO
Name
ALTAVDD2V98THRESFINE
Access
ALTAVDD2V98THRESCOARSE RO
0x140
Bit Position
31
Offset
Preliminary Rev. 0.2 | 51
EFM32JG1 Reference Manual
Memory and Bus System
4.7.33 VMONCAL1 - VMON Calibration Register 1
Bit
Name
Access
Description
31:28
IO02V98THRESCOARSE
RO
IO0 2.98 V Coarse Threshold Adjust
27:24
IO02V98THRESFINE
RO
IO0 2.98 V Fine Threshold Adjust
23:20
IO01V86THRESCOARSE
RO
IO0 1.86 V Coarse Threshold Adjust
19:16
IO01V86THRESFINE
RO
IO0 1.86 V Fine Threshold Adjust
15:12
DVDD2V98THRESCOARSE
RO
DVDD 2.98 V Coarse Threshold Adjust
11:8
DVDD2V98THRESFINE
RO
DVDD 2.98 V Fine Threshold Adjust
7:4
DVDD1V86THRESCOARSE
RO
DVDD 1.86 V Coarse Threshold Adjust
3:0
DVDD1V86THRESFINE
RO
DVDD 1.86 V Fine Threshold Adjust
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0
1
2
RO
DVDD1V86THRESFINE
3
4
5
6
DVDD1V86THRESCOARSE RO
7
8
9
10
RO
DVDD2V98THRESFINE
11
12
13
14
DVDD2V98THRESCOARSE RO
15
16
17
18
RO
IO01V86THRESFINE
19
20
21
22
RO
IO01V86THRESCOARSE
23
24
25
26
RO
27
28
29
30
IO02V98THRESFINE
Name
RO
Access
IO02V98THRESCOARSE
0x144
Bit Position
31
Offset
Preliminary Rev. 0.2 | 52
EFM32JG1 Reference Manual
Memory and Bus System
4.7.34 VMONCAL2 - VMON Calibration Register 2
Bit
Name
Access
Description
31:28
FVDD2V98THRESCOARSE
RO
FVDD 2.98 V Coarse Threshold Adjust
27:24
FVDD2V98THRESFINE
RO
FVDD 2.98 V Fine Threshold Adjust
23:20
FVDD1V86THRESCOARSE
RO
FVDD 1.86 V Coarse Threshold Adjust
19:16
FVDD1V86THRESFINE
RO
FVDD 1.86 V Fine Threshold Adjust
15:12
PAVDD2V98THRESCOARSE
RO
PAVDD 2.98 V Coarse Threshold Adjust
11:8
PAVDD2V98THRESFINE
RO
PAVDD 2.98 V Fine Threshold Adjust
7:4
PAVDD1V86THRESCOARSE
RO
PAVDD 1.86 V Coarse Threshold Adjust
3:0
PAVDD1V86THRESFINE
RO
PAVDD 1.86 V Fine Threshold Adjust
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0
1
2
RO
PAVDD1V86THRESFINE
3
4
5
6
PAVDD1V86THRESCOARSE RO
7
8
9
10
RO
PAVDD2V98THRESFINE
11
12
13
14
PAVDD2V98THRESCOARSE RO
15
16
17
18
RO
FVDD1V86THRESFINE
19
20
21
22
RO
FVDD1V86THRESCOARSE
23
24
25
26
RO
27
28
29
30
FVDD2V98THRESFINE
Name
RO
Access
FVDD2V98THRESCOARSE
0x148
Bit Position
31
Offset
Preliminary Rev. 0.2 | 53
EFM32JG1 Reference Manual
Memory and Bus System
4.7.35 IDAC0CAL0 - IDAC0 Calibration Register 0
Bit
Name
Access
Description
31:24
SOURCERANGE3TUNING
RO
Calibrated middle step (16) of current source mode
range 3
23:16
SOURCERANGE2TUNING
RO
Calibrated middle step (16) of current source mode
range 2
15:8
SOURCERANGE1TUNING
RO
Calibrated middle step (16) of current source mode
range 1
7:0
SOURCERANGE0TUNING
RO
Calibrated middle step (16) of current source mode
range 0
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
SOURCERANGE0TUNING RO
Name
SOURCERANGE1TUNING RO
Access
SOURCERANGE2TUNING RO
21
22
23
24
25
26
27
28
SOURCERANGE3TUNING RO
29
30
0x158
Bit Position
31
Offset
Preliminary Rev. 0.2 | 54
EFM32JG1 Reference Manual
Memory and Bus System
4.7.36 IDAC0CAL1 - IDAC0 Calibration Register 1
2
1
0
1
0
3
2
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
10
SINKRANGE0TUNING RO
Name
SINKRANGE1TUNING RO
Access
SINKRANGE2TUNING RO
21
22
23
24
25
26
27
28
SINKRANGE3TUNING RO
29
30
0x15C
Bit Position
31
Offset
Bit
Name
Access
Description
31:24
SINKRANGE3TUNING
RO
Calibrated middle step (16) of current sink mode
range 3
23:16
SINKRANGE2TUNING
RO
Calibrated middle step (16) of current sink mode
range 2
15:8
SINKRANGE1TUNING
RO
Calibrated middle step (16) of current sink mode
range 1
7:0
SINKRANGE0TUNING
RO
Calibrated middle step (16) of current sink mode
range 0
4.7.37 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0
Bit
Name
Access
Description
31:24
3V0LNATT1
RO
DCDC LNVREF Trim for 3.0V output, LNATT=1
23:16
1V8LNATT1
RO
DCDC LNVREF Trim for 1.8V output, LNATT=1
15:8
1V8LNATT0
RO
DCDC LNVREF Trim for 1.8V output, LNATT=0
7:0
1V2LNATT0
RO
DCDC LNVREF Trim for 1.2V output, LNATT=0
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3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
5
1V2LNATT0 RO
Name
1V8LNATT0 RO
Access
1V8LNATT1 RO
20
21
22
23
24
25
26
27
28
3V0LNATT1 RO
29
30
0x168
Bit Position
31
Offset
Preliminary Rev. 0.2 | 55
EFM32JG1 Reference Manual
Memory and Bus System
4.7.38 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0
Bit
Name
Access
Description
31:24
1V8LPATT0LPCMPBIAS1
RO
DCDC LPVREF Trim for 1.8V output, LPATT=0,
LPCMPBIAS=1
23:16
1V2LPATT0LPCMPBIAS1
RO
DCDC LPVREF Trim for 1.2V output, LPATT=0,
LPCMPBIAS=1
15:8
1V8LPATT0LPCMPBIAS0
RO
DCDC LPVREF Trim for 1.8V output, LPATT=0,
LPCMPBIAS=0
7:0
1V2LPATT0LPCMPBIAS0
RO
DCDC LPVREF Trim for 1.2V output, LPATT=0,
LPCMPBIAS=0
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
1V2LPATT0LPCMPBIAS0 RO
Name
1V8LPATT0LPCMPBIAS0 RO
Access
1V2LPATT0LPCMPBIAS1 RO
21
22
23
24
25
26
27
28
1V8LPATT0LPCMPBIAS1 RO
29
30
0x16C
Bit Position
31
Offset
Preliminary Rev. 0.2 | 56
EFM32JG1 Reference Manual
Memory and Bus System
4.7.39 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1
Bit
Name
Access
Description
31:24
1V8LPATT0LPCMPBIAS3
RO
DCDC LPVREF Trim for 1.8V output, LPATT=0,
LPCMPBIAS=3
23:16
1V2LPATT0LPCMPBIAS3
RO
DCDC LPVREF Trim for 1.2V output, LPATT=0,
LPCMPBIAS=3
15:8
1V8LPATT0LPCMPBIAS2
RO
DCDC LPVREF Trim for 1.8V output, LPATT=0,
LPCMPBIAS=2
7:0
1V2LPATT0LPCMPBIAS2
RO
DCDC LPVREF Trim for 1.2V output, LPATT=0,
LPCMPBIAS=2
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
1V2LPATT0LPCMPBIAS2 RO
Name
1V8LPATT0LPCMPBIAS2 RO
Access
1V2LPATT0LPCMPBIAS3 RO
21
22
23
24
25
26
27
28
1V8LPATT0LPCMPBIAS3 RO
29
30
0x170
Bit Position
31
Offset
Preliminary Rev. 0.2 | 57
EFM32JG1 Reference Manual
Memory and Bus System
4.7.40 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2
Bit
Name
Access
Description
31:24
3V0LPATT1LPCMPBIAS1
RO
DCDC LPVREF Trim for 3.0V output, LPATT=1,
LPCMPBIAS=1
23:16
1V8LPATT1LPCMPBIAS1
RO
DCDC LPVREF Trim for 1.8V output, LPATT=1,
LPCMPBIAS=1
15:8
3V0LPATT1LPCMPBIAS0
RO
DCDC LPVREF Trim for 3.0V output, LPATT=1,
LPCMPBIAS=0
7:0
1V8LPATT1LPCMPBIAS0
RO
DCDC LPVREF Trim for 1.8V output, LPATT=1,
LPCMPBIAS=0
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
1V8LPATT1LPCMPBIAS0 RO
Name
3V0LPATT1LPCMPBIAS0 RO
Access
1V8LPATT1LPCMPBIAS1 RO
21
22
23
24
25
26
27
28
3V0LPATT1LPCMPBIAS1 RO
29
30
0x174
Bit Position
31
Offset
Preliminary Rev. 0.2 | 58
EFM32JG1 Reference Manual
Memory and Bus System
4.7.41 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3
2
1
0
1
0
3
2
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
10
1V8LPATT1LPCMPBIAS2 RO
Name
3V0LPATT1LPCMPBIAS2 RO
Access
1V8LPATT1LPCMPBIAS3 RO
21
22
23
24
25
26
27
28
3V0LPATT1LPCMPBIAS3 RO
29
30
0x178
Bit Position
31
Offset
Bit
Name
Access
Description
31:24
3V0LPATT1LPCMPBIAS3
RO
DCDC LPVREF Trim for 3.0V output, LPATT=1,
LPCMPBIAS=3
23:16
1V8LPATT1LPCMPBIAS3
RO
DCDC LPVREF Trim for 1.8V output, LPATT=1,
LPCMPBIAS=3
15:8
3V0LPATT1LPCMPBIAS2
RO
DCDC LPVREF Trim for 3.0V output, LPATT=1,
LPCMPBIAS=3
7:0
1V8LPATT1LPCMPBIAS2
RO
DCDC LPVREF Trim for 1.8V output, LPATT=1,
LPCMPBIAS=2
4.7.42 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0
Name
Bit
Name
Access
31:16
Reserved
Reserved for future use
15:8
LPCMPHYSSELLPATT1
RO
DCDC LPCMPHYSSEL Trim, LPATT=1
7:0
LPCMPHYSSELLPATT0
RO
DCDC LPCMPHYSSEL Trim, LPATT=0
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3
4
5
LPCMPHYSSELLPATT0 RO
Access
6
7
8
9
10
11
12
LPCMPHYSSELLPATT1 RO
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x17C
Bit Position
31
Offset
Description
Preliminary Rev. 0.2 | 59
EFM32JG1 Reference Manual
Memory and Bus System
4.7.43 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1
Name
Access
Description
31:24
LPCMPHYSSELLPCMPBIAS3
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=3
23:16
LPCMPHYSSELLPCMPBIAS2
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=2
15:8
LPCMPHYSSELLPCMPBIAS1
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=1
7:0
LPCMPHYSSELLPCMPBIAS0
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=0
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Bit
LPCMPHYSSELLPCMPBIAS0 RO
Name
LPCMPHYSSELLPCMPBIAS1 RO
Access
LPCMPHYSSELLPCMPBIAS2 RO
21
22
23
24
25
26
27
28
LPCMPHYSSELLPCMPBIAS3 RO
29
30
0x180
Bit Position
31
Offset
Preliminary Rev. 0.2 | 60
EFM32JG1 Reference Manual
DBG - Debug Interface
5. DBG - Debug Interface
Quick Facts
What?
0 1 2 3
4
The Debug Interface is used to program and debug
EFM32 Jade Gecko devices.
Why?
The Debug Interface makes it easy to re-program
and update the system in the field, and allows debugging with minimal I/O pin usage.
How?
The Cortex-M3 supports advanced debugging features. EFM32 Jade Gecko devices can use a minimum of two port pins for debugging or programming.
The internal and external state of the system can be
examined with debug extensions supporting instruction or data access break and watch points.
ARM Cortex-M4
DBG
Debug Data
5.1 Introduction
The EFM32 Jade Gecko devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface or a 4-pin Joint
Test Action Group (JTAG) interface .
For more technical information about the debug interface the reader is referred to:
• ARM Cortex-M3 Technical Reference Manual
• ARM CoreSight Components Technical Reference Manual
• ARM Debug Interface v5 Architecture Specification
• IEEE Standard for Test Access Port and Boundary-Scan Architecture, IEEE 1149.1-2013
5.2 Features
• Debug Access Port Serial Wire JTAG (DAPSWJ)
• Implements the ADIv5 debug interface
• Authentication Access Point (AAP)
• Implements various user commands
• Flash Patch and Breakpoint (FPB) unit
• Implement breakpoints and code patches
• Data Watch point and Trace (DWT) unit
• Implement watch points, trigger resources and system profiling
• Instrumentation Trace Macrocell (ITM)
• Application-driven trace source that supports printf style debugging
5.3 Functional Description
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Preliminary Rev. 0.2 | 61
EFM32JG1 Reference Manual
DBG - Debug Interface
5.3.1 Debug Pins
The following pins are the debug connections for the device:
• Serial Wire Clock Input and Test Clock Input (SWCLKTCK) : This pin is enabled after reset and has a built-in pull down.
• Serial Wire Data Input/Output and Test Mode Select Input (SWDIOTMS) : This pin is enabled after reset and has a built-in pull-up.
• Test Data Output (TDO): This pin is disabled after reset.
• Test Data Input (TDI): This pin is disabled after reset. Once enabled, the pin has a built-in pull-up.
The debug pins have pull-down and pull-up enabled by default, so leaving them enabled may increase the current consumption if left
connected to supply or ground. The debug pins can be enabled and disabled through GPIO_ROUTE_PEN, see 26.3.4.2.3 Disabling
Debug Connections. Please remember that upon disabling the debug pins, debug contact with the device is lost once the DAPSWJ
power request bits are deasserted. If enabling the JTAG pins, the part must be power cycled to enable a SWD debug session.
5.3.2 Debug and EM2 DeepSleep/EM3 Stop
Leaving the debugger connected when issuing a WFI or WFE to enter EM2 DeepSleep or EM3 Stop will make the system enter a special EM2 DeepSleep. This mode differs from regular EM2 DeepSleep and EM3 Stop in that the high frequency clocks are still enabled,
and certain core functionality is still powered in order to maintain debug-functionality. Because of this, the current consumption in this
mode is closer to EM1 Sleep and it is therefore important to deassert the power requests in the DAPSWJ and disconnect the debugger
before doing current consumption measurements.
5.3.3 Authentication Access Point
The Authentication Acces Point (AAP) is a set of registers that provide a minimal amount of debugging and system level commands.
The AAP registers contain commands to issue a FLASH erase, a system reset, a CRC of user code pages, and stalling the system bus.
The user must program the APSEL bit field to 255 inside of the ARM DAPSWJ Debug Port SELECT register to access the AAP. The
AAP is only accessible from a debugger and not from the core.
5.3.3.1 Command Key
The AAP uses a command key to enable the DEVICEERASE and SYSRESETREQ AAP commands. The command key must be written with the correct key in order for the commands to execute.
5.3.3.2 Device Erase
The device can be erased by writing AAP_CMDKEY followed by writing the DEVICEERASE register bit. Upon writing the command bit,
the ERASEBUSY bit is asserted. The ERASEBUSY bit will be de-asserted once the erase is complete. The SYSRESETREQ bit must
then be set to resume a normal debugger session. The DEVICEERASE register is available at all times through the AAP once the
CMDKEY is enetered.
5.3.3.3 System Reset
The system can be reset by writing AAP_CMDKEY followed by writing the SYSRESTREQ register bit. This must be done afer asserting
DEVICEERASE or CRCREQ. Depending on the reset level setting for system reset, asserting SYSRESETREQ will either reset the entire AAP register space or just the SYSRESETREQ bit. See 8.3.1 Reset levels for more details on reset levels. The SYSRESETREQ
register is available at all times through the AAP once the CMDKEY is enetered.
5.3.3.4 System Bus Stall
The system bus can be stalled at any time using the SYSBUSSTALL register bit. Once the SYSBUSSTALL is set, the system bus will
remain stalled until SYSBUSSTALL is cleared. While the system bus is stalled, only the registers inside the Cortex-M3, AAP and the
debugger can be accessed. The SYSBUSSTALL register is available at all times through the AAP.
5.3.3.5 User Flash Page CRC
The CRCREQ command initiates a CRC calculation on a given Flash Page. The CRC is only available on the Main, User Data, and
Lock Bit pages. It is highly recommended that the system bus is stalled before any CRCREQ commands are issued. The CRC calculation uses the on chip CRC block configured in 32 bit CRC mode. The Flash Page address for the CRCREQ command is written to the
CRCADDR register. After issuing the CRCREQ, the CRCBUSY flag is asserted. Once the CRCBUSY flag is de-asserted, the resulting
page CRC can be found in the CRCRESULT register. Once issuing a CRC command, the CPU is stalled and remains stalled until a
system reset occurs. Multiple CRC requests can occur before resetting the system. However, a CRC request that occurs while the
CRCBUSY flag is asserted will be ignored. The CRC registers are available at all times through the AAP.
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DBG - Debug Interface
5.3.4 Debug Lock
The debug access to the Cortex-M3 is locked by clearing the Debug Lock Word (DLW) and resetting the device, see 6.3.2 Lock Bits
(LB) Page Description.
When debug access is locked, the debugger can access the DAPSWJ and AAP registers. However, the connection to the Cortex-M3
core and the whole bus-system is blocked. This mechanism is controlled by the Authentication Access Port (AAP) as illustrated by
Figure 5.1 AAP - Authentication Access Port on page 63.
ALW[3:0] == 0xF
DEVICEERASE
ERASEBUSY
DLW[3:0] == 0xF
SerialWire
debug
interface
SW-DP
Authentication
Access Port
(AAP)
Cortex
AHB-AP
Figure 5.1 AAP - Authentication Access Port
If the DLW is cleared, the device is locked. If the device is locked and the the AAP Lock Word (ALW) has not been cleared, it can be
unlocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit of the AAP_CMD register via the
debug interface. This operation erases the main block of flash, clears all lock bits, and debug access to the Cortex-M3 and bus-system
is enabled. The operation takes tens of mili seconds to complete. Note that the SRAM contents will also be deleted during a device
erase, while the UD-page is not erased.
The debugger may read the status of the device erase from the AAP_STATUS register. When the ERASEBUSY bit is set low after
DEVICEERASE of the AAP_CMD register is set, the debugger may set the SYSRESETREQ bit in the AAP_CMD register. After reset,
the debugger may resume a normal debug session through the AHB-AP.
5.3.5 AAP Lock
Take extreme caution when using this feature. Once the AAP has been locked, the state of the FLASH can not be changed via the
debugger.
5.3.6 Debugger reads of actionable registers
Some peripheral registers cause particular actions when read, e.g FIFOs which pop and IFC registers which clear the IF flags when
read. This can cause problems when debugging and the user wants to read the value without triggering the read action. For this reason, by default, the peripherals will not execute these triggered actions when an attached debugger is performing the read accesses
through the AAP. To override this behavior, the debugger can configure the MASTERTYPE bitfield of the Cortex-M3 AHB Access Port
CSW register in order to emulate a core access when performing system bus transfers.
Note: Registers with actionable reads are noted in their register descriptions. Please refer to .
5.3.7 Debug Recovery
Debug recovery is the ability to stall the system bus before the Cortex-M3 executes code. For example, the first few instructions may
disconnect the debugger pins. When this occurs it is difficult to connect the debugger and halt the Cortex-M3 before the Cortex-M3
starts to execute. By holding down pin reset, issuing the System Bus Stall AAP instruction, then releasing pin reset, the debugger can
stall the system bus before the Cortex-M3 has a chance to execute. Because the system is under reset during this procedure the Debugger can not look for ACK's from the part. Once the system bus is stalled, the FLASH can be erased by issuing the AAP_CMDKEY
and then the writting the DEVICEERASE in the AAP_CMD register.
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DBG - Debug Interface
5.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
AAP_CMD
W1
Command Register
0x004
AAP_CMDKEY
W1
Command Key Register
0x008
AAP_STATUS
R
Status Register
0x00C
AAP_CTRL
RW
Control Register
0x010
AAP_CRCCMD
W1
CRC Command Register
0x014
AAP_CRCSTATUS
R
CRC Status Register
0x018
AAP_CRCADDR
RW
CRC Address Register
0x01C
AAP_CRCRESULT
R
CRC Result Register
0x0FC
AAP_IDR
R
AAP Identification Register
5.5 Register Description
5.5.1 AAP_CMD - Command Register
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
SYSRESETREQ
0
W1
W1 0
0
Name
DEVICEERASE
Access
1
Reset
SYSRESETREQ W1 0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
Description
System Reset Request
A system reset request is generated when set to 1. This register is write enabled from the AAP_CMDKEY register.
0
DEVICEERASE
0
W1
Erase the Flash Main Block, SRAM and Lock Bits
When set, all data and program code in the main block is erased, the SRAM is cleared and then the Lock Bit (LB) page is
erased. This also includes the Debug Lock Word (DLW), causing debug access to be enabled after the next reset. The information block User Data page (UD) is left unchanged, but the User data page Lock Word (ULW) is erased. This register is
write enabled from the AAP_CMDKEY register.
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DBG - Debug Interface
5.5.2 AAP_CMDKEY - Command Key Register
2
2
0
3
3
1
4
6
6
4
7
7
5
8
8
5
9
9
10
11
12
13
14
15
16
WRITEKEY W1 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
WRITEKEY
0x00000000
W1
CMD Key Register
The key value must be written to this register to write enable the AAP_CMD register.
Value
Mode
Description
0xCFACC118
WRITEEN
Enable write to AAP_CMD
5.5.3 AAP_STATUS - Status Register
Name
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
LOCKED
0
R
0
0
ERASEBUSY R
1
LOCKED
Access
0
Reset
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Description
AAP Locked
Set when the AAP is locked, .e.g the AAP Lock Word AAP lsb bits are not 0xF
0
ERASEBUSY
0
R
Device Erase Command Status
This bit is set when a device erase is executing.
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DBG - Debug Interface
5.5.4 AAP_CTRL - Control Register
2
1
2
1
SYSBUSSTALL RW 0
Reset
0
3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
SYSBUSSTALL
0
RW
Description
Stall the System Bus
When this bit is set, the system bus is stalled. Only the Cortex registers are accessible
5.5.5 AAP_CRCCMD - CRC Command Register
CRCREQ W1 0
Reset
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
CRCREQ
0
W1
Description
CRC Request
A CRC request is generated when set to 1. This register is always available.
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DBG - Debug Interface
5.5.6 AAP_CRCSTATUS - CRC Status Register
3
2
1
0
3
2
1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x014
Bit Position
31
Offset
0
Reset
CRCBUSY R
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
CRCBUSY
0
R
Description
CRC Calculation is busy
Set when the CRC calculation is executing. Will transition from 1 to 0 on valid data.
5.5.7 AAP_CRCADDR - CRC Address Register
4
5
6
7
8
9
10
11
12
13
14
15
16
CRCADDR RW 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
CRCADDR
0x00000000
RW
Starting Page Address for CRC Execution
Set this to the address the CRC executes on.
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DBG - Debug Interface
5.5.8 AAP_CRCRESULT - CRC Result Register
4
3
2
1
0
3
2
1
0
6
6
4
7
7
5
8
8
5
9
9
10
11
12
13
14
15
16
0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Reset
CRCRESULT R
Access
Name
Bit
Name
Reset
Access
Description
31:0
CRCRESULT
0x00000000
R
CRC Result of the CRCADDRESS
Result of the CRC calculation using the CRCADDRESS.
5.5.9 AAP_IDR - AAP Identification Register
10
11
12
13
14
15
16
0x26E60011
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0FC
Bit Position
31
Offset
Reset
R
Access
ID
Name
Bit
Name
Reset
Access
Description
31:0
ID
0x26E60011
R
AAP Identification Register
Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID) .
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MSC - Memory System Controller
6. MSC - Memory System Controller
Quick Facts
What?
0 1 2 3
4
The user can perform Flash memory read, read configuration and write operations through the Memory
System Controller (MSC) .
Why?
01000101011011100110010101110010
01100111011110010010000001001101
01101001011000110111001001101111
00100000011100100111010101101100
01100101011100110010000001110100
01101000011001010010000001110111
01101111011100100110110001100100
00100000011011110110011000100000
01101100011011110111011100101101
01100101011011100110010101110010
01100111011110010010000001101101
01101001011000110111001001101111
01100011011011110110111001110100
01110010011011110110110001101100
01100101011100100010000001100100
01100101011100110110100101100111
01101110001000010100010101101110
The MSC allows the application code, user data and
flash lock bits to be stored in non-volatile Flash
memory. Certain memory system functions, such as
program memory wait-states and bus faults are also
configured from the MSC peripheral register interface, giving the developer the ability to dynamically
customize the memory system performance, security level, energy consumption and error handling capabilities to the requirements at hand.
How?
The MSC integrates a low-energy Flash IP with a
charge pump, enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory. An easy to use
write and erase interface is supported by an internal,
fixed-frequency oscillator and autonomous flash timing and control reduces software complexity while
not using other timer resources.
Application code may dynamically scale between
high energy optimization and high code execution
performance through advanced read modes.
A highly efficient low energy instruction cache reduces the number of flash reads significantly, thus
saving energy. Performance is also improved when
wait-states are used, since many of the wait-states
are eliminated. Built-in performance counters can be
used to measure the efficiency of the instruction
cache.
6.1 Introduction
The Memory System Controller (MSC) is the program memory unit of the EFM32 Jade Gecko microcontroller. The flash memory is
readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and
flash lock bits. There is also a read-only page in the information block containing system and device calibration data, and bootloader.
Read and write operations are supported in the energy modes EM0 Active and EM1 Sleep.
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MSC - Memory System Controller
6.2 Features
• AHB read interface
• Scalable access performance to optimize the Cortex-M3 code interface
• Zero wait-state access up to 32 MHz
• Advanced energy optimization functionality
• Conditional branch target prefetch suppression
• Cortex-M3 disfolding of if-then (IT) blocks
• Instruction Cache
• DMA read support in EM0 Active and EM1 Sleep
• Command and status interface
• Flash write and erase
• Accessible from Cortex-M3 in EM0 Active
• DMA write support in EM0 Active and EM1 Sleep
• Core clock independent Flash timing
• Internal oscillator and internal timers for precise and autonomous Flash timing
• General purpose timers are not occupied during Flash erase and write operations
• Configurable interrupt erase abort
• Improved interrupt predictability
• Memory and bus fault control
• Security features
• Lockable debug access
• Page lock bits
• SW Mass erase Lock bits
• Authentication Access Port (AAP) lock bits
• End-of-write and end-of-erase interrupts
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MSC - Memory System Controller
6.3 Functional Description
The size of the main block is device dependent. The largest size available is 256 KB (128 pages). The information block has 2048
available for user data. The information block also contains chip configuration data located in a reserved area. The main block is mapped to address 0x00000000 and the information block is mapped to address 0x0FE00000. Table 6.1 MSC Flash Memory Mapping on
page 71 outlines how the Flash is mapped in the memory space. All Flash memory is organized into 2048 pages.
Table 6.1. MSC Flash Memory Mapping
Block
Page
Base address
Write/Erase by
Main1
0
0x00000000
Software, debug Yes
.
Software reada- Purpose/Name
ble
Size
User code and data
16 KB - 256 KB
Reserved for flash expansion
~24 MB
Software, debug Yes
127
0x0003F800
Software, debug Yes
Reserved
-
0x00040000
-
Information
0
0x0FE00000
Software, debug Yes
User Data (UD)
2 KB
-
0x0FE00800
-
-
Reserved
-
1
0x0FE04000
Write: Software,
debug
Yes
Lock Bits (LB)
2 KB
-
Erase: Debug
only
1
-
0x0FE04800
-
-
Reserved
-
2
0x0FE08000
-
Yes
Device Information
(DI)
1 KB
-
0x0FE08400
-
-
Reserved
-
Reserved
-
0x0FE12800
-
-
Rest of
Reserved for
flash expansion code
space
Block/page erased by a device erase
6.3.1 User Data (UD) Page Description
This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the page is not erased by a device erase operation. The device erase
operation is described in 5.3.3 Authentication Access Point.
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MSC - Memory System Controller
6.3.2 Lock Bits (LB) Page Description
This page contains the following information:
• Main block Page Lock Words (PLWs)
• User data page Lock Word (ULWs)
• Debug Lock Word (DLW)
• Mass erase Lock Word (MLW)
• Authentication Access Port (AAP) lock word (ALW)
• Bootloader enable (CLW0)
• Pin reset soft (CLW0)
The words in this page are organized as shown in Table 6.2 Lock Bits Page Structure on page 72:
Table 6.2. Lock Bits Page Structure
127
DLW
126
ULW
125
MLW
124
ALW
122
CLW0
N
PLW[N]
…
…
1
PLW[1]
0
PLW[0]
There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW.
Thus, PLW[0] contains lock bits for page 0-31 in the main block, PLW[1] contains lock bits for page 32-63 etc. A page is locked when
the bit is 0. A locked page cannot be erased or written.
Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xF, then debug access is
enabled. Debug access to the core is disabled from power-on reset until the DLW is evaluated immediately before the Cortex-M3 starts
execution of the user application code. If the bits are not 0xF, then debug access to the core remains blocked.
Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in this word locks the Lock Bits
Page. The lock bits can be reset by a device erase operation initiated from the Authentication Access Port (AAP) registers. The AAP is
described in more detail in 5.3.3 Authentication Access Point. Note that the AAP is only accessible from the debug interface, and cannot be accessed from the Cortex-M3 core.
Word 125 is the mass erase lock word (MLW). Bit 0 locks the entire flash. The mass erase lock bits will not have any effect on device
erases initiated from the Authenitcation Access Port (AAP) registers. The AAP is described in more detail in 5.3.3 Authentication Access Point.
Word 124 is the Authentication Access Port (AAP) lock word (ALW) and the four LSBs of this word are the lock bits. If these bits are
0xF, then AAP access is enabled. If the bits are not 0xF, AAP is disabled and it is impossible to access the device through the AAP.
NOTE - locking AAP is irreversible. Once AAP is locked, it will be impossible to perform an external mass erase and AAP lock
cannot be reset. The only way to program the device when AAP is locked is through a boot loader or by SW already loaded into the
FLASH.
Word 122 is configuration word Zero. Bit[2] is the pinresetsoft bit. Bit[1] is the bootloader enable bit. .
6.3.3 Device Information (DI) Page
This read-only page holds oscillator and ADC calibration data from the production test as well as an unique device ID. The page is
further described in .
6.3.4 Bootloader
Bootloader is readable by software but not writable. The system is configured to boot from bootloader automatically after system reset.
User can bypass the bootloader by clear bit 1 in config lock word0 (CLW0) in word 122 of lockbit (LB) page.
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MSC - Memory System Controller
6.3.5 Device Revision
Family, FamilyAlt, RevMajor, RevMajorAlt, RevMinor can be accessed through ROM Table. The Revision number is extracted from the
PID2 and PID3 registers, as illustrated in Figure 6.1 Revision Number Extraction on page 73.The Rev[7:4] and Rev[3:0] must be combined to form the complete revision number Revision[7:0].
PID2 (0xE00FFFE8)
31:8
7:4
3:0
Rev[7:4]
PID3 (0xE00FFFEC)
31:8
7:4
3:0
Rev[3:0]
Figure 6.1 Revision Number Extraction
The Revision number is to be interpreted according to Table 6.3 Revision Number Interpretation on page 73.
Table 6.3. Revision Number Interpretation
Revision[7:0]
Revision
0x00
A
6.3.6 Post-reset Behavior
Calibration values are automatically written to registers by the MSC before application code startup. The values are also available to
read from the DI page for later reference by software. Other information such as the device ID and production date is also stored in the
DI page and is readable from software.
If bootloader is not bypassed, the system will boot up from the bootloader at address 0x0FE10000.
6.3.7 Flash Startup
On transitions from EM2/3 to EM0, the flash must be powered up. The time this takes depends on the current operating conditions. To
have a deterministic startup-time, set STDLY0 in MSC_STARTUP to 0x64 and clear STDLY1, ASTWAIT, STWSEN and STWS. This will
result in a 10 us delay before the flash is ready. The system will wake up before this, but the Cortex will stall on the first access to the
flash until it is ready. Execute code from RAM or cache to get a quicker startup
To get the fastest possible startup when wakeup, i.e. a startup that depends on the current operating conditions, set STDLY0 to 0x28
and set ASTWAIT in MSC_STARTUP. When configured this way, the system will poll the flash to determine when it is ready, and then
start execution.
For even quicker startup, run code in beginning with a set of wait-states. Set STDLY0 to 0x32, STDLY1 to 0x32, and set ASTWAIT and
STWSEN. Then configure STWS in MSC_STARTUP to the number of waitstates to run with. With this setup, sampling will begin with
the given number of waitstates after 5 us, and the system will run with this number of waitstates for the remaining 5 us before returning
to normal operation
A recommended setting for MSC_STARTUP register is to set STDLY0 to 0x32 for wait 5us and set ASTWAIT to one for active sampling
Set STWSEN to zero to bypass second delay period.
Flash wakeup on demand is supported when wakeup from EM2/3 to EM0. Set bit PWRUPONDEMAND of register MSC_CTRL to one
to enable the power up on demand. When enabled during powerup, flash will enter sleep mode and waiting for either pending flash
read transaction or software command to MSC_CMD.PWRUP bit. If software command wakeup, and interrupt of MSC_IF.PWRUPF will
be flaged if the MSC_IEN.PWRUPF is set
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MSC - Memory System Controller
6.3.8 Wait-states
Table 6.4. Flash Wait-States
Wait-States
Frequency
WS0
no more than 32 MHz
WS1
above 32 MHz and no more than 40 MHz
6.3.8.1 One Wait-state Access
After reset, the HFCORECLK is normally 19 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1
(one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 32 MHz. Software
must not select a zero wait-state mode unless the clock is guaranteed to be 32 MHz or below, otherwise the resulting behavior is undefined. If a HFCORECLK frequency above 32 MHz is to be set by software, the MODE field of the MSC_READCTRL register must be
set to WS1 before the core clock is switched to the higher frequency clock source.
When changing to a lower frequency, the MODE field of the MSC_READCTRL register must be set to WS0 only after the frequency
transition has completed. If the HFRCO is used, wait until the oscillator is stable on the new frequency. Otherwise, the behavior is unpredictable.
6.3.8.2 Zero Wait-state Access
At 32 MHz and below, read operations from flash may be performed without any wait-states. Zero wait-state access greatly improves
code execution performance at frequencies from 32 MHz and below. By default, the Cortex-M3 uses speculative prefetching and IfThen block folding to maximize code execution performance at the cost of additional flash accesses and energy consumption.
6.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP)
MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex-M3 conditional branch target
prefetches. Normally, the Cortex-M3 core prefetches both the next sequential instruction and the instruction at the branch target address when a conditional branch instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one
extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is taken or not. To optimize for
low energy, the MSC can be configured to cancel these speculative branch target prefetches. With this configuration, energy consumption is more optimal, as the branch target instruction fetch is delayed until the branch condition is evaluated.
The performance penalty with this mode enabled is source code dependent, but is normally less than 1% for core frequencies from 32
MHz and below. To enable the mode at frequencies from 32 MHz and below write WS0 with SCBTP to the MODE field of the
MSC_READCTRL register. For frequencies above 32 MHz, use the WS1 with SCBTP mode, and for frequencies above 40 MHz, use
the WS2 with SCBTP mode. An increased performance penalty per clock cycle must be expected compared to WS0 with SCBTP
mode. The performance penalty in WS1 with SCBTP/WS2 with SCBTP mode depends greatly on the density and organization of conditional branch instructions in the code.
6.3.10 Cortex-M3 If-Then Block Folding
The Cortex-M3 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks
are collapsed in the prefetch buffer if the condition evaluates to false. The instructions in the block then appear to execute in zero cycles. With this scheme, performance is optimized at the cost of higher energy consumption as the processor fetches more instructions
from memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary Control Register; see
the Cortex-M3 Technical Reference Manual for details. Normally, it is expected that this feature is most efficient at core frequencies
above 32 MHz. Folding is enabled by default.
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MSC - Memory System Controller
6.3.11 Instruction Cache
The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled
by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly,
thus saving energy. In most cases a cache hit-rate of more than 70 % is achievable. When a 32-bit instruction fetch hits in the cache the
data is returned to the processor in one clock cycle. Thus, performance is also improved when wait-states are used (i.e. running at
frequencies above 32 MHz).
The instruction cache is connected directly to the ICODE bus on the ARM core and functions as a memory access filter between the
processor and the memory system, as illustrated in Figure 6.2 Instruction Cache on page 75. The cache consists of an access filter,
lookup logic, SRAM, and two performance counters. The access filter checks that the address for the access is to on-chip flash memory
(instructions in RAM are not cached). If the address matches, the cache lookup logic and SRAM is enabled. Otherwise, the cache is
bypassed and the access is forwarded to the memory system. The cache is then updated when the memory access completes. The
access filter also disables cache updates for interrupt context accesses if caching in interrupt context is disabled. The performance
counters, when enabled, keep track of the number of cache hits and misses. The cachelines are filled up continuously one word at a
time as the individual words are requested by the processor. Thus, not all words of a cacheline might be valid at a given time.
Instruction Cache
ICODE
AHB-Lite Bus
Cache
Look-up Logic
Access
Filter
ICODE
AHB-Lite Bus
SRAM
CODE
Memory Space
IDCODE
AHB-Lite Bus
IDCODE
MUX
Performance Counters
ARM Core
DCODE
AHB-Lite Bus
Figure 6.2 Instruction Cache
By default, the instruction cache is automatically invalidated when the contents of the flash is changed (i.e. written or erased). In many
cases, however, the application only makes changes to data in the flash, not code. In this case, the automatic invalidate feature can be
disabled by setting AIDIS in MSC_READCTRL. The cache can (independent of the AIDIS setting) be manually invalidated by writing 1
to INVCACHE in MSC_CMD.
In general it is highly recommended to keep the cache enabled all the time. However, for some sections of code with very low cache hitrate more energy-efficient execution can be achieved by disabling the cache temporarily. To measure the hit-rate of a code-section, the
built-in performance counters can be used. Before the section, start the performance counters by writing 1 to STARTPC in MSC_CMD.
This starts the performance counters, counting from 0. At the end of the section, stop the performance counters by writing 1 to
STOPPC in MSC_CMD. The number of cache hits and cache misses for that section can then be read from MSC_CACHEHITS and
MSC_CACHEMISSES respectively. The total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES.
Thus, the cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES). When MSC_CACHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES overflows the CMOF interrupt flag is set. These flags
must be cleared explicitly by software. The range of the performance counters can thus be extended by increasing a counter in the
MSC interrupt routine. The performance counters only count when a cache lookup is performed. If the lookup fails, MSC_CACHEMISSES is increased. If the lookup is successful, MSC_CACHEHITS is increased. For example, a cache lookup is not performed if the cache
is disabled or the code is executed from RAM. When caching of vector fetches and instructions in interrupt routines is disabled (ICCDIS
in MSC_READCTRL is set), the performance counters do not count when these types of fetches occur (i.e. while in interrupt context).
By default, interrupt vector fetches and instructions in interrupt routines are also cached. Some applications may get better cache utilization by not caching instructions in interrupt context. This is done by setting ICCDIS in MSC_READCTRL. You should only set this bit
based on the results from a cache hit ratio measurement. In general, it is recommended to keep the ICCDIS bit cleared. Note that lookups in the cache are still performed, regardless of the ICCDIS setting - but instructions are not cached when cache misses occur inside
the interrupt routine. So, for example, if a cached function is called from the interrupt routine, the instructions for that function will be
taken from the cache.
The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in
MSC_READCTRL when entering these energy modes. Applications that switch frequently between EM0 and EM2/3 and executes the
very same non-looping code almost every time will most likely benefit from putting this code in RAM. The interrupt vectors can also be
put in RAM to reduce current consumption even further.
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MSC - Memory System Controller
6.3.12 Erase and Write Operations
The minimal frequency of system clock for flash write and erase operations is 500 KHz.
Both page erase and write operations require that the address is written into the MSC_ADDRB register. For erase operations, the address may be any within the page to be erased. Load the address by writing 1 to the LADDRIM bit in the MSC_WRITECMD register.
The LADDRIM bit only has to be written once when loading the first address. After each word is written the internal address register
ADDR will be incremented automatically by 4. The INVADDR bit of the MSC_STATUS register is set if the loaded address is outside the
flash and the LOCKED bit of the MSC_STATUS register is set if the page addressed is locked. Any attempts to command erase of or
write to the page are ignored if INVADDR or the LOCKED bits of the MSC_STATUS register are set. To abort an ongoing erase, set the
ERASEABORT bit in the MSC_WRITECMD register.
When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS register is cleared. When this status
bit is set, software or DMA may write the next word.
A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register. The operation is complete when
the BUSY bit of the MSC_STATUS register is cleared and control of the flash is handed back to the AHB interface, allowing application
code to resume execution.
For a DMA write the software must write the first word to the MSC_WDATA register and then set the WRITETRIG bit of the
MSC_WRITECMD register. DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set.
It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed. Let us take as an example
writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the same flash word this method can be used:
• Write 0xFFFFAAAA (word in flash becomes 0xFFFFAAAA)
• Write 0x5555FFFF (word in flash becomes 0x5555AAAA)
Note that there is a maximum of two writes to the same word between each erase due to a physical limitation of the flash.
Note:
During a write or erase, flash read accesses will be stalled, effectively halting code execution from flash. Code execution continues
upon write/erase completion. Code residing in RAM may be executed during a write/erase operation.
6.3.12.1 Mass erase
A mass erase can be initiated from software using ERASEMAIN0 MSC_WRITECMD. This command will start a mass erase of the entire flash. Prior to initiating a mass erase, MSC_MASSLOCK must be unlocked by writing 0x631A to it. After a mass erase has been
started, this register can be locked again to prevent runaway code from accidentally triggering a mass erase.
The regular flash page lock bits will not prevent a mass erase. To prevent software from initiating mass erases, use the mass erase lock
bits in the mass erase lock word (MLW).
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MSC - Memory System Controller
6.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
MSC_CTRL
RW
Memory System Control Register
0x004
MSC_READCTRL
RWH
Read Control Register
0x008
MSC_WRITECTRL
RW
Write Control Register
0x00C
MSC_WRITECMD
W1
Write Command Register
0x010
MSC_ADDRB
RW
Page Erase/Write Address Buffer
0x018
MSC_WDATA
RW
Write Data Register
0x01C
MSC_STATUS
R
Status Register
0x030
MSC_IF
R
Interrupt Flag Register
0x034
MSC_IFS
W1
Interrupt Flag Set Register
0x038
MSC_IFC
(R)W1
Interrupt Flag Clear Register
0x03C
MSC_IEN
RW
Interrupt Enable Register
0x040
MSC_LOCK
RWH
Configuration Lock Register
0x044
MSC_CACHECMD
W1
Flash Cache Command Register
0x048
MSC_CACHEHITS
R
Cache Hits Performance Counter
0x04C
MSC_CACHEMISSES
R
Cache Misses Performance Counter
0x054
MSC_MASSLOCK
RWH
Mass Erase Lock Register
0x05C
MSC_STARTUP
RW
Startup Control
0x074
MSC_CMD
W1
Command Register
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MSC - Memory System Controller
6.5 Register Description
6.5.1 MSC_CTRL - Memory System Control Register
2
1
RW 0
RW 1
CLKDISFAULTEN
ADDRFAULTEN
Name
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
IFCREADCLEAR
0
RW
0
3
IFCREADCLEAR
Access
RW 0
Reset
PWRUPONDEMAND RW 0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
Description
IFC Read Clears IF
This bit controls what happens when an IFC register in a module is read.
2
Value
Description
0
IFC register reads 0. No side-effect when reading.
1
IFC register reads the same value as IF, and the corresponding interrupt flags are cleared.
PWRUPONDEMAND 0
RW
Power Up On Demand During Wake Up
When set, during wake up, pending AHB transfer will cause IMEM to issue power up request to CMU. If not set, will always
issue power up request if PWRUPONCMD is not set either.
1
CLKDISFAULTEN
0
RW
Clock-disabled Bus Fault Response Enable
When this bit is set, busfaults are generated on accesses to peripherals/system devices with clocks disabled
0
ADDRFAULTEN
1
RW
Invalid Address Bus Fault Response Enable
When this bit is set, busfaults are generated on accesses to unmapped parts of system and code address space
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MSC - Memory System Controller
6.5.2 MSC_READCTRL - Read Control Register
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0
1
2
3
0
RW
IFCDIS
4
0
RW
AIDIS
5
0
RW
ICCDIS
6
7
8
1
RW
PREFETCH
9
0
RW
USEHPROT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RWH 0x1
MODE
26
27
28
RW
Name
Reset
0
Access
SCBTP
29
30
0x004
Bit Position
31
Offset
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EFM32JG1 Reference Manual
MSC - Memory System Controller
Bit
Name
Reset
Access
31:29
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
28
SCBTP
0
RW
Description
Suppress Conditional Branch Target Perfetch
Enable suppressed Conditional Branch Target Prefetch (SCBTP) function. SCBTP saves energy by delaying Cortex-M4
conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction
reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction
fetch is saved for each branch not taken, with a negligible performance penalty.
27:26
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
25:24
MODE
0x1
RWH
Read Mode
After reset, the core clock is 19 MHz from the HFRCO and the MODE field of MSC_READCTRL register is set to WS1. The
reset value is WS1 because the HFRCO may produce a frequency above 19 MHz before it is calibrated. A large wait states
is associated with high frequency. When changing to a higher frequency, this register must be set to a large wait states first
before the core clock is switched to the higher frequency. When changing to a lower frequency, this register should be set
to lower wait states after the frequency transition has been completed. If the HFRCO is used as clock source, wait until the
oscillator is stable on the new frequency to avoid unpredictable behavior.See Flash Wait-States table for the corresponding
threshold for different wait-states.
Value
Mode
Description
0
WS0
Zero wait-states inserted in fetch or read transfers
1
WS1
One wait-state inserted for each fetch or read transfer. See Flash WaitStates table for details
23:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9
USEHPROT
0
RW
AHB_HPROT Mode
Use ahb_hrpot to determine if the instruction is cacheable or not
8
PREFETCH
1
RW
Prefetch Mode
Set to configure level of prefetching.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ICCDIS
0
RW
Interrupt Context Cache Disable
Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will
still be performed in interrupt context. When set, the performance counters will not count when these types of fetches occur.
4
AIDIS
0
RW
Automatic Invalidate Disable
When this bit is set the cache is not automatically invalidated when a write or page erase is performed.
3
IFCDIS
0
RW
Internal Flash Cache Disable
Disable instruction cache for internal flash memory.
2:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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MSC - Memory System Controller
6.5.3 MSC_WRITECTRL - Write Control Register
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
IRQERASEABORT
0
RW
0
RW 0
2
WREN
Name
1
Access
IRQERASEABORT RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Description
Abort Page Erase on Interrupt
When this bit is set to 1, any Cortex-M4 interrupt aborts any current page erase operation. Executing that interrupt vector
from Flash will halt the CPU.
0
WREN
0
RW
Enable Write/Erase Controller
When this bit is set, the MSC write and erase functionality is enabled
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MSC - Memory System Controller
6.5.4 MSC_WRITECMD - Write Command Register
Access
W1 0
W1 0
ERASEPAGE
LADDRIM
31:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12
CLEARWDATA
0
W1
0
W1 0
WRITEEND
Reset
1
W1 0
WRITEONCE
Name
2
4
W1 0
WRITETRIG
Bit
3
5
6
7
8
ERASEABORT W1 0
Name
W1 0
Access
ERASEMAIN0
9
10
11
CLEARWDATA W1 0
Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Description
Clear WDATA state
Will set WDATAREADY and DMA request. Should only be used when no write is active.
11:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8
ERASEMAIN0
0
W1
Mass erase region 0
Initiate mass erase of region 0. Before use MSC_MASSLOCK must be unlocked. To completely prevent access from software, clear bit 0 in the mass erase lock-word (MLW)
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ERASEABORT
0
W1
Abort erase sequence
Writing to this bit will abort an ongoing erase sequence.
4
WRITETRIG
0
W1
Word Write Sequence Trigger
Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30us
timeout. When ADDR is incremented past the page boundary, ADDR is set to the base of the page. If WDOUBLE is set,
two words are required every time, and ADDR is incremented by 8.
3
WRITEONCE
0
W1
Word Write-Once Trigger
Write the word in MSC_WDATA to ADDR. Flash access is returned to the AHB interface as soon as the write operation
completes. The WREN bit in the MSC_WRITECTRL register must be set in order to use this command. Only a single word
is written, but the internal address is also incremented to allow a direct write of a new word without loading a new address
2
WRITEEND
0
W1
End Write Mode
Write 1 to end write mode when using the WRITETRIG command.
1
ERASEPAGE
0
W1
Erase Page
Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must
be set in order to use this command.
0
LADDRIM
0
W1
Load MSC_ADDRB into ADDR
Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incremented automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to
the base of the page.
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MSC - Memory System Controller
6.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADDRB RW 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
ADDRB
0x00000000
RW
Page Erase or Write Address Buffer
This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR
register when the LADDRIM field in MSC_CMD is set.
6.5.6 MSC_WDATA - Write Data Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
WDATA RW 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
WDATA
0x00000000
RW
Write Data
The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of
MSC_STATUS is set.
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MSC - Memory System Controller
6.5.7 MSC_STATUS - Status Register
Access
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
PCRUNNING
0
0
0
R
1
BUSY
31:7
0
2
R
Reset
R
3
LOCKED
Name
0
R
Bit
1
R
WDATAREADY
INVADDR
4
0
R
5
WORDTIMEOUT
Name
0
PCRUNNING
R
Access
ERASEABORTED R
0
Reset
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Description
Performance Counters Running
This bit is set while the performance counters are running. When one performance counter reaches the maximum value,
this bit is cleared.
5
ERASEABORTED
0
R
The Current Flash Erase Operation Aborted
When set, the current erase operation was aborted by interrupt.
4
WORDTIMEOUT
0
R
Flash Write Word Timeout
When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the
flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands
in MSC_WRITECMD are triggered.
3
WDATAREADY
1
R
WDATA Write Ready
When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated
with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.
2
INVADDR
0
R
Invalid Write Address or Erase Page
Set when software attempts to load an invalid (unmapped) address into ADDR
1
LOCKED
0
R
Access Locked
When set, the last erase or write is aborted due to erase/write access constraints
0
BUSY
0
R
Erase/Write Busy
When set, an erase or write operation is in progress and new commands are ignored
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MSC - Memory System Controller
6.5.8 MSC_IF - Interrupt Flag Register
Access
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ICACHERR
0
0
0
R
1
ERASE
31:6
0
2
R
Reset
R
3
WRITE
Name
0
R
CHOF
Bit
0
R
CMOF
4
0
R
5
PWRUPF
Name
0
Access
ICACHERR R
Reset
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Description
iCache RAM Parity Error Flag
If one, iCache RAM parity Error detected
4
PWRUPF
0
R
Flash Power Up Sequence Complete Flag
Set after MSC_CMD.PWRUP received, flash powered up complete and ready for read/write
3
CMOF
0
R
Cache Misses Overflow Interrupt Flag
Set when MSC_CACHEMISSES overflows
2
CHOF
0
R
Cache Hits Overflow Interrupt Flag
Set when MSC_CACHEHITS overflows
1
WRITE
0
R
Write Done Interrupt Read Flag
R
Erase Done Interrupt Read Flag
Set when a write is done
0
ERASE
0
Set when erase is done
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MSC - Memory System Controller
6.5.9 MSC_IFS - Interrupt Flag Set Register
Access
W1 0
ERASE
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ICACHERR
0
W1
0
W1 0
WRITE
Reset
1
W1 0
CHOF
Name
2
W1 0
CMOF
Bit
3
4
W1 0
6
7
8
9
PWRUPF
Name
5
Access
ICACHERR W1 0
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
Description
Set ICACHERR Interrupt Flag
Write 1 to set the ICACHERR interrupt flag
4
PWRUPF
0
W1
Set PWRUPF Interrupt Flag
Write 1 to set the PWRUPF interrupt flag
3
CMOF
0
W1
Set CMOF Interrupt Flag
W1
Set CHOF Interrupt Flag
W1
Set WRITE Interrupt Flag
W1
Set ERASE Interrupt Flag
Write 1 to set the CMOF interrupt flag
2
CHOF
0
Write 1 to set the CHOF interrupt flag
1
WRITE
0
Write 1 to set the WRITE interrupt flag
0
ERASE
0
Write 1 to set the ERASE interrupt flag
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MSC - Memory System Controller
6.5.10 MSC_IFC - Interrupt Flag Clear Register
Access
(R)W1 0
ERASE
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ICACHERR
0
(R)W1
0
(R)W1 0
WRITE
Reset
1
(R)W1 0
CHOF
Name
2
(R)W1 0
CMOF
Bit
3
4
(R)W1 0
6
7
8
PWRUPF
Name
5
Access
ICACHERR (R)W1 0
Reset
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x038
Bit Position
31
Offset
Description
Clear ICACHERR Interrupt Flag
Write 1 to clear the ICACHERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
4
PWRUPF
0
(R)W1
Clear PWRUPF Interrupt Flag
Write 1 to clear the PWRUPF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
3
CMOF
0
(R)W1
Clear CMOF Interrupt Flag
Write 1 to clear the CMOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
2
CHOF
0
(R)W1
Clear CHOF Interrupt Flag
Write 1 to clear the CHOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
1
WRITE
0
(R)W1
Clear WRITE Interrupt Flag
Write 1 to clear the WRITE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
0
ERASE
0
(R)W1
Clear ERASE Interrupt Flag
Write 1 to clear the ERASE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
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MSC - Memory System Controller
6.5.11 MSC_IEN - Interrupt Enable Register
Access
RW 0
ERASE
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ICACHERR
0
RW
0
RW 0
WRITE
Reset
1
RW 0
CHOF
Name
2
RW 0
CMOF
Bit
3
4
RW 0
6
7
8
9
PWRUPF
Name
5
Access
ICACHERR RW 0
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Description
ICACHERR Interrupt Enable
Enable/disable the ICACHERR interrupt
4
PWRUPF
0
RW
PWRUPF Interrupt Enable
RW
CMOF Interrupt Enable
RW
CHOF Interrupt Enable
RW
WRITE Interrupt Enable
RW
ERASE Interrupt Enable
Enable/disable the PWRUPF interrupt
3
CMOF
0
Enable/disable the CMOF interrupt
2
CHOF
0
Enable/disable the CHOF interrupt
1
WRITE
0
Enable/disable the WRITE interrupt
0
ERASE
0
Enable/disable the ERASE interrupt
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MSC - Memory System Controller
6.5.12 MSC_LOCK - Configuration Lock Register
0
1
2
3
4
5
6
7
8
LOCKKEY RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0000
RWH
Description
Configuration Lock
Write any other value than the unlock code to lock access to MSC_CTRL, MSC_READCTRL, MSC_WRITECMD,
MSC_STARTUP and MSC_AAPUNLOCKCMD. Write the unlock code to enable access. When reading the register, bit 0 is
set when the lock is enabled.
Mode
Value
Description
UNLOCKED
0
MSC registers are unlocked
LOCKED
1
MSC registers are locked
LOCK
0
Lock MSC registers
UNLOCK
0x1B71
Unlock MSC registers
Read Operation
Write Operation
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MSC - Memory System Controller
6.5.13 MSC_CACHECMD - Flash Cache Command Register
Reset
Access
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
STOPPC
0
W1
0
1
W1 0
INVCACHE W1 0
Name
0
Bit
STARTPC
Name
1
2
3
W1 0
Access
STOPPC
Reset
2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Description
Stop Performance Counters
Use this commant bit to stop the performance counters.
1
STARTPC
0
W1
Start Performance Counters
Use this command bit to start the performance counters. The performance counters always start counting from 0.
0
INVCACHE
0
W1
Invalidate Instruction Cache
Use this register to invalidate the instruction cache.
6.5.14 MSC_CACHEHITS - Cache Hits Performance Counter
3
4
5
6
7
8
9
10
0x00000
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x048
Bit Position
31
Offset
Reset
CACHEHITS R
Access
Name
Bit
Name
Reset
Access
31:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:0
CACHEHITS
0x00000
R
Description
Cache hits since last performance counter start command.
Use to measure cache performance for a particular code section.
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MSC - Memory System Controller
6.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter
1
0
1
0
2
3
4
5
6
7
8
9
10
0x00000
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x04C
Bit Position
31
Offset
Reset
CACHEMISSES R
Access
Name
Bit
Name
Reset
Access
31:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:0
CACHEMISSES
0x00000
R
Description
Cache misses since last performance counter start command.
Use to measure cache performance for a particular code section.
6.5.16 MSC_MASSLOCK - Mass Erase Lock Register
2
3
4
5
6
7
8
LOCKKEY RWH 0x0001
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x054
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0001
RWH
Description
Mass Erase Lock
Write any other value than the unlock code to lock access the the ERASEMAINn commands. Write the unlock code 631A to
enable access. When reading the register, bit 0 is set when the lock is enabled. Locked by default
Mode
Value
Description
UNLOCKED
0
Mass erase unlocked
LOCKED
1
Mass erase locked
LOCK
0
Lock mass erase
UNLOCK
0x631A
Unlock mass erase
Read Operation
Write Operation
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MSC - Memory System Controller
6.5.17 MSC_STARTUP - Startup Control
Bit
Name
Reset
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
30:28
STWS
0x1
RW
0
1
2
3
4
5
RW 0x04D
STDLY0
STDLY1
Access
6
7
8
9
10
11
12
13
14
15
16
17
RW 0x001
18
19
20
21
22
23
24
1
RW
ASTWAIT
25
1
RW
27
26
STWSEN
STWS
Name
0
Access
STWSAEN RW
RW
Reset
28
29
30
0x1
0x05C
Bit Position
31
Offset
Description
Startup Waitstates
Active wait for flash startup startup after SDLY0
27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26
STWSAEN
0
RW
Startup Waitstates Always Enable
Use the number of waitstates given by STWS during startup always
25
STWSEN
1
RW
Startup Waitstates Enable
Use the number of waitstates given by STWS during startup. During the optional STDLY1 timout
24
ASTWAIT
1
RW
Active Startup Wait
Active wait for flash startup startup after SDLY0
23:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:12
STDLY1
0x001
RW
Startup Delay 0
Number of cycles with startup waitstates, and also the maximum number of cycles startup sampling will be attempted before starting up system
11:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:0
STDLY0
0x04D
RW
Startup Delay 0
Number of idle cycles from exiting sleep mode
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MSC - Memory System Controller
6.5.18 MSC_CMD - Command Register
0
1
2
PWRUP W1 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x074
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
PWRUP
0
W1
Description
Flash Power Up Command
Write to this bit to power up the Flash. IRQ PWRUPF will be fired when power up sequence completed
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LDMA - Linked DMA Controller
7. LDMA - Linked DMA Controller
Quick Facts
What?
0 1 2 3
4
The LDMA controller can move data without CPU intervention, effectively reducing the energy consumption for a data transfer.
Why?
Flash
RAM
DMA
controller
External Bus
Interface
Peripherals
The LDMA can perform data transfers more energy
efficiently than the CPU and allows autonomous operation in low energy modes. For example the
LEUART can provide full UART communication in
EM2 DeepSleep, consuming only a few µA by using
the LDMA to move data between the LEUART and
RAM.
How?
The LDMA controller has multiple highly configurable, prioritized DMA channels. A linked list of flexible
descriptors makes it possible to tailor the controller
to the specific needs of an application.
7.1 Introduction
The Linked Direct Memory Access (LDMA) controller performs memory transfer operations independently of the CPU. This has the
benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes while
still routing data to memory and peripherals. For example, moving data from the LEUART to memory or memory to LEUART. Each of
the DMA channels on the EFM32 can be connected to any of the EFM32 peripherals.
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LDMA - Linked DMA Controller
7.1.1 Features
• Flexible Source and Destination transfers
• Memory-to-memory
• Memory-to-peripheral
• Peripheral-to-memory
• Peripheral-to-peripheral
• DMA transfers triggered by peripherals, software, or linked list
• Single or multiple data transfers for each peripheral or software request
• Inter-channel and hardware event synchronization via trigger and wait functions
• Supports single or multiple descriptors
• Single descriptor
• Linked list of descriptors
• Circular and ping-pong buffers
• Scatter-Gather
• Looping
• Pause and restart triggered by other channels
• Sophisticated flow control which can function without CPU interaction
• Channel arbitration includes:
• Fixed priority
• Simple round robin
• Round robin with programmable multiple interleaved entries for higher priority requesters
• Programmable data size and source and destination address strides
• Programmable interrupt generation at the end of each DMA descriptor execution
• Little-endian/big-endian conversion
• DMA write-immediate function
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LDMA - Linked DMA Controller
7.2 Block Diagram
An overview of the LDMA and the modules it interacts with is shown in Figure 7.1 LDMA Block Diagram on page 96.
Cortex
AHB
RAM
Interrupts
Error
LDMA Core
Channel
done
Channel 0
Peripheral
Channel 1
Peripheral
Channel
select
Descriptor A
ACK/
REQ
Channel N
Peripheral
Descriptor B
Descriptor C
Peripheral
LDMA
Figure 7.1 LDMA Block Diagram
The Linked DMA Controller consists of three main parts
• A DMA core that executes transers and communicates status to the core
• A channel select block that routes peripheral DMA requests and acknowledge signals to the DMA
• A set of internal channel configuration registers for tracking the progres of each DMA channel
The DMA has acces to all system memory through the AHB bus and the AHB->APB bridge. It can load channel descriptors from memory with no CPU intervention.
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LDMA - Linked DMA Controller
7.3 Functional Description
The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement
from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of
data or avoiding frequent interrupts to service peripherals needing more data or having available data. It can also be used to reduce the
system energy consumption by making the LDMA work autonomously with EM2 peripherals for data transfer in EM2 DeepSleep without
having to wake up the processor core from sleep.
The Linked DMA Controller has 8 independent channels. Each of these channels can be connected to any of the available peripheral
DMA transfer request input sources by writing to the channel configuration registers, see 7.3.2 Channel Configuration. In addition, each
channel can also be triggered directly by software, which is useful for memory-to-memory transfers.
The channel descriptors determine what the Linked DMA Controller will do when it receives DMA transfer request. The initial descriptor
is written directly to the LDMA's channel registers. If desired, the initial descriptor can link to additional linked descriptors stored in memory (RAM or Flash). Alternatively, software may also load the initial descriptor by writing the descriptor address to the LDMA_CHx_LINK
register and then setting the corresponding bit the LDMA_LINKLOAD register.
Before enabling a channel, the software must take care to properly configure the channel registers including the link address and any
linked descriptors. When a channel is triggered, the Linked DMA Controller will perform the memory transfers as specified by the descriptors. A descriptor contains the memory address to read from, the memory address to write to, link address of the next descriptor,
the number of bytes to be transferred, etc. The channel descriptor is described in detail in 7.3.7 Channel descriptor data structure.
The Linked DMA Controller supports both fixed priority and round robin arbitration. The number of fixed and round robin channels is
programmable. For round robin channels, the number of arbitration slots requested for each channel is programmable. Using this
scheme, it is possible to ensure that timing-critical transfers are serviced on time.
DMA transfers take place by reading a block of data at a time from the source, storing it in the LDMA’s local FIFO, then writing the block
out to the destination from the FIFO. Interrupts may optionally be signaled to the CPU’s interrupt controller at the end of any DMA transfer or at the completion of a descriptor if the DONEIFSEN bit is set. An AHB error will always generate an interrupt.
7.3.1 Channel Descriptor
Each DMA channel has descriptor registers. A transfer can be initialized by software writing to the registers or by the DMA itself copying
a descriptor from RAM to memory. When using a linked list of descriptors the first descriptor should be initialized by the CPU. The DMA
itself will then copy linked descriptors to its descriptor registers as required. In addition to manually initializing the first transfer, software
may also cause the LDMA to load the initial descriptor by writing the descriptor address to the LDMA_CHx_LINK register and then setting the corresponding bit the LDMA_LINKLOAD register.
The contents of the descriptor registers are dynamically updated during the DMA transfer. The contents of descriptors in memory are
not edited by the controller.
Some descriptor field values are only used for linked descriptors. For example, the SRCMODE and DSTMODE bits of the
LDMA_CHx_CTRL registers determine if a linked descriptor is using relative or absolute addressing. Software writes to the address
registers will always use absolute addressing and never set these bits. Therefore, these bits are read only.
7.3.1.1 DMA Transfer Size
A DMA transfer is the smallest unit of data that can be transfered by the LDMA. The LDMA supports byte, half-word and word sized
transfers. The SIZE field in the LDMA_CHx_CTRL register specifies the data width of one DMA transfer.
7.3.1.2 Source/Destination Increments
The SRCINC and DSTINC in the LDMA_CHx_CTRL register determines the increment between DMA transfers. The increment is in
units of DMA transfers and using an increment size of 1 will transfer contiguous bytes, half-words, or words depending on the value of
the SIZE field. Multiple unit increments are useful for transferring or packing/unpacking alligned data. For example using an increment
of 4 with a size of BYTE will transfer word aligned bytes. An increment of 2 units witha size of HALFWORD is suitable for the transfer of
word aligned half-word data. The LDMA can pack also pack or unpack data by using a different increment size for source and destination. For example - to convert from word aligned byte data (unpacked) to contigous byte data (packed), set the SIZE to BYTE, SRCINC
to 4, and DSTINC to 1.
SIZE may also be set to NONE which will cause the LDMA to read or write the same location for every DMA transfer. This is usfull for
accessing peripheral FIFO or data registers.
7.3.1.3 Block Size
The block size defines the amount of data transferred in one arbitration. It consists of one or more DMA transfers. See 7.3.6.1 Arbitration Priority for more details.
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LDMA - Linked DMA Controller
7.3.1.4 Transfer Count
The descriptor transfer count defines how many DMA transfers to perform. The number of bytes transferred by the descripter will depend on both the transfer count XFERCNT and the SIZE field settings. TOTAL_BYTES = XFERCNT * SIZE
7.3.1.5 Descriptor List
A descriptor list consists of one or more descriptors which are executed in serially. This list may be a simple sequence of descriptors, a
loop of descriptors, or a combination of the two.
Each descriptor in the list can be one of several types.
• Single Transfer descriptor: Transfers TOTAL_BYTES of data and then stops.
• Linked Transfer descriptor: Transfers TOTAL_BYTES of data and then loads the next linked descriptor.
• Loop Transfer descriptor: Transfers TOTAL_BYTES of data and performs loop control (see 7.3.2.2 Loop Counter).
• Sync descriptor: Handle synchronization of the list with other enteties (see 7.3.7.2 SYNC descriptor structure).
• WRI descriptor: Writes a value to a location in memory (see 7.3.7.3 WRI descriptor structure).
7.3.1.6 Addresses
Before initiating a transfer, software should write the source address, destination address, and if applicable the link address to the descriptor registers. Alternatively, software may load a descriptor from memory by writing the descriptor address to the LDMA_CHx_LINK
register and setting the corresponding bit in the LDMA_LINKLOAD register.
During a DMA transfer, the DMA source and destination address registers are pointers to the next transfer address. The LDMA will
update the SRC and DST addresses after each transfer. If software halts a DMA transfer by clearing the enable bit, the SRC and DST
addresses will indicate the next transfer address.
When a desriptor is finished the DMA will either halt or load the next (linked) descriptor depending on the value of the LINK field in the
LDMA_Chx_LINK register. After loading a linked descriptor, the descriptor registers will reflect the content of the loaded descriptor. Note
that the linked descriptor must be word aligned in memory. The two least significant bits of the LDMA_CHx_LINK register are used by
the LINK and LINKMODE bits. The two least significant bits of the link address are always zero.
7.3.1.7 Addressing Modes
The DMA descriptors support absolute addressing or relative addressing. When using relative addressing, the offset is relative to the
current contents of the respective address registers. Regardless of the descriptor addressing modes, the address registers always indicate the absolute address. For example, when loading a descriptor using relative SRC addressing, the LDMA will add the descriptor
source address (offset) to the contents of the SRCADDR register (base address). After loading, the SRCADDR register will indicate the
absolute address of the loaded descriptor.
The initial descriptor must use absolute addressing. The LDMA will ignore the DSTMODE, SRCMODE, and LINKMODE bits for the
initial descriptor and interpret the addresses as an absolute addresses.
Relative addressing is most useful for the link address. The initial descriptor will indicate the absolute address of the linked descriptors
in memory. The linked descriptors might be an array of structures. In this case the offset between descriptors is constant and is always
16 bytes. The LINK address is not incremented or decremented after each transfer. Thus, a relative offset of 0x10 may be used for all
linked descriptors.
The source and destination addresses also support relative addressing. When using relative addressing with the source or destination
address registers, the LDMA adds the relative offset to the current contents of the respective address register. Since the source and
destination addresses are normally incremented after each transfer, the final address will point to one unit past the last transfer. Thus,
an offset of zero will give the next sequential data address.
See the example 7.4.6 2D Copy for an common use of releative addressing.
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LDMA - Linked DMA Controller
7.3.1.8 Byte Swap
Enabling byte swap reverses the endianess of the incoming source data read into the LDMA’s FIFO. Byte swap is only valid for transfer
sizes of word and half-word. Note that linked structure reads are not byte swapped.
B3b7
B3
B3b0
B2b7
B2
B2b0
B1b7
B1
B1b0
B0b7
B2b0
B3b7
B1b0
B0b7
B0b0
B1b7
B0
B0b0
BYTESWAP=1
SIZE=WORD
B0b7
B3b7
B0
B0b0
B1b7
B3b0
B2b7
B1
B1b0
B2b7
B2b0
B1b7
B2
B1
B3
B0
B3b0
B0b0
BYTESWAP=1
SIZE=HALF
B2b7
B2b0
B3b7
B3b0
B0b7
B0
B1
B1b0
Figure 7.2 Word and Half-Word Endian Byte Swap Examples
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LDMA - Linked DMA Controller
7.3.1.9 DMA Size and Source/Destination Increment Programming
The DMA channels’ SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means
for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The
following figure shows how 32-bit words of data are read from a memory source into the DMA’s internal transfer FIFO, and then written
out to the memory destination. The memory organization in bytes is shown as well as the first read to and write from the DMA’s FIFO.
source
0x200
destination
0x400
kB3
lB3
mB3
nB3
oB3
pB3
qB3
rB3
sB3
tB3
uB3
vB3
wB3
xB3
yB3
zB3
Memory
kB2
kB1
lB2
lB1
mB2 mB1
nB2
nB1
oB2
oB1
pB2
pB1
qB2
qB1
rB2
rB1
sB2
sB1
tB2
tB1
uB2
uB1
vB2
vB1
wB2 wB1
xB2
xB1
yB2
yB1
zB2
zB1
kB0
lB0
mB0
nB0
oB0
pB0
qB0
rB0
sB0
tB0
uB0
vB0
wB0
xB0
yB0
zB0
kB3
lB3
mB3
kB2
lB2
mB2
kB0
lB0
mB0
kB1
lB1
mB1
First read transmit data=
kB3
kB2
kB1
kB0
Next read data=
oB3 opB2
oB1
oB0
DMA Controller FIFO
kB3
lB3
mB3
nB3
Next write data=
nB3
nB2
kB2
lB2
mB2
nB2
nB1
kB1
lB1
mB1
nB1
kB0
lB0
mB0
nB0
nB0
First write transmit data=
kB3
kB2
kB1
kB0
size[1:0] = WORD
src_inc[1:0 ]= WORD
dst_inc[1:0 ]= WORD
Figure 7.3 Memory-to-Memory Transfer WORD Size Example
The next example shows four variations of half-word sized transfers, with all possible combinations of half- and full-word source and
destination increments. Note that when the size and source/destination increments are all configured for half-word, the resulting DMA
transfer organization is equivalent to the full-word sized transfer in the previous example. The difference is that the half-word configuration requires twice as many DMA transfers.
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LDMA - Linked DMA Controller
source
0x200
destination
0x400
kB3
lB3
mB3
nB3
oB3
pB3
qB3
rB3
sB3
tB3
uB3
vB3
wB3
xB3
yB3
zB3
Memory
kB2
kB1
lB2
lB1
mB2 mB1
nB2
nB1
oB2
oB1
pB2
pB1
qB2
qB1
rB2
rB1
sB2
sB1
tB2
tB1
uB2
uB1
vB2
vB1
wB2 wB1
xB2
xB1
yB2
yB1
zB2
zB1
kB0
lB0
mB0
nB0
oB0
pB0
qB0
rB0
sB0
tB0
uB0
vB0
wB0
xB0
yB0
zB0
kB3
lB3
mB3
nB3
kB2
lB2
mB2
nB2
kB0
lB0
mB0
nB0
kB1
lB1
mB1
nB1
source
0x200
First read transmit data=
kB1
kB0
DMA Controller FIFO
kB3
lB3
mB3
nB3
kB2
lB2
mB2
nB2
kB1
lB1
mB1
nB1
kB0
lB0
mB0
nB0
kB3
lB3
mB3
nB3
oB3
pB3
qB3
rB3
sB3
tB3
uB3
vB3
wB3
xB3
yB3
zB3
destination
0x400
First write transmit data=
kB1
kB0
Memory
kB2
kB1
lB2
lB1
mB2 mB1
nB2
nB1
oB2
oB1
pB2
pB1
qB2
qB1
rB2
rB1
sB2
sB1
tB2
tB1
uB2
uB1
vB2
vB1
wB2 wB1
xB2
xB1
yB2
yB1
zB2
zB1
kB0
lB0
mB0
nB0
oB0
pB0
qB0
rB0
sB0
tB0
uB0
vB0
wB0
xB0
yB0
zB0
kB1
lB1
mB1
nB1
oB1
pB1
qB1
rB1
kB0
lB0
mB0
nB0
oB0
pB0
qB0
rB0
First read transmit data=
kB1
kB0
DMA Controller FIFO
lB1
lB0
kB1
kB0
nB1
nB0 mB1 mB0
pB1
pB0
oB1
oB0
rB1
rB0
qB1
qB0
First write transmit data=
kB1
kB0
size[1:0] = HALF
src_inc[1:0] = WORD
dst_inc[1:0] = WORD
size[1:0] = HALF
src_inc[1:0] = HALF
dst_inc[1:0] = HALF
source
0x200
destination
0x400
kB3
lB3
mB3
nB3
oB3
pB3
qB3
rB3
sB3
tB3
uB3
vB3
wB3
xB3
yB3
zB3
Memory
kB2
kB1
lB2
lB1
mB2 mB1
nB2
nB1
oB2
oB1
pB2
pB1
qB2
qB1
rB2
rB1
sB2
sB1
tB2
tB1
uB2
uB1
vB2
vB1
wB2 wB1
xB2
xB1
yB2
yB1
zB2
zB1
kB0
lB0
mB0
nB0
oB0
pB0
qB0
rB0
sB0
tB0
uB0
vB0
wB0
xB0
yB0
zB0
lB1
nB1
pB1
rB1
lB0
nB0
pB0
rB0
kB0
mB0
oB0
qB0
kB1
mB1
oB1
qB1
source
0x200
First read transmit data=
kB1
kB0
DMA Controller FIFO
lB1
nB1
pB1
rB1
lB0
nB0
pB0
rB0
kB1
mB1
oB1
qB1
kB0
mB0
oB0
qB0
destination
0x400
First write transmit data=
kB1
kB0
kB3
lB3
mB3
nB3
oB3
pB3
qB3
rB3
sB3
tB3
uB3
vB3
wB3
xB3
yB3
zB3
Memory
kB2
kB1
lB2
lB1
mB2 mB1
nB2
nB1
oB2
oB1
pB2
pB1
qB2
qB1
rB2
rB1
sB2
sB1
tB2
tB1
uB2
uB1
vB2
vB1
wB2 wB1
xB2
xB1
yB2
yB1
zB2
zB1
kB0
lB0
mB0
nB0
oB0
pB0
qB0
rB0
sB0
tB0
uB0
vB0
wB0
xB0
yB0
zB0
kB1
kB3
lB1
lB3
mB1
mB3
nB1
nB3
kB0
kB2
lB0
lB2
mB0
mB4
nB0
nB2
size[1:0] = HALF
src_inc[1:0] = WORD
dst_inc[1:0] = HALF
First read transmit data=
kB1
kB0
DMA Controller FIFO
kB3
lB3
mB3
nB3
kB2
lB2
mB2
nB2
kB1
lB1
mB1
nB1
kB0
lB0
mB0
nB0
First write transmit data=
kB1
kB0
size[1:0] = HALF
src_inc[1:0] = HALF
dst_inc[1:0] = WORD
Figure 7.4 Memory-to-Memory Transfer HALF Size Examples
Fields SRCINCSIGN and DSTINCSIGN allow for address decrement. These can be used to mirror an image, for example, in the pixel
copy application.
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7.3.2 Channel Configuration
Each DMA channel has associated configuration and loop counter registers for controlling direction of address increment , arbitration
slots, and descriptor looping.
7.3.2.1 Address Increment/Decrement
Normally DMA transfers increment the source and destination addresses after each DMA transfer. Each channel is also capable of decrementing the source and/or destination addresses after each DMA transfer. This may be useful for flipping an array or copying data
from tail to head. For example, a data packet might be prepared as an array of data with increasing addresses and then transmitted
from the highest address to the lowest address, from tail to head.
After reset the SRCINCSIGN and DSTINCSIGN bits in the LDMA_CHx_CFG register are cleared causing the source and destination
addresses to increment after each transfer. If the SRCINCSIGN bit is set , the DMA will decrement the source address after each transfer. If the DSTINCSIGN bit in the LDMA_CHx_CFG register is set , the DMA will decrement the destination address after each transfer.
Setting only one of these bits will flip the data. Setting both bits will copy from tail to head, but will not flip the data.
The SRCINCSIGN and DSTINCSIGN bits apply to all descriptors used by that channel. Software should take care to set the starting
source and/or destination address to the highest data address when decrementing.
7.3.2.2 Loop Counter
Each channel has a LDMA_CHx_LOOP register that includes a loop counter field. To use looping, software should initialize the loop
counter with the desired number of repetitions before enabling the transfer. A descriptor with the DECLOOPCNT bit set to TRUE will
repeat the loop and decrement the loop counter until LOOPCNT = 0.
For a looping descriptor, with DECLOOPCNT=1, the LINK address in the LDMA_CHx_LINK register is used as the loop address. While
LOOPCNT is greater than zero, the descriptor will execute and then the LDMA will load the next descriptor using the address specified
in the LDMA_CHx_LINK register. This feature enables looping of multiple descriptors. To repeat a single descriptor, the LINK address of
the descriptor should point to itself.
After LOOPCNT reaches zero, if the LINK bit in the descriptor LINK word is clear the transfer stops. If the LINK bit is set, the LDMA will
load the next sequential descriptor located immediately following the looping descriptor. The behavior of the LINK bit is different for a
looping descriptor. This is necessary because the LINK address is re-purposed as the loop address for a looping descriptor.
Note that LOOPCNT sets the number of repeats, not the number of iterations. The total number of loop iterations will be LOOPCNT
plus 1. Normally, the LOOPCNT should be set to one or more repeats.
Also note that because there is only one LOOPCNT per channel, software intervention is required to update the LOOPCNT if a sequence of transfers contains multiple loops. It is also possible to use a write immediate DMA data transfer to update the
LDMA_CHx_LOOP register.
7.3.3 Channel Select Configuration
The channel select block determines which peripheral request signal connects to each DMA channel.
This configuration is done by software through the SOURCESEL and SIGSEL fields of the LDMA_CHn_REQSEL register. SOURCESEL selects the peripheral and SIGSEL picks which DMA request signals to use from the selected peripheral.
7.3.4 Starting a transfer
A transfer may be started by software, a peripheral request, or a descriptor load.
Software may initiate a transfer by setting the bit for the desired channel in the LDMA_SREQ register. In this case the channel should
set SOURCESEL to NONE to prevent unintentional triggering of the channel by a peripheral.
A peripheral may trigger the channel by configuring the peripheral source and signal as described in 7.3.3 Channel Select Configuration
The LDMA may also be configured to begin a transfer immediatly after a new descriptor is loaded by setting the STRUCTREQ field of
the LDMA_CHx_CTRL register or descriptor word.
This configuration is done by software through the SOURCESEL and SIGSEL fields of the LDMA_CHn_REQSEL register. SOURCESEL selects the peripheral and SIGSEL picks which DMA request signals to use from the selected peripheral.
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7.3.4.1 Peripheral Transfer Requests
By default peripherals issue a Single Request (SREQ) when any data is present. For peripherals with a data buffer or FIFO this occurs
any time the FIFO is not empty. Uppon receving an SREQ the LDMA will perform one DMA transfer and stop till another request is
made.
It is generally more efficent to wait for a peripheral to accumulate data and transfer in a burst. This both reduces overhead of the DMA
engine and allows EM2 peripherals to save power by using the LDMA less often. To enable this set the IGNORESREQ bit in the
LDMA_CHx_CTRL register (or descriptor) which will cause the LDMA to ignore SREQ's and wait for a full Request (REQ) signal. When
the REQ is received the entire descriptor will be executed. For most peripherals with a FIFO the REQ signal is set when the FIFO is full,
or a predetermined threshold has been reached. See the individual peripheral chapters for more information.
7.3.5 Managing Transfer Errors
LDMA transfer errors are normally managed using interrupts. Software should clear the ERROR flag in the bit in the LDMA_IF register
and enable error interrupts by setting the ERROR bit in the LDMA_IEN register before initiating a DMA transfer
The LDMA interrupt handler should check the ERROR flag bit in the LDMA_IF register. If the ERROR flag bit is set, it should then read
the CHERROR field in the LDMA_STATUS register to determine the errant channel. The interrupt handler should reset the channel and
clear the ERROR flag bit in the LDMA_IF register before returning.
7.3.6 Arbitration
While multiple channels are configured simultaneously the LDMA engine can only be actively copying data for one channel at a time.
Arbitration determines which channel is being serviced at any point in time. The LDMA will choose a channel through arbitration, transfer BLOCK_SIZE elements of that channel and then arbitrate again choosing another channel to service. This allows high priority channels to be serviced while lower priority channels are in the middle of a transfer.
7.3.6.1 Arbitration Priority
There are two modes in determining priority when the controller arbitrates: fixed priority and round robin priority.
In fixed priority mode, channel 0 has the highest priority. As the channel number increases, the priority decreases. When the LDMA
controller is idle or when a transfer completes, the highest priority channel with an active request is granted the transfer. This mode
guarantees smallest latency for the highest priority requesters. It is best suited for systems where peak bandwidth is well below LDMA
controller’s maximum ability to serve. The drawback of this mode is the possibility of starvation for lowest priority requesters.
In the round robin priority mode, each active requesting channel is serviced in the order of priority. A late arriving request on a higher
priority channel will not get serviced until the next round. This mode minimizes the risk of starving low-priority latency-tolerant requesters. The drawback of this mode is higher risk of starving low-latency requesters.
The NUMFIXED field in the LDMA_CTRL register determines which channels are fixed priority and which are round robin. Channels
lower than NUMFIXED are fixed priority while those above it are round robin. A value of 0x0 implies all channels are round robin. A
value of 0x4 implies channels 0 through 3 are fixed priority and 4 through 7 are round robin. A value of 7 implies that channels 0
through 6 are fixed and channel 7 is round robin. This is functionally equivilent to having 8 fixed priority channels.
Fixed priority channels always take priority over round robin. As long as NUMFIXED is greater than 0, there is a possibility that a higher
priority channel can starve the remaining channels.
To address the drawbacks of using fixed priority or round robin priority the LDMA implements the concept of arbitration slots. This allows for channels to have high bandwidth and low latency while preventing starvation of latency tollerant low priority channels.
Each channel has a two bit ARBSLOT field in its LDM_CHx_CFG register. This field only applies to channels marked as round robin
(determined by NUMFIXED). The channels in the same arbitration slot are treated equally with round robin scheduling. Channels
marked with a higher arbitration slot will get serviced more frequently. By default all channels are placed in arbitration slot 1.
Every time the channels in slot 1 get serviced the channels in slot 2 get servicd twice, thoes in slot 4 get serviced 4 times, and thoes in
slot 8 get serviced 7 times. The specific arbitration allocation can be seen by the following table. The highest arbitration slot is serviced
every other arbitration cycle, allowing for low latency response. If there are no requests from channels in arbitration slot then that slot is
immediately skipped.
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Table 7.1. Arbitration Slot Order
Arbslot
order
8
4
8
2
8
4
8
Arbslot1
8
4
8
2
8
4
1
Arbslot2
1
Arbslot4
Arbslot8
1
1
1
1
1
1
1
1
1
1
1
1
1
The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpretation of the arbitration order.
For example, if we have one low latency channel (CHNL0) and two latency tolerant channels (CHNL1 and CHNL2). We could use the
following settings.
LDMA_CTRL.NUMFIXED = 0; set round robbin for all channels.
CHNL0_CFG.ARBSLOTS = TWO;
CHNL1_CFG.ARBSLOTS = ONE;
CHNL2_CFG.ARBSLOTS = ONE;
If all channels are constantly requesting transfers, then the arbitration order is: CHNL0, CHNL1, CHNL0, CHNL2, CHNL0, CHNL1,
CHNL0, CHNL2, CHNL0, etc
Note, there are no channels assigned to arbitration slot four or eight in this exampl, so thoes slots are skipped and the final sequence is
ARBSLOT2, ARBSLOT1, ARBSLOT2, ARBSLOT1, etc...
Channel 1 and Channel 2 are selected in round robin order when arbitration slot 1 is executed.
If we replace the ARBSLOTS value for channel 0 with EIGHT, then the sequence would look like the following:
CHNL0, CHNL0, CHNL0, CHNL0, CHNL1, CHNL0, CHNL0, CHNL0, CHNL2, CHNL0, CHNL0, CHNL0, CHNL0, CHNL1, etc.
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7.3.6.2 DMA Transfer Arbitration
In addition to the inter channel arbitration, software can configure when the controller arbitrates during a DMA transfer. This provides
reduced latency to higher priority channels when configuring low priority transfers with more arbitration cycles.
The LDMA provides four bits that configure how many DMA transfers occur before it re-arbitrates. These bits are known as the BLOCKSIZE bits and they map to the arbitration rate as shown below. For example, if BLOCKSIZE = 4 then the arbitration rate is 6, that is, the
controller arbitrates every 6 DMA transfers.
Table 7.2 AHB bus transfer arbitration interval on page 105 lists the arbitration rates.
Table 7.2. AHB bus transfer arbitration interval
BLOCKSIZE
Arbitrate after x DMA transfers
0
x = 1
1
x = 2
2
x = 3
3
x = 4
4
x = 6
5
x = 8
6
x = 12
7
x = 16
8
x = 24
9
x = 32
10
x = 64
11
x = 128
12
x = 256
13
x = 512
14
x = 1024
15
x = lock
Note:
Software must take care not to assign a low-priority channel with a large BLOCKSIZE because this prevents the controller from servicing high-priority requests, until it re-arbitrates.
The number of DMA transfers that need to be done is specified by the user in XFERCNT. When XFERCNT > BLOCKSIZE and is not an
integer multiple of BLOCKSIZE then the controller always performs sequences of BLOCKSIZE transfers until XFERCNT < BLOCKSIZE
remain to be transferred. The controller performs the remaining XFERCNT transfers at the end of the DMA cycle.
Software must store the value of the BLOCKSIZE bits in the channel control data structure. See 7.3.7.1 XFER descriptor structure for
more information about the location of the BLOCKSIZE bits in the data structure.
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7.3.7 Channel descriptor data structure
Each channel descriptor consists of four 32-bit words:
• CTRL - control word contains information like transfer count and block size.
• SRC - source address points to where to copy data from
• DST - destination address points to where to copy data to
• LINK - link address points to where to load the next linked descriptor
These words map directly to the LDMA_CHx_CTRL, LDMA_CHx_SRC, LDMA_CHx_DST, and LDMA_CHx_LINK registers. The usage
of the SRC and DST fields may differ depending on the structure type
There are three different types of descriptor data structures: XFER, SYNC, and WRI
7.3.7.1 XFER descriptor structure
This descriptor defines a typical data transfer which may be a Normal, Link, or Loop transfer.
Only this structure type can be written directly into LDMA's registers by the CPU. All descriptors may be linked to. Please refer to the
register descriptions for additional information.
For specifying XFER structure type, set STRUCTTYPE to 0. Please see the peripheral register descriptions for information on the fields
in this structure.
0
1
STRUCTTYPE
2
3
STRUCTREQ
4
5
6
7
8
9
XFERCNT
10
11
12
13
14
15
BYTESWAP
16
17
18
DSTADDR
LINKADDR
LINKMODE
20
DONEIFSEN
19
21
BLOCKSIZE
SRCADDR
LINK
LINK
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REQMODE
DECLOOPCNT 22
IGNORESREQ 23
24
25
SRCINC
26
27
SIZE
28
29
30
SRCMODE
DSTINC
31
DSTMODE
Bit Position
DST SRC
CTRL
N
a
m
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7.3.7.2 SYNC descriptor structure
This descriptor defines an intra-channel synchronizing structure. It allows the channel to wait for some external stimulus before continuing on to the next descriptor. This structure is also used to provide stimulus to another channel to indicate that it may continue.
For example channel 1 may be configured to transfer a header into a buffer while channel 2 is simlutaniously transfering data into the
same structure. When channel 1 has completed it can wait for a sync signal from channel 2 before transfering the now complete buffer
to a peripheral.
Synch descriptors do nothing untill a condition is met. The condition is formed by the SYNCTRIG field in the LDMA_SYNC register and
the MATCHEN and MATCHVAL fields of the descriptor. When (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN) the next descriptor is loaded. In addition to waiting for the condition a Link descriptor can set or clear bits in SYNCTRIG to meet the conditions of
another channel and cause it to continue. The CPU also has the ability to set and clear the SYNCTRIG bits from software.
This structure type can only be linked in from memory.
For specifying SYNC structure type, set STRUCTTYPE to 1.
N
a
m
e
0
1
SYNCSET
MATCHEN
MATCHVAL
LINKADDR
Bit
Name
Description
1:0
STRUCTTYPE
Descriptor Type
LINK
SYNCCLR
LINKMODE
STRUCTTYPE
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DONEIFSEN
21
22
23
24
25
26
27
28
29
30
LINK
DST SRC
CTRL
31
Bit Position
This field indicates which type of descriptor this is. It must be 1 for a SYNC descriptor.
20
DONEIFSEN
Done if Set indicator
If set the interrupt flag will be set descriptor completes.
7:0
SYNCCLR
Sync Trigger Clear
This bit-field is used to clear corresponding bits within the SYNCTRIG field of the SYNC LDMA_SYNC register. To clear
a given bit, a one should be loaded to the corresponding bit. Set is given priority over clear if both corresponding bits
are loaded with a one. The sync trigger clear function can only be used when loaded from a linked structure. Alternately, the user can directly write the SYNCTRIG bit-field if required.
7:0
SYNCSET
Sync Trigger Set
This bit-field is used to set corresponding bits within the SYNCTRIG bit-field. To set a given bit, a one should be loaded
to the corresponding bit. Set is given priority over clear if both corresponding bits are loaded with a one. The sync trigger set function can only be used when loaded from a linked structure. Alternately, the user can directly write the SYNCTRIG bit-field if required.
7:0
MATCHEN
Sync Trigger Match Enable
This bit-field serves as the SYNCTRIG match enable. A sync match triggers the load of the next linked DMA structure
as specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN).
7:0
MATCHVAL
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Bit
Name
Description
This bit-field serves as the SYNCTRIG match value. A sync match triggers the load of the next linked DMA structure as
specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN).
7.3.7.3 WRI descriptor structure
This descriptor defines a write-immediate structure. This allows a list of descriptors to write a value to a register or memory location. For
example, if a channel wishes to perform two loops in a descriptor sequence a WRI may be used to program the loop count for the
second loop.
This structure type can only be linked in from memory.
For specifying WRI structure type, set STRUCTTYPE to 2.
N
a
m
e
0
1
2
3
4
5
6
7
STRUCTTYPE
DST SRC
C
T
R
L
8
9
10
11
12
13
14
15
16
17
18
19
20
DONEIFSEN
21
22
23
24
25
26
27
28
29
IMMVAL
LINKADDR
Bit
Name
Description
1:0
STRUCTTYPE
Descriptor Type
LINKMODE
LINK
DSTADDR
LINK
30
31
Bit Position
This field indicates which type of descriptor this is. It must be 2 for a WRI descriptor.
20
DONEIFSEN
Done if Set indicator
If set the interrupt flag will be set descriptor completes.
31:0
IMMVAL
Immediate Value for Write
This bit-field specifies the immediate data value that is to be written to the address pointed to by DSTADDR. Only one
write occurs for WRI structures.
31:0
DSTADDR
Address to write
This bit-field specifies the address the immediate data should be written to.
7.3.8 Interaction with the EMU
The LDMA interacts with the Energy Management Unit (EMU) to allow transfers from a low energy peripheral while in EM2 DeepSleep.
For example, when using the LEUART in EM2 DeepSleep the EMU can wake up the LDMA sufficiently long to allow data transfers to
occur. See section "DMA Support" in the LEUART documentation.
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7.3.9 Interrupts
The LDMA_IF Interrupt flag register contains one DONE bit for each channel and one combined ERROR bit. When enabled, these interrupts are available as interrupts to the Cortex-M3 core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the
DMA is enabled in the ARM Cortex-M3 core, an interrupt will be made if one or more of the interrupt flags in LDMA_IF and their
corresponding bits in LDMA_IEN are set.
When a descriptor finishes execution the interrupt flag for that channel will be set if the DONEIFSEN field of the LDMA_CHx_LOOP
register is set. If LINK and DONEIFSEN are both set when the descriptor completes the interrupt and the linked descriptor will be immediatly loaded. When the final descriptor in a linked list (LINK = 0) is finished the interrupt flag is always set regardless of the state of
DONEIFSEN.
7.3.10 Debugging
For a peripheral request DMA transfer, if software sets a bit for a channel in the LDMA_DBGHALT register then the DMA will halt durring a debug halt and the SRC and DST registers in the debug window will show the transfer in progress. Otherwise, during debug halt
the DMA will continue to run and complete the entire transfer causing the descriptor registers to indicate the transfer has completed.
7.4 Examples
This section provides examples of common LDMA usage. All examples assume the LDMA is in the reset state with the channel being
configured disabled and LDAM_CHx_CFG, LDMA_CHx_LOOP, and LDMA_CHx_LINK cleared.
7.4.1 Single Direct Register DMA Transfer
This simple example uses only the Channel Descriptor registers directly and does not use linking. Software writes directly to the LDMA
channel registers. This example does not use a memory based descriptor list.
This example is suitable for most simple transfers that are limited to transferring one block of data. It supports anything that can be
done using a single descriptor. This includes endian conversion and packing/unpacking data. Channel 0 is used for this example.
The LDMA will be used to copy 127 contiguous half words (254 bytes) from 0x0 to 0x1000. It will allow arbitration every 4 transfers and
is triggerd by a CPU write to the LDMA_SWREQ register. The CH0 interrupt flag will be set when the transfer completes since the descriptor does not link to another descriptor.
• Configure LDMA_CH0_CTRL
• DSTMODE = 0 (absolute)
• SRCMODE = 0 (absolute)
• SIZE = HALFWORD (16 bits)
• DSTINC = 0 (1 half-word)
• SRCINC = 0 (1 half-word)
• DECLOOPCNT=0 (unused)
• REQMODE = 1 (one request transfers all data)
• BLOCKSIZE = 3 (4 transfers)
• BYTESWAP=0 (no byte swap)
• XFERCNT=127 (transfer 127 half words)
• STRUCTTPYE=0 (TRANSFER)
• Write source address to LDMA_CH0_SRC register
• Write destination address to LDMA_CH0_DST register
• Configure the LDMA_CH0REQSEL register for the desired peripheral or select none for a memory-to-memory transfer
• Clear and enable interrupts.
• Write a 1 to bit 0 of the LDMA_IFC register to clear the CH0 DONE flag
• Write a 1 to bit 0 of the LDMA_IEN register to enable the CH0 interrupt
• Write a 1 to bit 0 of the LDMA_CHEN register to enable CH0
The REQMODE field is normally cleared to zero for a peripheral request transfer and will transfer the specified block size for each peripheral request. The REQMODE may be set to 1 for a memory-to-memory transfer or any time it is desired for a single DMA request to
initiate complete transfer.
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7.4.2 Descriptor Linked List
This example shows how to use a Linked List of descriptors. Each descriptor has a link address which points to the next descriptor in
the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it.
Descriptor Linked lists are useful when handling an array of buffers for communication data. For example, a bad packet can be removed from a receiver queue by simply removing the descriptor from the linked list.
Software loads the first descriptor into the DMA by writing the descriptor address to LDMA_CHx_LINK and setting the bit for that channel in the LDMA_LINKLOAD register. This method is prefered when using a linked list in memory since it treats the first descriptor just
like all the others. However, it is also allowed acceptable for software to write the first descriptor directoy to the LDMA registers.
In this example 4 descriptors are executed in series. the interrupt flag is set after the 2nd and 4th (last) descriptors have completed.
• Prepare a list of descriptors using the XFER structure type in RAM
• Initialize the CTRL, SRC, and DST members as desired
• Setting STRUCTREQ in the CTRL word for descritpors 2-4 will cause them to begin transfering data as soon as they are loaded.
• Write 0x00000013 to the LINK member of all but the last descriptor
• LINKMODE = 1 (relative addressing)
• LINK = 1 (Link to the next descriptor)
• LINKADDR = 0x00000010 (size of descriptor)
• Set the DONEIFSEN bit in the CTRL member of the 2nd structure so that the interrupt flag will be set when it completes
• Write 0x00000000 to the LINK member of the last descriptor
• LINK = 0 (Do not link to the next descriptor)
• LINKMODE = 0 (don't care)
• LINKADDR = 0x00000000 (don't care)
Each descriptor now points to the start of the next descriptor as shown on the left in Figure 7.5 Descriptor Linked List on page 110. To
remove a descriptor from the linked list modify the LINK address of the descriptor of the one before to point to the one after. For example to remove the third descriptor, add 0x00000010 to the LINK register of the second descriptor. The second descriptor will now point
to the forth descriptor and skip over the third descriptor as shown on the right in Figure 7.5 Descriptor Linked List on page 110.
A
B
C
D
Linked
List
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
A
0x00000013
B
0x00000013
C
0x00000013
D
0x00000000
Third
Descriptor
Deleted
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
A
A
0x00000013
B
B
0x00000023
C
C
0x00000013
D
D
0x00000000
Figure 7.5 Descriptor Linked List
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To start execution of the linked list of descriptors:
• Write the absolute address of the first descriptor to the LINKADR field of the LDMA_CH0_LINK register
• Set the LINK bit of teh LDMA_CH0_LINK register.
• Configure the LDMA_CH0REQSEL register for the desired peripheral or select none for memory-to-memory
• Clear and enable interrupts as desired
• Set bit 0 in the LDMA_LINKLOAD register to initate loading and execution of the first descriptor
Alternativley, software can manually copy the first descriptor contents to the LDMA_CH0_CTRL, LDMA_CH0_SRC, LDMA_CH0_DST,
and LDMA_CH0_LINK registers and then enable the channel in the LDMA_CHEN register.
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7.4.3 Single Descriptor Looped Transfer
This example demonstrates how to use looping using a single descriptor. This method allows a single DMA transfer to be repeated a
specified number of times. The looping descriptor is stored in memory and reloaded by hardware. After a specified number of iterations,
the transfer stops.
CH0 is setup to copy 4 words frm the ADC FIFO into a 15 word buffer at 0x1000. It repeates 4 times to fill the entire 16 word buffere. An
interrupt will fire when the entire 16 words has been transfered.
Initialize the Linked descriptor in memory as follows:
• Configure CTRL member
• DSTMODE = 0 (absolute)
• SRCMODE = 0 (absolute)
• SIZE = WORD
• DSTINC = 0 (1 WORD)
• SRCINC = 3 (0 WORDS)
• DECLOOPCNT=1 (decrement loop count)
• REQMODE=1 (Use XFERCNT)
• BLOCKSIZE = 4 (4 words)
• BYTESWAP=0 (no swap)
• XFERCNT= 4 (4 words)
• STRUCTTPYE=0 (TRANSFER)
• IGNORESREQ=1 (ignore single requests)
• Write the address ADC0_SINGLEDATA register to the SRC member
• Write 0x1000 address to DST member
• Configure the LINKLink member
• LINK = 0 (stop after loop)
• MODE = 1 (relative link address)
• LINKADDR = 0 (point to ourself)
• Configure the Channel
• Write the desired number of repeats to the LDMA_CH0_LOOP register
• SOURCESEL in LDMA_CH0REQSEL = ADC0 (select the ADC)
• SIG in LDMA_CH0REQSEL = ADC0SCAN (select the single conversion request)
• Clear and enable interrupts
• Load the descriptor using LINKLOAD as described in 7.4.2 Descriptor Linked List
Memory
A
0x00
LINKADDR->A
DECLOOPCNT=1
LINK=0
Ctrl
Src
Dst
Link
A
link_addr->A
Figure 7.6 Single Descriptor Looped Transfer
Note that the looping descriptor must be stored in memory, because it must load itself from the link address in memory on each iteration.
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7.4.4 Descriptor List with Looping
This example uses a descriptor list in memory with looping over multiple descriptors. This example also uses the looping feature and
continues on with the next sequential descriptor after looping completes.
The descriptor list in memory is shown in figure Figure 7.7 Descriptor List with Looping on page 113. Descriptor A links to descriptor B.
Descriptor B has the DECLOOPCNT bit enabled and loops back to the start of descriptor A. The LINK address of descriptor B is used
for the loop address. The LINK bit is set to indicate that execution will continue after completion of looping. Once the LOOPCNT reaches zero, the LDMA will load descriptor C. Descriptor C must be located immediately following descriptor B.
Memory
0x00
0x10
A
C
B
Alternate link
0x20
LINKADDR->B
LINKADDR->A
DECLOOPCNT=1
LINK=0
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
Ctrl
Src
Dst
Link
A
link_addr->B
B
link_addr->A
C
link_addr=NA
Figure 7.7 Descriptor List with Looping
Initialization is similar to the single looping descriptor with the following modifications.
• Set the LINK bit in descriptors A and B
• write the adress of descriptor A into the LIKADDRESS of descriptor B
• write the adress of descriptor B into the LIKADDRESS of descriptor A
• Descriptor C must be located immediatly after descriptor B in memory
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7.4.5 Simple Inter-Channel Synchronization
The LDMA controller features synchronization structures which allow differing channels and/or hardware events to pause a DMA sequence, and wait for a synchronizing event to restart it.
In this example DMA channel 0 and 1 are tasked with the transfer of different sets of data. Channel 0 has two transfer structures, and
channel 1 just one, but channel 0 must wait until channel 1 has completed its transfer before it starts its second transfer structure.
Pausing channel 0 is accomplished by inserting a sync wait structure between the two transfer structures. This sync structure waits on
SYNCTRIG[7] to be set by a sync set/clear structure which is controlled by channel 1. Sync structures do not transfer data, they can
only set, clear, or wait to match the SYNCTRIG[7:0] bits. Note that sync structures cannot decrement loop counter.
LDMA_SYNC
SYNCTRIG=0x0 (at time 0)
LDMA_CH0
Structure A @ 0x00
CTRL
STRUCTTYPE=XFER
LINK
LINKADDR[29:0]=0x00000004
LINK=1
Structure B @ 0x10
Structure C @ 0x20
CTRL
CTRL
STRUCTTYPE=SYNC
STRUCTTYPE=XFER
LINK
LINK
LINKADDR[29:0]=0x00000008
LINKADDR[29:0]=NA
LINK=1
LINK=0
DST
MATCHEN=0x80
MATCHVAL=0x80 (waits for SYNCTRIG[7]=1)
LDMA_CH1
Structure Y @ 0x30
Structure Z @ 0x40
CTRL
CTRL
STRUCTTYPE=XFER
LINK
LINKADDR[29:0]=0x00000010
LINK=1
STRUCTTYPE=SYNC
LINK
LINKADDR=NA
LINK=0
SRC
SRCCLR=0x0
SRCSET=0x80 (sets SYNCTRIG[7])
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SYNC[7]
STRUCTTYPE=XFER
A
CH0
STRUCTTYPE=-SYNC
wait SYNCTRIG[7]=1
STRUCTTYPE=XFER
C
B
C not fetched until
sync_trig[7] is set
Z
Y
CH1
STRUCTTYPE=SYNC
set SYNC[7]
STRUCTTYPE=XFER
Time
Figure 7.8 Simple Intra-channel Synchronization Example
Both A and Y effectively start at the same time. A finishes earlier, then it links to B, which waits for the SYNCTRIG[7] bit to be set before
loading C. Y finishes after B is loaded, and it links to sync structure Z, which sets the SYNCTRIG[7] bit. Channel 0 responds to the
trigger set by loading C for the final data transfer.
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7.4.6 2D Copy
The LDMA can easily perform a 2D copy using a descriptor list with looping. This set up is visualized in Figure 7.9 2D copy on page
116
For an application working with graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to
another.
Source Buffer
Destination Buffer
Source
Address
Descriptor A
Descriptor B
Destination
Address
HEIGHT
HEIGHT
WIDTH
2D Copy Descriptors in Memory
Descriptor A
Descriptor B
Destination
Address
WIDTH
CTRL
SRC
DST
LINK
CTRL
SRC
DST
LINK
XFERCNT = WIDTH - 1
SRCMD = DSTMD = 0
A SRC = SRCADDR
DST = DSTADDR
LINK = 0x00000013
B
XFERCNT = WIDTH - 1
SRCMD = DSTMD = 1
SRCADDR = SRCSTRIDE - WIDTH
DSTADDR = DSTSTRIDE - WIDTH
LINK = 0x00000001
B
A
LINKADDR->B
SRCSTRIDE
LINKADDR->B
DECLOOPCNT=1
LINK=0
DSTSTRIDE
Figure 7.9 2D copy
The first descriptor will use absolute addressing mode and the source and destination addresses should point to the desired target addresses. The first descriptor will copy only the first row. The XFERCNT of the first descriptor is set to the desired width minus one.
• CTRL
• XFERCNT = WIDTH - 1
• SRCMD = 0 (absolute)
• DSTMD = 0 (absolute)
• SRCADDR = target source address
• DSTADDR = target destination address
• LINK = 0x00000013
• LINK=1
• LINKMD=1
• LINKADDR=0x00000010 (point to next descriptor)
The second descriptor will use relative addressing and the source and destination addresses are set to the desired offset. After the
completion of the first descriptor, the address registers will point to the last address transferred. Thus, the width must be subtracted
from the stride to get the offset. The second descriptor uses looping and the link register has not offset.
• CTRL
• XFERCNT = WIDTH - 1
• SRCMD = 1 (relative)
• DSTMD = 1 (relative)
• DECLOOPCNT = 1
• SRCADDR = desired source offset (SRCSTRIDE-WIDTH)
• DSTADDR = desired destination offset (DSTSTRIDE-WIDTH)
• LINK = 0x00000001
• LINK=0
• LINKMD=1 (relative)
• LINKADDR=0x000000000 (no offset)
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Because the first descriptor already transferred one row, the number of looping repeats should be the desired height minus two. Therefore, LOOPCNT should be set to HEIGHT minus two before initiating the transfer.
.
This same method is easily extended to copy multiple rectangles by linking descriptors together. To initialize the LDMA_CHx_LOOP
register, precede each descriptor pair described above with a write immediate descriptor which writes the desired value to the
LOOPCNT field of the LDMA_CHx_LOOP register.
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7.4.7 Ping-Pong
Communication peripherals often use ping-pong buffers. Ping-pong buffers allow the CPU to process data in one buffer while a peripheral transmits or receives data in the other buffer.
Both transmit and receive ping-pong buffers are easily implemented using the LDMA. In either case, this requires two descriptors as
shown in Figure 7.10 Infinite Ping-Pong Example on page 118. The LINKADDR field of the LINK member should point to the other
descriptor. Using two adjacent descriptors and relative link addressing ensures the descriptors are easily reloadable.
Memory
A
CTRL
SRC
DST
LINK
CTRL
SRC
DST
LINK
B
A
LINKADDR = 0x00000010
LINKMD = 1
B
LINKADDR = 0xFFFFFFF0
LINKMD = 1
Figure 7.10 Infinite Ping-Pong Example
A receiver ping-pong buffer controller consists of two buffers and two descriptors stored in memory that point to the two buffers. Once
initialized, as the peripheral receives data, it will fill the first buffer. Once the first buffer is full, it will link automatically to the second
buffer and generate an interrupt. Software will then process the data in the first buffer while the LDMA is transferring data to the second
buffer. For a receiver ping-pong buffer each descriptor should link to the other descriptor. The link bit should be set to provide infinite
ping pong between the two buffers. The DONIFS bit in each descriptor should be set to generate an interrupt on the completion of each
descriptor.
• Descriptor A
• CTRL
• DONEIFS = 1
• other settings as desired
• SRCADDR = peripheral source address
• DSTADDR = memory destination address
• LINK = 0x00000013
• LINKADDR = 0x00000010 (next descriptor)
• LINK = 1 (link to next descriptor)
• LINKMD = 1 (relative addressing)
• Descriptor B
• CTRL
• DONEIFS = 1
• other settings as desired
• SRCADDR = peripheral source address
• DSTADDR = memory destination address
• LINK = 0xFFFFFFF3
• LINKADDR = 0xFFFFFFF0 (previous descriptor)
• LINK = 1 (link to previous descriptor)
• LINKMD = 1 (relative addressing)
For transmitter ping-pong buffer, software will fill the first buffer and then initiate the DMA transfer. The LDMA will transmit the first
buffer data while software is filling the second buffer. In this case, the two descriptors should point to each other, but not automatically
continue to the second buffer. The LINK bit should be cleared to zero. Once software has loaded the first buffer, it will use the
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LINKLOAD bit to load the first descriptor and transmit the data. The DONIFS need not be set in each descriptor. The DMA will stop and
then generate an interrupt at the completion of each descriptor.
• Descriptor A
• CTRL
• DONEIFS = 0
• other settings as desired
• SRCADDR = memory source address
• DSTADDR = peripheral destination address
• LINK = 0x00000013
• LINKADDR = 0x00000010 (next descriptor)
• LINK = 0 (link to next descriptor)
• LINKMD = 1 (relative addressing)
• Descriptor B
• CTRL
• DONEIFS = 0
• other settings as desired
• SRCADDR = memory source address
• DSTADDR = peripheral destination address
• LINK = 0xFFFFFFF3
• LINKADDR = 0xFFFFFFF0 (previous descriptor)
• LINK = 0 (link to previous descriptor)
• LINKMD = 1 (relative addressing)
7.4.8 Scatter-Gather
Scatter-Gather in general refers to a process that copies data from multiple locations scattered in memory and gathers the data to a
single location in memory, or vice versa. A simple descriptor list allows data gathering. For example, data from a discontiguous list of
buffers might be copied to a contiguous sequential array of buffers. The inverse is also possible when a sequential array of buffers is
scattered to a discontiguous list of available buffers. See section 7.4.2 Descriptor Linked List.
Some DMAs which only have two descriptors implement scatter-gather by using one descriptor to modify the other descriptor. While it is
possible to implement this same behavior using the LDMA, it is much more straight-forward to just use a simple descriptor list.
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7.5 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
LDMA_CTRL
RW
DMA Control Register
0x004
LDMA_STATUS
R
DMA Status Register
0x008
LDMA_SYNC
RWH
DMA Synchronization Trigger Register (Single-Cycle RMW)
0x020
LDMA_CHEN
RWH
DMA Channel Enable Register (Single-Cycle RMW)
0x024
LDMA_CHBUSY
R
DMA Channel Busy Register
0x028
LDMA_CHDONE
RWH
DMA Channel Linking Done Register (Single-Cycle RMW)
0x02C
LDMA_DBGHALT
RW
DMA Channel Debug Halt Register
0x030
LDMA_SWREQ
W1
DMA Channel Software Transfer Request Register
0x034
LDMA_REQDIS
RW
DMA Channel Request Disable Register
0x038
LDMA_REQPEND
R
DMA Channel Requests Pending Register
0x03C
LDMA_LINKLOAD
W1
DMA Channel Link Load Register
0x040
LDMA_REQCLEAR
W1
DMA Channel Request Clear Register
0x060
LDMA_IF
R
Interrupt Flag Register
0x064
LDMA_IFS
W1
Interrupt Flag Set Register
0x068
LDMA_IFC
(R)W1
Interrupt Flag Clear Register
0x06C
LDMA_IEN
RW
Interrupt Enable register
0x080
LDMA_CH0_REQSEL
RW
Channel Peripheral Request Select Register
0x084
LDMA_CH0_CFG
RW
Channel Configuration Register
0x088
LDMA_CH0_LOOP
RWH
Channel Loop Counter Register
0x08C
LDMA_CH0_CTRL
RWH
Channel Descriptor Control Word Register
0x090
LDMA_CH0_SRC
RWH
Channel Descriptor Source Data Address Register
0x094
LDMA_CH0_DST
RWH
Channel Descriptor Destination Data Address Register
0x098
LDMA_CH0_LINK
RWH
Channel Descriptor Link Structure Address Register
...
LDMA_CHx_REQSEL
RW
Channel Peripheral Request Select Register
...
LDMA_CHx_CFG
RW
Channel Configuration Register
...
LDMA_CHx_LOOP
RWH
Channel Loop Counter Register
...
LDMA_CHx_CTRL
RWH
Channel Descriptor Control Word Register
...
LDMA_CHx_SRC
RWH
Channel Descriptor Source Data Address Register
...
LDMA_CHx_DST
RWH
Channel Descriptor Destination Data Address Register
...
LDMA_CHx_LINK
RWH
Channel Descriptor Link Structure Address Register
0x1D0
LDMA_CH7_REQSEL
RW
Channel Peripheral Request Select Register
0x1D4
LDMA_CH7_CFG
RW
Channel Configuration Register
0x1D8
LDMA_CH7_LOOP
RWH
Channel Loop Counter Register
0x1DC
LDMA_CH7_CTRL
RWH
Channel Descriptor Control Word Register
0x1E0
LDMA_CH7_SRC
RWH
Channel Descriptor Source Data Address Register
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Offset
Name
Type
Description
0x1E4
LDMA_CH7_DST
RWH
Channel Descriptor Destination Data Address Register
0x1E8
LDMA_CH7_LINK
RWH
Channel Descriptor Link Structure Address Register
7.6 Register Description
7.6.1 LDMA_CTRL - DMA Control Register
Name
Access
Bit
Name
Reset
31:27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
NUMFIXED
0x7
RW
0
1
2
3
4
6
7
8
9
10
11
12
13
5
SYNCPRSSETEN RW 0x00
NUMFIXED
Access
14
SYNCPRSCLREN RW 0x00
RW
Reset
15
16
17
18
19
20
21
22
23
24
25
0x7
26
27
28
29
30
0x000
Bit Position
31
Offset
Description
Number of Fixed Priority Channels
This field defines the number of Fixed Priority Arbitration channels. Channels CH0 though CH(n-1) are fixed, and channels
CH(n) through CH7 are round robin, where n is the field value. The reset value will give all fixed channels
23:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:8
SYNCPRSCLREN
0x00
RW
Synchronization PRS Clear Enable
Setting a bit in this field will enable the corresponding PRS input to clear the respective bit in the SYNCTRIG field of the
LDMA_SYNC register. Refer to the PRS section for a list of the PRS inputs.
7:0
SYNCPRSSETEN
0x00
RW
Synchronization PRS Set Enable
Setting a bit in this field will enable the corresponding PRS input to set the respective bit in the SYNCTRIG field of the
LDMA_SYNC register. Refer to the PRS section for a list of the PRS inputs.
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7.6.2 LDMA_STATUS - DMA Status Register
Access
0
R
ANYBUSY
0
1
0
R
2
ANYREQ
Bit
Name
Reset
31:29
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
28:24
CHNUM
0x08
R
3
4
R
CHGRANT
0x0
5
6
7
8
10
11
12
13
14
15
16
17
9
0x0
R
CHERROR
Name
0x10 18
FIFOLEVEL R
19
20
21
22
23
24
25
CHNUM
R
Access
0x08 26
Reset
27
28
29
30
0x004
Bit Position
31
Offset
Description
Number of Channels
The value of CHNUM always reads the total number of channels present for this instance of the DMA controller module.
23:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20:16
FIFOLEVEL
0x10
R
FIFO Level
The value of FIFOLEVEL indicates the number of entries currently in the FIFO. (Note when all channels are disabled, this
register will read the total number of entries in the FIFO.)
15:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10:8
CHERROR
0x0
R
Errant Channel Number
When the ERROR flag is set in the LDMA_IF register, the CHERROR field will indicate the most recent channel to have a
transfer error.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:3
CHGRANT
0x0
R
Granted Channel Number
The value of this field indicates the currently active channel or last active channel. Note that the reset value for this field is
zero.
2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
ANYREQ
0
R
Any DMA Channel Request Pending
The value of this bit will be TRUE (1) if any requests are pending
0
ANYBUSY
0
R
Any DMA Channel Busy
The value of this bit will be TRUE (1) if one or more DMA channels are actively transferring data
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7.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW)
0
1
2
3
4
SYNCTRIG RWH 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
SYNCTRIG
0x00
RWH
Description
Synchronization Trigger
The SYNC trigger field allows a transfer to pause until a specified trigger bit is set or cleared. The SYNC trigger bits may be
set and cleared by a SYNC descriptor, PRS signal, or software. Note: software requires to use single-cycle read-modifywrite, detailed in
7.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW)
0
1
2
3
4
CHEN RWH 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
CHEN
0x00
RWH
Description
Channel Enables
Setting one of these bits will enable the respective DMA channel. If cleared while a transfer is in progress, the current transfer block will complete. The remaining blocks will pause until resumed later by setting this bit again. Note: software requires
to use single-cycle read-modify-write, detailed in
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7.6.5 LDMA_CHBUSY - DMA Channel Busy Register
2
1
0
1
0
3
2
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Reset
BUSY R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
BUSY
0x00
R
Description
Channels Busy
The bits of this field read 1 when the corresponding channel is busy.
7.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW)
3
4
CHDONE RWH 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
CHDONE
0x00
RWH
Description
DMA Channel Linking or Done
Each DMA channel sets the corresponding bit in this register when the entire transfer is done. The interrupt service routine
should clear these bits. Enabling a DMA channel will also clear the corresponding LINKDONE bit. Note: software requires
to use single-cycle read-modify-write, detailed in 4.2.2 Peripheral Bit Set and Clear
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7.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register
0
1
2
3
4
DBGHALT RW 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
DBGHALT
0x00
RW
Description
DMA Debug Halt
Setting one of these bits will mask the corresponding DMA channel's peripheral request when debugging and the CPU is
halted. This may be useful for debugging DMA software.
7.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register
0
1
2
3
4
SWREQ W1 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
SWREQ
0x00
W1
Description
Software Transfer Requests
Setting one of these bits will trigger a DMA transfer for the corresponding channel. Writing zeros has no effect.
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LDMA - Linked DMA Controller
7.6.9 LDMA_REQDIS - DMA Channel Request Disable Register
0
1
2
3
4
REQDIS RW 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
REQDIS
0x00
RW
Description
DMA Request Disables
Setting one of these bits will disable peripheral requests for the corresponding channel. When cleared any pending peripheral requests will be serviced.
7.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register
0
1
2
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x038
Bit Position
31
Offset
Reset
REQPEND R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
REQPEND
0x00
R
Description
DMA Requests Pending
When a DMA channel has a pending peripheral request the corresponding REQPEND bit will read 1.
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LDMA - Linked DMA Controller
7.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register
0
1
2
3
4
LINKLOAD W1 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
LINKLOAD
0x00
W1
Description
DMA Link Loads
Setting one of these bits will force the corresponding DMA channel to load the next DMA structure and enable the channel.
This empowers software to step through a sequence of descriptors.
7.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register
0
1
2
3
4
REQCLEAR W1 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
REQCLEAR
0x00
W1
Description
DMA Request Clear
Setting one of these bits will clear any internally registered transfer requests for the corresponding channel.
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LDMA - Linked DMA Controller
7.6.13 LDMA_IF - Interrupt Flag Register
Name
0
1
2
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
R
DONE
Access
0
Reset
ERROR R
0x060
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31
ERROR
0
R
Transfer Error Interrupt Flag
The ERRORIF flag is set when a read or write error occurs. The CHERROR field in the LDMA_STATUS register reflects the
number of the channel which had the last error.
30:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
DONE
0x00
R
DMA Structure Operation Done Interrupt Flag
When a channel completes a transfer or sync operation, the corresponding DONE bit is set in the LDMA_IF register.
7.6.14 LDMA_IFS - Interrupt Flag Set Register
Name
0
1
2
3
4
W1 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
25
DONE
Access
0
Reset
ERROR W1
0x064
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31
ERROR
0
W1
Set ERROR Interrupt Flag
Write 1 to set the ERROR interrupt flag
30:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
DONE
0x00
W1
Set DONE Interrupt Flag
Write 1 to set the DONE interrupt flag
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LDMA - Linked DMA Controller
7.6.15 LDMA_IFC - Interrupt Flag Clear Register
Name
0
1
2
3
4
(R)W1 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DONE
Access
0
Reset
ERROR (R)W1
0x068
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31
ERROR
0
(R)W1
Clear ERROR Interrupt Flag
Write 1 to clear the ERROR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
30:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
DONE
0x00
(R)W1
Clear DONE Interrupt Flag
Write 1 to clear the DONE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
7.6.16 LDMA_IEN - Interrupt Enable register
Name
0
1
2
3
4
RW 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
25
DONE
Access
0
Reset
ERROR RW
0x06C
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31
ERROR
0
RW
ERROR Interrupt Enable
Enable/disable the ERROR interrupt
30:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
DONE
0x00
RW
DONE Interrupt Enable
Enable/disable the DONE interrupt
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LDMA - Linked DMA Controller
7.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register
Name
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0
1
2
RW
0x0
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5
SIGSEL
Access
SOURCESEL RW 0x00
Reset
22
23
24
25
26
27
28
29
30
0x080
Bit Position
31
Offset
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EFM32JG1 Reference Manual
LDMA - Linked DMA Controller
Bit
Name
Reset
Access
31:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:16
SOURCESEL
0x00
RW
Description
Source Select
Select input source to DMA channel.
Value
Mode
Description
0b000000
NONE
No source selected
0b000001
PRS
Peripheral Reflex System
0b001000
ADC0
Analog to Digital Converter 0
0b001100
USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0b001101
USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0b010000
LEUART0
Low Energy UART 0
0b010100
I2C0
I2C 0
0b011000
TIMER0
Timer 0
0b011001
TIMER1
Timer 1
0b110000
MSC
0b110001
CRYPTO
15:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
SIGSEL
0x0
Advanced Encryption Standard Accelerator
RW
Signal Select
Select input signal to DMA channel.
Value
Mode
Description
OFF
Channel input selection is turned off
0b0000
PRSREQ0
PRSREQ0
0b0001
PRSREQ1
PRSREQ1
0b0000
ADC0SINGLE
ADC0SINGLE REQ/SREQ
0b0001
ADC0SCAN
ADC0SCAN REQ/SREQ
0b0000
USART0RXDATAV
USART0RXDATAV REQ/SREQ
0b0001
USART0TXBL
USART0TXBL REQ/SREQ
0b0010
USART0TXEMPTY
USART0TXEMPTY
0b0000
USART1RXDATAV
USART1RXDATAV REQ/SREQ
0b0001
USART1TXBL
USART1TXBL REQ/SREQ
SOURCESEL
=
0b000000 (NONE)
0bxxxx
SOURCESEL =
0b000001 (PRS)
SOURCESEL =
0b001000 (ADC0)
SOURCESEL
=
0b001100 (USART0)
SOURCESEL
=
0b001101 (USART1)
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LDMA - Linked DMA Controller
Bit
Name
Reset
Access
Description
0b0010
USART1TXEMPTY
USART1TXEMPTY
0b0011
USART1RXDATAVRIGHT
USART1RXDATAVRIGHT REQ/SREQ
0b0100
USART1TXBLRIGHT
USART1TXBLRIGHT REQ/SREQ
0b0000
LEUART0RXDATAV
LEUART0RXDATAV
0b0001
LEUART0TXBL
LEUART0TXBL
0b0010
LEUART0TXEMPTY
LEUART0TXEMPTY
0b0000
I2C0RXDATAV
I2C0RXDATAV REQ/SREQ
0b0001
I2C0TXBL
I2C0TXBL REQ/SREQ
0b0000
TIMER0UFOF
TIMER0UFOF
0b0001
TIMER0CC0
TIMER0CC0
0b0010
TIMER0CC1
TIMER0CC1
0b0011
TIMER0CC2
TIMER0CC2
0b0000
TIMER1UFOF
TIMER1UFOF
0b0001
TIMER1CC0
TIMER1CC0
0b0010
TIMER1CC1
TIMER1CC1
0b0011
TIMER1CC2
TIMER1CC2
0b0100
TIMER1CC3
TIMER1CC3
MSCWDATA
MSCWDATA
0b0000
CRYPTODATA0WR
CRYPTODATA0WR
0b0001
CRYPTODATA0XWR
CRYPTODATA0XWR
0b0010
CRYPTODATA0RD
CRYPTODATA0RD
0b0011
CRYPTODATA1WR
CRYPTODATA1WR
0b0100
CRYPTODATA1RD
CRYPTODATA1RD
SOURCESEL =
0b010000
(LEUART0)
SOURCESEL =
0b010100 (I2C0)
SOURCESEL
=
0b011000 (TIMER0)
SOURCESEL
=
0b011001 (TIMER1)
SOURCESEL =
0b110000 (MSC)
0b0000
SOURCESEL
=
0b110001 (CRYPTO)
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LDMA - Linked DMA Controller
7.6.18 LDMA_CHx_CFG - Channel Configuration Register
Name
Reset
31:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21
DSTINCSIGN
0
Value
Mode
Description
0
POSITIVE
Increment destination address
1
NEGATIVE
Decrement destination address
SRCINCSIGN
0
Value
Mode
Description
0
POSITIVE
Increment source address
1
NEGATIVE
Decrement source address
19:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
ARBSLOTS
0x0
RW
RW
RW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
RW 0x0
ARBSLOTS
Bit
20
Access
18
19
20
0
21
0
Name
SRCINCSIGN RW
Access
DSTINCSIGN RW
Reset
22
23
24
25
26
27
28
29
30
0x084
Bit Position
31
Offset
Description
Destination Address Increment Sign
Source Address Increment Sign
Arbitration Slot Number Select
For channels using round robin arbitration, this bit-field is used to select the number of slots in the round robin queue.
15:0
Value
Mode
Description
0
ONE
One arbitration slot selected
1
TWO
Two arbitration slots selected
2
FOUR
Four arbitration slots selected
3
EIGHT
Eight arbitration slots selected
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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LDMA - Linked DMA Controller
7.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register
0
1
2
3
4
LOOPCNT RWH 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x088
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
LOOPCNT
0x00
RWH
Description
Linked Structure Sequence Loop Counter
This bit-field specifies the number of iterations when using looping descriptors. Software should write to LOOPCNT before
using a looping descriptor.
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RWH
RWH
RWH
RWH 0x000 9
DONEIFSEN
BLOCKSIZE
BYTESWAP
XFERCNT
R
RWH
REQMODE
STRUCTTYPE
0
DECLOOPCNT RWH
W1
0
RWH
IGNORESREQ
0x0
0
0
0x0
0
0x0
0
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Offset
STRUCTREQ
0
RWH
SRCINC
0x0
28
RWH
29
SIZE
0x0
30
RWH
0
31
DSTINC
R
Name
SRCMODE
Access
0
Reset
R
0x08C
DSTMODE
LDMA - Linked DMA Controller
EFM32JG1 Reference Manual
7.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register
Bit Position
Preliminary Rev. 0.2 | 135
EFM32JG1 Reference Manual
LDMA - Linked DMA Controller
Bit
Name
Reset
Access
Description
31
DSTMODE
0
R
Destination Addressing Mode
This field specifies the destination addressing mode of linked descriptors. After loading a linked descriptor, reading this field
will indicate the destination addressing mode of the linked descriptor. Note that the first descriptor always uses absolute
addressing mode.
30
Value
Mode
Description
0
ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1
RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of
the destination data.
SRCMODE
0
R
Source Addressing Mode
This field specifies the source addressing mode of linked descriptors. After loading a linked descriptor, reading this field will
indicate the source addressing mode of the linked descriptor. Note that the first descriptor always uses absolute addressing
mode.
29:28
Value
Mode
Description
0
ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1
RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of
the source data.
DSTINC
0x0
RWH
Destination Address Increment Size
This bit-field specifies the stride or number of unit data addresses to increment the destination address after each unit of
data is transferred. The unit data width is controlled by the SIZE bit-field and can be a byte, half-word or word.
27:26
Value
Mode
Description
0
ONE
Increment destination address by one unit data size after each write
1
TWO
Increment destination address by two unit data sizes after each write
2
FOUR
Increment destination address by four unit data sizes after each write
3
NONE
Do not increment the destination address. Writes are made to a fixed
destination address, for example writing to a FIFO.
SIZE
0x0
RWH
Unit Data Transfer Size
This field specifies the size of data transferred.
25:24
Value
Mode
Description
0
BYTE
Each unit transfer is a byte
1
HALFWORD
Each unit transfer is a half-word
2
WORD
Each unit transfer is a word
SRCINC
0x0
RWH
Source Address Increment Size
This bit-field specifies the stride or number of unit data addresses to increment the source address after each unit of data is
transferred. The unit data width is controlled by the SIZE bit-field and can be a byte, half-word or word.
Value
Mode
Description
0
ONE
Increment source address by one unit data size after each read
1
TWO
Increment source address by two unit data sizes after each read
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LDMA - Linked DMA Controller
Bit
23
Name
Reset
Access
2
FOUR
Increment source address by four unit data sizes after each read
3
NONE
Do not increment the source address. In this mode reads are made
from a fixed source address, for example reading FIFO.
IGNORESREQ
0
RWH
Description
Ignore Sreq
The channel arbiter will ignore single requests (SREQ) and only respond to multiple requests (REQ) when this bit is set.
22
DECLOOPCNT
0
RWH
Decrement Loop Count
When using looping, setting this bit will decrement the LOOPCNT field in the LDMA_CHx_LOOP register after each descriptor execution.
21
20
REQMODE
0
RWH
Value
Mode
Description
0
BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1
ALL
One transfer request transfers all units as defined by the XFRCNT
field.
DONEIFSEN
0
RWH
DMA Request Transfer Mode Select
DMA Operation Done Interrupt Flag Set Enable
Setting this bit will set the interrupt flag when the transfer is done, or linked in the case where the LINK bit is set, or
synchronized in the case of a SYNC transfer.
19:16
BLOCKSIZE
0x0
RWH
Block Transfer Size
This bit-field controls the number of unit data transfers per arbitration cycle
15
Value
Mode
Description
0
UNIT1
One unit transfer per arbitration
1
UNIT2
Two unit transfers per arbitration
2
UNIT3
Three unit transfers per arbitration
3
UNIT4
Four unit transfers per arbitration
4
UNIT6
Six unit transfers per arbitration
5
UNIT8
Eight unit transfers per arbitration
7
UNIT16
Sixteen unit transfers per arbitration
9
UNIT32
32 unit transfers per arbitration
10
UNIT64
64 unit transfers per arbitration
11
UNIT128
128 unit transfers per arbitration
12
UNIT256
256 unit transfers per arbitration
13
UNIT512
512 unit transfers per arbitration
14
UNIT1024
1024 unit transfers per arbitration
15
ALL
Transfer all units as specified by the XFRCNT field
BYTESWAP
0
RWH
Endian Byte Swap
For word and half-word transfers, setting this bit will swap all bytes of each word or half-word.
14:4
XFERCNT
0x000
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RWH
DMA Unit Data Transfer Count
Preliminary Rev. 0.2 | 137
EFM32JG1 Reference Manual
LDMA - Linked DMA Controller
Bit
Name
Reset
Access
Description
Specifies number of unit data (words, half-words, or bytes) to transfer, as determined by the SIZE field. The value written
should be one less than the desired transfer count.
3
STRUCTREQ
0
W1
Structure DMA Transfer Request
When a linked descriptor is loaded with this bit set, it will immediately trigger a transfer.
2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1:0
STRUCTTYPE
0x0
Value
Mode
Description
0
TRANSFER
DMA transfer structure type selected.
1
SYNCHRONIZE
Synchronization structure type selected.
2
WRITE
Write immediate value structure type selected.
R
DMA Structure Type
7.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SRCADDR RWH 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x090
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
SRCADDR
0x00000000
RWH
Source Data Address
Writing to this register sets the source address. Reading from this register during a DMA transfer will indicate the next
source read address. The value of this register is incremented or decremented with each source read.
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LDMA - Linked DMA Controller
7.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DSTADDR RWH 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x094
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
DSTADDR
0x00000000
RWH
Destination Data Address
Writing to this register sets the destination address. Reading from this register during a DMA transfer will indicate the next
destination write address. This value of this register is incremented or decremented with each destination write.
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LDMA - Linked DMA Controller
7.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register
Name
Bit
Name
Reset
Access
Description
31:2
LINKADDR
0x00000000
RWH
Link Structure Address
0
0
1
0
2
3
4
6
7
8
5
RWH
R
LINKMODE
LINKADDR
Access
LINK
Reset
9
10
11
12
13
14
15
16
17
RWH 0x00000000
18
19
20
21
22
23
24
25
26
27
28
29
30
0x098
Bit Position
31
Offset
To use linking, write the address of the the first linked descriptor to this register. When a linked descriptor is loaded, it may
also be linked to another descriptor. Reading this register will reflect the address of the next linked descriptor.
1
LINK
0
RWH
Link Next Structure
After completing the initial transfer, if this bit is set, the DMA will load the next linked descriptor. If the next linked descriptor
also has this bit set, the DMA will load the next linked descriptor.
0
LINKMODE
0
R
Link Structure Addressing Mode
This field specifies the addressing mode of linked descriptors. After loading a linked descriptor, reading this field will indicate the addressing mode of the loaded linked descriptor. Note that the first descriptor always uses absolute addressing
mode.
Value
Mode
Description
0
ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1
RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of
the linked descriptor.
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RMU - Reset Management Unit
8. RMU - Reset Management Unit
Quick Facts
What?
0 1 2 3
4
The RMU ensures correct reset operation. It is responsible for connecting the different reset sources
to the reset lines of the EFM32 Jade Gecko.
Why?
A correct reset sequence is needed to ensure safe
and synchronous startup of the EFM32 Jade Gecko.
In the case of error situations such as power supply
glitches or software crash, the RMU provides proper
reset and startup of the EFM32 Jade Gecko.
RESETn
POWERON
BROWNOUT
Reset Management Unit
RESET
LOCKUP
SYSRESETREQ
WATCHDOG
How?
The Power-on Reset and Brown-out Detector of the
EFM32 Jade Gecko provides power line monitoring
with exceptionally low power consumption. The
cause of the reset may be read from a register, thus
providing software with information about the cause
of the reset.
8.1 Introduction
The RMU is responsible for handling the reset functionality of the EFM32 Jade Gecko.
8.2 Features
• Reset sources
• Power-on Reset (POR)
• Brown-out Detection (BOD) on the following power domains:
• Analog Unregulated Power Domain AVDD
• Digital Unregulated Power Domain DVDD
• Regulated Digital Domain DECOUPLE (DEC)
• RESETn pin reset
• Watchdog reset
• EM4 Hibernate/Shutoff wakeup reset from GPIO pin
• Software triggered reset (SYSRESETREQ)
• Core LOCKUP condition
• EM4 Hibernate/Shutoff Detection
• Configurable reset levels
• A software readable register indicates the cause of the last reset
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RMU - Reset Management Unit
8.3 Functional Description
The RMU monitors each of the reset sources of the EFM32 Jade Gecko. If one or more reset sources go active, the RMU applies reset
to the EFM32 Jade Gecko. When the reset sources go inactive the EFM32 Jade Gecko starts up. At startup the EFM32 Jade Gecko
loads the stack pointer and program entry point from memory, and starts execution. Figure 8.1 RMU Reset Input Sources and Connections on page 142 shows an overview of the reset system on EFM32 Jade Gecko.
Lockbit
PAD_RESETn
Reset Management Unit
EXTRSTTn
Filter
POR
PORESETn
EMU
RMU
PORSTn
AVDD
BOD
DVDD
BOD
DEC
BOD
AVDDBODn
FULLRESETn
DVDDBODn
FULLRESTn
CRYOTIMER,
LFOSC Ctrl
DECBODn
EXRST
WDOGRST
EM4H/EM4S
Wakeup Resetn
Enable
Full
Reset
LOCKUPRST
SYSREQRST
DEBUGRESETn
Debug Interface
EXTRST
EXTENDEDRESETn
WDOGRST
Enable
LOCKUPRST Extended
Reset
SYSREQRST
SYSEXTENDEDRESETn
EM4S
only
RTCC
VMON
EXTRST
WDOGRST
LOCKUPRST
SYSREQRST
Enable
Limited
Reset
LIMITEDRESETn
SYSRESETn
CORE,
CMU,
and
Peripherals
EM4H/EM4S
Wakeup Resetn
EM4 Pin Wakeup cause
SYSNORETRESETn
RCCLR
RMU_RSTCAUSE
Enabled
Reset
EM4
CACHE
EM23 Wakeup
Resetn
EM23 and
Subsystem
Figure 8.1 RMU Reset Input Sources and Connections
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RMU - Reset Management Unit
8.3.1 Reset levels
The reset sources on EFM32 Jade Gecko can be divided in two main groups; Hard resets and Soft resets.
The soft resets can be configured to be either DISABLED, LIMITED, EXTENDED or FULL. The reset level for soft reset sources is
configured in the xxxRMODE bitfields in RMU_CTRL.
Table 8.1. Reset levels
RMU_CTRL_xxxRMODE
Parts of system reset
DISABLED
Nothing is reset, request will not be registered in
RMU_RSTCAUSE
LIMITED
Everything reset, with exception of CRYOTIMER, DEBUGGER,
RTCC, VMON and parts of CMU, RMU and EMU.
EXTENDED
Everything reset, with exception of CRYOTIMER, DEBUGGER,
and parts of CMU, RMU and EMU.
FULL
Everything reset, with exception of some registers in RMU and
EMU.
The reset sources resulting in a soft reset are:
• Watchdog reset
• Lockup reset
• System reset request
• Pin reset1
1
Pin reset can be configured to be either a soft or a hard reset, see 8.3.5 RESETn pin Reset for details
Note: LIMITED and EXTENDED resets are synchronized to HFSRCCLK. If HFSRCCLK is slow, there will be latency on reset assertion.
If HFSRCCLK is not running, reset will be asserted after a timeout.
Hard resets will reset the entire chip, the reset sources resulting in a hard reset are:
• Power-on reset
• Brown-out reset
• Pin reset1
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RMU - Reset Management Unit
8.3.2 RMU_RSTCAUSE Register
Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may
investigate this register in order to determine the cause of the reset. The register is cleared upon POR and software write to
RMU_CMD_RCCLR. The register should be cleared after the value has been read at startup, otherwise the register may indicate multiple causes for the reset at next startup.
RMU_RSTCAUSE should be interpreted according to Table 8.2 RMU Reset Cause Register Interpretation on page 144. In Table
8.2 RMU Reset Cause Register Interpretation on page 144, the reset causes are ordered by severity from right to left. A reset cause bit
is invalidated (i.e. can not be trusted) one of the bits to the right of it does not match the table. X bits are don't care.
Note:
Notice that it is possible to have multiple reset causes. For example, an external reset and a watchdog reset may happen simultaneously.
Table 8.2. RMU Reset Cause Register Interpretation
RMU_RSTCAUSE
EM4R
ST
1
Reset cause
SYSWDOG
REQR
RST
ST
LOCKEXTRS DECUPRS
T
BOD
T
DVDD
BOD
AVDD- PORS
BOD
T
X
X
X
X
X
X
X
X
1
Power on reset
X
X
X
X
X
X
X
1
0
Brown-out on AVDD power
X
X
X
X
X
X
1
X
0
Brown-out on DVDD power
X
X
X
X
X
1
X
X
0
Brown-out on DEC power
X
X
X
X
1
X
X
X
0
Pin reset
X
X
X
1
0/X1
0
0
0
0
Lockup reset
X
X
1
X
0/X1
0
0
0
0
System reset request
X
1
X
X
0/X1
0
0
0
0
Watchdog reset
1
X
X
X
0/X1
0
0
0
0
System has been in EM4
Pin reset configured as hard/soft
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RMU - Reset Management Unit
8.3.3 Power-On Reset (POR)
The POR ensures that the EFM32 Jade Gecko does not start up before the supply voltage VDD has reached the threshold voltage
VPORthr (see Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, the EFM32 Jade Gecko
is kept in reset state. The operation of the POR is illustrated in Figure 8.2 RMU Power-on Reset Operation on page 145, with the active
low POWERONn reset signal. The reason for the “unknown” region is that the corresponding supply voltage is too low for any reliable
operation.
V
VDD
VPORthr
POWERONn
Unknown
time
Figure 8.2 RMU Power-on Reset Operation
8.3.4 Brown-Out Detector (BOD)
The EFM32 Jade Gecko The BODs also include hysteresis, which prevents instability in the corresponding BROWNOUTn line when
the supply is crossing the VBODthr limit or the AVDD bods drops below decouple pin (DEC). The operation of the BOD is illustrated in
Figure 8.3 RMU Brown-out Detector Operation on page 145. The “unknown” regions are handled by the POR module.
V
VBODhyst
VBODthr
VBODhyst
VDD
BROWNOUTn
Unknown
Unknown
time
Figure 8.3 RMU Brown-out Detector Operation
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RMU - Reset Management Unit
8.3.5 RESETn pin Reset
The pin reset on EFM32 Jade Gecko can be configured to be either hard or soft. By default, pin reset is configured as a soft reset
source. To configure it as a hard reset, clear the PINRESETSOFT bit in CLW0 in the Lock bit page, see 6.3.2 Lock Bits (LB) Page
Description for details. Forcing the RESETn pin low generates a reset of the EFM32 Jade Gecko. The RESETn pin includes an on-chip
pull-up resistor, and can therefore be left unconnected if no external reset source is needed. Also connected to the RESETn line is a
filter which prevents glitches from resetting the EFM32 Jade Gecko.
8.3.6 Watchdog Reset
The Watchdog circuit is a timer which (when enabled) must be cleared by software regularly. If software does not clear it, a Watchdog
reset is activated. This functionality provides recovery from a software stalemate. Refer to the Watchdog section for specifications and
description. The Watchdog reset can be configured to cause different levels of reset as determined by WDOGRMODE in the
RMU_CTRL register.
8.3.7 Lockup Reset
A Cortex-M3 lockup is the result of the core being locked up because of an unrecoverable exception following the activation of the processor’s built-in system state protection hardware.
A Cortex-M3 lockup gives immediate indication of seriously errant kernel software. This is the result of the core being locked up due to
an unrecoverable exception following the activation of the processor’s built in system state protection hardware. For more information
about the Cortex-M3 lockup conditions see the ARMv7-M Architecture Reference Manual. The Lockup reset does not reset the Debug
Interface, unless configured as a FULL reset. The Lockup reset can be configured to cause different levels of reset as determined by
the LOCKUPRMODE bits in the RMU_CTRL register. This includes disabling the reset.
8.3.8 System Reset Request
Software may initiate a reset (e.g. if it finds itself in a non-recoverable state). By asserting the SYSRESETREQ in the Application Interrupt and Reset Control Register, a reset is issued. The SYSRESETREQ does not reset the Debug Interface, unless configured as a
FULL reset. The SYSRESTREQ reset can be configured to cause different levels of reset as determined by SYSRESETRMODE bits in
the RMU_CTRL register. This includes disabling the reset.
8.3.9 Reset state
The RESETSTATE bitfield in RMU_CTRL is a read-write register intended for software use only, and can be used to keep track of state
throughout a reset. This bitfield if only reset by POR and hard pin reset.
8.3.10 Registers with alternate reset
Figure 8.1 RMU Reset Input Sources and Connections on page 142 shows an overview of how the different parts of the design are
affected by the different levels of reset. For RMU, EMU and CMU there are some exceptions. These are given in the following tables.
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RMU - Reset Management Unit
8.4 Registers with alternate reset
Alternate reset for registers in RMU
RMU reset levels
POR and hard pin reset
RMU_CTRL
Alternate reset for registers in CMU
CMU reset levels
FULL reset
CMU_LFRCOCTRL
CMU_LFXOCTRL
EXTENDED reset
CMU_LFECLKSEL
CMU_LFECLKEN0
CMU_LFEPRESC0
Alternate reset for registers in EMU
EMU reset levels
POR, BOD, and hard pin reset
EMU_PWRCTRL
EMU_DCDCCTRL
EMU_DCDCMISCCTRL
EMU_DCDCZDETCTRL
EMU_DCDCCLIMCTRL
EMU_DCDCTIMING
EMU_DCDCLPVCTRL
EMU_DCDCLPCTRL
EMU_DCDCLNFREQCTRL
EXTENDED reset
EMU_VMONAVDDCTRL
EMU_VMONALTAVDDCTRL
EMU_VMONDVDDCTRL
EMU_VMONIO0CTRL
FULL reset
EMU_EM4CTRL
EMU_PWRCFG
EMU_DCDCLNVCTRL_LNATT
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RMU - Reset Management Unit
8.5 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
RMU_CTRL
RW
Control Register
0x004
RMU_RSTCAUSE
R
Reset Cause Register
0x008
RMU_CMD
W1
Command Register
0x00C
RMU_RST
RW
Reset Control Register
0x010
RMU_LOCK
RWH
Configuration Lock Register
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RMU - Reset Management Unit
8.6 Register Description
8.6.1 RMU_CTRL - Control Register
0
RW 0x4 1
WDOGRMODE
2
3
4
LOCKUPRMODE RW 0x2 5
6
7
8
RW 0x2 9
SYSRMODE
10
11
12
14
15
16
17
18
19
20
21
RW 0x4 13
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22
23
24
25
26
27
28
29
PINRMODE
Name
RW 0x0
Access
RESETSTATE
Reset
30
0x000
Bit Position
31
Offset
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RMU - Reset Management Unit
Bit
Name
Reset
Access
31:26
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
25:24
RESETSTATE
0x0
RW
Description
System Software Reset State
Bit-field for software use only. This field has no effect on the RMU and is reset by power-on reset and hard pin reset only.
23:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14:12
PINRMODE
0x4
RW
PIN Reset Mode
Controls the reset level for Pin reset request. These settings only apply when PINRESETSOFT in CLW0 in the Lock bit
page is set.
Value
Mode
Description
0
DISABLED
Reset request is blocked.
1
LIMITED
The CRYOTIMER, DEBUGGER, RTCC, are not reset.
2
EXTENDED
The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.
4
FULL
The entire device is reset except some EMU and RMU registers.
11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10:8
SYSRMODE
0x2
RW
Core Sysreset Reset Mode
Controls the reset level for Core SYSREST reset request.
Value
Mode
Description
0
DISABLED
Reset request is blocked.
1
LIMITED
The CRYOTIMER, DEBUGGER, RTCC, are not reset.
2
EXTENDED
The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.
4
FULL
The entire device is reset except some EMU and RMU registers.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:4
LOCKUPRMODE
0x2
RW
Core LOCKUP Reset Mode
Controls the reset level for Core LOCKUP reset request.
Value
Mode
Description
0
DISABLED
Reset request is blocked.
1
LIMITED
The CRYOTIMER, DEBUGGER, RTCC, are not reset.
2
EXTENDED
The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.
4
FULL
The entire device is reset except some EMU and RMU registers.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
WDOGRMODE
0x4
RW
WDOG Reset Mode
Controls the reset level for WDOG reset request.
Value
Mode
Description
0
DISABLED
Reset request is blocked. This disable bit is redundant with enable/
disable bit in WDOG
1
LIMITED
The CRYOTIMER, DEBUGGER, RTCC, are not reset.
2
EXTENDED
The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.
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RMU - Reset Management Unit
Bit
Name
Reset
4
FULL
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Access
Description
The entire device is reset except some EMU and RMU registers.
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RMU - Reset Management Unit
8.6.2 RMU_RSTCAUSE - Reset Cause Register
Access
0
R
PORST
0
1
2
3
R
AVDDBOD
0
R
DVDDBOD
Bit
Name
Reset
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
EM4RST
0
R
0
4
R
DECBOD
0
5
6
7
8
0
R
EXTRST
9
0
LOCKUPRST R
10
0
SYSREQRST R
11
12
0
R
WDOGRST
13
14
15
16
17
0
Name
R
Access
EM4RST
Reset
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Description
EM4 Reset
Set if the system has been in EM4. Must be cleared by software. Please see Table 8.2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit.
15:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
WDOGRST
0
R
Watchdog Reset
Set if a watchdog reset has been performed. Must be cleared by software. Please see Table 8.2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit.
10
SYSREQRST
0
R
System Request Reset
Set if a system request reset has been performed. Must be cleared by software. Please see Table 8.2 RMU Reset Cause
Register Interpretation on page 144 for details on how to interpret this bit.
9
LOCKUPRST
0
R
LOCKUP Reset
Set if a LOCKUP reset has been requested. Must be cleared by software. Please see Table 8.2 RMU Reset Cause Register
Interpretation on page 144 for details on how to interpret this bit.
8
EXTRST
0
R
External Pin Reset
Set if an external pin reset has been performed. Must be cleared by software. Please see Table 8.2 RMU Reset Cause
Register Interpretation on page 144 for details on how to interpret this bit.
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
DECBOD
0
R
Brown Out Detector Decouple Domain Reset
Set if a regulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table
8.2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit.
3
DVDDBOD
0
R
Brown Out Detector DVDD Reset
Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table
8.2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit.
2
AVDDBOD
0
R
Brown Out Detector AVDD Reset
Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table
8.2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
PORST
0
R
Power On Reset
Set if a power on reset has been performed. Must be cleared by software. Please see Table 8.2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit.
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RMU - Reset Management Unit
8.6.3 RMU_CMD - Command Register
3
2
1
0
3
2
1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
RCCLR W1 0
Reset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
RCCLR
0
W1
Description
Reset Cause Clear
Set this bit to clear the RSTCAUSE register.
8.6.4 RMU_RST - Reset Control Register
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
31:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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Description
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RMU - Reset Management Unit
8.6.5 RMU_LOCK - Configuration Lock Register
0
1
2
3
4
5
6
7
8
LOCKKEY RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0000
RWH
Description
Configuration Lock Key
Write any other value than the unlock code to lock RMU_CTRL and RMU_RST from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.
Mode
Value
Description
UNLOCKED
0
RMU registers are unlocked
LOCKED
1
RMU registers are locked
LOCK
0
Lock RMU registers
UNLOCK
0xE084
Unlock RMU registers
Read Operation
Write Operation
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EMU - Energy Management Unit
9. EMU - Energy Management Unit
Quick Facts
What?
The EMU (Energy Management Unit) handles the
different low energy modes in EFM32 Jade Gecko
Why?
0 1 2 3
4
The need for performance and peripheral functions
varies over time in most applications. By efficiently
scaling the available resources in real-time to match
the demands of the application, the energy consumption can be kept at a minimum.
How?
With a broad selection of energy modes, a high
number of low-energy peripherals available even in
EM2 DeepSleep, and short wake-up time (2 µs from
EM2 DeepSleep and EM3 Stop), applications can
dynamically minimize energy consumption during
program execution.
9.1 Introduction
The Energy Management Unit (EMU) manages all the low energy modes (EM) in EFM32 Jade Gecko. Each energy mode manages if
the CPU and the various peripherals are available. The energy modes range from EM0 Active to EM4 Shutoff. EM0 Active mode provides the highest amount of features enabling the CPU, and peripherals with highest clock frequency. While EM4 Shutoff Mode provides the lowest power state allowing the part to return to EM0 Active on a wakeup condition. The EMU also controls the various power
routing configurations, internal regulators settings, and voltage monitoring needed for optimal power configuration and protection.
9.2 Features
The primary features of the EMU are listed below:
• Energy Modes control
• Entering EM4 Hibernate or EM4 Shutoff
• Configure the regulators and clocks for each Energy Mode
• Configure various EM4 Hibernate/Shutoff wakeup conditions
• Configure RAM power and retention settings
• Configure GPIO retention settings
• Power routing configurations
• DCDC control
• Internal power switches allowing for extensible system power architecture
• Temperature measurement control and status
• Brown Out Detection
• Voltage Monitoring
• Four dedicated continous monitor channels
• Optional monitor features include interrupt generation, low power mode wakeup, EM4 Entry,&
• State Retention
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EMU - Energy Management Unit
9.3 Functional Description
he EMU is responsible for managing the wide range of energy modes available in EFM32 Jade Gecko. The block works in harmony
with the entire platform to easily transition between energy modes in the most efficient manner possible. The following diagram Figure
9.1 EMU Overview on page 156, shows the relative connectivity to the various blocks in the system.
Peripheral bus
Memory
System
Control and
Status Registers
Energy Management Unit
State Machine & Control
Oscillators
Voltage
Regulators
CPU Core
(Not all devices)
PRS
Interrupt
Handler
The combined state of these modules
defines the required energy mode
Figure 9.1 EMU Overview
The EMU is available on the peripheral bus. The energy management state machine controls the internal voltage regulators, oscillators,
memories and interrupt system. Events, interrupts and resets can trigger the energy management state machine to return to the active
state. This is further described in the following sections.
The power architecture is highly configurable to meet system power performance needs. Several external power configurations are
supported. The EMU allows flexible control of internal DCDC, Digital Regulator (DIGREG), and internal power switching.
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EMU - Energy Management Unit
9.3.1 Energy Modes
EFM32 Jade Gecko features six main energy modes, referred to as Energy Mode 0 (EM0 Active) through Energy Mode 4 (EM4 Shutoff). The Cortex-M3 is only available for program execution in EM0 Active. In EM0 Active/EM1 Sleep any peripheral function can be
enabled. EM2 DeepSleep through EM4 Shutoff, also referred to as low energy modes, provide a significantly reduced energy consumption while still allowing a rich set of peripheral functionality. The following Table 9.1 table on page 157 shows the possible transitions
between different energy modes.
Table 9.1. Energy Mode Transitions
Current Mode
EM Transition Action
Enter EM0 Ac- Enter EM1
tive
Sleep
EM0 Active
Sleep (WFI,
WFE)
EM1 Sleep
IRQ
EM2 DeepSleep
IRQ
Peripheral
wake up req1
EM3 Stop
IRQ
Peripheral
wake up req1
EM4 Hibernate
Wake Up
EM4 Shutoff
Wake Up
1
Enter EM2
DeepSleep
EnterEM3
Stop
EnterEM4 Hibernate
Enter EM4
Shutoff
Deep Sleep
(WFI, WFE)
Deep Sleep
(WFI, WFE)
EM4 Entry
EM4 Entry
Peripheral
Peripheral
wake up done1 wake up done1
Peripheral wakeup from EM2/3 to EM1 and then automatically back to EM2/3 when done.
The ADC, and LEUART have the ability to temporarily wakeup up the part from either EM2 DeepSleep or EM3 Stop to EM1 Sleep in
order to transfer data. Once completed, the part is automatically placed back into the EM2 DeepSleep or EM3 Stop mode.
The Core can always request to go to EM1 Sleep with the WFI or WFE command during EM0 Active. The core will be prevented from
entering EM2 DeepSleep, EM3 Stop, EM4 Hibernate, or EM4 Shutoff if Flash is programming or erasing.
An overview of supported energy modes and available functionality is shown in Table 9.2 Table 2. EMU Energy Mode Overview on
page 157. By default, the system is configured in the lowest configuration within each energy mode. Functionality may be selectively
enabled.
Table 9.2. EMU Energy Mode Overview
EM0 Active
EM1 Sleep
EM2 DeepSleep
EM3 Stop
EM4 Hibernate
EM4 Shutoff
Wakeup time to EM0 Active/EM1 Sleep
-
-
2 µs 1
2 µs 1
160 µs 1
160 µs 1
Core Active
On
-
-
-
-
-
High frequency clock and peripherals
Available
Available
-
-
-
-
High frequency oscillator
Available
Available
Available2
-
-
-
Low frequency clock and peripherals
Available
Available
Available
-
Available
Available
Low frequency oscillator
Available
Available
Available
Available
Available
Available
Ultra low frequency clock and peripherals
on
Available
Available
Available
Available
Available
Available
Digital logic and system RAM retained
Available
Available
Available
Available
-
-
RTCC RAM Retained
Available
Available
Available
Available
Available
-
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EM0 Active
EM1 Sleep
EM2 DeepSleep
EM3 Stop
EM4 Hibernate
EM4 Shutoff
LEUART (Low Energy UART)
Available
Available
Available
-
-
-
I2C
Available
Available
Available3
Available3
-
-
ACMP (Analog Comparator)
Available
Available
Available4
Available4
-
-
PCNT (Pulse Counter)
Available
Available
Available
Available
-
-
LETIMER (Low Energy Timer)
Available
Available
Available
Available5
-
-
WDOG (Watchdog)
Available
Available
Available
Available5
-
-
RTCC (Real Time Clock)
Available
Available
Available
Available5
Available
-
CRYOTIMER
Available
Available
Available
Available5
Available
Available
Pin interrupts
Available
Available
Available
Available
Available6
Available6
TEMPCHANGE (Temperature Change)
Available
Available
Available
Available
Available
-
VMON Wakeup or Reset
Available
Available
Available
Available
Available
-
DCDC
Available
Available
Available
Available
Available
-
BOD/Power On Reset
On
On
On
On
On
On
Pin Reset
On
On
On
On
On
On
GPIO state retention
On
On
On
On
On
On
1
approximate time. refer to datasheet
2
HFXO can be kept running in EM2 DeepSleep
3
I2C functionality limited to receive address recognition
4
ACMP functionality limited to edge interrupt
5
Must be using ULFRCO
6
Pin wakeup from selected pins.
The different Energy Modes are summarized in the following sections.
9.3.1.1 EM0 Active
EM0 Active provides all system features.
• Cortex-M3 is executing code
• High and low frequency clock trees are active
• All peripheral functionality is available
9.3.1.2 EM1 Sleep
EM1 Sleep disables the core but leaves the remaining system fully available.
• Cortex-M3 is in sleep mode. Clocks to the core are off
• High and low frequency clock trees are active
• All peripheral functionality is available
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9.3.1.3 EM2 DeepSleep
This is the first level into the low power energy modes. Most of the high frequency peripherals are disabled or have reduced functionality. Memory and registers retain their values.
• Cortex-M3 is in sleep mode. Clocks to the core are off
• High frequency clock tree is inactive
• High frequency oscillator may still be enabled for fast startup
• Low frequency clock tree are still active
• The following low frequency peripherals are available
• RTCC, WDOG, LEUART, LETIMER, PCNT, CRYOTIMER
• Wakeup to EM0 Active through
• Peripheral interrupt, reset pin, power on reset, asynchronous pin interrupt, I2C address recognition, or ACMP edge interrupt
• RAM and register values are preserved
• Options
• Ability to have DIGREG in full power mode for fast wakeup
• Selectively pick which memories to retain
9.3.1.4 EM3 Stop
This low energy mode has both high frequency and low frequency clocks stopped. Most peripherals are disabled or have reduced functionality. Memory and registers retain their values.
• Cortex-M3 is in sleep mode. Clocks to the core are off
• High frequency clock tree is inactive
• High frequency oscillator may still be enabled for fast startup
• Low frequency clock tree is inactive
• The following low frequency peripherals are available if using ULFRCO
• RTCC, WDOG, CRYOTIMER
• Wakeup to EM0 Active through
• Peripheral interrupt, reset pin, power on reset, asynchronous pin interrupt, I2C address recognition, or ACMP edge interrupt
• RAM and register values are preserved
• Options
• Ability to have DIGREG in full power mode for fast wakeup
• Selectively pick which memories to retain
9.3.1.5 EM4 Hibernate
The majority of peripherals are shutoff to reduce leakage power. A few selected peripherals are available. System memory and registers do not retain values. GPIO PAD state and RTCC RAM are retained. Wakeup from EM4 Hibernate requires a reset to the system,
returning it back to EM0 Active
• Cortex-M3 is off
• High frequency clock tree is off
• Low frequency clock tree may be active
• The following low frequency peripherals are available
• RTCC, CRYOTIMER
• Wakeup to EM0 Active through
• VMON, TEMPCHANGE, RTCC, CRYOTIMER, reset pin, power on reset, asynchronous pin interrupt
• RTCC RAM retained
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9.3.1.6 EM4 Shutoff
EM4 Shutoff is the lowest energy mode of the part. There is no retention except for GPIO PAD state. Wakeup from EM4 Shutoff requires a reset to the system, returning it back to EM0 Active
• Cortex-M3 is off
• High frequency clock tree is off
• Low frequency clock tree may be active
• The following low frequency peripherals are available
• CRYOTIMER
• Wakeup to EM0 Active through
• CRYOTIMER, reset pin, power on reset, asynchronous pin interrupt
9.3.2 Entering Low Energy Modes
The following sections describe the requirements for entering the various Energy Modes.
9.3.2.1 Entry into EM1 Sleep
Energy mode EM1 Sleep is entered when the Cortex-M3 executes the Wait For Interrupt (WFI) or Wait For Event (WFE) instruction
while the SLEEPDEEP bit the Cortex-M3 System Control Register is cleared. The MCU can re-enter sleep automatically out of an Interrupt Service Routine (ISR) if the SLEEPONEXIT bit in the Cortex-M3 System Control Register is set. Refer to ARM documentation on
entering Sleep modes.
Alternately, EM1 Sleep can be entered from either EM2 DeepSleep or EM3 Stop from a Peripheral Wakeup Request allowing transfers
from the Peripheral to System RAM. On EFM32, the ADC, or LEUART peripherals can request this wakeup event. Please refer to their
respective register specification to enable this option. The system will return back to EM2 DeepSleep or EM3 Stop once the ADC, or
LEUART have completed its transfers and processing.
During Peripheral Wakeup Request, additional system resources such as FLASH and other Peripherals can be enabled for access.
Refer to EMU_PERWUCONF for more details into system options.
9.3.2.2 Entry into EM2 DeepSleep or EM3 Stop
Energy mode EM2 DeepSleep or EM3 Stop is entered when all of the following conditions are true:
•
•
•
•
IDAC is curently not updating output.
Cortex-M3 (if present) is in DEEPSLEEP state
Flash Program/Erase Inactive
DMA done with all current requests
Entry into EM2 DeepSleep and EM3 Stop can be blocked by setting the EMU_CTRL->EM2BLOCK bit.
Note: When EM2 DeepSleep or EM3 Stop entry is blocked, the part is not able to enter a lower energy state. The core will be in a sleep
state, similar to EM1, where it is waiting for a proper interrupt of other valid wakeup event. Once the blocking conditions are removed,
then the part will automatically enter a lower energy state.
Energy mode EM2 DeepSleep is entered from EM0 Active when the Cortex-M3 executes the Wait For Interrupt (WFI) or Wait For Event
(WFE) instruction while the SLEEPDEEP bit the Cortex-M3 System Control Register is set. The MCU can re-enter DeepSleep automatically out of an Interrupt Service Routine (ISR) if the SLEEPONEXIT bit in the Cortex-M3 System Control Register is set. Refer to ARM
documentation on entering Sleep modes.
9.3.2.3 Entry into EM4 Hibernate
Energy mode EM4 Hibernate and EM4 Shutoff is entered through register access.
Entry into EM4 Hibernate/Shutoff will be blocked by setting the EMU_CTRL->EM2BLOCK bit. Software must ensure no modules are
active, such as RAC, when entering EM4 Hibernate/Shutoff.EM4CTRL->EM4STATE field must be configured to select either Hibernate
(EM4H) or Shutoff (EM4S) mode prior to entering EM4.
Software may enter EM4 Hibernate/Shutoff from EM0 Active by writing the sequence 2-3-2-3 to EM4CTRL->EM4ENTRY bit field.
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9.3.3 Exiting a Low Energy Mode
A system in EM2 DeepSleep and EM3 Stop can be woken up to EM0 Active through regular interrupt requests from active peripherals.
Since state and RAM retention is available, the EFM32 is fully restored and can continue to operate as before it went into the Low
Energy Mode.
Wakeup from EM4 Hibernate or EM4 Shutoff is performed through reset. Wakeup from a specific module must be enabled en
EMU_EM4WUCONF.
Enabled interrupts that can cause wakeup from a low energy mode are shown in Table 9.3 EMU Wakeup Triggers from Low Energy
Modes on page 161. The wakeup triggers always return the EFM32 to EM0 Active/EM1 Sleep. Additionally, any reset source will return
to EM0 Active.
Table 9.3. EMU Wakeup Triggers from Low Energy Modes
Peripheral
Wakeup Trigger
EM2 Deep- EM3 Stop
Sleep
EM4 Hiber- EM4 Shutnate
off
LEUART (Low Energy Uart)
Receive / transmit
Yes
-
-
-
LETIMER
Any enabled interrupt
Yes
-
-
-
I2C
Receive address recognition
Yes
Yes
-
-
ACMP
Any enabled edge interrupt
Yes
Yes
-
-
PCNT
Any enabled interrupt
Yes
Yes1
-
-
CRYOTIMER
Timeout
Yes
Yes
-
-
RTCC
Any enabled interrupt
Yes
Yes
Yes2
VMON
Rising or falling edge on any monitored power
Yes
Yes
Yes2
-
TEMPCHANGE
Measured temperature outside the de- Yes
fined limits
Yes
Yes2
-
CRYOTIMER
Timeout
Yes
Yes
Yes2
Yes2
Pin Interrupts
Transition
Yes
Yes
Yes23
Yes23
Reset Pin
Assertion
Yes
Yes
Yes
Yes
Power
Cycle Off/On
Yes
Yes
Yes
Yes
1
When using an external clock
2
Corresponding bit in EMU_WUEN must be set.
3
Only available on a subset of the pins. Please refer to the Data Sheet for details.
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9.3.4 Power Configurations
The EFM32 Jade Gecko allows up to 2 external hookup configurations with additional options giving flexible power architecture selection.
In order to provide the lowest power consuming solutions, the EFM32 Jade Gecko comes with a DCDC module to power internal circuits. The DCDC requires an external inductor and capacitor (please refer to the Data Sheet for preferred values).
The EFM32 Jade Gecko has 5 internal power domains: DCDC, Analog Blocks, FLASH, DVDD, and Low Voltage Digital Logic (also
referred to as DECOUPLE). Additional detail for each configuration and option is given in the following sections.
When assigning supply sources, the following requirement must be adhered to:
• VREGVDD = AVDD (Must be the highest voltage in the system)
• VREGVDD >= DVDD
• VREGVDD >= IOVDD
• DVDD >= DECOUPLE
The system boots up in a safe power state but must be immediately programmed to the desired configuration by writing to the
EMU_PWRCFG->PWRCFG bitfield. Out of POR, the PWRCFG is set to STARTUP, locking access to various power control registers.
Once written, the PWRCFG cannot be changed.
9.3.4.1 Power Configuration Selection
The following decision tree should be used to help select the best power configuration for your system.
Does your system need to be
pin backwards compatible
with legacy Gecko Products
No
Lowest power application
Yes
Power Config CFG1:
No DCDC
Yes
Power Config CFG2:
DCDC powers DVDD
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9.3.4.2 Power Configuration 0: STARTUP
The part boots up in STARTUP Power Configuration 0. This mode is the default mode and allows power up with all other power configurations. The power is bypassed internally through the DCDC module to the digital regulator. The internal digital regulator powers the
Digital Logic and connected DECOUPLE pin. All other power pins, regardless of external configuration, will be brought up to the Main
Supply. The PWRCFG register can only be written once to a valid value and is then locked. This should be done immediately out of
boot to select the proper power configuration. The DCDC and PWRCTRL registers will be locked until the PWRCFG register is configured.
VREGVDD
AVDD_*
DCDC
Main
Supply
Bypass
ON
Analog
Blocks
FLASH
Digital
Regulator
Digital
Logic
+
DCDC
Driver
VREGSW
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9.3.4.3 Power Configuration 1: No DCDC (NODCDC)
In this configuration the power is bypassed internally through the DCDC to the digital regulator. The internal digital regulator powers the
Digital Logic and connected DECOUPLE pin. The Main Supply is connected to all of the other power pins. This configuration is backward pin compatibility with legacy products where there is no dcdc.
VREGVDD
AVDD_*
DCDC
Main
Supply
Bypass
ON
Analog
Blocks
FLASH
Digital
Regulator
Digital
Logic
+
DCDC
Driver
VREGSW
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9.3.4.4 Power Configuration 2: DCDC to DVDD (DCDCTODVDD)
Power Configuration 2 allows for a lower power configuration with VDCDC connected to DVDD externally. The Analog Blocks can be
connected to the VDCDC supply internally using the ANASW register bit. This allows for a tradeoff between lower power from DCDC
vs. lower noise from Main Supply. The DCDC can be put into High Performance or Low Power mode. Additionally, the DCDC can transition back and forth between bypass mode and regulation mode, allowing for additional savings when Main Supply drops too low for
efficient regulation.
VREGVDD
AVDD_*
DCDC
Main
Supply
Bypass
MODE=OFF
Analog
Blocks
FLASH
Digital
Regulator
Digital
Logic
ANASW
+
DCDC
Driver
VREGSW
DVDD
DEC
VDCDC
L
In DCDCTODVDD power configuration, the Main Supply can drop to a level that becomes inefficient for the DCDC module to drive
VDCDC. In this case, the system can be dynamically switched into DCDC bypass mode as seen the following diagram. The DCDC is
effectively turned off. Once the Main Supply margin returns, the system can be switched back into DCDC regulation mode.
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VREGVDD
AVDD_*
DCDC
Main
Supply
Bypass
MODE=ON
Analog
Blocks
FLASH
Digital
Regulator
Digital
Logic
ANASW
+
DCDC
Driver
VREGSW
DVDD
DEC
VDCDC
L
9.3.5 IOVDD Connections and Pad state
The IOVDD can be connected to either the DCDC Output or Battery supply. When powered from the DCDC, the system must be designed with consideration into the maximum power consumption allowable from DCDC. Refer to datasheet for DCDC specification.
IOVDD must be less than or equal to AVDD.
9.3.6 DC-to-DC Interface
The EFM32 Jade Gecko features a DC-to-DC power converter which requires a single external inductor and a single external capacitor.
The converter takes the VREGVDD input voltage and converts it down to an output range between VREGVDD and 1.8V with the peak
efficency of approximately 85% in either low-noise (LN) mode or low-power (LP) mode. Refer to datasheet for DCDC specification.
The low noise (LN) controller contains an RC ramp oscillator. The ramp gets compared to an error voltage which is the difference between a feed-back sense voltage and an internal reference. The output of the comparator becomes a modulated pulse. This pulse goes
to the external LC filter in order to generate the regulated voltage. The LN controller supports load current from sub-mA to approximately 200mA.
The low power (LP) controller contains a ring oscillator which gets turned on once the feed-back voltage drops below the internal reference. The pulse train charges up the external capacitor and once the feed-back voltage is at the expected level, the osicllator turns offf.
The mode uses a comparator with hysteresis. The LP controller supports load current upto approximately 10mA.
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9.3.6.1 DC-to-DC Programming Guidelines
To enable DC-to-DC, first configure the PWRCFG register to DCDCTODVDD to unlock access to DCDC registers. Set the DCDC feedback source register, EMU_PWRCTRL->DCDCVREGSEL, to be DVDD . Set the desired output voltage level for both LP and LN
modes using translation table in the Device Information page (DI) and writing to EMU_DCDCLNVCTRL and EMU_DCDCLPCTRL registers.
Last step is to enable the DCDC by setting the DCDCMODE to LOWNOISE setting. Software can change the MODE after
DCDCCTRLBUSY bit in the DCDCSYNC register goes to zero. The EMU will automatically configure DCDC to LOWPOWER when entering EM2 DeepSleep, EM3 Stop, or EM4 Hibernate/Shutoff and revert back to DCDCMODE mode setting when exiting back to EM0
Active or EM1 Sleep.
Note: Refer to Application Note AN0948: "Power Configurations and DC-DC" for more information. Application Notes can be found on
the Silicon Labs website (www.silabs.com/32bit-appnotes) or using the [Application Notes] tile in Simplicity Studio.
9.3.7 Brown Out Detector (BOD)
9.3.7.1 AVDD BOD
The EFM32 Jade Gecko has a fast response Brown Out Detector (BOD) that are always present. These BOD ensure the minimal supply is provided to AVDD supply, which is also connected VREGVDD. System reset will be applied once triggered.
Note: In EM4 Hibernate/Shutoff a low power version of the AVDD BOD, called EM4BOD, is available to trigger a reset at level lower
than in other enery modes. All Other BOD's are disabled during EM4 Hibernate/Shutoff
9.3.7.2 DVDD and DECOUPLE BOD
Additional BODs will monitor DVDD and DECOUPLE during EM0 Active through EM3 Stop. This can cause reset to the internal logic,
but will not reset the supply selection nor RTCC.
9.3.8 Voltage Monitor (VMON)
The EFM32 features an extremely low energy Voltage Monitor (VMON) capable of running down to EM4 Hibernate. Trigger points are
preloaded but may be reconfigured.
• AVDD X 2
• DVDD
• IOVDD0
Table 9.4. VMON Events
Feature
Condition
AVDD
DVDD
DEC
IOVDD
Hysteresis (separate rise and fall
triggers)
-
Yes
-
-
-
Interrupt
Fall or Rise
Yes
Yes
Yes
Yes
Wakeup from EM4 Hibernate
Fall or Rise
Yes
Yes
Yes
Yes
The status of the VMON is reflected in the EMU_STATUS register.
The status of the sticky interrupt can be found at EMU_IF.
9.3.9 Powering off SRAM blocks
SRAM blocks may be powered off using the EMU->RAM0CTRL POWERDOWN fields. One SRAM block will always be powered on for
proper system functionality.
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9.3.10 Temperature Sensor Status
EMU provides low energy periodic temperature measurement. Temperature measurement is taken every 250ms with results stored in
EMU->TEMP register.
Note: EMU temperature sensor is always running (except in EM4 Shutoff) and is independent from ADC temperature sensor.
The EMU provides the following features around temperature changes
• Wakeup from EM4 Hibernate on Temperature Change
• Interrupt from High Level Trip
• Interrupt from Low Level Trip
9.3.11 Registers latched in EM4
The following registers will be latched when enterring EM4. After wakeup from EM4, these registers will be reset and require reprogramming prior to writing the EMU_CMD_EM4UNLATCH command.
• CMU_LFRCOCTRL
• CMU_LFXOCTRL
• CMU_LFECLKSEL
• CMU_LFECLKEN0
• CMU_LFEPRESC0
9.3.12 Register Resets
Each EMU register requires retaining state in various energy modes and power transitions and will consequently need to be reset with a
different condtion. The following reset conditions will apply to the appropriate set of registers as marked in the Register Description table.
• Reset with POR or Hard Pin Reset
• Reset with POR, Hard Pin Reset, or any BOD reset
• Reset with SYSEXTENDEDRESETn
• Reset with FULLRESETn (default)
If a register field is not marked with a specific reset condition then it is assumed to be reset with FULLRESETn.
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9.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
EMU_CTRL
RW
Control Register
0x004
EMU_STATUS
R
Status Register
0x008
EMU_LOCK
RWH
Configuration Lock Register
0x00C
EMU_RAM0CTRL
RW
Memory Control Register
0x010
EMU_CMD
W1
Command Register
0x018
EMU_EM4CTRL
RW
EM4 Control Register
0x01C
EMU_TEMPLIMITS
RW
Temperature limits for interrupt generation
0x020
EMU_TEMP
R
Value of last temperature measurement
0x024
EMU_IF
R
Interrupt Flag Register
0x028
EMU_IFS
W1
Interrupt Flag Set Register
0x02C
EMU_IFC
(R)W1
Interrupt Flag Clear Register
0x030
EMU_IEN
RW
Interrupt Enable Register
0x034
EMU_PWRLOCK
RW
Regulator and Supply Lock Register
0x038
EMU_PWRCFG
RW
Power Configuration Register.
0x03C
EMU_PWRCTRL
RW
Power Control Register.
0x040
EMU_DCDCCTRL
RW
DCDC Control
0x04C
EMU_DCDCMISCCTRL
RW
DCDC Miscellaneous Control Register
0x050
EMU_DCDCZDETCTRL
RW
DCDC Power Train NFET Zero Current Detector Control Register
0x054
EMU_DCDCCLIMCTRL
RW
DCDC Power Train PFET Current Limiter Control Register
0x05C
EMU_DCDCLNVCTRL
RWH
DCDC Low Noise Voltage Register
0x060
EMU_DCDCTIMING
RW
DCDC Controller Timing Value Register
0x064
EMU_DCDCLPVCTRL
RW
DCDC Low Power Voltage Register
0x06C
EMU_DCDCLPCTRL
RW
DCDC Low Power Control Register
0x070
EMU_DCDCLNFREQCTRL
RW
DCDC Low Noise Controller Frequency Control
0x078
EMU_DCDCSYNC
R
DCDC Read Status Register
0x090
EMU_VMONAVDDCTRL
RW
VMON AVDD Channel Control
0x094
EMU_VMONALTAVDDCTRL
RW
Alternate VMON AVDD Channel Control
0x098
EMU_VMONDVDDCTRL
RW
VMON DVDD Channel Control
0x09C
EMU_VMONIO0CTRL
RW
VMON IOVDD0 Channel Control
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9.5 Register Description
9.5.1 EMU_CTRL - Control Register
0
1
2
EM2BLOCK RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
EM2BLOCK
0
RW
Description
Energy Mode 2 Block
This bit is used to prevent the MCU to enter Energy Mode 2 or lower.
0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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9.5.2 EMU_STATUS - Status Register
Access
31:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
EM4IORET
0
R
0
R
VMONRDY
Reset
0
0
R
VMONAVDD
Name
1
0
Bit
2
3
0
R
VMONALTAVDD R
VMONDVDD
4
5
6
7
0
R
VMONIO0
Name
8
0
R
EM4IORET
VMONFVDD
R
Access
9
10
11
12
13
14
15
16
17
18
19
0
Reset
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Description
IO Retention Status
The status of IO retention. Will be set upon EM4 entry based on EM4IORETMODE in EMU_EM4CTRL. Cleared by setting
EM4UNLATCH in EMU_CMD, and can also be cleared in EM4H by the VMON.
Value
Mode
Description
0
DISABLED
IO retention is disabled.
1
ENABLED
IO retention is enbled.
19:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8
VMONFVDD
0
R
VMON VDDFLASH Channel.
Indicates the status of the VDDFLASH channel of the VMON.
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
VMONIO0
0
R
VMON IOVDD0 Channel.
Indicates the status of the IOVDD0 channel of the VMON.
3
VMONDVDD
0
R
VMON DVDD Channel.
Indicates the status of the DVDD channel of the VMON.
2
VMONALTAVDD
0
R
Alternate VMON AVDD Channel.
Indicates the status of the Alternate AVDD channel of the VMON.
1
VMONAVDD
0
R
VMON AVDD Channel.
Indicates the status of the AVDD channel of the VMON.
0
VMONRDY
0
R
VMON ready
VMON status. When high, this bit indicates that all the enabled channels are ready. When low, it indicates that one or more
of the enabled channels are not ready.
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EMU - Energy Management Unit
9.5.3 EMU_LOCK - Configuration Lock Register
0
1
2
3
4
5
6
7
8
LOCKKEY RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0000
RWH
Description
Configuration Lock Key
Write any other value than the unlock code to lock all EMU registers, except the interrupt registers and regulator control
registers, from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.
Mode
Value
Description
UNLOCKED
0
EMU registers are unlocked
LOCKED
1
EMU registers are locked
LOCK
0
Lock EMU registers
UNLOCK
0xADE8
Unlock EMU registers
Read Operation
Write Operation
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EMU - Energy Management Unit
9.5.4 EMU_RAM0CTRL - Memory Control Register
0
1
2
RAMPOWERDOWN RW 0x0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
RAMPOWERDOWN
0x0
RW
Description
RAM0 blockset power-down
RAM blockset power-down in EM23 with full access in EM01. Block 0 (address range 0x20000000-0x20003FFF) may never be powered down.
Value
Mode
Description
0
NONE
None of the RAM blocks powered down
8
BLK4
Power down RAM blocks 4 and above (address range
0x20006000-0x20007BFF)
12
BLK3TO4
Power down RAM blocks 3 and above (address range
0x20004000-0x20007BFF)
14
BLK2TO4
Power down RAM blocks 2 and above (address range
0x20002000-0x20007BFF)
15
BLK1TO4
Power down RAM blocks 1 and above (address range
0x20001000-0x20007BFF)
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EMU - Energy Management Unit
9.5.5 EMU_CMD - Command Register
0
1
2
EM4UNLATCH W1 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
EM4UNLATCH
0
W1
Description
EM4 Unlatch
When entering EM4, several registers will be latched in order to maintain constant functionality throughout EM4. Upon
wakeup, these registers will be reset and can have contradictory values to the latched values. To ensure a seamless transition from EM4 to EM0, the unlatch command should be given after properly reconfiguring these latched registers. The unlatch command can be executed after any reset condition but is only needed after EM4 wakeup.
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EMU - Energy Management Unit
9.5.6 EMU_EM4CTRL - EM4 Control Register
Access
Name
Reset
31:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
EM4ENTRY
0x0
W1
0
RW
EM4STATE
0
1
RW
RETAINLFRCO
0
3
2
0
RW
0
RW
4
5
6
7
8
9
Bit
RETAINULFRCO
Name
RETAINLFXO
EM4ENTRY
Access
EM4IORETMODE RW 0x0
Reset
10
11
12
13
14
15
16
17
W1 0x0
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Description
Energy Mode 4 Entry
This register is used to enter the Energy Mode 4 sequence. Writing the sequence 2,3,2,3,2,3,2,3,2 will enter the part into
Energy Mode 4.
15:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:4
EM4IORETMODE
0x0
RW
EM4 IO Retention Disable
Determine when IO retention will be applied and removed.
3
Value
Mode
Description
0
DISABLE
No Retention: Pads enter reset state when entering EM4
1
EM4EXIT
Retention through EM4: Pads enter reset state when exiting EM4
2
SWUNLATCH
Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention
RETAINULFRCO
0
RW
ULFRCO Retain during EM4S
Retain the ULFRCO upon EM4S entry. If set to 1, an already running ULFRCO will be retained in its running state in EM4.
ULFRCO will always be retained if EM4STATE is in EM4H.
2
RETAINLFXO
0
RW
LFXO Retain during EM4
Retain the LFXO upon EM4(SH/H) entry. If set to 1, an already running LFXO will be retained in its running state in EM4.
1
RETAINLFRCO
0
RW
LFRCO Retain during EM4
Retain the LFRCO upon EM4(S/H) entry. If set to 1, an already running LFRCO will be retained in its running state in EM4.
0
EM4STATE
0
RW
Energy Mode 4 State
When set, the system will enter Hibrenate state (EM4H) when entering EM4. In EM4H, the regulator will be on in reduced
mode allowing for RTCC. Otherwise, when entering in EM4, the regulator will be disabled allowing for lowest power mode,
Shutoff state (EM4S).
Value
Mode
Description
0
EM4S
EM4S Shutoff state
1
EM4H
EM4H Hibernate state
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EMU - Energy Management Unit
9.5.7 EMU_TEMPLIMITS - Temperature limits for interrupt generation
0
0
2
3
RW 0x00
4
5
6
7
8
9
10
Bit
Name
Reset
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
EM4WUEN
0
RW
1
Access
1
Name
TEMPLOW
EM4WUEN
Access
11
12
TEMPHIGH RW 0xFF
13
14
15
RW
0
Reset
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Description
Enable EM4 Wakeup due to low/high temerature
Enable EM4 wakeup from low or high temperature from EM4H
15:8
TEMPHIGH
0xFF
RW
Temperature High Limit
The TEMPHIGH interrupt flag is set when a periodic temperature measurement is equal to or higher than this value
7:0
TEMPLOW
0x00
RW
Temperature Low Limit
The TEMPLOW interrupt flag is set when a periodic temperature measurement is equal to or lower than this value
9.5.8 EMU_TEMP - Value of last temperature measurement
2
3
4
0xXX
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Reset
TEMP R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TEMP
0xXX
R
Description
Temperature Measurement
Value of last periodic temperature measurement. Value is asynchronously updated. Value is stable for 250ms after a Temperature based interupt and can be read with a single read operation. Otherwise, reading register not based on interrupt
generation will require reading multiple times until two consequetive values are the same.
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R
VMONAVDDFALL
R
VMONIO0FALL
R
R
VMONIO0RISE
VMONAVDDRISE
R
VMONFVDDFALL
R
R
VMONFVDDRISE
R
PFETOVERCURRENTLIMIT R
VMONALTAVDDFALL
NFETOVERCURRENTLIMIT R
VMONALTAVDDRISE
R
DCDCLPRUNNING
R
0
R
DCDCLNRUNNING
VMONDVDDFALL
0
R
DCDCINBYPASS
R
0
R
EM23WAKEUP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset
VMONDVDDRISE
0
R
0
R
TEMP
Name
TEMPLOW
Access
0
Reset
R
0x024
TEMPHIGH
EMU - Energy Management Unit
EFM32JG1 Reference Manual
9.5.9 EMU_IF - Interrupt Flag Register
Bit Position
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EFM32JG1 Reference Manual
EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
31
TEMPHIGH
0
R
Temperature High Limit Reached
Set when the value of a periodic remperature measurement is higher or equal than TEMPHIGH in EMU_TEMPLIMITS
30
TEMPLOW
0
R
Temperature Low Limit Reached
Set when the value of a periodic remperature measurement is lower or equal than TEMPHIGH in EMU_TEMPLIMITS
29
TEMP
0
R
New Temperature Measurement Valid
Set when a new periodic temperature measurement is available
28:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
EM23WAKEUP
0
R
Wakeup IRQ from EM2 and EM3
Will be set when the system wakes up from EM2 and EM3. This interrupt can be used to run initialization code need to
reconfigure the system when returning from EM2 and EM3.
23:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
DCDCINBYPASS
0
R
DCDC is in bypass
0
R
LN mode is running
DCDC is in bypass
19
DCDCLNRUNNING
This flag is set once the dcdc regulator started to run in ln mode
18
DCDCLPRUNNING
0
R
LP mode is running
This flag is set once the DCDC regulator started to run in LP mode
17
NFETOVERCURRENTLIMIT
0
R
NFET current limit hit
R
PFET current limit hit
R
VMON VDDFLASH Channel Rise
Reserved for internal use.
16
PFETOVERCURRENTLIMIT
0
Reserved for internal use.
15
VMONFVDDRISE
0
A rising edge on VMON VDDFLASH channel has been detected.
14
VMONFVDDFALL
0
R
VMON VDDFLASH Channel Fall
A falling edge on VMON VDDFLASH channel has been detected.
13:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
VMONIO0RISE
0
R
VMON IOVDD0 Channel Rise
A rising edge on VMON IOVDD0 channel has been detected.
6
VMONIO0FALL
0
R
VMON IOVDD0 Channel Fall
A falling edge on VMON IOVDD0 channel has been detected.
5
VMONDVDDRISE
0
R
VMON DVDD Channel Rise
A rising edge on VMON DVDD channel has been detected.
4
VMONDVDDFALL
0
R
VMON DVDD Channel Fall
A falling edge on VMON DVDD channel has been detected.
3
VMONALTAVDDRISE 0
R
Alternate VMON AVDD Channel Rise
A rising edge on Alternate VMON AVDD channel has been detected.
2
VMONALTAVDDFALL 0
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R
Alternate VMON AVDD Channel Fall
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EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
A falling edge on Alternate VMON AVDD channel has been detected.
1
VMONAVDDRISE
0
R
VMON AVDD Channel Rise
A rising edge on VMON AVDD channel has been detected.
0
VMONAVDDFALL
0
R
VMON AVDD Channel Fall
A falling edge on VMON AVDD channel has been detected.
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W1 0
VMONIO0FALL
W1 0
W1 0
VMONIO0RISE
VMONAVDDFALL
W1 0
VMONPAVDDFALL
W1 0
W1 0
VMONPAVDDRISE
VMONAVDDRISE
W1 0
VMONFVDDFALL
W1 0
W1 0
VMONFVDDRISE
W1 0
PFETOVERCURRENTLIMIT W1 0
VMONALTAVDDFALL
NFETOVERCURRENTLIMIT W1 0
VMONALTAVDDRISE
W1 0
DCDCLPRUNNING
W1 0
15
W1 0
DCDCLNRUNNING
VMONDVDDFALL
16
W1 0
DCDCINBYPASS
W1 0
17
W1 0
EM23WAKEUP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
19
20
21
22
23
24
25
26
27
28
29
Offset
VMONDVDDRISE
18
W1 0
30
W1 0
TEMP
Name
TEMPLOW
Access
W1 0
Reset
31
0x028
TEMPHIGH
EMU - Energy Management Unit
EFM32JG1 Reference Manual
9.5.10 EMU_IFS - Interrupt Flag Set Register
Bit Position
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EFM32JG1 Reference Manual
EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
31
TEMPHIGH
0
W1
Set TEMPHIGH Interrupt Flag
Write 1 to set the TEMPHIGH interrupt flag
30
TEMPLOW
0
W1
Set TEMPLOW Interrupt Flag
Write 1 to set the TEMPLOW interrupt flag
29
TEMP
0
W1
Set TEMP Interrupt Flag
Write 1 to set the TEMP interrupt flag
28:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
EM23WAKEUP
0
W1
Set EM23WAKEUP Interrupt Flag
Write 1 to set the EM23WAKEUP interrupt flag
23:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
DCDCINBYPASS
0
W1
Set DCDCINBYPASS Interrupt Flag
Write 1 to set the DCDCINBYPASS interrupt flag
19
DCDCLNRUNNING
0
W1
Set DCDCLNRUNNING Interrupt Flag
Write 1 to set the DCDCLNRUNNING interrupt flag
18
DCDCLPRUNNING
0
W1
Set DCDCLPRUNNING Interrupt Flag
Write 1 to set the DCDCLPRUNNING interrupt flag
17
NFETOVERCURRENTLIMIT
0
W1
Set NFETOVERCURRENTLIMIT Interrupt Flag
Write 1 to set the NFETOVERCURRENTLIMIT interrupt flag
16
PFETOVERCURRENTLIMIT
0
W1
Set PFETOVERCURRENTLIMIT Interrupt Flag
Write 1 to set the PFETOVERCURRENTLIMIT interrupt flag
15
VMONFVDDRISE
0
W1
Set VMONFVDDRISE Interrupt Flag
Write 1 to set the VMONFVDDRISE interrupt flag
14
VMONFVDDFALL
0
W1
Set VMONFVDDFALL Interrupt Flag
Write 1 to set the VMONFVDDFALL interrupt flag
13
VMONPAVDDRISE
0
W1
Set VMONPAVDDRISE Interrupt Flag
Write 1 to set the VMONPAVDDRISE interrupt flag
12
VMONPAVDDFALL
0
W1
Set VMONPAVDDFALL Interrupt Flag
Write 1 to set the VMONPAVDDFALL interrupt flag
11:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
VMONIO0RISE
0
W1
Set VMONIO0RISE Interrupt Flag
Write 1 to set the VMONIO0RISE interrupt flag
6
VMONIO0FALL
0
W1
Set VMONIO0FALL Interrupt Flag
Write 1 to set the VMONIO0FALL interrupt flag
5
VMONDVDDRISE
0
W1
Set VMONDVDDRISE Interrupt Flag
Write 1 to set the VMONDVDDRISE interrupt flag
4
VMONDVDDFALL
0
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W1
Set VMONDVDDFALL Interrupt Flag
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EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
Write 1 to set the VMONDVDDFALL interrupt flag
3
VMONALTAVDDRISE 0
W1
Set VMONALTAVDDRISE Interrupt Flag
Write 1 to set the VMONALTAVDDRISE interrupt flag
2
VMONALTAVDDFALL 0
W1
Set VMONALTAVDDFALL Interrupt Flag
Write 1 to set the VMONALTAVDDFALL interrupt flag
1
VMONAVDDRISE
0
W1
Set VMONAVDDRISE Interrupt Flag
Write 1 to set the VMONAVDDRISE interrupt flag
0
VMONAVDDFALL
0
W1
Set VMONAVDDFALL Interrupt Flag
Write 1 to set the VMONAVDDFALL interrupt flag
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(R)W1 0
VMONIO0FALL
(R)W1 0
(R)W1 0
VMONIO0RISE
VMONAVDDFALL
(R)W1 0
VMONPAVDDFALL
(R)W1 0
(R)W1 0
VMONPAVDDRISE
VMONAVDDRISE
(R)W1 0
VMONFVDDFALL
(R)W1 0
(R)W1 0
VMONFVDDRISE
(R)W1 0
PFETOVERCURRENTLIMIT (R)W1 0
VMONALTAVDDFALL
NFETOVERCURRENTLIMIT (R)W1 0
VMONALTAVDDRISE
(R)W1 0
DCDCLPRUNNING
(R)W1 0
15
(R)W1 0
DCDCLNRUNNING
VMONDVDDFALL
16
(R)W1 0
DCDCINBYPASS
(R)W1 0
17
(R)W1 0
EM23WAKEUP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
19
20
21
22
23
24
25
26
27
28
29
Offset
VMONDVDDRISE
18
(R)W1 0
30
(R)W1 0
TEMPLOW
Name
TEMP
Access
(R)W1 0
Reset
31
0x02C
TEMPHIGH
EMU - Energy Management Unit
EFM32JG1 Reference Manual
9.5.11 EMU_IFC - Interrupt Flag Clear Register
Bit Position
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EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
31
TEMPHIGH
0
(R)W1
Clear TEMPHIGH Interrupt Flag
Write 1 to clear the TEMPHIGH interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
30
TEMPLOW
0
(R)W1
Clear TEMPLOW Interrupt Flag
Write 1 to clear the TEMPLOW interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
29
TEMP
0
(R)W1
Clear TEMP Interrupt Flag
Write 1 to clear the TEMP interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
28:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
EM23WAKEUP
0
(R)W1
Clear EM23WAKEUP Interrupt Flag
Write 1 to clear the EM23WAKEUP interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
23:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
DCDCINBYPASS
0
(R)W1
Clear DCDCINBYPASS Interrupt Flag
Write 1 to clear the DCDCINBYPASS interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
19
DCDCLNRUNNING
0
(R)W1
Clear DCDCLNRUNNING Interrupt Flag
Write 1 to clear the DCDCLNRUNNING interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
18
DCDCLPRUNNING
0
(R)W1
Clear DCDCLPRUNNING Interrupt Flag
Write 1 to clear the DCDCLPRUNNING interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
17
NFETOVERCURRENTLIMIT
0
(R)W1
Clear NFETOVERCURRENTLIMIT Interrupt Flag
Write 1 to clear the NFETOVERCURRENTLIMIT interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
16
PFETOVERCURRENTLIMIT
0
(R)W1
Clear PFETOVERCURRENTLIMIT Interrupt Flag
Write 1 to clear the PFETOVERCURRENTLIMIT interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
15
VMONFVDDRISE
0
(R)W1
Clear VMONFVDDRISE Interrupt Flag
Write 1 to clear the VMONFVDDRISE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
14
VMONFVDDFALL
0
(R)W1
Clear VMONFVDDFALL Interrupt Flag
Write 1 to clear the VMONFVDDFALL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
13
VMONPAVDDRISE
0
(R)W1
Clear VMONPAVDDRISE Interrupt Flag
Write 1 to clear the VMONPAVDDRISE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
12
VMONPAVDDFALL
0
(R)W1
Clear VMONPAVDDFALL Interrupt Flag
Write 1 to clear the VMONPAVDDFALL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
11:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
7
VMONIO0RISE
0
(R)W1
Clear VMONIO0RISE Interrupt Flag
Write 1 to clear the VMONIO0RISE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
6
VMONIO0FALL
0
(R)W1
Clear VMONIO0FALL Interrupt Flag
Write 1 to clear the VMONIO0FALL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
5
VMONDVDDRISE
0
(R)W1
Clear VMONDVDDRISE Interrupt Flag
Write 1 to clear the VMONDVDDRISE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
4
VMONDVDDFALL
0
(R)W1
Clear VMONDVDDFALL Interrupt Flag
Write 1 to clear the VMONDVDDFALL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
3
VMONALTAVDDRISE 0
(R)W1
Clear VMONALTAVDDRISE Interrupt Flag
Write 1 to clear the VMONALTAVDDRISE interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
2
VMONALTAVDDFALL 0
(R)W1
Clear VMONALTAVDDFALL Interrupt Flag
Write 1 to clear the VMONALTAVDDFALL interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
1
VMONAVDDRISE
0
(R)W1
Clear VMONAVDDRISE Interrupt Flag
Write 1 to clear the VMONAVDDRISE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
0
VMONAVDDFALL
0
(R)W1
Clear VMONAVDDFALL Interrupt Flag
Write 1 to clear the VMONAVDDFALL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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RW 0
VMONIO0FALL
RW 0
RW 0
VMONIO0RISE
VMONAVDDFALL
RW 0
VMONPAVDDFALL
RW 0
RW 0
VMONPAVDDRISE
VMONAVDDRISE
RW 0
VMONFVDDFALL
RW 0
RW 0
VMONFVDDRISE
RW 0
PFETOVERCURRENTLIMIT RW 0
VMONALTAVDDFALL
NFETOVERCURRENTLIMIT RW 0
VMONALTAVDDRISE
RW 0
DCDCLPRUNNING
RW 0
15
RW 0
DCDCLNRUNNING
VMONDVDDFALL
16
RW 0
DCDCINBYPASS
RW 0
17
RW 0
EM23WAKEUP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
19
20
21
22
23
24
25
26
27
28
29
Offset
VMONDVDDRISE
18
RW 0
30
RW 0
TEMPLOW
Name
TEMP
Access
RW 0
Reset
31
0x030
TEMPHIGH
EMU - Energy Management Unit
EFM32JG1 Reference Manual
9.5.12 EMU_IEN - Interrupt Enable Register
Bit Position
Preliminary Rev. 0.2 | 186
EFM32JG1 Reference Manual
EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
31
TEMPHIGH
0
RW
TEMPHIGH Interrupt Enable
Enable/disable the TEMPHIGH interrupt
30
TEMPLOW
0
RW
TEMPLOW Interrupt Enable
Enable/disable the TEMPLOW interrupt
29
TEMP
0
RW
TEMP Interrupt Enable
Enable/disable the TEMP interrupt
28:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
EM23WAKEUP
0
RW
EM23WAKEUP Interrupt Enable
Enable/disable the EM23WAKEUP interrupt
23:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
DCDCINBYPASS
0
RW
DCDCINBYPASS Interrupt Enable
Enable/disable the DCDCINBYPASS interrupt
19
DCDCLNRUNNING
0
RW
DCDCLNRUNNING Interrupt Enable
Enable/disable the DCDCLNRUNNING interrupt
18
DCDCLPRUNNING
0
RW
DCDCLPRUNNING Interrupt Enable
Enable/disable the DCDCLPRUNNING interrupt
17
NFETOVERCURRENTLIMIT
0
RW
NFETOVERCURRENTLIMIT Interrupt Enable
Enable/disable the NFETOVERCURRENTLIMIT interrupt
16
PFETOVERCURRENTLIMIT
0
RW
PFETOVERCURRENTLIMIT Interrupt Enable
Enable/disable the PFETOVERCURRENTLIMIT interrupt
15
VMONFVDDRISE
0
RW
VMONFVDDRISE Interrupt Enable
Enable/disable the VMONFVDDRISE interrupt
14
VMONFVDDFALL
0
RW
VMONFVDDFALL Interrupt Enable
Enable/disable the VMONFVDDFALL interrupt
13
VMONPAVDDRISE
0
RW
VMONPAVDDRISE Interrupt Enable
Enable/disable the VMONPAVDDRISE interrupt
12
VMONPAVDDFALL
0
RW
VMONPAVDDFALL Interrupt Enable
Enable/disable the VMONPAVDDFALL interrupt
11:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
VMONIO0RISE
0
RW
VMONIO0RISE Interrupt Enable
Enable/disable the VMONIO0RISE interrupt
6
VMONIO0FALL
0
RW
VMONIO0FALL Interrupt Enable
Enable/disable the VMONIO0FALL interrupt
5
VMONDVDDRISE
0
RW
VMONDVDDRISE Interrupt Enable
Enable/disable the VMONDVDDRISE interrupt
4
VMONDVDDFALL
0
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RW
VMONDVDDFALL Interrupt Enable
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EMU - Energy Management Unit
Bit
Name
Reset
Access
Description
Enable/disable the VMONDVDDFALL interrupt
3
VMONALTAVDDRISE 0
RW
VMONALTAVDDRISE Interrupt Enable
Enable/disable the VMONALTAVDDRISE interrupt
2
VMONALTAVDDFALL 0
RW
VMONALTAVDDFALL Interrupt Enable
Enable/disable the VMONALTAVDDFALL interrupt
1
VMONAVDDRISE
0
RW
VMONAVDDRISE Interrupt Enable
Enable/disable the VMONAVDDRISE interrupt
0
VMONAVDDFALL
0
RW
VMONAVDDFALL Interrupt Enable
Enable/disable the VMONAVDDFALL interrupt
9.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register
0
1
2
3
4
5
6
7
8
LOCKKEY RW 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0000
RW
Description
Regulator and Supply Configuration Lock Key
Write any other value than the unlock code to lock all regulator control registers, from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled. Registers that are locked: PWRCFG, PWRCTRL and
DCDC* registers.
Mode
Value
Description
UNLOCKED
0
EMU Regulator registers are unlocked
LOCKED
1
EMU Regulator registers are locked
LOCK
0
Lock EMU Regulator registers
UNLOCK
0xADE8
Unlock EMU Regulator registers
Read Operation
Write Operation
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EMU - Energy Management Unit
9.5.14 EMU_PWRCFG - Power Configuration Register.
0
1
2
PWRCFG RW 0x0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x038
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
PWRCFG
0x0
RW
Description
Power Configuration
Update this to match the external power configuration. This field can only be written once to a non-STARTUP value.
PWRCTRL register is locked until PWRCFG is configured.
Value
Mode
Description
0
STARTUP
Power up configuration. Works with any external configuration.
1
NODCDC
DCDC Disabled. AVDD Bypassed to DVDD internally
2
DCDCTODVDD
DCDC filterred and routed to DVDD
9.5.15 EMU_PWRCTRL - Power Control Register.
0
1
2
3
4
5
6
7
8
9
10
ANASW RW 0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
ANASW
0
RW
Description
Analog Switch Selection
Determines the power supply routed to the analog supply (VDDX_ANA) used by the analog peripherals (ULFRCO, LFRCO,
LFXO, HFRCO, AUXHFRCO, VMON, IDAC, and ADC). Field can only be modified when PWRCFG == DCDCTODVDD.
Reset with POR, Hard Pin Reset, or BOD Reset.
4:0
Value
Mode
Description
0
AVDD
Select AVDD power supply
1
DVDD
Select DVDD power supply
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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EMU - Energy Management Unit
9.5.16 EMU_DCDCCTRL - DCDC Control
Bit
Name
Reset
Access
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
DCDCMODEEM4
1
RW
0
2
3
1
RW 0x0
DCDCMODE
Name
4
1
DCDCMODEEM23 RW
5
DCDCMODEEM4
Access
1
Reset
RW
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
Description
DCDC Mode EM4H
Determines the DCDC mode in EM4H.When the DCDCMODE field is set to OFF, this bit must be cleared so that the DCDC
remains off. Reset with POR, Hard Pin Reset, or BOD Reset.
4
Value
Mode
Description
0
EM4SW
DCDC mode is according to DCDCMODE field.
1
EM4LOWPOWER
DCDC mode is low power.
DCDCMODEEM23
1
DCDC Mode EM23
RW
Determines the DCDC mode in EM2 and EM3. When the DCDCMODE field is set to OFF, this bit must be cleared so that
the DCDC remains off. Reset with POR, Hard Pin Reset, or BOD Reset.
Value
Mode
Description
0
EM23SW
DCDC mode is according to DCDCMODE field.
1
EM23LOWPOWER
DCDC mode is low power.
3:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1:0
DCDCMODE
0x0
RW
Regulator Mode
Determines the operating mode of the DCDC regulator. When the DCDCMODE is set of OFF, DCDCMODEEM23 and
DCDCMODEEM4 must be cleared. Reset with POR, Hard Pin Reset, or BOD Reset.
Value
Mode
Description
0
BYPASS
DCDC regulator is operating in bypass mode.
1
LOWNOISE
DCDC regulator is operating in low noise mode.
2
LOWPOWER
DCDC regulator is operating in low power mode.
3
OFF
DCDC regulator is off. Note: DVDD must be supplied externally
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9.5.17 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register
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0
LNFORCECCM
RW
0
1
2
3
4
5
6
7
8
9
10
RW 0x7
PFETCNT
11
12
13
14
RW 0x7
NFETCNT
15
16
17
18
RW 0x0
BYPLIMSEL
19
20
LPCLIMILIMSEL RW 0x3 21
22
23
24
26
27
28
29
LNCLIMILIMSEL RW 0x3 25
Name
RW 0x3
Access
LPCMPBIAS
Reset
30
0x04C
Bit Position
31
Offset
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EMU - Energy Management Unit
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:28
LPCMPBIAS
0x3
RW
Description
LP mode comparator bias selection
LP mode comparator bias selection. Reset with POR, Hard Pin Reset, or BOD Reset.
Value
Mode
Description
0
BIAS0
Nominal load current less than 10uA.
1
BIAS1
Nominal load current less than 100uA.
2
BIAS2
Nominal load current less than 1mA.
3
BIAS3
Nominal load current less than 10mA.
27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
LNCLIMILIMSEL
0x3
RW
Current limiter current threshold selection during low noise mode
Current limiter current threshold selection while in low noise mode; current limit=5mA*PFETCNT*(1+LNCLIMILIMSEL). Reset with POR, Hard Pin Reset, or BOD Reset.
23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
22:20
LPCLIMILIMSEL
0x3
RW
Current limiter current threshold selection during low power mode
Current limiter current threshold selection while in low power mode; current limit=5mA*PFETCNT*(1+LPCLIMILIMSEL). Reset with POR, Hard Pin Reset, or BOD Reset.
19:16
BYPLIMSEL
0x0
RW
Current Limit In Bypass Mode
Set current limit in bypass mode when BYPLIMEN equals one. The limit is from 20mA to 320mA, with 20mA/step. Reset
with POR, Hard Pin Reset, or BOD Reset.
15:12
NFETCNT
0x7
RW
NFET switch number selection
NFET power switch count number. The selected number of switches are NFETCNT+1. This value applies to both LN and
LP mode. Because of this, when transitioning from LN to LP mode, software may need to update the NFETCNT setting
desired for LP mode while still in LN mode. This may cause a very momentary efficiency hit. Reset with POR, Hard Pin
Reset, or BOD Reset.
11:8
PFETCNT
0x7
RW
PFET switch number selection
PFET power switch count number. The selected number of switches are PFETCNT+1. This value applies to both LN and
LP mode. Because of this, when transitioning from LN to LP mode, software may need to update the PFETCNT setting
desired for LP mode while still in LN mode. This may cause a very momentary efficiency hit. Reset with POR, Hard Pin
Reset, or BOD Reset.
7:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
LNFORCECCM
0
RW
Force DCDC into CCM mode in low noise operation
When this bit is set, the DCDC ignores the zero-threshold detection, resulting in current flowing backwards to the supply pin
in periods of the DCDC cycle when the DCDC is lightly loaded.
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EMU - Energy Management Unit
9.5.18 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register
Access
Name
Access
Bit
Name
Reset
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:8
ZDETBLANKDLY
0x1
RW
0
1
2
3
4
ZDETILIMSEL
Reset
RW 0x3 5
6
7
8
9
ZDETBLANKDLY RW 0x1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x050
Bit Position
31
Offset
Description
Reserved for internal use. Do not change.
Reserved for internal use. Do not change.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:4
ZDETILIMSEL
0x3
RW
Reverse current limit level for zero detector
NFET zero current detector current theshold selection when LNFORCECCM equals one. The current limit is
2.5mA*(1+NFETCNT)*ZDETILIMSEL. When ZDETILIMSEL=0, it is equivalent to disabling the zero detector's reverse current monitoring when LNFORCECCM equals zero. Reset with POR, Hard Pin Reset, or BOD Reset.
3:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9.5.19 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register
Name
Access
Bit
Name
Reset
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13
BYPLIMEN
1
RW
0
1
2
3
4
5
6
7
8
9
CLIMBLANKDLY RW 0x1
RW
BYPLIMEN
Access
10
11
12
13
14
1
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x054
Bit Position
31
Offset
Description
Bypass Current Limit Enable
Bypass current limit enable. Setting this bit limits maximum current drawn from DCDC input supply while DCDC is in BYPASS mode. Reset with POR, Hard Pin Reset, or BOD Reset.
12:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:8
CLIMBLANKDLY
0x1
RW
Reserved for internal use. Do not change.
Reserved for internal use. Do not change.
7:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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EMU - Energy Management Unit
9.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register
Name
Access
0
1
2
0
Bit
Name
Reset
31:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14:8
LNVREF
0x71
RWH
3
4
6
7
8
9
10
12
5
RW
Access
LNATT
Reset
LNVREF RWH 0x71 11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x05C
Bit Position
31
Offset
Description
Low Noise Mode VREF Trim
Low noise mode Vref trim. LNATT and LNVREF set the output of the DCDC to 3*(1+LNATT)*(235.48+3.226*LNVREF).
Customers should use the emlib functions for configuring this field. Reset with POR, Hard Pin Reset, or BOD Reset.
7:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
LNATT
0
RW
Low Noise Mode Feedback Attenuation
Low noise mode feedback attenuation. Customers should use the emlib functions for configuring this field. Reset with POR,
Hard Pin Reset, or BOD Reset.
0
Value
Mode
Description
0
DIV3
Feedback Ratio is 1/3
1
DIV6
Feedback Ratio is 1/6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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EMU - Energy Management Unit
9.5.21 EMU_DCDCTIMING - DCDC Controller Timing Value Register
Access
Bit
Name
Reset
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
30:29
DUTYSCALE
0x0
RW
0
1
2
3
4
LPINITWAIT
RW 0xFF
5
6
7
8
9
10
12
11
1
COMPENPRCHGEN RW
13
RW 0x1F 14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0
RW 0xFF
LNWAIT
Name
BYPWAIT
Access
RW
Reset
DUTYSCALE
0x060
Bit Position
31
Offset
Description
Select bias duty cycle clock.
Reserved for internal use. Do not change.
28
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
27:20
BYPWAIT
0xFF
RW
Bypass mode transition from low power or low noise modes wait
Bypass initialization wait. Add 1 to the value. Should be programmed to 119 to ensure at least 10us. Wait time = (BYPWAIT
+1)*(100ns +/- 20%) ns. Reset with POR, Hard Pin Reset, or BOD Reset.
19:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16:12
LNWAIT
0x1F
RW
Low Noise Controller Initialization wait time
Low noise controller Initialization wait time. Add 1 to the value. Should be programmed to 11 to ensure a minimum of 1us.
Wait time = (LNWAIT+1)*(100ns +/- 20%) ns. Reset with POR, Hard Pin Reset, or BOD Reset
11
COMPENPRCHGEN 1
RW
LN mode precharge enable
Reserved for internal use. Do not change.
10:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
LPINITWAIT
0xFF
RW
Low power initialization wait time
Low power initialization wait time. Add 1 to the value. Should be programmed to 119 to ensure at least 10us. Wait time =
(LPINITWAIT+1)*(100ns +/- 20%) ns. Reset with POR, Hard Pin Reset, or BOD Reset
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EMU - Energy Management Unit
9.5.22 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register
Access
Name
Bit
Name
Reset
Access
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:1
LPVREF
0xB4
RW
0
0
RW
Reset
LPATT
1
2
3
4
5
LPVREF RW 0xB4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x064
Bit Position
31
Offset
Description
LP mode vref trim
Select vref level. Maximum available code is 8'b11100111. LPATT and LPVREFSEL set the output of the DCDC to
4*(1+LPATT)*(30+LPVREF)*2.2mV. Customers should use the emlib functions for configuring this field. Reset with POR,
Hard Pin Reset, or BOD Reset.
0
LPATT
0
RW
Low power feedback attenuation
Low power feedback attenuation select. Customers should use the emlib functions for configuring this field. Reset with
POR, Hard Pin Reset, or BOD Reset.
Value
Mode
Description
0
DIV4
Feedback Ratio is 1/4
1
DIV8
Feedback Ratio is 1/8
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9.5.23 EMU_DCDCLPCTRL - DCDC Low Power Control Register
LPBLANK
Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RW 0x7
15
16
17
18
19
20
21
22
24
23
LPCMPHYSSEL
Access
0
Reset
LPVREFDUTYEN RW
25
26
RW 0x0
27
28
29
30
0x06C
Bit Position
31
Offset
Bit
Name
Reset
Access
31:27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:25
LPBLANK
0x0
RW
Description
Reserved for internal use. Do not change.
Reserved for internal use. Do not change.
24
LPVREFDUTYEN
0
RW
Lp mode duty cycling enable
Allow duty cycling of the bias. This is to minimize DC bias. Reset with POR, Hard Pin Reset, or BOD Reset.
23:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:12
LPCMPHYSSEL
0x7
RW
LP mode hysteresis selection
User-programmable hysteresis level for the low power comparator. Hysteresis voltage at the output is
4*(1+LPATT)*LPCMPHYSSEL*3.13mv. Customers should use the emlib functions for configuring this field. Reset with
POR, Hard Pin Reset, or BOD Reset.
11:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9.5.24 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control
0
1
0x0
2
RCOBAND RW
Name
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
RCOTRIM
Access
RW 0x10 26
Reset
28
29
30
0x070
Bit Position
31
Offset
Bit
Name
Reset
Access
31:29
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
28:24
RCOTRIM
0x10
RW
Description
Reserved for internal use. Do not change.
Reserved for internal use. Do not change.
23:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
RCOBAND
0x0
RW
LN mode RCO frequency band selection
Low noise mode RCO frequency selection. 0~7: 3~8.95MHz, approximately 0.85MHz/step. Reset with POR, Hard Pin Reset, or BOD Reset.
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EMU - Energy Management Unit
9.5.25 EMU_DCDCSYNC - DCDC Read Status Register
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x078
Bit Position
31
Offset
DCDCCTRLBUSY R
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
DCDCCTRLBUSY
0
R
Description
DCDC CTRL Register Transfer Busy.
Indicates the status of the DCDCCTRL transfer to the EMU OSC clock domain. Software cannot re-write the register until
this signal goes down.
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9.5.26 EMU_VMONAVDDCTRL - VMON AVDD Channel Control
Access
Name
Reset
31:24
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
23:20
RISETHRESCOARSE
0x0
RW
0
RW
EN
0
RW
RISEWU
1
2
3
RW
FALLWU
0
Bit
0
4
5
6
7
8
9
11
12
13
14
15
16
17
18
10
RW 0x0
FALLTHRESFINE
Name
FALLTHRESCOARSE RW 0x0
Access
RW 0x0
Reset
RISETHRESFINE
19
20
21
22
RISETHRESCOARSE RW 0x0
23
24
25
26
27
28
29
30
0x090
Bit Position
31
Offset
Description
Rising Threshold Coarse Adjust
Rising threshold adjust in 200 mV steps. Valid values are 0x0 (1.2 V) through 0xD (3.8 V). Reset with SYSEXTENDEDRESETn.
19:16
RISETHRESFINE
0x0
RW
Rising Threshold Fine Adjust
Rising threshold adjust in 20 mV steps. Valid values are 0x0 through 0x9. Reset with SYSEXTENDEDRESETn.
15:12
FALLTHRESCOARSE
0x0
RW
Falling Threshold Coarse Adjust
Falling threshold adjust in 200 mV steps. Valid values are 0x0 (1.2 V) through 0xD (3.8 V). Reset with SYSEXTENDEDRESETn.
11:8
FALLTHRESFINE
0x0
RW
Falling Threshold Fine Adjust
Falling threshold adjust in 20 mV steps. Valid values are 0x0 through 0x9. Reset with SYSEXTENDEDRESETn.
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
FALLWU
0
RW
Fall Wakeup
When set, a wakeup from EM4H will take place upon a falling edge. Reset with SYSEXTENDEDRESETn.
2
RISEWU
0
RW
Rise Wakeup
When set, a wakeup from EM4H will take place upon a rising edge. Reset with SYSEXTENDEDRESETn.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
EN
0
RW
Enable
Set this bit to enable the AVDD VMON. Reset with SYSEXTENDEDRESETn.
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EMU - Energy Management Unit
9.5.27 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control
Access
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:12
THRESCOARSE
0x0
RW
0
RW
EN
0
RW
1
2
3
RW
0
Name
0
4
5
6
7
8
9
10
Bit
FALLWU
Name
RISEWU
Access
RW 0x0
Reset
THRESFINE
11
12
13
14
THRESCOARSE RW 0x0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x094
Bit Position
31
Offset
Description
Threshold Coarse Adjust
Threshold adjust in 200 mV steps. Valid values are 0x0 (1.2 V) through 0xD (3.8 V). Reset with SYSEXTENDEDRESETn.
11:8
THRESFINE
0x0
RW
Threshold Fine Adjust
Threshold adjust in 20 mV steps. Valid values are 0x0 through 0x9. Reset with SYSEXTENDEDRESETn.
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
FALLWU
0
RW
Fall Wakeup
When set, a wakeup from EM4H will take place upon a falling edge. Reset with SYSEXTENDEDRESETn.
2
RISEWU
0
RW
Rise Wakeup
When set, a wakeup from EM4H will take place upon a rising edge. Reset with SYSEXTENDEDRESETn.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
EN
0
RW
Enable
Set this bit to enable the ALTAVDD VMON. Reset with SYSEXTENDEDRESETn.
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EMU - Energy Management Unit
9.5.28 EMU_VMONDVDDCTRL - VMON DVDD Channel Control
Access
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:12
THRESCOARSE
0x0
RW
0
RW
EN
0
RW
1
2
3
RW
FALLWU
0
Name
0
4
5
6
7
8
9
10
Bit
RISEWU
Name
RW 0x0
Access
THRESFINE
Reset
11
12
13
14
THRESCOARSE RW 0x0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x098
Bit Position
31
Offset
Description
Threshold Coarse Adjust
Threshold adjust in 200 mV steps. Valid values are 0x0 (1.2 V) through 0xD (3.8 V). Reset with SYSEXTENDEDRESETn.
11:8
THRESFINE
0x0
RW
Threshold Fine Adjust
Threshold adjust in 20 mV steps. Valid values are 0x0 through 0x9. Reset with SYSEXTENDEDRESETn.
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
FALLWU
0
RW
Fall Wakeup
When set, a wakeup from EM4H will take place upon a falling edge. Reset with SYSEXTENDEDRESETn.
2
RISEWU
0
RW
Rise Wakeup
When set, a wakeup from EM4H will take place upon a rising edge. Reset with SYSEXTENDEDRESETn.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
EN
0
RW
Enable
Set this bit to enable the DVDD VMON. Reset with SYSEXTENDEDRESETn.
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EMU - Energy Management Unit
9.5.29 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control
Access
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:12
THRESCOARSE
0x0
0
0
RW
1
2
EN
Name
RW
3
RW
Bit
0
0
RW
FALLWU
RISEWU
4
0
RW
6
7
8
9
10
5
RETDIS
Name
RW 0x0
Access
THRESFINE
Reset
11
12
13
14
THRESCOARSE RW 0x0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x09C
Bit Position
31
Offset
Description
Threshold Coarse Adjust
Threshold adjust in 200 mV steps. Valid values are 0x0 (1.2 V) through 0xD (3.8 V). Reset with SYSEXTENDEDRESETn.
11:8
THRESFINE
0x0
RW
Threshold Fine Adjust
Threshold adjust in 20 mV steps. Valid values are 0x0 through 0x9. Reset with SYSEXTENDEDRESETn.
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
RETDIS
0
RW
EM4 IO0 Retention disable
When set, the IO0 Retention will be disabled when this IO0 voltage drops below the threshold set. Reset with SYSEXTENDEDRESETn.
3
FALLWU
0
RW
Fall Wakeup
When set, a wakeup from EM4H will take place upon a falling edge. Reset with SYSEXTENDEDRESETn.
2
RISEWU
0
RW
Rise Wakeup
When set, a wakeup from EM4H will take place upon a rising edge. Reset with SYSEXTENDEDRESETn.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
EN
0
RW
Enable
Set this bit to enable the IO0 VMON. Reset with SYSEXTENDEDRESETn.
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CMU - Clock Management Unit
10. CMU - Clock Management Unit
Quick Facts
What?
0 1 2 3
4
Oscillators
The CMU controls oscillators and clocks. EFM32
Jade Gecko supports 6 different oscillators with
minimized power consumption and short start-up
time. The CMU has HW support for calibration of RC
oscillators.
WDOG clock
Why?
LETIMER clock
LEUART clock
Oscillators and clocks contribute significantly to the
power consumption of the MCU. With the low power
oscillators combined with the flexible clock control
scheme, it is possible to minimize the energy consumption in any given application.
Peripheral A clock
How?
Peripheral B clock
The CMU can configure different clock sources, enable/disable clocks to peripherals on an individual basis and set the prescaler for the different clocks. The
short oscillator start-up times makes duty-cycling between active mode and the different low energy
modes (EM2 DeepSleep, EM3 Stop, and EM4 Hibernate/Shutoff) very efficient. The calibration feature ensures high accuracy RC oscillators. Several
interrupts are available to avoid CPU polling of flags.
CMU
Peripheral C clock
Peripheral D clock
CPU clock
10.1 Introduction
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks in the EFM32 Jade Gecko. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application
by not wasting power on peripherals and oscillators that do not need to be active.
10.2 Features
• Multiple clock sources available:
• 38 MHz - 40 MHz High Frequency Crystal Oscillator (HFXO)
• 1 MHz - 38 MHz High Frequency RC Oscillator (HFRCO)
• 1 MHz - 38 MHz Auxiliary High Frequency RC Oscillator (AUXHFRCO)
• 32768 Hz Low Frequency Crystal Oscillator (LFXO)
• 32768 Hz Low Frequency RC Oscillator (LFRCO)
• 1000 Hz Ultra Low Frequency RC Oscillator (ULFRCO)
• Low power oscillators.
• Low start-up times.
• Separate prescalers for High Frequency Core Clocks (HFCORECLK), and Peripheral Clocks (HFPERCLK).
• Individual clock prescaler selection for each Low Energy Peripheral.
• Clock gating on an individual basis to core modules and all peripherals.
• Selectable clocks can be output on two external pins and/or PRS.
• Wakeup interrupt based on LFRCO or LFXO ready, allowing to wait for low frequency oscillator startup while being in EM2 DeepSleep avoiding the need for polling.
• Auxiliary 1 MHz - 38 MHz RC oscillator (AUXHFRCO), which is asynchronous to the HFSRCCLK system clock, can be selected for
ADC operation and debug trace.
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CMU - Clock Management Unit
10.3 Functional Description
An overview of the CMU is shown in Figure 10.1 CMU Overview on page 204. This figure shows the CMU for the largest device in the
EFM32 family. Please refer to the Configuration Summary in the Device Datasheet to see which core, and peripheral modules, and
therefore clock connections, are present in a specific device.
HFPERCLKADCn
CMU_ADCCTRL.ADCCLKINV
HFSRCCLK
HFXO
xor
CMU_ADCCTRL.ADCCLKSEL
AUX
HFRCO
Timeout
ADC_CLK
ADC
ADCCLKMODE
MSC
(Flash Programming)
AUXCLK
CMU_DBGCLKSEL.DBG
clock
switch
DBGCLK
Debug Trace
CMU_HFPRESC.PRESC
HFXO
HFRCO
Timeout
clock
switch
HFSRCCLK
prescaler
Timeout
CMU_HFPERCLKEN0.TIMER0
HFCLK
Clock
Gate
HFPERCLKTIMER0
Clock
Gate
HFPERCLKI2C0
Clock
Gate
HFCORECLKCORTEX
CMU_HFBUSCLKEN0.GPIO
Clock
Gate
HFBUSCLKGPIO
CMU_HFBUSCLKEN0.DMA
Clock
Gate
CMU_HFCLKSEL.HF
CMU_CTRL.HFPERCLKEN
prescaler
HFPERCLK
CMU_HFPERCLKEN0.I2C0
CMU_HFPERPRESC.PRESC
CMU_HFCOREPRESC.PRESC
EM0
prescaler
HFCORECLK
CMU_HFEXPPRESC.PRESC
prescaler
HFEXPCLK
HFBUSCLK
HFBUSCLKDMA
HFBUSCLKBUSMATRIX
HFBUSCLKDMEM
CMU_HFBUSCLKEN0.LE
LFXO
Timeout
LFRCO
Timeout
HFCLKLE
Clock
Gate
HFBUSCLKLE
Clock
Gate
LFACLKLETIMER0
Prescaler
( /2, /4 )
CMU_HFPRESC.HFCLKLEPRESC
CMU_LFACLKEN0.LETIMER0
clock
switch
LFACLK
prescaler
ULFRCO
CMU_LFAPRESC0.LETIMER0
CMU_LFACLKSEL.LFA
PCNTn_S0
PCNTnCLK
CMU_PCNTCTRL.PCNTnCLKSEL
CMU_LFBCLKSEL.LFB
CMU_LFBPRESC0.LEUART0
clock
switch
LFBCLK
CMU_LFBCLKEN0.LEUART0
prescaler
Clock
Gate
LFBCLKLEUART0
CMU_LFELKSEL.LFE
clock
switch
CMU_LFECLKEN0.RTCC
LFECLK
WDOGCLK
WDOG
WDOG_CTRL.CLKSEL
CRYOCLK
CRYOTIMER_CTRL.OSCSEL
CRYOTIMER
Clock
Gate
LFECLKRTCC
Availability of oscillators and clocks in Eneryg Modes:
· Available in EM0/EM1
· Available in EM0/EM1/EM2
· Available in EM0/EM1/EM2/EM3
· Available in EM0/EM1/EM2/EM3/EM4H
· Available in EM0/EM1/EM2/EM4H/EM4S
· Available in EM0/EM1/EM2/EM3/EM4H/EM4S
Figure 10.1 CMU Overview
10.3.1 System Clocks
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CMU - Clock Management Unit
10.3.1.1 HFCLK - High Frequency Clock
HFSRCCLK is the selected High Frequency Source Clock. HFCLK is an optionally prescaled version of HFSRCCLK. The HFSRCCLK,
and therefore HFCLK, can be driven by a high-frequency oscillator (HFRCO or HFXO) or one of the low-frequency oscillators (LFRCO
or LFXO). By default the HFRCO is selected. In most applications, one of the high frequency oscillators will be the preferred choice. To
change the selected clock source, write to the HF bitfield in CMU_HFCLKSEL. The high frequency clock source can also be changed
automatically by hardware as explained in 10.3.2.9 Automatic HFXO Start. The currently selected source for HFSRCCLK and HFCLK
can be read from CMU_HFCLKSTATUS. The HFSRCCLK is running in EM0 Active and EM1 Sleep and is automatically stopped in
EM2 DeepSleep.
Note:
If a low frequency clock (i.e. LFRCO or LFXO) is selected as source clock for HFSRCCLK via the HF bitfield in CMU_HFCLKSEL, then
no register reads should be performed from Low Energy Peripherals for registers which can change value every clock cycle (e.g. a
counter register). In addition to the peripherals on LFACLK, LFBCLK and LFECLK, this restriction applies in general to any low frequency peripheral, which is not directly or indirectly clocked from HFSRCCLK (e.g. the WDOG).
HFCLK can optionally be prescaled by setting PRESC in CMU_HFPRESC to a non-zero value. This prescales HFCLK to all high frequency components and is typically used to save energy in applications where the system is not required to run at the highest frequency. The prescaler setting can be changed dynamically and the new setting takes effect immediately. HFCLK is used by the CMU and
drives the prescalers that generate HFCORECLK and HFPERCLK allowing for flexible clock prescaling. The HFBUSCLK, used in e.g.
the bus and memory system, is equal to HFCLK.
10.3.1.2 HFCORECLK - High Frequency Core Clock
HFCORECLK is a prescaled version of HFCLK. This clock drives the Core Modules, which consists of the CPU and modules that are
tightly coupled to the CPU, e.g. the cache. The prescale factor for prescaling HFCLK into HFCORECLK is set using the CMU_HFCOREPRESC register. The setting can be changed dynamically and the new setting takes effect immediately.
Note:
Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules will increase with the ratio between the clocks. Please refer to 4.2.4 Bus Matrix for more details.
10.3.1.3 HFBUSCLK - High Frequency Bus Clock
HFBUSCLK is equal to HFCLK. This clock drives Bus and Memory System Modules as for example the Bus Matrix, MSC, RAM, DMA,
GPIO and Crypto. HFBUSCLK is also used to drive the bus interface to the Low Energy Peripherals as described further in
10.3.1.5 LFACLK - Low Frequency A Clock, 10.3.1.6 LFBCLK - Low Frequency B Clock and 10.3.1.7 LFECLK - Low Frequency E
Clock. Some of the modules that are driven by this clock can be clock gated completely when not in use. This is done by clearing the
clock enable bit for the specific module in CMU_HFBUSCLKEN0. The frequency of HFBUSCLK is equal to the frequency of HFCLK
and can therefore only be prescaled by using the PRESC bitfield in CMU_HFPRESC.
10.3.1.4 HFPERCLK - High Frequency Peripheral Clock
Like HFCORECLK, HFPERCLK also is a prescaled version of HFCLK. This clock drives the High-Frequency Peripherals. All the peripherals that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the
specific peripheral in CMU_HFPERCLKEN0. The peripherals can also be gated simultaneously by clearing the HFPERCLKEN bit in the
CMU_CTRL register. The prescale factor for prescaling HFCLK into HFPERCLK is set using the CMU_HFPERPRESC register. The
setting can be changed dynamically and the new setting takes effect immediately.
Note:
Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules will increase with the ratio between the clocks. E.g. if a bus-access normally takes three cycles, it will take 9 cycles if HFPERCLK runs three
times as fast as the HFCORECLK.
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CMU - Clock Management Unit
10.3.1.5 LFACLK - Low Frequency A Clock
LFACLK is the selected clock for the Low Energy A Peripherals. There are three selectable sources for LFACLK: LFRCO, LFXO and
ULFRCO. In addition, the LFACLK can be disabled, which is the default setting. The selection is configured using the LFA field in
CMU_LFACLKSEL.
The bus interface to the Low Energy A Peripherals is clocked by HFBUSCLKLE and this clock therefore needs to be enabled when
programming a Low Energy (LE) peripheral.
Each Low Energy Peripheral that is clocked by LFACLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFAPRESC0 and the clock enable bits can be found in CMU_LFACLKEN0.
When operating in oversampling mode, the pulse counters are clocked by LFACLK. This is configured for each pulse counter (n) individually by setting PCNTnCLKSEL in CMU_PCNTCTRL.
10.3.1.6 LFBCLK - Low Frequency B Clock
LFBCLK is the selected clock for the Low Energy B Peripherals. There are four selectable sources for LFBCLK: LFRCO, LFXO,
HFCLKLE and ULFRCO. In addition, the LFBCLK can be disabled, which is the default setting. The selection is configured using the
LFB field in CMU_LFBCLKSEL. The HFCLKLE setting allows the Low Energy B Peripherals to be used as high-frequency peripherals.
The bus interface to the Low Energy B Peripherals is clocked by HFBUSCLKLE and this clock therefore needs to be enabled when
programming a LE peripheral.
Note:
If HFCLKLE is selected as LFBCLK, the clock will stop in EM2 DeepSleep and EM3 Stop.
Each Low Energy Peripheral that is clocked by LFBCLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFBPRESC0 and the clock enable bits can be found in CMU_LFBCLKEN0.
10.3.1.7 LFECLK - Low Frequency E Clock
LFECLK is the selected clock for the Low Energy E Peripherals. There are three selectable sources for LFECLK: LFRCO, LFXO and
ULFRCO. In addition, the LFECLK can be disabled, which is the default setting. The selection is configured using the LFE field in
CMU_LFECLKSEL.
The bus interface to the Low Energy E Peripherals is clocked by HFBUSCLKLE and this clock therefore needs to be enabled when
programming a LE peripheral.
Note:
LFECLK is in a different power domain than LFACLK and LFBCLK, which makes it available all the way down to EM4 Hibernate.
Each Low Energy Peripheral that is clocked by LFECLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFEPRESC0 and the clock enable bits can be found in CMU_LFECLKEN0.
10.3.1.8 PCNTnCLK - Pulse Counter n Clock
Each available pulse counter is driven by its own clock, PCNTnCLK where n is the pulse counter instance number. Each pulse counter
can be configured to use an external pin (PCNTn_S0) or LFACLK as PCNTnCLK.
10.3.1.9 WDOGCLK - Watchdog Timer Clock
The Watchdog Timer (WDOG) can be configured to use one of three different clock sources: LFRCO, LFXO or ULFRCO.
10.3.1.10 CRYOCLK - Cryotimer Clock
The Cryotimer clock can be configured to use one of three different clock sources: LFRCO, LFXO or ULFRCO. The Cryotimer can also
run in EM4 Hibernate/Shutoff provided that its selected clock is kept enabled as configured in EMU_EM4CTRL.
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CMU - Clock Management Unit
10.3.1.11 AUXCLK - Auxiliary Clock
AUXCLK is a 1 MHz - 38 MHz clock driven by a separate RC oscillator, the AUXHFRCO. This clock can be used for ADC operation and
Serial Wire Output (SWO). When the AUXHFRCO is selected as the ADC clock via the ADC0CLKSEL bitfield in the CMU_ADCCTRL
register this clock will become active automatically when needed. Even if the AUXHFRCO has not been enabled explicitly by software,
the ADC can automatically start and stop it. The AUXHFRCO is explicitely enabled by writing a 1 to AUXHFRCOEN in
CMU_OSCENCMD. This explicit enabling is required when using the selecting AUXCLK for SWO operation.
10.3.1.12 Debug Trace Clock
The CMU selects the clock used for debug trace via the DBGCLKSEL register. The user can use the AUXHFRCO or the HFCLK. The
selected debug trace clock will be used to run the Cortex-M3 trace logic.
Note:
When using AUXHFRCO as the debug trace clock, it must be stopped before entering EM2 or EM3.
10.3.2 Oscillators
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CMU - Clock Management Unit
10.3.2.1 Enabling and Disabling
The different oscillators can typically be enabled and disabled via both hardware and software mechanisms. Enabling via software is
done by writing a 1 to the corresponding enable bit in the CMU_OSCENCMD register. Disabling via software is done by writing a 1 to
the corresponding disable bit in CMU_OSCENCMD. Enabling via hardware can be performed by various peripherals and varies per
oscillator. Disabling via hardware is typically performed on entry of low energy modes. The enable and disable mechanisms for each of
the oscillators are summarized in Table 10.1 Software based and Hardware based Enabling and Disabling of Oscillators on page 208
and described in more detail below.
Table 10.1. Software based and Hardware based Enabling and Disabling of Oscillators
Oscillator
SW Enable
SW Disable
HW Enable
HW Disable
ULFRCO
-
-
Enabled when in
EM0/EM1/EM2/EM3/
EM4H.
EM4S entry depending
on configuration in
EMU_EM4CTRL.
LFRCO
Via LFRCOEN in
CMU_OSCENCMD.
Via LFRCODIS in
CMU_OSCENCMD.
Via the WDOG if it is
EM3 entry. EM4 entry deconfigured to use LFRCO pending on configuration
as its clock source via
in EMU_EM4CTRL.
the CLKSEL bitfield in
WDOG_CTRL while
SWOSCBLOCK is set.
LFXO
Via LFXOEN in
CMU_OSCENCMD.
Via LFXODIS in
CMU_OSCENCMD.
Via the WDOG if it is
configured to use LFXO
as its clock source via
the CLKSEL bitfield in
WDOG_CTRL while
SWOSCBLOCK is set.
EM3 entry. EM4 entry depending on configuration
in EMU_EM4CTRL.
HFRCO
Via HFRCOEN in
CMU_OSCENCMD.
Via HFRCODIS in
CMU_OSCENCMD.
Reset exit. EM2/EM3 exit. Automatic control by
LEUART RX/TX DMA
wake-up as configured in
LEUARTn_CTRL.
EM2/EM3/EM4 entry. Automatic control by
LEUART RX/TX DMA
wake-up as configured in
LEUARTn_CTRL. Automatic start and selection
of HFXO causes HFRCO
disable.
AUXHFRCO
Via AUXHFRCOEN in
CMU_OSCENCMD.
Via AUXHFRCODIS in
CMU_OSCENCMD.
Automatic control by
ADC.
EM2/EM3/EM4 entry. Automatic control by ADC
even in EM2/EM3.
HFXO
Via HFXOEN in
CMU_OSCENCMD.
Via HFXODIS in
CMU_OSCENCMD.
Automatic start by
EM0/EM1 entry as configured in
CMU_HFXOCTRL.
EM2/EM3/EM4 entry.
The LFXO and LFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. The WDOG can be configured to
force the LFXO or LFRCO to become (and remain) enabled when such an oscillator is selected as its clock source via the CLKSEL
bitfield in the WDOG_CTRL register while SWOSCBLOCK is set. In that case LFXODIS and LFRCODIS commands are blocked. They
are automatically disabled when entering EM3. Upon EM4 entry they are default turned off, but they can optionally be retained depending on the EMU_EM4CTRL configuration. Retaining of the LFXO or LFRCO in EM4 is needed if such an oscillator is required by a
specific peripheral in EM4. Retaining can also be used to guarantee quick oscillator availability after EM4 exit.
Note:
In order to support usage of LFRCO and LFXO in EM4, their settings are automatically latched upon EM4 entry. These settings remain
latched upon wake-up from EM4 to EM0 although the related registers (CMU_LFRCOCTRL, CMU_LFXOCTRL, CMU_LFECLKSEL,
CMU_LFECLKEN0 and CMU_LEEPRESC0) will have been reset. The registers can be rewritten by software, but they will only affect
the LFRCO and LFXO after unlatching their settings by writing 1 to EM4UNLATCH in the EMU_CMD register.
Note:
Turning off the LFRCO and LFXO upon EM4 Hibernate/Shutoff entry is most easily done by using the RETAINLFRCO and RETAINLFXO bitfields from the EMU_EM4CTRL register, which are default such that the LFRCO and LFXO are turned off automatically upon
EM4 Hibernate/Shutoff entry. Alternatively the LFRCO and LFXO can be disabled via the CMU_OSCENCMD register, in which case
software should wait for the oscillators to be properly disabled before executing the EM4 Hibernate/Shutoff entry routine.
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CMU - Clock Management Unit
After enabling the LFRCO (or LFXO) it should not be disabled before it has been signaled to be ready. Similarly, after disabling the
LFRCO (or LFXO) it should not be re-enabled before it has been signaled to be non-ready. Before entering EM4, software should check
that the LFRCO (or LFXO) is signaled to be ready before allowing or initiating the EM4 entry if that oscillator is required in EM4. Also, to
guarantee latching the latest settings, no control write should be ongoing upon EM4 entry as can be checked via the CMU_SYNCBUSY
register. Typical enable and disable sequences are as follows:
CMU->OSCENCMD = CMU_OSCENCMD_LFRCOEN;
while ((CMU->STATUS & CMU_STATUS_LFRCORDY) != CMU_STATUS_LFRCORDY);
CMU->OSCENCMD = CMU_OSCENCMD_LFRCODIS;
while ((CMU->STATUS & CMU_STATUS_LFRCORDY) == CMU_STATUS_LFRCORDY);
When the LFXO is disabled, the interface to the LFXTAL_N and LFXTAL_P pins are set in a high-Z state. The XTAL oscillations will not
stop immediately when LFXO is disabled, but typically die out gradually over some 100 ms. If the LFXO is enabled before XTAL oscillations have had time to reach zero amplitude, startup time can be significantly shorter.
Note:
The LFRCORDY and LFXORDY interrupts can be used to wake up the system from EM2 DeepSleep. In this way busy waiting for the
LFRCO or LFXO to become ready can be avoided by going into EM2 after enabling these oscillators and sleeping until the interrupt
causes a wakeup.
The ULFRCO is automatically enabled in EM0, EM1, EM2, EM3, and EM4H and cannot be controlled via CMU_OSCENCMD. It is automatically disabled upon entering EM4S unless prevented by the configuration in EMU_EM4CTRL.
The HFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. The HFRCO is disabled automatically when
entering EM2, EM3, or EM4. Further hardware based enabling and disabling can be performed by the LEUART when using automatic
RX/TX DMA wakeup as controlled by the RXDMAWU and TXDMAWU bits in the LEUARTn_CTRL register. An automatic start and selection of the HFXO will lead to an automatic HFRCO disabling.
The AUXHFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. The AUXHFRCO is disabled automatically when entering EM2, EM3, or EM4. Hardware based AUXHFRCO enabling and disabling is however performed by the ADC module when AUXCLK is selected for its operation making it available even when being in EM2/EM3.
After enabling the AUXHFRCO, it should not be disabled before it has been signaled to be enabled. Similarly, after disabling the
AUXHFRCO, it should not be re-enabled before it has been signaled to be non-enabled. Typical enable and disable sequences are as
follows:
CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
while ((CMU->STATUS & CMU_STATUS_AUXHFRCOENS) != CMU_STATUS_AUXHFRCOENS);
CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS;
while ((CMU->STATUS & CMU_STATUS_AUXHFRCOENS) == CMU_STATUS_AUXHFRCOENS);
Note:
When using AUXHFRCO as the debug trace clock (as selected in CMU_DBGCLKSEL), it must be stopped before entering EM2 or
EM3.
The HFXO can be enabled and disabled by software via the CMU_OSCENCMD register. The HFXO is disabled automatically when
entering EM2, EM3, or EM4. Hardware based HFXO enabling can be initiated by various peripherals as configured via the AUTOSTARTEM0EM1, AUTOSTARTSELEM0EM1 bits in the CMU_HFXOCTRL register. The interaction between hardware based and software
based control of the HFXO is further explained in 10.3.2.9 Automatic HFXO Start.
After enabling the HFXO, it should not be disabled before it has been signaled to be enabled. Similarly, after disabling the HFXO it
should not be re-enabled before it has been signaled to be non-enabled. Typical enable and disable sequences are as follows:
CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN;
while ((CMU->STATUS & CMU_STATUS_HFXOENS) != CMU_STATUS_HFXOENS);
CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS;
while ((CMU->STATUS & CMU_STATUS_HFXOENS) == CMU_STATUS_HFXOENS);
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10.3.2.2 Oscillator Start-up Time and Time-out
The start-up time differs per oscillator and the usage of an oscillator clock can further be delayed by a time-out. The LFRCO, LFXO and
the HFXO have a configurable time-out which is set by software in the (various) TIMEOUT bitfields of the CMU_LFRCOCTRL,
CMU_LFXOCTRL and CMU_HFXOTIMEOUTCTRL registers respectively. The time-out delays the assertion of the READY signal for
LFRCO, LFXO and HFXO and should allow for enough time for the oscillator to stabilize. The time-out can be optimized for the chosen
crystal (for LFXO and HFXO) used in the application. In case LFRCO and/or LFXO has been retained throughout EM4 Hibernate/Shutoff, such retained oscillators can be quickly restarted for use as LFACLK, LFBCLK or LFECLK by using the minimum TIMEOUT settings
for them. For the other RC oscillators (HFRCO, AUXHFRCO, and ULFRCO), the start-up time is known and a fixed time-out is used.
There are individual bits in the CMU_STATUS register for each oscillator indicating the status of the oscillator:
• ENABLED - Indicates that the oscillator is enabled
• READY - Start-up time including time-out is exceeded
These status bits are located in the CMU_STATUS register.
Additionaly, the HFXO has a second time-out counter which can be used to achieve deterministic start-up time based on timing from
e.g. the LFXO. This second counter runs off LFECLK and can be programmed via the LFTIMEOUT bitfield in the CMU_HFXOCTRL
register. It can be used when waking up from EM2 when either ULFRCO, LFRCO or LFXO is already running and stable. In this case
the HFXO ready assertion can be delayed with the number of LFECLK cycles as programmed in LFTIMEOUT. The HFXO ready signal
is asserted when both the TIMEOUT counter (configured via the CMU_HFXOTIMEOUTCTRL register) and the LFTIMEOUT counter
(configured via CMU_HFXOCTRL register) have timed out as shown in Figure 10.2 CMU Deterministic HFXO startup using LFTIMEOUT on page 210. The TIMEOUT should cover the actual crystal startup time. Typically the time base used for the TIMEOUT counter
is not as accurate as the time base accuracy that can be achieved for the LFTIMEOUT counter, specifically if that one is based on the
LFXO timing. If LFTIMEOUT is triggered before TIMEOUT is triggered, then the LFTIMEOUTERR bitfield in CMU_IF will be set to 1.
Note that use of LFTIMEOUT requires that the peripheral causing the wake-up is on the LFECLK domain.
Wake-up from EM2 with automatic HFXO start
HFXO stable (non-deterministic)
HFXO ready (deterministic)
Automatic switch to HFXO and disable of HFRCO
status
CMU_STATUS.HFXORDY
CMU_STATUS.HFXOENS
CMU_HFCLKSEL.HF = HFXO
clocks
HFCLK
HFRCO
HFXO
TIMEOUT (based on CMU_HFXOTIMEOUTCTRL)
LFECLK
LFTIMEOUT (counting LFECLK cycles)
Figure 10.2 CMU Deterministic HFXO startup using LFTIMEOUT
The startup behavior of the HFXO also depends on how and how long the HFXO is disabled. This can be controlled by configuring the
XTI2GND, and XTO2GND bitfields in the CMU_HFXOCTRL register.
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CMU - Clock Management Unit
10.3.2.3 Switching Clock Source
The HFRCO oscillator is a low energy oscillator with extremely short start-up time. Therefore, this oscillator is always chosen by hardware as the clock source for HFCLK when the device starts up (e.g. after reset and after waking up from EM2 DeepSleep and EM3
Stop). After reset, the HFRCO frequency is 19 MHz.
Software can switch between the different clock sources at run-time. E.g., when the HFRCO is the clock source, software can switch to
HFXO by writing the field HF in the CMU_HFCLKSEL command register. See Figure 10.3 CMU Switching from HFRCO to HFXO before HFXO is ready on page 211 for a description of the sequence of events for this specific operation.
Note:
Before switching the HFCLKSRC to HFXO via the HF bitfield in CMU_HFCLKSEL it is important to first enable the HFXO. Switching to
a disabled oscillator will effectively stop HFSRCCLK and only a reset can recover the system.
When selecting an oscillator which has been enabled, but which is not ready yet, the HFSRCCLK will stop for the duration of the oscillator start-up time since the oscillator driving it is not ready. This effectively stalls the Core Modules and the High-Frequency Peripherals.
It is possible to avoid this by first enabling the target oscillator, e.g. HFXO, and then wait for that oscillator to become ready before
switching the clock source. This way, the system continues to run on the HFRCO until the target oscillator, e.g. HFXO, has timed out
and provides a reliable clock. This sequence of events is shown in Figure 10.4 CMU Switching from HFRCO to HFXO after HFXO is
ready on page 212.
A separate flag is set when the oscillator is ready. This flag can also be configured to generate an interrupt.
command
CMU_CMD.HFCLKSEL
00
02
00
CMU_OSCENCMD.HFRCOEN
CMU_OSCENCMD.HFRCODIS
CMU_OSCENCMD.HFXOEN
CMU_OSCENCMD.HFXODIS
CMU_STATUS.HFRCORDY
CMU_STATUS.HFRCOENS
status
CMU_STATUS.HFRCOSEL
CMU_STATUS..HFXORDY
CMU_STATUS.HFXOENS
CMU_STATUS.HFXOSEL
clocks
HFCLK
HFRCO
HFXO
HFXO time-out period
Figure 10.3 CMU Switching from HFRCO to HFXO before HFXO is ready
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00
CMU_CMD.HFCLKSEL
02
00
command
CMU_OSCENCMD.HFRCOEN
CMU_OSCENCMD.HFRCODIS
CMU_OSCENCMD.HFXOEN
CMU_OSCENCMD.HFXODIS
CMU_STATUS.HFRCORDY
CMU_STATUS.HFRCOENS
status
CMU_STATUS.HFRCOSEL
CMU_STATUS.HFXORDY
CMU_STATUS.HFXOENS
CMU_STATUS.HFXOSEL
clocks
HFCLK
HFRCO
HFXO
HFXO time-out period
Figure 10.4 CMU Switching from HFRCO to HFXO after HFXO is ready
Switching clock source for LFACLK, LFBCLK, and LFECLK is done by setting the LFA, LFB and LFE bitfields in CMU_LFACLKSEL,
CMU_LFBCLKSEL, and CMU_LFECLKSEL respectively. To ensure no stalls in the Low Energy Peripherals, the clock source should be
ready before switching to it.
Note:
To save energy, remember to turn off all oscillators not in use.
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10.3.2.4 HFXO Configuration
The High Frequency Crystal Oscillator needs to be configured to ensure safe startup for the given crystal. Refer to the Device Datasheet and application notes for guidelines in selecting correct components and crystals as well as for configuration trade-offs.
The HFXO crystal is connected to the HFXTAL_N/HFXTAL_P pins as shown in Figure 10.5 HFXO Pin Connection on page 213
Gecko Device
HFXTAL_N
HFXTAL_P
38.0 – 40.0
MHz
CTUNE
CL1
CTUNE
CL2
Figure 10.5 HFXO Pin Connection
It is possible to connect an external clock source to the HFXTAL_N pin of the HFXO oscillator. Default the HFXO is started in crystal
mode, but an active external sine wave or square wave clock can also be used as clock source. By configuring the MODE field in
CMU_HFXOCTRL to EXTCLK, the HFXO can be bypassed and the source clock can be provided through the HFXTAL_N pin.
Upon enabling the HFXO, a hardware state machine sequentially applies the configurable startup state and steady state control settings from the CMU_HFXOSTARTUPCTRL and CMU_HFXOSTEADYSTATECTRL registers. Configuration is required for both the
startup state and the steady state of the HFXO. After reaching the steady operation state of the HFXO, further optimization can optionally be performed to optimize the HFXO for noise and current consumption. Optimization for noise can be performed by an automatic
Peak Detection Algorithm (PDA). Optimization for current can be performed by an automatic Shunt Current Optimization algorithm
(SCO). HFXO operation is possible without PDA and SCO at the cost of higher noise and current consumption than required.
Upon fully disabling the HFXO, the HFXTAL_N and HFXTAL_P pins can optionally be automatically pulled to ground as configured via
the XTI2GND and XTO2GND bits respectively from the CMU_HFXOCTRL register. Do not set XTI2GND to 1 when the HFXO is in
EXTCLK mode and an external wave is connected.
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CMU - Clock Management Unit
Reset ||
EM2/EM3 entry ||
(CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS)
OFF
HFXO major mode configuration from CMU->HFXOCTRL:
· MODE
· LOWPOWER
Startup state configuration from CMU->HFXOSTARTUPCTRL:
· IBTRIMXOCORE
· CTUNE
· REGISH
· LOWPOWER
CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN
OFF
Timeout configuration from CMU->HFXOTIMEOUTCTRL:
STARTUP
· STARTUPTIMEOUT
Steady state configuration from CMU->HFXOSTEADYSTATECTRL:
· IBTRIMXOCORE
· CTUNE
· REGISH
OFF
Timeout configuration from CMU->HFXOTIMEOUTCTRL:
STEADY
· STEADYTIMEOUT
HFXORDY = 1
READY
CMU->CMD = CMU_CMD_HFXOSHUNTOPTSTART && PEAKDETSHUNTOPTMODE = CMD
OFF
HFXOSHUNTOPTRDY = 1
PEAKDETSHUNTOPTMODE = AUTOCMD ||
CMU->CMD = CMU_CMD_HFXOPEAKDETSTART && PEAKDETSHUNTOPTMODE = CMD
PEAKDETSHUNTOPTMODE = CMD
HFXOPEAKDETRDY = 1
PDA
(Peak
Detection
Algorithm)
PEAKDETSHUNTOPTMODE = AUTOCMD
SCO
(Shunt Current
Optimization)
HFXOPEAKDETRDY = 1
OFF
OFF
Timeout configuration from CMU->HFXOTIMEOUTCTRL:
Timeout configuration from CMU->HFXOTIMEOUTCTRL:
· PEAKDETTIMEOUT
· SHUNTOPTTIMEOUT
Figure 10.6 CMU HFXO control state machine
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Refer to the Device Datasheet to find the configuration values for a given crystal. The startup state configuration needs to be written
into the IBTRIMXOCORE and CTUNE bitfields of the CMU_HFXOSTARTUPCTRL register. The duration of the startup phase is configured in the STARTUPTIMEOUT bitfield of the CMU_HFXOTIMEOUTCTRL register. Similarly, the Device Datasheet provides the steady
state configuration depending on the crystal's CL, RESR and oscillation frequency. This configuration is programmed into the IBTRIMXOCORE, REGISH and CTUNE bitfields of the CMU_HFXOSTEADYSTATECTRL register. The duration of the steady phase is configured in the STEADYTIMEOUT bitfield of the CMU_HFXOTIMEOUTCTRL register.
All HFXO configuration needs to be performed prior to enabling the HFXO via HFXOEN in CMU_OSCENCMD unless noted otherwise.
The HFXOENS flag in CMU_STATUS indicates if the HFXO has been succesfully enabled. Once the HFXO startup time (STARTUPTIMEOUT plus STEADYTIMEOUT) has exceeded, the HFXO is ready for use as indicated by the HFXORDY flag in CMU_STATUS. If
PDA and SCO are enabled, the HFXOPEAKDETRDY and HFXOSHUNTOPTRDY flags in the CMU_STATUS register indicate when
these algorithms are ready and it is advised to also wait for these flags before using the HFXO.
The HFXO crystal bias current may be optimized and set to a value which decreases output phase noise without sacrificing PSR. This
is done by programming the recommended IBTRIMXOCORE value into the CMU_HFXOSTEADYSTATECTRL register. The built-in
Peak Detector Algorithm (PDA) performs further optimization to accommodate for process variations. Once PDA is ready as indicated
by the HFXOPEAKDETRDY flag, the found optimal bias current setting is available in the IBTRIMXOCORE bitfield of the CMU_HFXOTRIMSTATUS register. This IBTRIMXOCORE setting should be saved and can be applied directly during a future HFXO startup as a
low noise setting by programming it into the corresponding bitfield in CMU_HFXOSTEADYSTATECTRL while the HFXO is off.
If low noise is not required, the same PDA algorithm can be configured to optimize the HFXO for low current consumption by enabling
LOWPOWER in the CMU_HFXOCTRL register before starting up the HFXO. The found IBTRIMXOCORE setting can be saved as a
future low current setting.
Default PDA is started automatically once the HFXO has become ready. Repeated PDA can be triggered by writing HFXOPEAKDETSTART to 1 in the CMU_CMD register. PDA can also be triggered only by the command register by configuring PEAKDETSHUNTOPTMODE to CMD in the CMU_HFXOCTRL register before starting the HFXO. For PDA to work correctly, the REGISHUPPER bitfield of
CMU_HFXOSTEADYSTATECTRL should be programmed to the value of the steady state REGISH + 3. The PEAKDETTIMEOUT bitfield in the CMU_HFXOTIMEOUTCTRL register is used to time the PDA steps and needs to be configured according to the Device
Datasheet for the given crystal. The PEAKDETEN bitfield of the CMU_HFXOSTEADYSTATECTRL register is only used during manual
(i.e. fully software controlled) peak detection and is ignored during automatic or command based triggering of the PDA. Note that the
manual PDA mode is not recommended for general usage and therefore it is not further described. PDA should not be used when using
an external wave as clock source.
Current consumption can be (further) reduced by running Shunt Current Optimization (SCO) after PDA. Once SCO is ready as indicated by the HFXOSHUNTOPTRDY flag, the found optimal regulator output current setting is available in the REGISH bitfield of the
CMU_HFXOTRIMSTATUS register. This REGISH setting should be saved and can be applied directly during a future HFXO startup as
a low current setting by programming it into the corresponding bitfield in CMU_HFXOSTEADYSTATECTRL while the HFXO is off. Normally SCO is run only for initial HFXO start up. The amplitude of the oscillator is not strongly dependent on temperature, but further
optimization may be done each time that the temperature changes significantly. In that case, run SCO again by writing HFXOSHUNTOPTSTART to 1 in the CMU_CMD register. SCO depends on the LOWPOWER setting in the CMU_HFXOCTRL and needs to be rerun if that value has been changed.
Default SCO is started automatically once the HFXO has become ready and PDA has finished. Repeated SCO can be triggered by
writing HFXOSHUNTOPTSTART to 1 in the CMU_CMD register. SCO can also be triggered only by the command register by configuring PEAKDETSHUNTOPTMODE to CMD in the CMU_HFXOCTRL register before starting the HFXO. For SCO to work correctly, the
REGISHUPPER bitfield of CMU_HFXOSTEADYSTATECTRL should be programmed to the value of the steady state REGISH + 3. The
SHUNTOPTTIMEOUT bitfield in the CMU_HFXOTIMEOUTCTRL register is used to time the SCO steps and needs to be configured
according to the Device Datasheet for the given crystal. The REGSELILOW bitfield of the CMU_HFXOSTEADYSTATECTRL register is
only used during manual (i.e. fully software controlled) shunt current optimization and is ignored during automatic or command based
triggering of the SCO. Note that the manual SCO mode is not recommended for general usage and therefore it is not further described.
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10.3.2.5 LFXO Configuration
The Low Frequency Crystal Oscillator (LFXO) is default configured to ensure safe startup for all crystals. In order to optimize startup
time and power consumption for a given crystal, it is possible to adjust the startup gain in the oscillator by programming the GAIN field
in CMU_LFXOCTRL. Refer to the Device Datasheet and application notes for guidelines in selecting correct components and crystals
as well as for configuration trade-offs.
The LFXO can be retained on in EM4 Hibernate/Shutoff. In that case its required configuration is latched/retained throughout EM4 even
though the CMU_LFXOCTRL register itself will be reset. Upon EM4 exit the CMU_LFXOCTRL register therefore needs to be reconfigured to its original settings and the LFXO needs to be restarted via CMU_OSCENCMD, before optionally unlatching the retained LFXO
configuration by writing 1 to EM4UNLATCH in the EMU_CMD register. The LFXO startup time is configured via the TIMEOUT bitfield of
the CMU_LFXOCTRL register. In case the LFXO has been retained throughout EM4 Hibernate/Shutoff, it can be quickly restarted for
use as LFACLK, LFBCLK or LFECLK by using its minimum TIMEOUT setting. While retained, the LFXO can be used downto EM4 Hibernate as source for LFECLK and downto EM4 Shutoff as source for CRYOCLK.
The LFXO crystal is connected to the LFXTAL_N/LFXTAL_P pins as shown in Figure 10.7 LFXO Pin Connection on page 216
Figure 10.7 LFXO Pin Connection
It is possible to connect an external clock source to the LFXTAL_N pin of the LFXO oscillator. By configuring the MODE field in
CMU_LFXOCTRL, the LFXO can be bypassed. If MODE is set to BUFEXTCLK, an external active sine source can be used as clock
source. If MODE is set to DIGEXTCLK, an external active CMOS source can be used as clock source.
The LFXO includes on-chip tunable capacitance, which can replace external load capacitors. The TUNING bitfield of the
CMU_LFXOCTRL register is used to tune the internal load capacitance connected between LFXTAL_P and ground and LFXTAL_N and
ground symmetrically. The capacitance range and step size information is available in the device datasheets. Use the formula below to
calculate the TUNING bitfield:
TUNING = ((desiredTotalLoadCap * 2 - Min(CLFXO_T)) / CLFXO_TS)
Equation: CMU LFXO Tuning Capacitance Equation
These tunable capacitors can also be used to compensate for temperature drift of the XTAL in software. Crystals normally have a temperature dependency which is given by a parabolic function. The crystal has highest frequency at its turnover temperature, normally
25C. The frequency is reduced following a parabola for higher and lower temperatures. The LFXO offers a mechanism to internally add
capacitance on the LFXTAL_N and LFXTAL_P pins (in parallel to an optional external load capacitance). The variation in frequency as
a function of temperature can therefore be compensated by adjusting the load capacitance. When the temperature compensation
scheme is used, the maximum internal capacitance should be used to obtain good frequency matching at the turnover temperature. For
higher and lower temperatures one then has the maximum tuning range available. The external load capacitance must then of course
be reduced accordingly. Note that the ADC (22. ADC - Analog to Digital Converter) includes an embedded temperature sensor and that
the EMU (9. EMU - Energy Management Unit) offers a temperature management interface, both of which can be used in combination
with this LFXO temperature compensation scheme.
The XTAL oscillation amplitude can be controlled via the HIGHAMPL bitfield in CMU_LFXOCTRL. Setting HIGHAMPL to 1 will result in
higher amplitude, which in turn provides safer operation, somewhat improved duty cycle, and lower sensitivity to noise at the cost of
increased current consumption.
The AGC bit of the CMU_LFXOCTRL register is used to turn on or off the Automatic Gain Control module that adjusts the amplitude of
the XTAL. When disabled, the LFXO will run at the startup current and the XTAL will oscillate rail to rail, again providing safer operation,
improved duty cycle, and lower sensitivity to noise at the cost of increased current consumption.
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10.3.2.6 HFRCO and AUXHFRCO Configuration
It is possible to calibrate the HFRCO and AUXHFRCO to achieve higher accuracy (see the device datasheets for details on accuracy).
The frequency is adjusted by changing the TUNING and FINETUNING bitfields in CMU_HFRCOCTRL and CMU_AUXHFRCOCTRL.
Changing to a higher value will result in a lower frequency. Please refer to the datasheet for stepsize details.
The HFRCO and AUXHFRCO can be set to one of several different frequency bands from 1 MHz to 38 MHz by setting the FREQRANGE field in CMU_HFRCOCTRL and CMU_AUXHFRCOCTRL. The HFRCO and AUXHFRCO frequency bands are calibrated during production test, and the production tested calibration values can be read from the Device Information (DI) page. The DI page contains a separate tuning value for each frequency band. During reset, HFRCO and AUXHFRCO tuning values are set to the production
calibrated values for the 19 MHz band, which is the default frequency band. When changing to a different HFRCO or AUXHFRCO
band, make sure to also update the TUNING value and other bitfields in the CMU_HFRCOCTRL and CMU_AUXHFRCOCTRL registers. Typically the entire register is written with a value obtained from the Device Information (DI) page. Please refer to for information
on which frequency band settings are stored in the DI page.
The frequency can be tuned more accurately, at the cost of increased current consumption, via the FINETUNING bitfield if finetuning
has been enabled via the FINETUNINGEN bit. The HFRCO and AUXHFRCO both contain a local prescaler, which can be used in combination with any FREQRANGE setting. These prescalers allow the output clocks to be divided by 1, 2, or 4 as configured in the
CLKDIV bitfield.
10.3.2.7 LFRCO Configuration
It is possible to calibrate the LFRCO to achieve higher accuracy (see the device datasheets for details on accuracy). The frequency is
adjusted by changing the TUNING bitfield in CMU_LFRCOCTRL. Changing to a higher value will result in a lower frequency. Please
refer to the datasheet for stepsize details.
The LFRCO can be retained on in EM4 Hibernate/Shutoff. In that case its required configuration is latched/retained throughout EM4
even though the CMU_LFRCOCTRL register itself will be reset. Upon EM4 exit the CMU_LFRCOCTRL register therefore needs to be
reconfigured to its original settings and the LFRCO needs to be restarted via CMU_OSCENCMD, before optionally unlatching the retained LFRCO configuration by writing 1 to EM4UNLATCH in the EMU_CMD register. The LFRCO startup time is configured via the
TIMEOUT bitfield of the CMU_LFRCOCTRL register. Default its 16 cycle startup should be used. However, in case the LFRCO has
been retained throughout EM4 Hibernate/Shutoff, it can be quickly restarted for use as LFACLK or LFBCLK by using its minimum TIMEOUT setting. While retained, the LFRCO can be used downto EM4 Hibernate as source for LFECLK and downto EM4 Shutoff as
source for CRYOCLK.
The LFRCO is also calibrated in production and its TUNING values are set to the correct value during reset.
The LFRCO can be put in duty cycle mode by setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. This will
reduce current consumption, but will result in slightly worse accuracy especially at high temperatures. Setting the ENCHOP and/or ENDEM bitfields to 1 in CMU_LFRCOCTRL register will improve the average LFRCO frequency accuracy at the cost of a worse cycle to
cycle accuracy.
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CMU - Clock Management Unit
10.3.2.8 RC Oscillator Calibration
The CMU has built-in HW support to efficiently calibrate the RC oscillators (LFRCO, HFRCO, AUXHFRCO) at run-time, see Figure
10.9 HW-support for RC Oscillator Calibration on page 218 for an illustration of this circuit. The concept is to select a reference and
compare the RC frequency with the reference frequency. When the calibration circuit is started, one down-counter running on a selectable clock (DOWNSEL in CMU_CALCTRL) and one up-counter running on a selectable clock (UPSEL in CMU_CALCTRL) are started
simultaneously. The top value for the down-counter must be written to CMU_CALCNT before calibration is started. The down-counter
counts for CMU_CALCNT+1 cycles. When the down-counter has reached 0, the up-counter is sampled and the CALRDY interrupt flag
is set. If CONT in CMU_CALCTRL is cleared, the counters are stopped after finishing the ongoing calibration. If continuous mode is
selected by setting CONT in CMU_CALCTRL the down-counter reloads the top value and continues counting and the up-counter restarts from 0. Software can then read out the sampled up-counter value from CMU_CALCNT. The up-counter has counted (the sampled
value)+1 cycles. The ratio between the reference and the oscillator subject to the calibration can easily be found using top+1 and sample+1. Overflows of the up-counter will not occur. If the up-counter reaches its top value before the down-counter reaches 0, the upcounter stays at its top value. Calibration can be stopped by writing CALSTOP in CMU_CMD. With this HW support, it is simple to write
efficient calibration algorithms in software.
DOWNCLK Domain
Reload down-counter with
top value in continuous
mode.
CMU_CALCTRL.DOWNSEL
AUXHFRCO
HFRCO
LFRCO
DOWNCLK
HFXO
20-bit down-counter
Write top-value using
CMU_CALCNT before
starting calibration.
TOP
LFXO
PRS[PRSDOWNSEL]
(Default) HFCLK
=0?
UPCLK Domain
SYNC
Take snapshot of up-counter
in up-counter bufffer. If in
continuous mode, restart upcounter from 0.
CMU_CALCTRL.UPSEL
AUXHFRCO
HFRCO
LFRCO
UPCLK
20-bit up-counter
HFXO
20-bit up-counter
buffer
LFXO
PRS[PRSUPSEL]
SYNC
HFCLK Domain
CMU_CALCNT
SYNC
Set CMU_IF.CALRDY
Figure 10.9 HW-support for RC Oscillator Calibration
The counter operation for single and continuous mode are shown in Figure 10.10 Single Calibration (CONT=0) on page 219 and Figure 10.11 Continuous Calibration (CONT=1) on page 219 respectively.
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Up-counter sampled and CALRDY
interrupt flag set.
Sampled value available in
CMU_CALCNT.
Up-counter
0
TOP
Down-counter
0
Calibration Started
Calibration Stopped
(counters stopped)
Figure 10.10 Single Calibration (CONT=0)
Up-counter sampled and CALRDY
interrupt flag set.
Sampled value available in
CMU_CALCNT.
Up-counter sampled and CALRDY
interrupt flag set.
Sampled value available in
CMU_CALCNT.
Up-counter
0
TOP
Down-counter
0
Calibration Started
Figure 10.11 Continuous Calibration (CONT=1)
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CMU - Clock Management Unit
10.3.2.9 Automatic HFXO Start
The enabling of the HFXO and its selection as HFCLKSRC source can be performed automatically by hardware. Automatic control of
the HFXO is controlled via the AUTOSTARTSELEM0EM1 and AUTOSTARTEM0EM1 bits in the CMU_HFXOCTRL register. It further
depends on the energy mode of the EFM32 .
An automatic HFXO enable is performed only if any of the following conditions are met:
• EFM32 is in EM0/EM1 and AUTOSTARTEM0EM1 or AUTOSTARTSELEM0EM1 are set to 1.
An automatic HFXO select is performed only if any of the following conditions is met:
• EFM32 is in EM0/EM1 and AUTOSTARTSELEM0EM1 is set to 1.
Whenever any of the conditions for automatic HFXO enable is met, software is not alllowed to disable the HFXO. An attempt to do so
(e.g. by writing 1 to the HFXODIS bit) is ignored and causes the HFXODISERR bit in the CMU_IF register to be set to 1. Similarly,
whenever any of the conditions for automatic HFXO selection is met, software is not alllowed to deselect the HFXO as clock source for
HFSRCCLK. An attempt to do so (e.g. by selecting another clock source via CMU_HFCLKSEL) is ignored and causes the HFXODISERR bit in the CMU_IF register to be set to 1. Note that CMUERR is not implied by HFXODISERR. CMUERR will not get set to 1 for
the above scenarios in which HFXODISERR gets set.
Software can only disable or deselect the HFXO after removing all of the HFXO automatic enable or select reasons. Note that if the
autostart functionality is not used, software can always disable or deselect the HFXO even if hardware requires the HFXO as indicated
via HFXOREQ bitfield in CMU_STATUS. The HFXODISERR flag will not get set in that case. The HFXO is only disabled by hardware
upon EM2, EM3 or EM4 entry.
In case that AUTOSTARTSELEM0EM1 is set to 1 in EM0/EM1 (irrespective of the other autostart bits), the HFXO select will occur immediately, even if HFXO is not ready yet. Upon wake-up into EM0/EM1 this can therefore lead to a relatively long startup time as the
system will not start operating from the HFRCO as it would otherwise do.
Note that the user should take care that the settings in the MSC_READCTRL and CMU_CTRL registers, as described in 10.3.3 Configuration For Operating Frequencies, are compatible with 40 MHz HFXO operation before enabling the HFXO automatic startup feature.
A basic automatic HFXO start scenario is shown in Figure 10.12 CMU Automatic startup and selection of HFXO on page 220.
EM0/EM1 entry with CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 1
HFXO ready
Automatic switch to HFXO (and disable of HFRCO)
CMU_STATUS.HFRCORDY
CMU_STATUS.HFRCOENS
status
CMU_HFCLKSTATUS.HF = HFRCO
CMU_STATUS.HFXORDY
CMU_STATUS.HFXOENS
CMU_HFCLKSTATUS.HF = HFXO
clocks
HFCLK
HFRCO
HFXO
Figure 10.12 CMU Automatic startup and selection of HFXO
If an automatic selection of HFXO is performed, which switches the clock source used for HFCLKSRC, then the HFXOAUTOSW bit in
CMU_IF is set to 1. After automatic enable and selection of the HFXO, the HFRCO is automatically disabled in case it is running. The
disabling of a running HFRCO is signalled via the HFRCODIS bit in CMU_IF. This only applies to the HFRCO. If for example the LFXO
was used as HFSRCCLK at the time of automatic selection of the HFXO, the LFXO remains unaffected.
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The interaction between automatic HFXO startup and selection with startup and selection of HFRCO is shown in Figure 10.13 CMU
HFRCO startup/selection while awaiting automatic HFXO startup/selection on page 221.
EM0/EM1 entry with CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 0
EM0/EM1 Entry
&&
CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 0
HFRCO selected
HFXO ready
Automatic switch to HFXO and disable of HFRCO
CMU_STATUS.HFRCORDY
CMU_STATUS.HFRCOENS
status
CMU_HFCLKSTATUS.HF = HFRCO
CMU_STATUS.HFXORDY
CMU_STATUS.HFXOENS
CMU_HFCLKSTATUS.HF = HFXO
clocks
HFCLK
HFRCO
HFXO
Figure 10.13 CMU HFRCO startup/selection while awaiting automatic HFXO startup/selection
Figure 10.14 CMU Automatic HFXO startup/selection while HFRCO started/selected
10.3.3 Configuration For Operating Frequencies
The HFXO is capable of driving crystals up to 40 MHz, which allows the EFM32 to run at up to this frequency. The MSC and the Low
Energy Peripheral Interface however need to be configured correctly to allow operation at higher frequencies as explained below.
The MODE bitfield in MSC_READCTRL makes sure the flash is able to operate at the given HFCLK frequency by inserting wait states
for flash accesses. The required settings for controlling flash wait states are shown in Table 10.2 Configuration For Operating Frequencies: Flash Wait States on page 221. The WSHFLE bitfield in CMU_CTRL is used to ensure that the Low Energy Peripheral Interface is
able to operate at the given HFBUSCLK LE frequency by inserting wait states when using this interface. The required settings are shown
in Table 10.3 Configuration For Operating Frequencies: Low Energy Peripheral Interface on page 221.
Before going to a high frequency, make sure the registers in the table have the correct values. When going down in frequency, make
sure to keep the registers at the values required by the higher frequency until after the switch has been done.
Table 10.2. Configuration For Operating Frequencies: Flash Wait States
Condition
MODE in MSC_READCTRL
HFCLK <= 25 MHz
WS0 / WS1
HFCLK > 25 MHz
WS1
Table 10.3. Configuration For Operating Frequencies: Low Energy Peripheral Interface
Condition
WSHFLE in CMU_CTRL
HFBUSCLKLE <= 32 MHz
0/1
HFBUSCLKLE > 32 MHz
1
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CMU - Clock Management Unit
10.3.4 Energy Modes
The availability of oscillators and system clocks depends on the chosen energy mode. Default the high frequency oscillators (HFRCO,
AUXHFRCO, and HFXO) and high frequency clocks (HFSRCLK, HFCLK, HFCORECLK, HFBUSCLK, HFPERCLK, HFCLKLE) are
available downto EM1 Sleep. From EM2 DeepSleep onwards these oscillators and clocks are normally off, although special cases exist
as summarized in Table 10.4 Oscillator and clock availability in Energy Modes on page 222 and Table 9.2 EMU Energy Mode Overview
on page 157. The CMU overview figure in Figure 10.1 CMU Overview on page 204 also indicates which oscillators and clocks can be
used in what energy modes.
The low frequency oscillators (LFRCO and LFXO) are available in all energy modes except in EM3 Stop when they are off by definition.
Default these oscillators are also off in EM4 Hibernate and EM4 Shutoff, but they can be retained on in these states as well if needed.
The ultra low frequency oscillator (ULFRCO) is default on in all energy modes, except for EM4 Shutoff, but it can be retained on in that
state as well if needed. The low frequency clocks (LFACLK, LFBCLK, LFECLK, WDOGCLK, and CRYOCLK) are in various power domains and therefore their availability not only depends on the chosen clock source, but also on the chosen energy mode as indicated in
Table 10.4 Oscillator and clock availability in Energy Modes on page 222.
Table 10.4. Oscillator and clock availability in Energy Modes
EM0 Active/EM1
Sleep
EM2 DeepSleep
EM3 Stop
EM4 Hibernate
EM4 Shutoff
HFRCO
On1
Off
Off
Off
Off
HFXO
On1
Off
Off
Off
Off
AUXHFRCO
On1
On2
On2
Off
Off
LFRCO, LFXO
On1
On1
Off
Retained on3
Retained on3
ULFRCO
On
On
On
On
Retained on3
HFSRCLK, HFCLK,
HFCORECLK,
HFBUSCLK,
HFPERCLK,
HFCLKLE
On1
Off
Off
Off
Off
AUXCLK
On1
On2
On2
Off
Off
LFACLK, LFBCLK
On1
On1
On4
Off
Off
LFECLK
On1
On1
On4
Retained on3
Off
WDOGCLK
On1
On1
On4
Off
Off
CRYOCLK
On1
On1
On4
Retained on3
Retained on3
RFSENSECLK
On1
On1
On4
Retained on3
Retained on3
1
Under software control.
2
Default off, but kept active if used by the ADC.
3
Default off, but can be retained on.
4
On only if ULFRCO is used as clock source.
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10.3.5 Clock Output on a Pin
It is possible to configure the CMU to output clocks on the CMU_OUT0 and CMU_OUT1 pins. This clock selection is done using the
CLKOUTSEL0 and CLKOUTSEL1 bitfields respectively in CMU_CTRL. The required output pins must be enabled in the CMU_ROUTEPEN register and the pin locations can be configured in the CMU_ROUTELOC0 register. The following clocks can be output on a
pin:
• HFSRCCLK and HFEXPCLK. The HFSRCCLK is the high frequency clock before any prescaling has been applied. The HFEXPCLK
is a prescaled version of HFCLK as controlled by the HFEXPPRESC bitfield in the CMU_HFPRESC register.
• The unqualified clock output from any of the oscillators (ULFRCO, LFRCO, LFXO, HFXO). Note that these unqualified clocks can
exhibit glitches or skewed duty-cycle during startup and therefore these clock outputs are normally not used before observing the
related ready flag being set to 1 in CMU_STATUS.
• The qualified clock from any of the oscillators (ULFRCO, LFRCO, LFXO, HFXO, HFRCO, AUXHFRCO). A qualified clock will not
have any glitches or skewed duty-cycle during startup. For LFRCO, LFXO and HFXO correct configuration of the TIMEOUT bitfield(s) in CMU_LFRCOCTRL, CMU_LFXOCTRL and CMU_HFXOTIMEOUTCTRL respectively is required to guarantee a properly
qualified clock.
HFCLK will not have a 50-50 duty cycle when any other division factor than 1 is used in CMU_HFPRESC (i.e. if PRESC is not equal to
0). In such a case, the exported HFEXPCLK will therefore also not be 50-50 when its division factor is not set to an even number in
CMU_HFEXPPRESC.
10.3.6 Clock Output on PRS
The CMU can be used as a PRS producer. It can output clocks onto PRS which can be selected by a consumer as CMUCLKOUT0 and
CMUCLKOUT1. The clocks which can be produced via CMUCLKOUT0 and CMUCLKOUT1 are selected via the CLKOUTSEL0 and
CLKOUTSEL1 fields respectively in CMU_CTRL.
Note that the CLKOUTSEL0 and CLKOUTSEL1 fields are also used for selecting which clock is output onto a pin as described in
10.3.5 Clock Output on a Pin. In contrast with clock output on a pin however, output of a clock onto PRS does not depend on any
configuration of the CMU_ROUTEPEN and CMU_ROUTELOC0 registers.
10.3.7 Error Handling
Certain restrictions apply to how and when the CMU registers can be configured as is desribed for the respective registers. Not adhering to these restrictions can lead to unpredictable and non-defined behaviour. Some of these software restrictions are checked in hardware and not adhering to them will cause the CMUERR interrupt flag in CMU_IF to be set to 1. The restrictions impacting CMUERR are
as follows:
• CMU_HFRCOCTRL should not be written while HFRCOBSY in the CMU_SYNCBUSY register is set to 1.
• CMU_AUXHFRCOCTRL should not be written while AUXHFRCOBSY in the CMU_SYNCBUSY register is set to 1.
• CMU_HFXOSTARTUPCTRL, CMU_HFXOSTEADYSTATECTRL and CMU_HFXOTIMEOUTCTRL should not be written while
HFXOBSY in the CMU_SYNCBUSY register is set to 1. Note that writes to CMU_HFXOCTRL do not impact CMUERR. Although
most of its bitfields need to be configured before enabling the HFXO, it it allowed to change the AUTOSTART bits (i.e. AUTOSTARTSELEM0EM1 and AUTOSTARTEM0EM1) at any time.
• HFXO should not be enabled before it has been properly disabled (so only enable HFXO when HFXOENS=0 or HFXOBSY=0). Likewise, HFXO should not be disabled before it has been properly enabled (so only disable HFXO when HFXOENS=1 or HFXOBSY=0).
• CMU_LFRCOCTRL should not be written while LFRCOBSY in the CMU_SYNCBUSY register is set to 1. The GMCCURTUNE bitfield should not be written with a differing value while the LFRCOVREFBSY flag is set to 1.
• CMU_LFXOCTRL should not be written while LFXOBSY in the CMU_SYNCBUSY register is set to 1.
10.3.8 Interrupts
The interrupts generated by the CMU module are combined into one interrupt vector. If CMU interrupts are enabled, an interrupt will be
made if one or more of the interrupt flags in CMU_IF and their corresponding bits in CMU_IEN are set.
10.3.9 Wake-up
The CMU can be (partially) active all the way down to EM4 Shutoff. It can wake up the CPU from EM2 upon LFRCO or LFXO becoming
ready as LFRCORDY and LFXORDY can be used as wake-up interrupt.
10.3.10 Protection
It is possible to lock the control- and command registers to prevent unintended software writes to critical clock settings. This is controlled by the CMU_LOCK register.
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10.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
CMU_CTRL
RW
CMU Control Register
0x010
CMU_HFRCOCTRL
RWH
HFRCO Control Register
0x018
CMU_AUXHFRCOCTRL
RW
AUXHFRCO Control Register
0x020
CMU_LFRCOCTRL
RW
LFRCO Control Register
0x024
CMU_HFXOCTRL
RW
HFXO Control Register
0x028
CMU_HFXOCTRL1
RW
HFXO Control 1
0x02C
CMU_HFXOSTARTUPCTRL
RW
HFXO Startup Control
0x030
CMU_HFXOSTEADYSTATECTRL RW
HFXO Steady State control
0x034
CMU_HFXOTIMEOUTCTRL
RW
HFXO Timeout Control
0x038
CMU_LFXOCTRL
RW
LFXO Control Register
0x050
CMU_CALCTRL
RW
Calibration Control Register
0x054
CMU_CALCNT
RWH
Calibration Counter Register
0x060
CMU_OSCENCMD
W1
Oscillator Enable/Disable Command Register
0x064
CMU_CMD
W1
Command Register
0x070
CMU_DBGCLKSEL
RW
Debug Trace Clock Select
0x074
CMU_HFCLKSEL
W1
High Frequency Clock Select Command Register
0x080
CMU_LFACLKSEL
RW
Low Frequency A Clock Select Register
0x084
CMU_LFBCLKSEL
RW
Low Frequency B Clock Select Register
0x088
CMU_LFECLKSEL
RW
Low Frequency E Clock Select Register
0x090
CMU_STATUS
R
Status Register
0x094
CMU_HFCLKSTATUS
R
HFCLK Status Register
0x09C
CMU_HFXOTRIMSTATUS
R
HFXO Trim Status
0x0A0
CMU_IF
R
Interrupt Flag Register
0x0A4
CMU_IFS
W1
Interrupt Flag Set Register
0x0A8
CMU_IFC
(R)W1
Interrupt Flag Clear Register
0x0AC
CMU_IEN
RW
Interrupt Enable Register
0x0B0
CMU_HFBUSCLKEN0
RW
High Frequency Bus Clock Enable Register 0
0x0C0
CMU_HFPERCLKEN0
RW
High Frequency Peripheral Clock Enable Register 0
0x0E0
CMU_LFACLKEN0
RW
Low Frequency A Clock Enable Register 0 (Async Reg)
0x0E8
CMU_LFBCLKEN0
RW
Low Frequency B Clock Enable Register 0 (Async Reg)
0x0F0
CMU_LFECLKEN0
RW
Low Frequency E Clock Enable Register 0 (Async Reg)
0x100
CMU_HFPRESC
RW
High Frequency Clock Prescaler Register
0x108
CMU_HFCOREPRESC
RW
High Frequency Core Clock Prescaler Register
0x10C
CMU_HFPERPRESC
RW
High Frequency Peripheral Clock Prescaler Register
0x114
CMU_HFEXPPRESC
RW
High Frequency Export Clock Prescaler Register
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Offset
Name
Type
Description
0x120
CMU_LFAPRESC0
RW
Low Frequency A Prescaler Register 0 (Async Reg)
0x128
CMU_LFBPRESC0
RW
Low Frequency B Prescaler Register 0 (Async Reg)
0x130
CMU_LFEPRESC0
W
Low Frequency E Prescaler Register 0 (Async Reg). When waking up
from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to
take effect
0x140
CMU_SYNCBUSY
R
Synchronization Busy Register
0x144
CMU_FREEZE
RW
Freeze Register
0x150
CMU_PCNTCTRL
RW
PCNT Control Register
0x15C
CMU_ADCCTRL
RW
ADC Control Register
0x170
CMU_ROUTEPEN
RW
I/O Routing Pin Enable Register
0x174
CMU_ROUTELOC0
RW
I/O Routing Location Register
0x180
CMU_LOCK
RWH
Configuration Lock Register
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10.5 Register Description
10.5.1 CMU_CTRL - CMU Control Register
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0
1
2
CLKOUTSEL0
RW 0x0
3
4
5
6
7
RW 0x0
CLKOUTSEL1
8
9
10
11
12
13
14
15
16
0
RW
17
18
19
21
20
WSHFLE
Name
1
Access
HFPERCLKEN RW
Reset
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
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CMU - Clock Management Unit
Bit
Name
Reset
Access
31:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
HFPERCLKEN
1
RW
Description
HFPERCLK Enable
Set to enable the HFPERCLK.
19:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
WSHFLE
0
RW
Wait State for High-Frequency LE Interface
Set to allow access to LE peripherals when running HFBUSCLKLE at frequencies higher than 32 MHz
15:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:5
CLKOUTSEL1
0x0
RW
Clock Output Select 1
Controls the clock output multiplexer. To actually output on the pin, set CLKOUT1PEN in CMU_ROUTE.
Value
Mode
Description
0
DISABLED
Disabled
1
ULFRCO
ULFRCO (directly from oscillator)
2
LFRCO
LFRCO (directly from oscillator)
3
LFXO
LFXO (directly from oscillator)
6
HFXO
HFXO (directly from oscillator)
7
HFEXPCLK
HFEXPCLK
9
ULFRCOQ
ULFRCO (qualified)
10
LFRCOQ
LFRCO (qualified)
11
LFXOQ
LFXO (qualified)
12
HFRCOQ
HFRCO (qualified)
13
AUXHFRCOQ
AUXHFRCO (qualified)
14
HFXOQ
HFXO (qualified)
15
HFSRCCLK
HFSRCCLK
4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
CLKOUTSEL0
0x0
RW
Clock Output Select 0
Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE.
Value
Mode
Description
0
DISABLED
Disabled
1
ULFRCO
ULFRCO (directly from oscillator)
2
LFRCO
LFRCO (directly from oscillator)
3
LFXO
LFXO (directly from oscillator)
6
HFXO
HFXO (directly from oscillator)
7
HFEXPCLK
HFEXPCLK
9
ULFRCOQ
ULFRCO (qualified)
10
LFRCOQ
LFRCO (qualified)
11
LFXOQ
LFXO (qualified)
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Bit
Name
Reset
12
HFRCOQ
HFRCO (qualified)
13
AUXHFRCOQ
AUXHFRCO (qualified)
14
HFXOQ
HFXO (qualified)
15
HFSRCCLK
HFSRCCLK
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CMU - Clock Management Unit
10.5.2 CMU_HFRCOCTRL - HFRCO Control Register
Write this register to set the frequency band in which the HFRCO is to operate. Always update all fields in this registers at once by
writing the value for the desired band, which has been obtained from the Device Information page entry for that band. The TUNING,
FINETUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a nonpreconfigured frequency. When changing this setting there will be no glitches on the HFRCO output, hence it is safe to change this
setting even while the system is running on the HFRCO. Only write CMU_HFRCOCTRL when it is ready for an update as indicated by
HFRCOBSY=0 in CMU_SYNCBUSY.
0
1
2
RWH 0x3C 3
TUNING
4
5
6
7
8
9
10
11
RWH 0x1F
FINETUNING
12
13
14
15
16
17
0x08 18
RW
FREQRANGE
19
20
21
22
RW
CMPBIAS
0x2
23
24
RW
LDOHP
1
25
26
RW
CLKDIV
0x0
27
RW
FINETUNINGEN
Name
0
28
29
30
0xB
Access
RW
Reset
VREFTC
0x010
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31:28
VREFTC
0xB
RW
HFRCO Temperature Coefficient Trim on Comparator Reference
Writing this field adjusts the temperature coefficient trim on comparator reference.
27
FINETUNINGEN
0
RW
Enable reference for fine tuning
Settings this bit enables HFRCO fine tuning.
26:25
CLKDIV
0x0
RW
Locally divide HFRCO Clock Output
Writing this field configures the HFRCO clock output divider.
24
Value
Mode
Description
0
DIV1
Divide by 1.
1
DIV2
Divide by 2.
2
DIV4
Divide by 4.
LDOHP
1
RW
HFRCO LDO High Power Mode
Settings this bit puts the HFRCO LDO in high power mode.
23:21
CMPBIAS
0x2
RW
HFRCO Comparator Bias Current
Writing this field adjusts the HFRCO comparator bias current.
20:16
FREQRANGE
0x08
RW
HFRCO Frequency Range
Writing this field adjusts the HFRCO frequency range.
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
FINETUNING
0x1F
RWH
HFRCO Fine Tuning Value
Writing this field adjusts the HFRCO fine tuning value. Higher value means lower frequency. Fine tuning is only enabled
when FINETUNINGEN is set.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:0
TUNING
0x3C
RWH
HFRCO Tuning Value
Writing this field adjusts the HFRCO tuning value. Higher value means lower frequency.
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10.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register
Write this register with the production calibrated values from the Device Info pages. The TUNING, FINETUNING, FINETUNINGEN and
CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non-preconfigured frequency. Only write
CMU_AUXHFRCOCTRL when it is ready for an update as indicated by AUXHFRCOBSY=0 in CMU_SYNCBUSY.
0
1
2
TUNING
RW 0x3C 3
4
5
6
7
8
9
10
11
RW 0x1F
FINETUNING
12
13
14
15
16
17
FREQRANGE
RW 0x08 18
19
20
21
22
0x2
RW
CMPBIAS
23
24
1
RW
LDOHP
25
26
0x0
27
RW
VREFTC
Name
CLKDIV
Access
0
RW
Reset
FINETUNINGEN RW
28
29
30
0xB
0x018
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31:28
VREFTC
0xB
RW
AUXHFRCO Temperature Coefficient Trim on Comparator Reference
Writing this field adjusts the temperature coefficient trim on comparator reference.
27
FINETUNINGEN
0
RW
Enable reference for fine tuning
Settings this bit enables AUXHFRCO fine tuning.
26:25
CLKDIV
0x0
RW
Locally divide AUXHFRCO Clock Output
Writing this field configures the AUXHFRCO clock output divider.
24
Value
Mode
Description
0
DIV1
Divide by 1.
1
DIV2
Divide by 2.
2
DIV4
Divide by 4.
LDOHP
1
RW
AUXHFRCO LDO High Power Mode
Settings this bit puts the AUXHFRCO LDO in high power mode.
23:21
CMPBIAS
0x2
RW
AUXHFRCO Comparator Bias Current
Writing this field adjusts the AUXHFRCO comparator bias current.
20:16
FREQRANGE
0x08
RW
AUXHFRCO Frequency Range
Writing this field adjusts the AUXHFRCO frequency range.
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
FINETUNING
0x1F
RW
AUXHFRCO Fine Tuning Value
Writing this field adjusts the AUXHFRCO fine tuning value. Higher value means lower frequency. Fine tuning is only enabled when FINETUNINGEN is set.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:0
TUNING
0x3C
RW
AUXHFRCO Tuning Value
Writing this field adjusts the AUXHFRCO tuning value. Higher value means lower frequency.
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CMU - Clock Management Unit
10.5.4 CMU_LFRCOCTRL - LFRCO Control Register
Bit
Name
Reset
Access
Description
31:28
GMCCURTUNE
0x8
RW
Tuning of gmc current
0
1
2
3
TUNING
RW 0x100 4
5
6
7
8
9
10
11
12
13
14
15
16
RW
ENVREF
0
17
RW
ENCHOP
1
18
19
20
22
23
24
25
21
1
RW
ENDEM
Name
RW
Access
TIMEOUT
GMCCURTUNE RW
Reset
0x1
26
27
28
29
30
0x8
0x020
Bit Position
31
Offset
Set to tune GMC current. This field is updated with the production calibrated value during reset, and the reset value might
therefore vary between devices.
27:26
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
25:24
TIMEOUT
0x1
RW
LFRCO Timeout
Configures the start-up delay for LFRCO. Do not change while LFRCO is enabled. When starting up the LFRCO after it has
been completely turned off, use TIMEOUT=16cycles. If the LFRCO has been retained on in EM4, then the TIMEOUT=2cycles configuration is also allowed when re-enabling the LFRCO after EM4 exit (as it is still running).
Value
Mode
Description
0
2CYCLES
Timeout period of 2 cycles
1
16CYCLES
Timeout period of 16 cycles
2
32CYCLES
Timeout period of 32 cycles
23:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18
ENDEM
1
RW
Enable dynamic element matching
Set to enable dynamic element matching. This improves average frequency accuracy at the cost of increased jitter.
17
ENCHOP
1
RW
Enable comparator chopping
Set to enable comparator chopping. This improves average frequency accuracy at the cost of increased jitter.
16
ENVREF
0
RW
Enable duty cycling of vref
Set to enable duty cycling of vref. Clear during calibration of LFRCO. Only change when LFRCO is off.
15:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
TUNING
0x100
RW
LFRCO Tuning Value
Writing this field adjusts the LFRCO frequency (the higher the value, the lower the frequency). This field is updated with the
production calibrated value during reset, and the reset value might therefore vary between devices.
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EFM32JG1 Reference Manual
CMU - Clock Management Unit
10.5.5 CMU_HFXOCTRL - HFXO Control Register
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0
0
RW
MODE
1
2
3
4
5
PEAKDETSHUNTOPTMODE RW 0x0
6
7
8
RW
LOWPOWER
0
9
RW
XTI2GND
0
10
0
RW
XTO2GND
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RW 0x0 25
LFTIMEOUT
26
27
28
0
30
29
0
RW
Name
AUTOSTARTEM0EM1
Access
RW
Reset
AUTOSTARTSELEM0EM1
0x024
Bit Position
31
Offset
Preliminary Rev. 0.2 | 232
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29
AUTOSTARTSELEM0EM1
0
RW
Description
Automatically start and select of HFXO upon EM0/EM1 entry from
EM2/EM3
This bit enables automatic start-up and immediate selection of the HFXO when in EM0/EM1 (also after entry from EM2/
EM3). Note that setting this bit to 1 will stall HFSRCCLK until HFXO becomes ready. Allowed to change at any time.
28
AUTOSTARTEM0EM1
0
RW
Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3
This bit enables automatic start-up of the HFXO when in EM0/EM1 (also after entry from EM2/EM3) without causing an
automatic HFXO selection. Allowed to change at any time.
27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
LFTIMEOUT
0x0
RW
HFXO Low Frequency Timeout
Configures the start-up delay for HFXO measured in LFECLK cycles. Only change when both HFXO and LFECLK are off.
Value
Mode
Description
0
0CYCLES
Timeout period of 0 cycles (disabled)
1
2CYCLES
Timeout period of 2 cycles
2
4CYCLES
Timeout period of 4 cycles
3
16CYCLES
Timeout period of 16 cycles
4
32CYCLES
Timeout period of 32 cycles
5
64CYCLES
Timeout period of 64 cycles
6
1KCYCLES
Timeout period of 1024 cycles
7
4KCYCLES
Timeout period of 4096 cycles
23:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
XTO2GND
0
RW
Clamp HFXTAL_P pin to ground when HFXO oscillator is off.
Set to enable grounding of HFXTAL_P pin when HFXO oscillator is off
9
XTI2GND
0
RW
Clamp HFXTAL_N pin to ground when HFXO oscillator is off.
Set to enable grounding of HFXTAL_N pin when HFXO oscillator is off. Do not enable if MODE=EXTCLK and an external
source is supplied.
8
LOWPOWER
0
RW
Low power mode control.
Set LOWPOWER=1 to enable low current consumption.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:4
PEAKDETSHUNTOPTMODE
0x0
RW
HFXO Automatic Peak Detection and shunt current optimization
mode
Set to AUTOCMD to allow automatic HFXO peak detection and shunt current optimization (MANUAL mode provides direct
control of IBTRIMXOCORE, REGISH, PEAKDETEN, REGSELILOW).
Value
Mode
Description
0
AUTOCMD
Automatic control of HFXO peak detection and shunt optimization sequences. CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPTSTART can also be used.
1
CMD
CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPTSTART can
be used to trigger peak detection and shunt optimization sequences.
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CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
2
MANUAL
3:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
MODE
0
CMU_HFXOSTEADYSTATECTRL IBTRIMXOCORE, REGISH, REGSELILOW, and PEAKDETEN are under full software control and are
allowed to be changed once HFXO is ready.
RW
HFXO Mode
Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in
CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD.
Value
Mode
Description
0
XTAL
38 MHz - 40 MHz crystal oscillator
1
EXTCLK
External clock can be supplied (square or wave) on HFXTAL_N pin.
10.5.6 CMU_HFXOCTRL1 - HFXO Control 1
Access
Name
Reset
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9
XTIBIASEN
1
RW
0
2
3
4
RW 0x4 5
Bit
PEAKDETTHR RW 0x0 1
Name
REGLVL
RW
XTIBIASEN
Access
6
7
8
9
10
11
12
13
14
1
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Description
Reserved for internal use. Do not change.
Reserved for internal use. Do not change.
8:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:4
REGLVL
0x4
RW
Reserved for internal use. Do not change.
Reserved for internal use. Do not change.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
PEAKDETTHR
0x0
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RW
Sets the Peak Detector amplitude detection threshold levels
Preliminary Rev. 0.2 | 234
EFM32JG1 Reference Manual
CMU - Clock Management Unit
10.5.7 CMU_HFXOSTARTUPCTRL - HFXO Startup Control
Bit
Name
Reset
Access
31:28
RESERVED1
0xA
RW
27:21
RESERVED0
0x09
RW
20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:11
CTUNE
0x0A0
RW
0
1
2
3
IBTRIMXOCORE RW
0x60
4
5
6
7
8
9
10
11
12
13
14
RW 0x0A0 15
16
17
18
19
20
21
22
23
24
0x09
26
27
28
29
30
0xA
25
RW
CTUNE
Name
RESERVED0
Access
RW
Reset
RESERVED1
0x02C
Bit Position
31
Offset
Description
Sets oscillator tuning capacitance. Capacitance on HFXTAL_N and
HFXTAL_P (pF) = Ctune = Cpar + CTUNE<8:0> x 40fF. Max Ctune
25pF (CLmax ~12.5pF). CL(DNLmax)=50fF ~ 0.6ppm (12.5ppm/pF)
This CTUNE value is applied during the startup phase of the HFXO
10:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:0
IBTRIMXOCORE
0x60
RW
Sets the startup oscillator core bias current. Current (uA) = IBTRIMXOCORE x 40uA. Bits 6 and 5 may only be high in the crystal
oscillator startup phase
This IBTRIMXOCORE value is applied during the startup phase of the HFXO
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CMU - Clock Management Unit
10.5.8 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State control
0
1
2
3
0x09
4
5
6
7
8
9
IBTRIMXOCORE RW
0xA
RW
10
11
12
13
14
CTUNE
REGISH
RW
REGSELILOW
RW 0x155 15
16
17
18
19
20
21
22
23
24
25
0x3
26
0
27
28
29
30
0xA
RW
Name
PEAKDETEN
Access
RW
Reset
REGISHUPPER
0x030
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31:28
REGISHUPPER
0xA
RW
Set regulator output current level (shunt regulator). Ish = 120uA +
REGISHUPPER x 120uA
Set to steady state value of REGISH + 3.
27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26
PEAKDETEN
0
RW
Enables oscillator peak detectors
Direct control allowed when PEAKDETSHUNTOPTMODE=MANUAL and HFXO is ready.
25:24
REGSELILOW
0x3
RW
Controls regulator minimum shunt current detection relative to
nominal
Steady state used during HFXO FSM. Direct control allowed when PEAKDETSHUNTOPTMODE=MANUAL and HFXO is
ready.
23:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:11
CTUNE
0x155
RW
Sets oscillator tuning capacitance. Capacitance on HFXTAL_N and
HFXTAL_P (pF) = Ctune = Cpar + CTUNE<8:0> x 40fF. Max Ctune
25pF (CLmax ~12.5pF). CL(DNLmax)=50fF ~ 0.6ppm (12.5ppm/pF)
This CTUNE value is applied during the steady state phase of the HFXO (as well as during the peak detection and shunt
current optimization algorithms)
10:7
REGISH
0xA
RW
Sets the steady state regulator output current level (shunt regulator). Ish = 120uA + REGISH x 120uA
This REGISH value is applied during the steady state phase of the HFXO. Direct control allowed when PEAKDETSHUNTOPTMODE=MANUAL and HFXO is ready.
6:0
IBTRIMXOCORE
0x09
RW
Sets the steady state oscillator core bias current. Current (uA) =
IBTRIMXOCORE x 40uA. Bits 6 and 5 may only be high in the crystal oscillator startup phase
This IBTRIMXOCORE value is applied during the steady state phase of the HFXO. It is also used as the initial value during
the peak detection algorithm. Direct control allowed when PEAKDETSHUNTOPTMODE=MANUAL and HFXO is ready.
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CMU - Clock Management Unit
10.5.9 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control
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0
1
2
RW 0x7
STARTUPTIMEOUT
3
4
5
6
RW 0x6
STEADYTIMEOUT
7
8
9
10
RW 0x6
RESERVED2
11
12
13
15
16
17
18
19
20
21
14
RW 0x6
Name
PEAKDETTIMEOUT
Access
SHUNTOPTTIMEOUT RW 0x2
Reset
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
Preliminary Rev. 0.2 | 237
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
31:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:16
SHUNTOPTTIMEOUT
0x2
RW
Description
Wait duration in HFXO shunt current optimization wait state
Wait duration depends on the chosen XTAL (expected value is around 1 us). Program the desired duration measured in
cycles of (at least) 83 ns.
15:12
Value
Mode
Description
0
2CYCLES
Timeout period of 2 cycles
1
4CYCLES
Timeout period of 4 cycles
2
16CYCLES
Timeout period of 16 cycles
3
32CYCLES
Timeout period of 32 cycles
4
256CYCLES
Timeout period of 256 cycles
5
1KCYCLES
Timeout period of 1024 cycles
6
2KCYCLES
Timeout period of 2048 cycles
7
4KCYCLES
Timeout period of 4096 cycles
8
8KCYCLES
Timeout period of 8192 cycles
9
16KCYCLES
Timeout period of 16384 cycles
10
32KCYCLES
Timeout period of 32768 cycles
PEAKDETTIMEOUT
0x6
RW
Wait duration in HFXO peak detection wait state
Wait duration depends on the chosen XTAL (expected value is between 25 us and 200 us). Program the desired duration
measured in cycles of (at least) 83 ns.
Value
Mode
Description
0
2CYCLES
Timeout period of 2 cycles
1
4CYCLES
Timeout period of 4 cycles
2
16CYCLES
Timeout period of 16 cycles
3
32CYCLES
Timeout period of 32 cycles
4
256CYCLES
Timeout period of 256 cycles
5
1KCYCLES
Timeout period of 1024 cycles
6
2KCYCLES
Timeout period of 2048 cycles
7
4KCYCLES
Timeout period of 4096 cycles
8
8KCYCLES
Timeout period of 8192 cycles
9
16KCYCLES
Timeout period of 16384 cycles
10
32KCYCLES
Timeout period of 32768 cycles
11:8
RESERVED2
0x6
RW
7:4
STEADYTIMEOUT
0x6
RW
Wait duration in HFXO startup steady wait state
Wait duration depends on the chosen XTAL (expected value is around 100 us). Program the desired duration measured in
cycles of (at least) 83 ns.
Value
Mode
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Description
Preliminary Rev. 0.2 | 238
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
3:0
Name
Reset
Access
0
2CYCLES
Timeout period of 2 cycles
1
4CYCLES
Timeout period of 4 cycles
2
16CYCLES
Timeout period of 16 cycles
3
32CYCLES
Timeout period of 32 cycles
4
256CYCLES
Timeout period of 256 cycles
5
1KCYCLES
Timeout period of 1024 cycles
6
2KCYCLES
Timeout period of 2048 cycles
7
4KCYCLES
Timeout period of 4096 cycles
8
8KCYCLES
Timeout period of 8192 cycles
9
16KCYCLES
Timeout period of 16384 cycles
10
32KCYCLES
Timeout period of 32768 cycles
STARTUPTIMEOUT
0x7
RW
Description
Wait duration in HFXO startup enable wait state
Wait duration depends on the chosen XTAL (expected value is between 100 us and 1600 us). Program the desired duration
measured in cycles of (at least) 83 ns.
Value
Mode
Description
0
2CYCLES
Timeout period of 2 cycles
1
4CYCLES
Timeout period of 4 cycles
2
16CYCLES
Timeout period of 16 cycles
3
32CYCLES
Timeout period of 32 cycles
4
256CYCLES
Timeout period of 256 cycles
5
1KCYCLES
Timeout period of 1024 cycles
6
2KCYCLES
Timeout period of 2048 cycles
7
4KCYCLES
Timeout period of 4096 cycles
8
8KCYCLES
Timeout period of 8192 cycles
9
16KCYCLES
Timeout period of 16384 cycles
10
32KCYCLES
Timeout period of 32768 cycles
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CMU - Clock Management Unit
10.5.10 CMU_LFXOCTRL - LFXO Control Register
0
1
2
RW 0x00 3
TUNING
4
5
6
7
8
9
0x0
RW
MODE
10
11
12
0x2
RW
GAIN
13
14
0
HIGHAMPL RW
15
1
RW
AGC
16
17
0x0
RW
18
19
20
21
CUR
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0
RW
BUFCUR
22
23
24
25
RW
Name
Reset
0x7
Access
TIMEOUT
26
27
28
29
30
0x038
Bit Position
31
Offset
Preliminary Rev. 0.2 | 240
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
31:27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
TIMEOUT
0x7
RW
Description
LFXO Timeout
Configures the start-up delay for LFXO. Do not change while LFXO is enabled. When starting up the LFXO after it has been
completely turned off, use the TIMEOUT setting required by the XTAL. If the LFXO has been retained on in EM4, then the
TIMEOUT=2cycles configuration is also allowed when re-enabling the LFXO after EM4 exit (as it is still running).
Value
Mode
Description
0
2CYCLES
Timeout period of 2 cycles
1
256CYCLES
Timeout period of 256 cycles
2
1KCYCLES
Timeout period of 1024 cycles
3
2KCYCLES
Timeout period of 2048 cycles
4
4KCYCLES
Timeout period of 4096 cycles
5
8KCYCLES
Timeout period of 8192 cycles
6
16KCYCLES
Timeout period of 16384 cycles
7
32KCYCLES
Timeout period of 32768 cycles
23:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20
BUFCUR
0
RW
LFXO Buffer Bias Current
The default value is intended to cover all use cases and reprogramming is not recommended. Do not change while LFXO is
enabled.
19:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
CUR
0x0
RW
LFXO Current Trim
The default value is intended to cover all use cases and reprogramming is not recommended. Do not change while LFXO is
enabled.
15
AGC
1
RW
LFXO AGC Enable
Set this bit to enable automatic gain control which limits XTAL oscillation amplitude. Do not change while LFXO is enabled.
14
HIGHAMPL
0
RW
LFXO High XTAL Oscillation Amplitude Enable
Set this bit to enable high XTAL oscillation amplitude. Do not change while LFXO is enabled.
13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12:11
GAIN
0x2
RW
LFXO Startup Gain
The optimal value for maximum startup margin depends on the chosen XTAL. Please refer to the Device Datasheet or Simplicity Studio for more information.
10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:8
MODE
0x0
RW
LFXO Mode
Set this to configure the external source for the LFXO. Do not change while LFXO is enabled. The oscillator setting takes
effect when 1 is written to LFXOEN in CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to
LFXODIS in CMU_OSCENCMD.
Value
Mode
Description
0
XTAL
32768 Hz crystal oscillator
1
BUFEXTCLK
An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable
for external sinus wave (32768 Hz).
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CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
2
DIGEXTCLK
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:0
TUNING
0x00
Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.
RW
LFXO Internal Capacitor Array Tuning Value
Writing this field adjusts the internal load capacitance connected between LFXTAL_P and ground and LFXTAL_N and
ground symmetrically (the higher the value, the higher the capacitance, the lower the frequency). Only increment or decrement by 1 LSB at a time.
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CMU - Clock Management Unit
10.5.11 CMU_CALCTRL - Calibration Control Register
0
RW 0x0 1
UPSEL
2
3
4
RW 0x0 5
DOWNSEL
6
7
8
0
RW
CONT
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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RW 0x0
Name
PRSUPSEL
Access
PRSDOWNSEL RW 0x0
Reset
30
0x050
Bit Position
31
Offset
Preliminary Rev. 0.2 | 243
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
31:28
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
27:24
PRSDOWNSEL
0x0
RW
Description
PRS Select for PRS Input when selected in DOWNSEL
Select PRS input for PRS based calibration. Only change when calibration circuit is off.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected as input
1
PRSCH1
PRS Channel 1 selected as input
2
PRSCH2
PRS Channel 2 selected as input
3
PRSCH3
PRS Channel 3 selected as input
4
PRSCH4
PRS Channel 4 selected as input
5
PRSCH5
PRS Channel 5 selected as input
6
PRSCH6
PRS Channel 6 selected as input
7
PRSCH7
PRS Channel 7 selected as input
8
PRSCH8
PRS Channel 8 selected as input
9
PRSCH9
PRS Channel 9 selected as input
10
PRSCH10
PRS Channel 10 selected as input
11
PRSCH11
PRS Channel 11 selected as input
23:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:16
PRSUPSEL
0x0
RW
PRS Select for PRS Input when selected in UPSEL
Select PRS input for PRS based calibration. Only change when calibration circuit is off.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected as input
1
PRSCH1
PRS Channel 1 selected as input
2
PRSCH2
PRS Channel 2 selected as input
3
PRSCH3
PRS Channel 3 selected as input
4
PRSCH4
PRS Channel 4 selected as input
5
PRSCH5
PRS Channel 5 selected as input
6
PRSCH6
PRS Channel 6 selected as input
7
PRSCH7
PRS Channel 7 selected as input
8
PRSCH8
PRS Channel 8 selected as input
9
PRSCH9
PRS Channel 9 selected as input
10
PRSCH10
PRS Channel 10 selected as input
11
PRSCH11
PRS Channel 11 selected as input
15:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8
CONT
0
RW
Continuous Calibration
Set this bit to enable continuous calibration
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
6:4
DOWNSEL
0x0
RW
Calibration Down-counter Select
Selects clock source for the calibration down-counter. Only change when calibration circuit is off.
Value
Mode
Description
0
HFCLK
Select HFCLK for down-counter
1
HFXO
Select HFXO for down-counter
2
LFXO
Select LFXO for down-counter
3
HFRCO
Select HFRCO for down-counter
4
LFRCO
Select LFRCO for down-counter
5
AUXHFRCO
Select AUXHFRCO for down-counter
6
PRS
Select PRS input selected by PRSDOWNSEL as down-counter
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
UPSEL
0x0
RW
Calibration Up-counter Select
Selects clock source for the calibration up-counter. Only change when calibration circuit is off.
Value
Mode
Description
0
HFXO
Select HFXO as up-counter
1
LFXO
Select LFXO as up-counter
2
HFRCO
Select HFRCO as up-counter
3
LFRCO
Select LFRCO as up-counter
4
AUXHFRCO
Select AUXHFRCO as up-counter
5
PRS
Select PRS input selected by PRSUPSEL as up-counter
10.5.12 CMU_CALCNT - Calibration Counter Register
0
1
2
3
4
5
6
7
8
9
10
CALCNT RWH 0x00000
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x054
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:0
CALCNT
0x00000
RWH
Description
Calibration Counter
Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set.
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CMU - Clock Management Unit
10.5.13 CMU_OSCENCMD - Oscillator Enable/Disable Command Register
Access
W1 0
W1 0
HFRCODIS
HFRCOEN
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9
LFXODIS
0
W1
0
W1 0
HFXOEN
Reset
1
W1 0
HFXODIS
Name
2
4
W1 0
AUXHFRCOEN
Bit
3
5
AUXHFRCODIS W1 0
6
W1 0
LFRCOEN
7
W1 0
LFRCODIS
8
W1 0
10
11
9
LFXOEN
Name
W1 0
Access
LFXODIS
Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x060
Bit Position
31
Offset
Description
LFXO Disable
Disables the LFXO. LFXOEN has higher priority if written simultaneously. WARNING: Do not disable the LFXO if this oscillator is selected as the source for HFCLK. When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for
this to take effect
8
LFXOEN
0
W1
LFXO Enable
Enables the LFXO. When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect
7
LFRCODIS
0
W1
LFRCO Disable
Disables the LFRCO. LFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the LFRCO if this
oscillator is selected as the source for HFCLK. When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set
for this to take effect
6
LFRCOEN
0
W1
LFRCO Enable
Enables the LFRCO. When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect
5
AUXHFRCODIS
0
W1
AUXHFRCO Disable
Disables the AUXHFRCO. AUXHFRCOEN has higher priority if written simultaneously.
4
AUXHFRCOEN
0
W1
AUXHFRCO Enable
W1
HFXO Disable
Enables the AUXHFRCO.
3
HFXODIS
0
Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFXO if this oscillator is selected as the source for HFCLK.
2
HFXOEN
0
W1
HFXO Enable
0
W1
HFRCO Disable
Enables the HFXO.
1
HFRCODIS
Disables the HFRCO. HFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRCO if this
oscillator is selected as the source for HFCLK.
0
HFRCOEN
0
W1
HFRCO Enable
Enables the HFRCO.
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CMU - Clock Management Unit
10.5.14 CMU_CMD - Command Register
Access
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
HFXOSHUNTOPTSTART
0
W1
0
W1 0
CALSTART
Reset
1
W1 0
Name
2
CALSTOP
Bit
3
4
W1 0
6
HFXOPEAKDETSTART
Name
5
Access
HFXOSHUNTOPTSTART W1 0
Reset
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x064
Bit Position
31
Offset
Description
HFXO Shunt Current Optimization Start
Starts the HFXO Shunt Current Optimization and runs it one time.
4
HFXOPEAKDETSTART
0
W1
HFXO Peak Detection Start
Starts the HFXO peak detection and runs it one time.
3:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
CALSTOP
0
W1
Calibration Stop
W1
Calibration Start
Stops the calibration counters.
0
CALSTART
0
Starts the calibration, effectively loading the CMU_CALCNT into the down-counter and start decrementing.
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CMU - Clock Management Unit
10.5.15 CMU_DBGCLKSEL - Debug Trace Clock Select
3
2
1
DBG RW 0x0 0
3
2
HF W1 0x0 1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x070
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0:0
DBG
0x0
RW
Description
Debug Trace Clock
Select clock used for debug trace.
Value
Mode
Description
0
AUXHFRCO
AUXHFRCO is the debug trace clock
1
HFCLK
HFCLK is the debug trace clock
10.5.16 CMU_HFCLKSEL - High Frequency Clock Select Command Register
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x074
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
HF
0x0
W1
Description
HFCLK Select
Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop.
Check the status register and confirm that oscillator is ready before switching. If the system can deal with a temporarily
stopped system clock, then it is okay to switch to an oscillator as soon as the status register indicates that the oscillator has
been enabled successfully.
Value
Mode
Description
1
HFRCO
Select HFRCO as HFCLK
2
HFXO
Select HFXO as HFCLK
3
LFRCO
Select LFRCO as HFCLK
4
LFXO
Select LFXO as HFCLK
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CMU - Clock Management Unit
10.5.17 CMU_LFACLKSEL - Low Frequency A Clock Select Register
3
2
LFA RW 0x0 1
0
3
2
LFB RW 0x0 1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x080
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
LFA
0x0
RW
Description
Clock Select for LFA
Selects the clock source for LFACLK.
Value
Mode
Description
0
DISABLED
LFACLK is disabled
1
LFRCO
LFRCO selected as LFACLK
2
LFXO
LFXO selected as LFACLK
4
ULFRCO
ULFRCO selected as LFACLK
10.5.18 CMU_LFBCLKSEL - Low Frequency B Clock Select Register
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x084
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
LFB
0x0
RW
Description
Clock Select for LFB
Selects the clock source for LFBCLK.
Value
Mode
Description
0
DISABLED
LFBCLK is disabled
1
LFRCO
LFRCO selected as LFBCLK
2
LFXO
LFXO selected as LFBCLK
3
HFCLKLE
HFCLK divided by two/four is selected as LFBCLK
4
ULFRCO
ULFRCO selected as LFBCLK
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CMU - Clock Management Unit
10.5.19 CMU_LFECLKSEL - Low Frequency E Clock Select Register
Access
Name
Bit
Name
Reset
Access
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
LFE
0x0
RW
0
2
LFE RW 0x0 1
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x088
Bit Position
31
Offset
Description
Clock Select for LFE
Selects the clock source for LFECLK. When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to
take effect
Value
Mode
Description
0
DISABLED
LFECLK is disabled
1
LFRCO
LFRCO selected as LFECLK
2
LFXO
LFXO selected as LFECLK
4
ULFRCO
ULFRCO selected as LFECLK
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R
R
R
HFRCORDY
HFRCOENS
R
LFRCOENS
R
R
LFRCORDY
HFXORDY
R
LFXOENS
HFXOENS
R
LFXORDY
R
R
CALRDY
AUXHFRCOENS
0
R
HFXOPEAKDETRDY
R
0
HFXOSHUNTOPTRDY R
1
1
0
0
0
0
0
0
0
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Offset
AUXHFRCORDY
0
R
HFXOAMPHIGH
0
0
R
Name
HFXOAMPLOW
Access
R
Reset
HFXOREGILOW
0x090
31
CMU - Clock Management Unit
EFM32JG1 Reference Manual
10.5.20 CMU_STATUS - Status Register
Bit Position
Preliminary Rev. 0.2 | 251
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
31:27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26
HFXOREGILOW
0
R
Description
HFXO regulator shunt current too low
HFXO regulator shunt current too low. When using PEAKDETSHUNTOPTMODE=MANUAL, the REGISH value in
CMU_HFXOSTEADYSTATECTRL should be tuned up by 1 LSB.
25
HFXOAMPLOW
0
R
HFXO amplitude tuning value too low
HFXO oscillation amplitude is too low. When using PEAKDETSHUNTOPTMODE=MANUAL, the IBTRIMXOCORE value in
CMU_HFXOSTEADYSTATECTRL should be tuned up by 1 LSB.
24
HFXOAMPHIGH
0
R
HFXO oscillation amplitude is too high
HFXO oscillation amplitude is too high. When using PEAKDETSHUNTOPTMODE=MANUAL, the IBTRIMXOCORE value in
CMU_HFXOSTEADYSTATECTRL should be tuned down by 1 LSB.
23
HFXOSHUNTOPTRDY
0
R
HFXO Shunt Current Optimization ready
HFXO shunt current optimization is ready.
22
HFXOPEAKDETRDY 0
R
HFXO Peak Detection Ready
HFXO peak detection is ready.
21:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
CALRDY
1
R
Calibration Ready
Calibration is Ready (0 when calibration is ongoing).
15:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9
LFXORDY
0
R
LFXO Ready
LFXO is enabled and start-up time has exceeded.
8
LFXOENS
0
R
LFXO Enable Status
LFXO is enabled (shows disabled status if EM4 repaint is required).
7
LFRCORDY
0
R
LFRCO Ready
LFRCO is enabled and start-up time has exceeded.
6
LFRCOENS
0
R
LFRCO Enable Status
LFRCO is enabled (shows disabled status if EM4 repaint is required).
5
AUXHFRCORDY
0
R
AUXHFRCO Ready
AUXHFRCO is enabled and start-up time has exceeded.
4
AUXHFRCOENS
0
R
AUXHFRCO Enable Status
R
HFXO Ready
AUXHFRCO is enabled.
3
HFXORDY
0
HFXO is enabled and start-up time has exceeded.
2
HFXOENS
0
R
HFXO Enable Status
1
R
HFRCO Ready
HFXO is enabled.
1
HFRCORDY
HFRCO is enabled and start-up time has exceeded.
0
HFRCOENS
1
R
HFRCO Enable Status
HFRCO is enabled.
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CMU - Clock Management Unit
10.5.21 CMU_HFCLKSTATUS - HFCLK Status Register
2
0x1 1
2
1
Reset
SELECTED R
Access
0
3
0x00 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x094
Bit Position
31
Offset
Name
Bit
Name
Reset
Access
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
SELECTED
0x1
R
Description
HFCLK Selected
Clock selected as HFCLK clock source.
Value
Mode
Description
1
HFRCO
HFRCO is selected as HFCLK clock source
2
HFXO
HFXO is selected as HFCLK clock source
3
LFRCO
LFRCO is selected as HFCLK clock source
4
LFXO
LFXO is selected as HFCLK clock source
10.5.22 CMU_HFXOTRIMSTATUS - HFXO Trim Status
R
Access
REGISH
Name
IBTRIMXOCORE R
Reset
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10:7
REGISH
0xA
R
Value of REGISH found by automatic HFXO shunt current optimization algorithm. Can be used as initial value for REGISH value in
the CMU_HFXOSTEADYSTATECTRL register if HFXO is to be started again.
6:0
IBTRIMXOCORE
0x00
R
Value of IBTRIMXOCORE found by automatic HFXO peak detection algorithm. Can be used as initial value for IBTRIMXOCORE in
the CMU_HFXOSTEADYSTATECTRL register if HFXO is to be started again.
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Access
0
4
5
6
7
8
9
0xA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x09C
Bit Position
31
Offset
Description
Preliminary Rev. 0.2 | 253
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0
R
HFRCODIS
R
R
R
R
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
R
CALOF
R
R
HFXODISERR
AUXHFRCORDY
R
HFXOAUTOSW
R
R
HFXOPEAKDETERR
CALRDY
0
R
1
0
0
0
0
0
0
0
0
0
0
HFXOSHUNTOPTRDY R
HFXOPEAKDETRDY
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset
0
R
Name
LFTIMEOUTERR
Access
0
Reset
R
0x0A0
CMUERR
CMU - Clock Management Unit
EFM32JG1 Reference Manual
10.5.23 CMU_IF - Interrupt Flag Register
Bit Position
Preliminary Rev. 0.2 | 254
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
31
CMUERR
0
R
CMU Error Interrupt Flag
Set upon illegal CMU write attempt (e.g. writing CMU_LFRCOCTRL while LFRCOBSY is set).
30:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14
LFTIMEOUTERR
0
R
Low Frequency Timeout Error Interrupt Flag
Set when LFTIMEOUT of CMU_HFXOCTRL triggers before the combined STARTUPTIMEOUT plus STEADYTIMEOUT of
the CMU_HFXOTIMEOUTCTRL register triggers.
13
HFRCODIS
0
R
HFRCO Disable Interrupt Flag
Set when a running HFRCO is disabled because of automatic HFXO start and selection.
12
HFXOSHUNTOPTRDY
0
R
HFXO Automatic Shunt Current Optimization Ready Interrupt Flag
Set when automatic HFXO shunt current optimization is ready.
11
HFXOPEAKDETRDY 0
R
HFXO Automatic Peak Detection Ready Interrupt Flag
Set when automatic HFXO peak detection is ready.
10
HFXOPEAKDETERR 0
R
HFXO Automatic Peak Detection Error Interrupt Flag
Set when automatic HFXO peak detection failed.
9
HFXOAUTOSW
0
R
HFXO Automatic Switch Interrupt Flag
Set when automatic selection of HFXO causes a switch of the source clock used for HFCLKSRC.
8
HFXODISERR
0
R
HFXO Disable Error Interrupt Flag
Set when software tries to disable/deselect the HFXO in case the automatic enable/select reason is met. The HFXO was
not disabled/deselected.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
CALOF
0
R
Calibration Overflow Interrupt Flag
Set when calibration overflow has occurred (i.e. if a new calibration completes before CMU_CALCNT has been read).
5
CALRDY
0
R
Calibration Ready Interrupt Flag
R
AUXHFRCO Ready Interrupt Flag
Set when calibration is completed.
4
AUXHFRCORDY
0
Set when AUXHFRCO is ready (start-up time exceeded).
3
LFXORDY
0
R
LFXO Ready Interrupt Flag
Set when LFXO is ready (start-up time exceeded). LFXORDY can be used as wake-up interrupt.
2
LFRCORDY
0
R
LFRCO Ready Interrupt Flag
Set when LFRCO is ready (start-up time exceeded). LFRCORDY can be used as wake-up interrupt.
1
HFXORDY
0
R
HFXO Ready Interrupt Flag
Set when HFXO is ready (start-up time exceeded).
0
HFRCORDY
1
R
HFRCO Ready Interrupt Flag
Set when HFRCO is ready (start-up time exceeded).
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13
W1 0
HFRCODIS
W1 0
W1 0
W1 0
W1 0
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
W1 0
CALOF
W1 0
W1 0
HFXODISERR
AUXHFRCORDY
W1 0
HFXOAUTOSW
W1 0
W1 0
HFXOPEAKDETERR
CALRDY
11
W1 0
0
1
2
3
4
5
6
7
8
9
10
12
HFXOSHUNTOPTRDY W1 0
HFXOPEAKDETRDY
14
15
16
Offset
17
18
19
20
21
22
23
24
25
26
27
28
29
30
W1 0
Name
LFTIMEOUTERR
Access
W1 0
Reset
31
0x0A4
CMUERR
CMU - Clock Management Unit
EFM32JG1 Reference Manual
10.5.24 CMU_IFS - Interrupt Flag Set Register
Bit Position
Preliminary Rev. 0.2 | 256
EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
31
CMUERR
0
W1
Set CMUERR Interrupt Flag
Write 1 to set the CMUERR interrupt flag
30:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14
LFTIMEOUTERR
0
W1
Set LFTIMEOUTERR Interrupt Flag
Write 1 to set the LFTIMEOUTERR interrupt flag
13
HFRCODIS
0
W1
Set HFRCODIS Interrupt Flag
Write 1 to set the HFRCODIS interrupt flag
12
HFXOSHUNTOPTRDY
0
W1
Set HFXOSHUNTOPTRDY Interrupt Flag
Write 1 to set the HFXOSHUNTOPTRDY interrupt flag
11
HFXOPEAKDETRDY 0
W1
Set HFXOPEAKDETRDY Interrupt Flag
Write 1 to set the HFXOPEAKDETRDY interrupt flag
10
HFXOPEAKDETERR 0
W1
Set HFXOPEAKDETERR Interrupt Flag
Write 1 to set the HFXOPEAKDETERR interrupt flag
9
HFXOAUTOSW
0
W1
Set HFXOAUTOSW Interrupt Flag
Write 1 to set the HFXOAUTOSW interrupt flag
8
HFXODISERR
0
W1
Set HFXODISERR Interrupt Flag
Write 1 to set the HFXODISERR interrupt flag
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
CALOF
0
W1
Set CALOF Interrupt Flag
W1
Set CALRDY Interrupt Flag
Write 1 to set the CALOF interrupt flag
5
CALRDY
0
Write 1 to set the CALRDY interrupt flag
4
AUXHFRCORDY
0
W1
Set AUXHFRCORDY Interrupt Flag
Write 1 to set the AUXHFRCORDY interrupt flag
3
LFXORDY
0
W1
Set LFXORDY Interrupt Flag
Write 1 to set the LFXORDY interrupt flag
2
LFRCORDY
0
W1
Set LFRCORDY Interrupt Flag
Write 1 to set the LFRCORDY interrupt flag
1
HFXORDY
0
W1
Set HFXORDY Interrupt Flag
Write 1 to set the HFXORDY interrupt flag
0
HFRCORDY
0
W1
Set HFRCORDY Interrupt Flag
Write 1 to set the HFRCORDY interrupt flag
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13
(R)W1 0
HFRCODIS
(R)W1 0
(R)W1 0
(R)W1 0
(R)W1 0
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
(R)W1 0
CALOF
(R)W1 0
(R)W1 0
HFXODISERR
AUXHFRCORDY
(R)W1 0
HFXOAUTOSW
(R)W1 0
(R)W1 0
HFXOPEAKDETERR
CALRDY
11
(R)W1 0
0
1
2
3
4
5
6
7
8
9
10
12
HFXOSHUNTOPTRDY (R)W1 0
HFXOPEAKDETRDY
14
15
16
Offset
17
18
19
20
21
22
23
24
25
26
27
28
29
30
(R)W1 0
Name
LFTIMEOUTERR
Access
(R)W1 0
Reset
31
0x0A8
CMUERR
CMU - Clock Management Unit
EFM32JG1 Reference Manual
10.5.25 CMU_IFC - Interrupt Flag Clear Register
Bit Position
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CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
31
CMUERR
0
(R)W1
Clear CMUERR Interrupt Flag
Write 1 to clear the CMUERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
30:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14
LFTIMEOUTERR
0
(R)W1
Clear LFTIMEOUTERR Interrupt Flag
Write 1 to clear the LFTIMEOUTERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
13
HFRCODIS
0
(R)W1
Clear HFRCODIS Interrupt Flag
Write 1 to clear the HFRCODIS interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
12
HFXOSHUNTOPTRDY
0
(R)W1
Clear HFXOSHUNTOPTRDY Interrupt Flag
Write 1 to clear the HFXOSHUNTOPTRDY interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
11
HFXOPEAKDETRDY 0
(R)W1
Clear HFXOPEAKDETRDY Interrupt Flag
Write 1 to clear the HFXOPEAKDETRDY interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
10
HFXOPEAKDETERR 0
(R)W1
Clear HFXOPEAKDETERR Interrupt Flag
Write 1 to clear the HFXOPEAKDETERR interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
9
HFXOAUTOSW
0
(R)W1
Clear HFXOAUTOSW Interrupt Flag
Write 1 to clear the HFXOAUTOSW interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
8
HFXODISERR
0
(R)W1
Clear HFXODISERR Interrupt Flag
Write 1 to clear the HFXODISERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
CALOF
0
(R)W1
Clear CALOF Interrupt Flag
Write 1 to clear the CALOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
5
CALRDY
0
(R)W1
Clear CALRDY Interrupt Flag
Write 1 to clear the CALRDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
4
AUXHFRCORDY
0
(R)W1
Clear AUXHFRCORDY Interrupt Flag
Write 1 to clear the AUXHFRCORDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
3
LFXORDY
0
(R)W1
Clear LFXORDY Interrupt Flag
Write 1 to clear the LFXORDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
2
LFRCORDY
0
(R)W1
Clear LFRCORDY Interrupt Flag
Write 1 to clear the LFRCORDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
1
HFXORDY
0
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(R)W1
Clear HFXORDY Interrupt Flag
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EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
Write 1 to clear the HFXORDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
0
HFRCORDY
0
(R)W1
Clear HFRCORDY Interrupt Flag
Write 1 to clear the HFRCORDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
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13
RW 0
HFRCODIS
RW 0
RW 0
RW 0
RW 0
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
RW 0
CALOF
RW 0
RW 0
HFXODISERR
AUXHFRCORDY
RW 0
HFXOAUTOSW
RW 0
RW 0
HFXOPEAKDETERR
CALRDY
11
RW 0
0
1
2
3
4
5
6
7
8
9
10
12
HFXOSHUNTOPTRDY RW 0
HFXOPEAKDETRDY
14
15
16
Offset
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RW 0
Name
LFTIMEOUTERR
Access
RW 0
Reset
31
0x0AC
CMUERR
CMU - Clock Management Unit
EFM32JG1 Reference Manual
10.5.26 CMU_IEN - Interrupt Enable Register
Bit Position
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EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
31
CMUERR
0
RW
CMUERR Interrupt Enable
Enable/disable the CMUERR interrupt
30:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14
LFTIMEOUTERR
0
RW
LFTIMEOUTERR Interrupt Enable
Enable/disable the LFTIMEOUTERR interrupt
13
HFRCODIS
0
RW
HFRCODIS Interrupt Enable
Enable/disable the HFRCODIS interrupt
12
HFXOSHUNTOPTRDY
0
RW
HFXOSHUNTOPTRDY Interrupt Enable
Enable/disable the HFXOSHUNTOPTRDY interrupt
11
HFXOPEAKDETRDY 0
RW
HFXOPEAKDETRDY Interrupt Enable
Enable/disable the HFXOPEAKDETRDY interrupt
10
HFXOPEAKDETERR 0
RW
HFXOPEAKDETERR Interrupt Enable
Enable/disable the HFXOPEAKDETERR interrupt
9
HFXOAUTOSW
0
RW
HFXOAUTOSW Interrupt Enable
Enable/disable the HFXOAUTOSW interrupt
8
HFXODISERR
0
RW
HFXODISERR Interrupt Enable
Enable/disable the HFXODISERR interrupt
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
CALOF
0
RW
CALOF Interrupt Enable
RW
CALRDY Interrupt Enable
RW
AUXHFRCORDY Interrupt Enable
Enable/disable the CALOF interrupt
5
CALRDY
0
Enable/disable the CALRDY interrupt
4
AUXHFRCORDY
0
Enable/disable the AUXHFRCORDY interrupt
3
LFXORDY
0
RW
LFXORDY Interrupt Enable
RW
LFRCORDY Interrupt Enable
Enable/disable the LFXORDY interrupt
2
LFRCORDY
0
Enable/disable the LFRCORDY interrupt
1
HFXORDY
0
RW
HFXORDY Interrupt Enable
Enable/disable the HFXORDY interrupt
0
HFRCORDY
0
RW
HFRCORDY Interrupt Enable
Enable/disable the HFRCORDY interrupt
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CMU - Clock Management Unit
10.5.27 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0
Access
1
0
CRYPTO RW 0
LE
Name
Reset
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
GPCRC
0
RW 0
2
RW 0
GPIO
Bit
3
RW 0
PRS
4
5
RW 0
Name
LDMA
Access
RW 0
Reset
GPCRC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0B0
Bit Position
31
Offset
Description
RW
General Purpose CRC Clock Enable
RW
Linked Direct Memory Access Controller Clock Enable
RW
Peripheral Reflex System Clock Enable
RW
General purpose Input/Output Clock Enable
RW
Advanced Encryption Standard Accelerator Clock Enable
RW
Low Energy Peripheral Interface Clock Enable
Set to enable the clock for GPCRC.
4
LDMA
0
Set to enable the clock for LDMA.
3
PRS
0
Set to enable the clock for PRS.
2
GPIO
0
Set to enable the clock for GPIO.
1
CRYPTO
0
Set to enable the clock for CRYPTO.
0
LE
0
Set to enable the clock for LE. Interface used for bus access to Low Energy peripherals.
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CMU - Clock Management Unit
10.5.28 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0
Access
0
RW 0
TIMER0
1
RW 0
TIMER1
2
RW 0
USART0
3
RW 0
USART1
4
RW 0
ACMP0
5
RW 0
6
CRYOTIMER RW 0
ACMP1
7
RW 0
I2C0
8
RW 0
9
10
ADC0
Name
RW 0
Access
IDAC0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0C0
Bit Position
31
Offset
Bit
Name
Reset
Description
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9
IDAC0
0
RW
Current Digital to Analog Converter 0 Clock Enable
RW
Analog to Digital Converter 0 Clock Enable
RW
I2C 0 Clock Enable
RW
CryoTimer Clock Enable
Set to enable the clock for IDAC0.
8
ADC0
0
Set to enable the clock for ADC0.
7
I2C0
0
Set to enable the clock for I2C0.
6
CRYOTIMER
0
Set to enable the clock for CRYOTIMER.
5
ACMP1
0
RW
Analog Comparator 1 Clock Enable
RW
Analog Comparator 0 Clock Enable
RW
Universal Synchronous/Asynchronous Receiver/Transmitter 1
Clock Enable
RW
Universal Synchronous/Asynchronous Receiver/Transmitter 0
Clock Enable
RW
Timer 1 Clock Enable
RW
Timer 0 Clock Enable
Set to enable the clock for ACMP1.
4
ACMP0
0
Set to enable the clock for ACMP0.
3
USART1
0
Set to enable the clock for USART1.
2
USART0
0
Set to enable the clock for USART0.
1
TIMER1
0
Set to enable the clock for TIMER1.
0
TIMER0
0
Set to enable the clock for TIMER0.
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CMU - Clock Management Unit
10.5.29 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg)
LETIMER0 RW 0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0E0
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
LETIMER0
0
RW
Description
Low Energy Timer 0 Clock Enable
Set to enable the clock for LETIMER0.
10.5.30 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg)
2
1
2
1
LEUART0 RW 0
Reset
0
3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0E8
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
LEUART0
0
RW
Description
Low Energy UART 0 Clock Enable
Set to enable the clock for LEUART0.
10.5.31 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg)
RTCC RW 0
Reset
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x0F0
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
RTCC
0
RW
Description
Real-Time Counter and Calendar Clock Enable
Set to enable the clock for RTCC.
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CMU - Clock Management Unit
10.5.32 CMU_HFPRESC - High Frequency Clock Prescaler Register
Name
0
1
2
3
4
5
6
7
8
9
11
RW 0x00 10
Access
PRESC
HFCLKLEPRESC RW
Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
0x0
25
26
27
28
29
30
0x100
Bit Position
31
Offset
Bit
Name
Reset
Access
31:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24:24
HFCLKLEPRESC
0x0
RW
Description
HFCLKLE prescaler
Specifies the clock divider for HFCLKLE.
Value
Mode
Description
0
DIV2
HFCLKLE is HFBUSCLKLE divided by 2.
1
DIV4
HFCLKLE is HFBUSCLKLE divided by 4.
23:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12:8
PRESC
0x00
RW
HFCLK Prescaler
Specifies the clock divider for HFCLK (relative to HFSRCCLK).
7:0
Value
Description
PRESC
Clock division factor of
PRESC+1.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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CMU - Clock Management Unit
10.5.33 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register
To ensure compatibility with future devices, always write bits to 0. More information in
16:8
PRESC
0x000
RW
0
Reserved
0
31:17
1
Reset
1
4
5
6
7
8
9
10
Name
2
Access
11
Bit
3
Name
2
Access
3
Reset
PRESC RW 0x000 12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x108
Bit Position
31
Offset
Description
HFCORECLK Prescaler
Specifies the clock divider for HFCORECLK (relative to HFCLK).
7:0
Value
Description
PRESC
Clock division factor of
PRESC+1.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10.5.34 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register
Reset
Access
Name
Access
4
5
6
7
8
9
10
11
PRESC RW 0x000 12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x10C
Bit Position
31
Offset
Bit
Name
Reset
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16:8
PRESC
0x000
RW
Description
HFPERCLK Prescaler
Specifies the clock divider for the HFPERCLK (relative to HFCLK).
7:0
Value
Description
PRESC
Clock division factor of
PRESC+1.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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CMU - Clock Management Unit
10.5.35 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register
Access
Name
Access
Bit
Name
Reset
31:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12:8
PRESC
0x00
RW
0
1
2
3
4
5
6
7
8
9
11
PRESC RW 0x00 10
Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x114
Bit Position
31
Offset
Description
HFEXPCLK Prescaler
Specifies the clock divider for HFEXPCLK (relative to HFCLK).
7:0
Value
Description
PRESC
Clock division factor of
PRESC+1.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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CMU - Clock Management Unit
10.5.36 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg)
0
1
2
LETIMER0 RW 0x0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x120
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
LETIMER0
0x0
RW
Description
Low Energy Timer 0 Prescaler
Configure Low Energy Timer 0 prescaler
Value
Mode
Description
0
DIV1
LFACLKLETIMER0 = LFACLK
1
DIV2
LFACLKLETIMER0 = LFACLK/2
2
DIV4
LFACLKLETIMER0 = LFACLK/4
3
DIV8
LFACLKLETIMER0 = LFACLK/8
4
DIV16
LFACLKLETIMER0 = LFACLK/16
5
DIV32
LFACLKLETIMER0 = LFACLK/32
6
DIV64
LFACLKLETIMER0 = LFACLK/64
7
DIV128
LFACLKLETIMER0 = LFACLK/128
8
DIV256
LFACLKLETIMER0 = LFACLK/256
9
DIV512
LFACLKLETIMER0 = LFACLK/512
10
DIV1024
LFACLKLETIMER0 = LFACLK/1024
11
DIV2048
LFACLKLETIMER0 = LFACLK/2048
12
DIV4096
LFACLKLETIMER0 = LFACLK/4096
13
DIV8192
LFACLKLETIMER0 = LFACLK/8192
14
DIV16384
LFACLKLETIMER0 = LFACLK/16384
15
DIV32768
LFACLKLETIMER0 = LFACLK/32768
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CMU - Clock Management Unit
10.5.37 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg)
0
1
LEUART0 RW 0x0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x128
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1:0
LEUART0
0x0
RW
Description
Low Energy UART 0 Prescaler
Configure Low Energy UART 0 prescaler
Value
Mode
Description
0
DIV1
LFBCLKLEUART0 = LFBCLK
1
DIV2
LFBCLKLEUART0 = LFBCLK/2
2
DIV4
LFBCLKLEUART0 = LFBCLK/4
3
DIV8
LFBCLKLEUART0 = LFBCLK/8
10.5.38 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure
EM4UNLATCH in EMU_CMD is set for this to take effect
0
1
0x0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x130
Bit Position
31
Offset
Reset
RTCC
Access
Name
Bit
Name
Reset
Access
Description
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
RTCC
0x0
Real-Time Counter and Calendar Prescaler
Configure Real-Time Counter and Calendar prescaler
Value
Mode
Description
0
DIV1
LFECLKRTCC = LFECLK
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CMU - Clock Management Unit
10.5.39 CMU_SYNCBUSY - Synchronization Busy Register
0
0
R
LFACLKEN0
1
2
3
R
LFAPRESC0
0
4
R
LFBCLKEN0
0
5
6
0
R
LFBPRESC0
7
8
9
10
11
12
13
14
15
16
0
R
17
18
LFECLKEN0
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0
R
LFEPRESC0
19
20
21
22
23
24
0
R
HFRCOBSY
25
0
R
AUXHFRCOBSY
26
0
R
LFRCOBSY
27
0
LFRCOVREFBSY R
28
0
R
Name
HFXOBSY
29
R
30
Access
LFXOBSY
Reset
0
0x140
Bit Position
31
Offset
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EFM32JG1 Reference Manual
CMU - Clock Management Unit
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29
LFXOBSY
0
R
Description
LFXO Busy
Used to check the synchronization status of CMU_LFXOCTRL.
28
Value
Description
0
CMU_LFXOCTRL is ready for update
1
CMU_LFXOCTRL is busy synchronizing new value
HFXOBSY
0
R
HFXO Busy
Used to check the synchronization status of CMU_HFXOCTRL, CMU_HFXOSTARTUPCTRL, CMU_HFXOSTEADYSTATECTRL, CMU_HFXOTIMEOUTCTRL, CMU_HFXOCTRL1.
27
Value
Description
0
CMU_HFXOCTRL, CMU_HFXOSTARTUPCTRL, CMU_HFXOSTEADYSTATECTRL, CMU_HFXOTIMEOUTCTRL, CMU_HFXOCTRL1 are
ready for update
1
CMU_HFXOCTRL, CMU_HFXOSTARTUPCTRL, CMU_HFXOSTEADYSTATECTRL, CMU_HFXOTIMEOUTCTRL, CMU_HFXOCTRL1 are
busy synchronizing new value
LFRCOVREFBSY
0
R
LFRCO VREF Busy
Used to check the synchronization status of GMCCURTUNE.
26
Value
Description
0
CMU_LFRCOCTRL GMCCURTUNE bitfield is ready for update
1
CMU_LFRCOCTRL GMCCURTUNE bitfield is busy synchronizing new
value
LFRCOBSY
0
R
LFRCO Busy
Used to check the synchronization status of CMU_LFRCOCTRL.
25
Value
Description
0
CMU_LFRCOCTRL is ready for update
1
CMU_LFRCOCTRL is busy synchronizing new value
AUXHFRCOBSY
0
R
AUXHFRCO Busy
Used to check the synchronization status of CMU_AUXHFRCOCTRL.
24
Value
Description
0
CMU_AUXHFRCOCTRL is ready for update
1
CMU_AUXHFRCOCTRL is busy synchronizing new value
HFRCOBSY
0
R
HFRCO Busy
Used to check the synchronization status of CMU_HFRCOCTRL.
Value
Description
0
CMU_HFRCOCTRL is ready for update
1
CMU_HFRCOCTRL is busy synchronizing new value
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Bit
Name
Reset
Access
23:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18
LFEPRESC0
0
R
Description
Low Frequency E Prescaler 0 Busy
Used to check the synchronization status of CMU_LFEPRESC0.
Value
Description
0
CMU_LFEPRESC0 is ready for update
1
CMU_LFEPRESC0 is busy synchronizing new value
17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
LFECLKEN0
0
R
Low Frequency E Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFECLKEN0.
Value
Description
0
CMU_LFECLKEN0 is ready for update
1
CMU_LFECLKEN0 is busy synchronizing new value
15:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
LFBPRESC0
0
R
Low Frequency B Prescaler 0 Busy
Used to check the synchronization status of CMU_LFBPRESC0.
Value
Description
0
CMU_LFBPRESC0 is ready for update
1
CMU_LFBPRESC0 is busy synchronizing new value
5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
LFBCLKEN0
0
R
Low Frequency B Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFBCLKEN0.
Value
Description
0
CMU_LFBCLKEN0 is ready for update
1
CMU_LFBCLKEN0 is busy synchronizing new value
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
LFAPRESC0
0
R
Low Frequency A Prescaler 0 Busy
Used to check the synchronization status of CMU_LFAPRESC0.
Value
Description
0
CMU_LFAPRESC0 is ready for update
1
CMU_LFAPRESC0 is busy synchronizing new value
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
LFACLKEN0
0
R
Low Frequency A Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFACLKEN0.
Value
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CMU - Clock Management Unit
Bit
Name
Reset
Access
Description
0
CMU_LFACLKEN0 is ready for update
1
CMU_LFACLKEN0 is busy synchronizing new value
10.5.40 CMU_FREEZE - Freeze Register
REGFREEZE RW 0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x144
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
REGFREEZE
0
RW
Description
Register Update Freeze
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value
Mode
Description
0
UPDATE
Each write access to a Low Frequency clock control register is updated
into the Low Frequency domain as soon as possible.
1
FREEZE
The LE Clock Control registers are not updated with the new written
value.
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CMU - Clock Management Unit
10.5.41 CMU_PCNTCTRL - PCNT Control Register
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
PCNT0CLKSEL
0
RW
0
RW 0
2
PCNT0CLKEN
Name
1
Access
PCNT0CLKSEL RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x150
Bit Position
31
Offset
Description
PCNT0 Clock Select
This bit controls which clock that is used for the PCNT.
0
Value
Mode
Description
0
LFACLK
LFACLK is clocking PCNT0
1
PCNT0S0
External pin PCNT0_S0 is clocking PCNT0
PCNT0CLKEN
0
RW
PCNT0 Clock Enable
This bit enables/disables the clock to the PCNT.
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CMU - Clock Management Unit
10.5.42 CMU_ADCCTRL - ADC Control Register
Name
Access
Bit
Name
Reset
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8
ADC0CLKINV
0
RW
0
1
2
3
4
6
5
ADC0CLKSEL RW 0x0
RW
ADC0CLKINV
Access
7
8
9
0
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x15C
Bit Position
31
Offset
Description
Invert clock selected by ADC0CLKSEL
This bit enables inverting the selected clock to ADC0.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:4
ADC0CLKSEL
0x0
RW
ADC0 Clock Select
This bit controls which clock is used for ADC0 in case ADCCLKMODE in ADCn_CTRL is set to ASYNC. It should only be
changed when ADCCLKMODE in ADCn_CTRL is set to SYNC. HFXO should never be selected as clock source for ADC0
when disabling the HFXO (e.g. because of EM2 entry).
3:0
Value
Mode
Description
0
DISABLED
ADC0 is not clocked
1
AUXHFRCO
AUXHFRCO is clocking ADC0
2
HFXO
HFXO is clocking ADC0
3
HFSRCCLK
HFSRCCLK is clocking ADC0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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CMU - Clock Management Unit
10.5.43 CMU_ROUTEPEN - I/O Routing Pin Enable Register
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
CLKOUT1PEN
0
RW
0
2
CLKOUT0PEN RW 0
Name
1
Access
CLKOUT1PEN RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x170
Bit Position
31
Offset
Description
CLKOUT1 Pin Enable
When set, the CLKOUT1 pin is enabled.
0
CLKOUT0PEN
0
RW
CLKOUT0 Pin Enable
When set, the CLKOUT0 pin is enabled.
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CMU - Clock Management Unit
10.5.44 CMU_ROUTELOC0 - I/O Routing Location Register
Reset
Access
Name
Access
Bit
Name
Reset
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
CLKOUT1LOC
0x00
RW
0
1
2
3
CLKOUT0LOC RW 0x00
4
5
6
7
8
9
10
11
CLKOUT1LOC RW 0x00
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x174
Bit Position
31
Offset
Description
I/O Location
Decides the location of the CLKOUT1.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
CLKOUT0LOC
0x00
RW
I/O Location
Decides the location of the CMU CLKOUT0.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
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CMU - Clock Management Unit
10.5.45 CMU_LOCK - Configuration Lock Register
0
1
2
3
4
5
6
7
8
LOCKKEY RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x180
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0000
RWH
Description
Configuration Lock Key
Write any other value than the unlock code to lock CMU_CTRL, CMU_HFRCOCTRL, CMU_AUXHFRCOCTRL,
CMU_LFRCOCTRL, CMU_ULFRCOCTRL, CMU_HFXOCTRL, CMU_HFXOCTRL1, CMU_LFXOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_DBGCLKSEL, CMU_HFCLKSEL, CMU_LFCLKSEL, CMU_HFBUSCLKEN0, CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_HFPRESC, CMU_HFCOREPRESC, CMU_HFPERPRESC, CMU_HFEXPPRESC, CMU_LFACLKEN0, CMU_LFBCLKEN0, CMU_LFECLKEN0, CMU_LFAPRESC0, CMU_LFBPRESC0,
CMU_LFEPRESC0, CMU_ADCCTRL and CMU_PCNTCTRL from editing. Write the unlock code to unlock. When reading
the register, bit 0 is set when the lock is enabled.
Mode
Value
Description
UNLOCKED
0
CMU registers are unlocked
LOCKED
1
CMU registers are locked
LOCK
0
Lock CMU registers
UNLOCK
0x580E
Unlock CMU registers
Read Operation
Write Operation
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RTCC - Real Time Counter and Calendar
11. RTCC - Real Time Counter and Calendar
Quick Facts
What?
The Real Time Counter and Calendar (RTCC) is a
32-bit counter ensuring timekeeping in low energy
modes. The RTCC also includes a calendar mode
for easy time and date keeping. In addition, the
RTCC includes 128 bytes of general purpose retention data, allowing persistent data storage in all energy modes except EM4H.
0 1 2 34
Why?
Timekeeping over long time periods while using as
little power as possible is required in many low power applications.
How?
A low frequency oscillator is used as clock signal
and the RTCC has three different Capture/Compare
channels which can trigger wake-up, generate PRS
signalling, or capture system events. 32-bit resolution and selectable prescaling allows the system to
stay in low energy modes for long periods of time
and still maintain reliable timekeeping.
0 1 2 34
11.1 Introduction
The Real Time Counter and Calendar (RTCC) contains a 32-bit counter/calendar in combination with a 15-bit pre-counter to allow flexible prescaling of the main counter. The RTCC is available in all energy modes except EM4H.
Three individually configurable Capture/Compare channels are available in the RTCC. These can be used to trigger interrupts, generate
PRS signals, capture system events, and to wake the device up from a low energy mode. The RTCC also includes 128 bytes of general
purpose storage, and a Binary Coded Decimal (BCD) calendar mode, enabling easy time and date keeping.
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RTCC - Real Time Counter and Calendar
11.2 Features
•
•
•
•
•
•
•
32-bit Real Time Counter.
15-bit pre-counter, for flexible frequency scaling or for use as an independent counter.
EM4H operation and wakeup.
128 byte general purpose retention data.
Oscillator failure detection.
Can continue through system reset; only reset by power loss, pin, or software reset.
Calendar mode.
• BCD encoding.
• Three programmable alarms.
• Leap year correction.
• Three Capture/Compare registers.
• Capture of PRS events from other parts of the system.
• Compare match or input capture can trigger interrupts.
• Compare register 1, RTCC_CC1_CCV can be used as a top value for the main counter.
• Compare register 0, RTCC_CC0_CCV can be used as a top value for the pre-counter.
• Compare match events are available to other peripherals through the Peripheral Reflex System (PRS).
11.3 Functional Description
The RTCC is a 32-bit up-counter with three Capture/Compare channels. In addition, the RTCC includes a 15-bit pre-counter which can
be used as an independent counter, or to prescale the main counter. An overview of the RTCC module is shown in Figure 11.1 RTCC
Overview on page 281.
RTCC_CTRL_COMP1TOP
RTCC_CTRL_CNTTICK = CCV0MATCH
CC1 compare match
Clear
Counter
RTCC_CNT /
RTCC_TIME, RTCC_DATE
Pre-Counter
RTCC_PRECNT
RTCC_CC_CTRL_CMOA
[31:0]
PRS output
CC2
CC1
CC0
OSCFAIL
OF
Interrupt
generation
RTCC_PRECNT = RTCC_CC0_CCV[14:0]
Clear
[16:0]
CNT
=
LFCLKRTCC
[14:0]
PRECNT
Mask
RTCC_CC_CTRL_COMPBASE
Capture/Compare
RTCC_CCx_CCV
Capture
Capture
logic n
PRS
Inputs
Oscillator failure
CNT Overflow
RTCC_CC_CTRL_COMPMASK
CC2
CC1
CC0
Capture / Compare Channel n
n = {0, 1, 2}
RTCC_CC2_CCV output to FRC
Figure 11.1 RTCC Overview
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RTCC - Real Time Counter and Calendar
11.3.1 Counter
The RTCC consists of two counters; the 32-bit main counter, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode), and a 15bit pre-counter, RTCC_PRECNT. The pre-counter can be used as an independent counter, or to generate a specific frequency for the
main counter. In both configurations, the pre-counter can be used to generate compare match events or be captured in the Capture/
Compare channels as a result of an external PRS event. Refer to 11.3.2 Capture/Compare Channels for details on how to configure the
Capture/Compare channels for use with the pre-counter.
RTCC_PRECNT
LFCLKRTCC
.........................
=
RTCC_CTRL_CNTPRESC
PRESC
RTCC_CC0_CCV[14:0]
CCV0MATCH
RTCC_CNT /
RTCC_TIME, RTCC_DATE
RTCC_CTRL_CNTTICK
Figure 11.2 RTCC counters
The RTCC is enabled by setting the ENABLE bit in RTCC_CTRL. When the RTCC is enabled, the pre-counter (RTCC_PRECNT) increments upon each positive clock edge of LFCLKRTCC. If CNTTICK in RTCC_CTRL is set to PRESC, the pre-counter will continue to
count up, wrapping around to zero when it overflows. If CNTTICK in RTCC_CTRL is set to CCV0MATCH, the pre-counter will wrap
around when it hits the value configured in RTCC_CC0_CCV.
The main counter of the RTCC, RTCC_CNT, has two modes; normal mode and calendar mode. In normal mode, the main counter is
available in RTCC_CNT and increments upon each tick given from the pre-counter. Refer to 11.3.1.1 Normal Mode for a description on
how to configure the frequency of these ticks. In calendar mode, the counter value is available in RTCC_TIME and RTCC_DATE, keeping track of seconds, minutes, hours, day of month, day of week, months, and years, all encoded in BCD format. Refer to
11.3.1.2 Calendar Mode for details on this mode. The mode of the main counter is configured in CNTMODE in RTCC_CTRL. The differences between the two modes are summarized below.
• Normal mode
• Incremental counter, RTCC_CNT.
• RTCC_CCx_CCV used for Capture/Compare value.
• Calendar mode
• BCD counters, RTCC_DATE, RTCC_TIME.
• RTCC_CCx_TIME and RTCC_CCx_DATE used for Capture/Compare value.
Note: The mode of the RTCC must be configured for CALENDAR mode in RTCC_CTRL_CNTMODE before writing to the mode dependent registers, RTCC_TIME, RTCC_DATE, RTCC_CCx_TIME, and RTCC_CCx_DATE. Writes to these registers when in NORMAL
mode will be ignored.
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RTCC - Real Time Counter and Calendar
11.3.1.1 Normal Mode
The main counter can receive a tick based on different tappings from the pre-counter, allowing the ticks to be power of 2 divisions of the
LFCLKRTCC. For more accurate configuration of the tick frequency, RTCC_CC0_CCV[14:0] can be used as a top value for
RTCC_PRECNT. When reaching the top value, the main counter receives a tick, and the pre-counter wraps around. Table 11.1 RTCC
Resolution vs Overflow, FLFCLK = 32768 Hz on page 283 summarizes the resolutions available when using a 32768 Hz oscillator as
source for LFCLKRTCC.
Table 11.1. RTCC Resolution vs Overflow, FLFCLK = 32768 Hz
RTCC_CTRL_CNTTICK
CCV0MATCH
PRESC
Main counter period, TCNT
RTCC_CTRL_CNTPRESC
Overflow
Don't care
(RTCC_CC0_CCV + 1)/FLFCLK s
232*TCNT seconds
DIV1
30.5 µs
36.4 hours
DIV2
61 µs
72.8 hours
DIV4
122 µs
145.6 hours
DIV8
244 µs
12 days
DIV16
488 µs
24 days
DIV32
977 µs
48 days
DIV64
1.95 ms
97 days
DIV128
3.91 ms
194 days
DIV256
7.81 ms
388 days
DIV512
15.6 ms
776 days
DIV1024
31.25 ms
4.2 years
DIV2048
62.5 ms
8.5 years
DIV4096
0.125 s
17 years
DIV8192
0.25 s
34 years
DIV16384
0.5 s
68 years
DIV32768
1s
136 years
By default, the counter will keep counting until it reaches the top value, 0xFFFFFFFF, before it wraps around and continues counting
from zero. By setting CCV1TOP in RTCC_CTRL, a Capture/Compare channel 1 compare match will result in the main counter wrapping to 0. The timer will then wrap around on a channel 1 compare match (RTCC_CNT = RTCC_CC1_CCV). If using the CCV1TOP
setting, make sure to set this bit prior to or at the same time the RTCC is enabled. Setting CCV1TOP after enabling the RTCC
(RTCC_CTRL_MODE != DISABLED) may cause unintended operation (e.g. if RTCC_CNT > RTCC_CC1_CCV, RTCC_CNT will wrap
when reaching 0xFFFFFFFF rather than RTCC_CC1_CCV).
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RTCC - Real Time Counter and Calendar
11.3.1.2 Calendar Mode
The RTCC includes a calendar mode which implements time and date decoding in hardware. Calendar mode is enabled by configuring
CNTMODE in RTCC_CTRL to CALENDAR. When in calendar mode, the counter value is available in RTCC_TIME and RTCC_DATE.
RTCC_TIME shows seconds, minutes, and hours while RTCC_DATE shows day of month, month, year, and day of week. RTCC_TIME
and RTCC_DATE are encoded in BCD format. In calendar mode, the pre-counter should be configured to give ticks with a period of one
second, i.e. RTCC_CTRL_CNTTICK should be set to PRESC, and the CNTPRESC bitfield of the RTCC_CTRL register should be set
to DIV32768 if a 32768 Hz clock source is used.
In calendar mode, the time and date registers of the capture compare channels, RTCC_CCx_TIME and RTCC_CCx_DATE, are used to
set compare values. Compare values can be set on seconds, minutes, hours, days, and months. Whether day of week, or day of month
is used for a Capture/Compare channel is configured in RTCC_CCx_CTRL_DAYCC in the respective Capture/Compare channel.
The RTCC will automatically compensate for 28-, 29- (leap year), 30-, and 31-day months. The day of week counter,
RTCC_DATE_DAYOW, is a three bit counter incrementing when RTCC_TIME_HOURT overflows, wrapping around every seventh day.
Automatic leap year correction, extending the month of February from 28 to 29 days every fourth year is by default enabled, but can be
disabled by setting the LYEARCORRDIS bit in RTCC_CTRL. The pseudocode for leap year correction is as follows:
if RTCC_DATE_YEART modulo 2 = 0:
if RTCC_DATE_YEARU modulo 4 = 0:
leap_year = true
else:
leap_year = false
else:
if (RTCC_DATE_YEARU + 2) modulo 4 = 0:
leap_year = true
else:
leap_year = false
The seconds, minute, hour segments are represented in 24-hour BCD format. The month segments are enumerated as shown in Table
11.2 RTCC calendar enumeration on page 284.
Table 11.2. RTCC calendar enumeration
Month
RTCC_DATE_MONTHT
RTCC_DATE_MONTHU
January
0b0
0b0001
February
0b0
0b0010
March
0b0
0b0011
April
0b0
0b0100
May
0b0
0b0101
June
0b0
0b0110
July
0b0
0b0111
August
0b0
0b1000
September
0b0
0b1001
October
0b1
0b0000
November
0b1
0b0001
December
0b1
0b0010
11.3.1.3 RTCC Initialization
The counters of the RTCC, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode) and RTCC_PRECNT, can at any time be
written by software, as long as the registers are not locked using RTCC_LOCKKEY. All RTCC registers use the immediate synchronization scheme, described in 4.3.1 Writing.
Note: Writing to the RTCC_PRECNT register may alter the frequency of the ticks for the RTCC_CNT register.
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RTCC - Real Time Counter and Calendar
11.3.2 Capture/Compare Channels
Three capture/compare channels are available in the RTCC. Each channel can be configured as input capture or output compare, by
setting the corresponding MODE in the RTCC_CCx_CTRL register.
RTCC_CNT
RTCC_CC0_CCV
RTCC_CC1_CCV
RTCC_CC2_CCV
0
CC2 PRS output,
CMOA=PULSE
1 LFCLKRTCC cycle
CC1 PRS output,
CMOA=TOGGLE
CC0 PRS output,
CMOA=SET
Figure 11.3 RTCC Compare match and PRS output illustration
In input capture mode the RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode) register is captured into the
RTCC_CCx_CCV (RTCC_CCx_TIME and RTCC_CCx_DATE in calendar mode) register when an edge is detected on the selected
PRS input channel. The active capture edge is configured in the ICEDGE control bits.
In output compare mode the compare values are set by writing to the RTCC compare channel registers RTCC_CCx_CCV
(RTCC_CCx_TIME and RTCC_CCx_DATE in calendar mode). These values will be compared to the main counter, RTCC_CNT
(RTCC_TIME and RTCC_DATE in calendar mode), or a mixture of the main counter and the pre-counter, as illustrated in Figure
11.4 RTCC Compare base illustration on page 286. Compare base for the capture compare channels is set by configuring COMPBASE
in RTCC_CCx_CTRL.
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RTCC - Real Time Counter and Calendar
RTCC_CCx_CTRL_COMPBASE = CNT
CNT
PRECNT
MASK
=
Compare match
MASK
CCx_CCV
RTCC_CCx_CTRL_COMPBASE = PRECNT
16
CNT
0 14
PRECNT
0
MASK
Compare match
=
MASK
CCx_CCV
Figure 11.4 RTCC Compare base illustration
Table 11.3 RTCC Capture/Compare subjects on page 286 summarizes which registers being subject to comparison for different configurations of RTCC_CTRL_CNTMODE and RTCC_CCx_CTRL_COMPBASE.
Table 11.3. RTCC Capture/Compare subjects
RTCC_CTRL_CNTMODE
NORMAL
CALENDAR
RTCC_CCx_CTRL_COMPBASE =
CNT
RTCC_CNT vs. RTCC_CCx_CCV
RTCC_TIME vs. RTCC_CCx_TIME and
RTCC_DATE vs. RTCC_CCx_DATE
RTCC_CCx_CTRL_COMPBASE =
PRECNT
{RTCC_CNT[16:0],RTCC_PRECNT[14:0]} vs.
RTCC_PRECNT vs. RTCC_CCx_CCV[14:0]
RTCC_CCx_CCV
Figure 11.5 RTCC Compare in calendar mode, COMPBASE = CNT on page 287 illustrates how the compare events are evaluated
when in calendar mode with RTCC_CCx_CTRL_COMPBASE = CNT. The SECU, SECT, MINU, MINT, HOURU, HOURT, MONTHU,
and MONTHT bitfields in RTCC_CCx_TIME and RTCC_CCx_DATE are compared to the corresponding bitfields in RTCC_DATE and
RTCC_TIME. The DAYU and DAYT bitfields in RTCC_CCx_DATE will be compared to {RTCC_DATE_DAYOMT, RTCC_DATE_DAYOMU} if DAYCC in RTCC_CCx_CTRL is set to MONTH. If DAYCC in RTCC_CCx_CTRL is set to WEEK, the DAYU and DAYT bitfields in
RTCC_CCx_DATE will be compared to {0b000, RTCC_DATE_DAYOW}.
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RTCC_DATE
RTCC_TIME
[DAYOMT,
DAYOMU]
[0b000,
DAYOW]
RTCC_CCx_CTRL_DAYCC
[MONTHT,MONTHU]
MASK
=
Compare match
MASK
[MONTHT,MONTHU]
[DAYT,DAYU]
RTCC_CCx_DATE
RTCC_CCx_TIME
Figure 11.5 RTCC Compare in calendar mode, COMPBASE = CNT
To generate periodically recurring events, is possible to mask out parts of the compare match values. By configuring COMPMASK in
RTCC_CCx_CTRL, parts of the compare values will be masked out, limiting which part of the compare register being subject to comparison with the counter. Figure 11.6 RTCC Compare mask illustration, COMPMASK=11 on page 287 illustrates the effect of COMPMASK when in normal mode and calendar mode.
CCV
31
21 20
0
CC_CTRL_COMPMASK
MONTHT
31
MONTHU
30
DAYT
27 26
DAYU
25 24
HOURT
21 20
HOURU
19 18
MASKED
MINT
15 14
MINU
12 11
SECT
87
SECU
5 4
1
0
Subject to comparison
Figure 11.6 RTCC Compare mask illustration, COMPMASK=11
Upon a compare match, the respective Capture/Compare interrupt flag CCx is set. Additionally, the event selected by the CMOA setting
is generated on the corresponding PRS output. This is illustrated in Figure 11.3 RTCC Compare match and PRS output illustration on
page 285.
11.3.3 Interrupts and PRS Output
The RTCC has one interrupt for each of its 3 Capture/Compare channels, CC0, CC1, and CC2. Each Capture/Compare channel has a
PRS output with configurable actions upon compare match.
The interrupt flag CNTTICK is set each time the main counter receives a tick (each second in calendar mode). In calendar mode, there
are also interrupt flags being set each minute, hour, day, week, and month.
Upon oscillator failure detection, the OSCFAIL flag will be set.
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11.3.3.1 Main Counter Tick PRS Output
To output the ticks for the main counter on PRS, it is possible to use a Capture/Compare channel and mask all the bits, i.e.
RTCC_CCx_CTRL_COMPBASE=CNT and RTCC_CCx_CTRL_COMPMASK=31. PRS output of main counter ticks does not work if
the main counter is not prescaled.
Note:
To be able to mask all bits in the main counter, RTCC_CTRL_CNTMODE has to be set to CALENDAR. In NORMAL mode, the least
significant bit can not be masked out.
11.3.4 Energy Mode Availability
The RTCC is available in all Energy Modes except EM4H. To enable RTCC operation in EM4H, the EMU_EM4CTRL register in the
EMU has to be configured. Any enabled RTCC interrupt will wake the system up from EM4H; if EM4WU if RTCC_EM4WUEN is set.
Refer to 9. EMU - Energy Management Unit for details on how to configure the EMU.
11.3.5 Register Lock
To prevent accidental writes to the RTCC registers, the RTCC_LOCKKEY register can be written to any other value than the unlock
value. To unlock the register, write the unlock value to RTCC_LOCKKEY. Registers affected by this lock are:
• RTCC_CTRL
• RTCC_PRECNT
• RTCC_CNT
• RTCC_TIME
• RTCC_DATE
• RTCC_IEN
• RTCC_POWERDOWN
• RTCC_CCx_CTRL
• RTCC_CCx_CCV
• RTCC_CCx_TIME
• RTCC_CCx_DATE
11.3.6 Oscillator Failure Detection
To be able to detect OSC failure, the RTCC includes a security mechanism ensuring that at least three OSC cycles are detected within
one period of the ULFRCO. If no OSC cycles are detected, the OSCFAIL interrupt flag is set. OSC failure detection is enabled by setting the OSCFDETEN bit in RTCC_CTRL.
11.3.7 Retention Registers
The RTCC includes 32 x 32 bit registers which can be retained in all energy modes except EM4H. The registers are accessible through
the RETx_REG registers. Retention is by default enabled in EM0 Active through EM4 Hibernate/Shutoff. The registers can be shut off
to save power by setting the RAM bit in RTCC_POWERDOWN.
Note:
The retention registers are mapped to a RAM instance and have undefined state out of reset.
11.3.8 Frame Controller Interface
For easy timestamping of frames, RTCC_CC2_CCV is directly available for the Frame Controller, FRC.
11.3.9 Debug Session
By default, the RTCC is halted when code execution is halted from the debugger. By setting the DEBUGRUN bit in the RTCC_CTRL
register, the RTCC will continue to run even when the debugger has halted the system.
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11.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
RTCC_CTRL
RW
Control Register
0x004
RTCC_PRECNT
RWH
Pre-Counter Value Register
0x008
RTCC_CNT
RWH
Counter Value Register
0x00C
RTCC_COMBCNT
R
Combined Pre-Counter and Counter Value Register
0x010
RTCC_TIME
RWH
Time of day register
0x014
RTCC_DATE
RWH
Date register
0x018
RTCC_IF
R
RTCC Interrupt Flags
0x01C
RTCC_IFS
W1
Interrupt Flag Set Register
0x020
RTCC_IFC
(R)W1
Interrupt Flag Clear Register
0x024
RTCC_IEN
RW
Interrupt Enable Register
0x028
RTCC_STATUS
R
Status register
0x02C
RTCC_CMD
W1
Command Register
0x030
RTCC_SYNCBUSY
R
Synchronization Busy Register
0x034
RTCC_POWERDOWN
RW
Retention RAM power-down register
0x038
RTCC_LOCK
RWH
Configuration Lock Register
0x03C
RTCC_EM4WUEN
RW
Wake Up Enable
0x040
RTCC_CC0_CTRL
RW
CC Channel Control Register
0x044
RTCC_CC0_CCV
RWH
Capture/Compare Value Register
0x048
RTCC_CC0_TIME
RWH
Capture/Compare Time Register
0x04C
RTCC_CC0_DATE
RWH
Capture/Compare Date Register
0x050
RTCC_CC1_CTRL
RW
CC Channel Control Register
0x054
RTCC_CC1_CCV
RWH
Capture/Compare Value Register
0x058
RTCC_CC1_TIME
RWH
Capture/Compare Time Register
0x05C
RTCC_CC1_DATE
RWH
Capture/Compare Date Register
0x060
RTCC_CC2_CTRL
RW
CC Channel Control Register
0x064
RTCC_CC2_CCV
RWH
Capture/Compare Value Register
0x068
RTCC_CC2_TIME
RWH
Capture/Compare Time Register
0x06C
RTCC_CC2_DATE
RWH
Capture/Compare Date Register
0x104
RTCC_RET0_REG
RW
Retention register
0x108
RTCC_RET1_REG
RW
Retention register
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11.5 Register Description
11.5.1 RTCC_CTRL - Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
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0
0
RW
ENABLE
1
2
3
RW
DEBUGRUN
0
4
RW
PRECCV0TOP
0
5
0
RW
CCV1TOP
6
7
8
9
10
RW 0x0
CNTPRESC
11
12
0
RW
CNTTICK
13
14
15
0
RW
OSCFDETEN
16
0
RW
18
19
20
21
17
CNTMODE
Name
0
Access
LYEARCORRDIS RW
Reset
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
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Bit
Name
Reset
Access
31:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17
LYEARCORRDIS
0
RW
Description
Leap year correction disabled.
When cleared, February has 29 days in leap years. When set, February always has 28 days.
16
CNTMODE
0
RW
Main counter mode
Configure count mode for the main counter.
15
Value
Mode
Description
0
NORMAL
The main counter is incremented with 1 for each tick.
1
CALENDAR
The main counter is in calendar mode.
OSCFDETEN
0
RW
Oscillator failure detection enable
When set, the OSCFAIL interrupt flag will be set if no ticks are detected on LFCLKRTCC within one ULFRCO cycle.
14:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12
CNTTICK
0
RW
Counter prescaler mode.
Select whether the main counter should tick on RTCC_CC0_CCV[14:0] compare match with the pre-counter or tick on a
pre-counter tap selected in CNTPRESC bitfield in the RTCC_CTRL register.
11:8
Value
Mode
Description
0
PRESC
CNT register ticks according to configuration in CNTPRESC.
1
CCV0MATCH
CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0]
CNTPRESC
0x0
RW
Counter prescaler value.
Configure counting frequency of the CNT register.
Value
Mode
Description
0
DIV1
CLKCNT = LFECLKRTCC/1
1
DIV2
CLKCNT = LFECLKRTCC/2
2
DIV4
CLKCNT = LFECLKRTCC/4
3
DIV8
CLKCNT = LFECLKRTCC/8
4
DIV16
CLKCNT = LFECLKRTCC/16
5
DIV32
CLKCNT = LFECLKRTCC/32
6
DIV64
CLKCNT = LFECLKRTCC/64
7
DIV128
CLKCNT = LFECLKRTCC/128
8
DIV256
CLKCNT = LFECLKRTCC/256
9
DIV512
CLKCNT = LFECLKRTCC/512
10
DIV1024
CLKCNT = LFECLKRTCC/1024
11
DIV2048
CLKCNT = LFECLKRTCC/2048
12
DIV4096
CLKCNT = LFECLKRTCC/4096
13
DIV8192
CLKCNT = LFECLKRTCC/8192
14
DIV16384
CLKCNT = LFECLKRTCC/16384
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Bit
Name
Reset
Access
Description
15
DIV32768
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
CCV1TOP
0
CLKCNT = LFECLKRTCC/32768
RW
CCV1 top value enable
When set, the counter wraps around on a CC1 event.
4
PRECCV0TOP
0
RW
Pre-counter CCV0 top value enable.
When set, the pre-counter wraps around when PRECNT equals RTCC_CC0_CCV[14:0].
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
DEBUGRUN
0
RW
Debug Mode Run Enable
Set this bit to keep the RTCC running during a debug halt.
Value
Description
0
RTCC is frozen in debug mode
1
RTCC is running in debug mode
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
ENABLE
0
RW
RTCC Enable
Enable the RTCC.
11.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Name
Access
Bit
Name
Reset
31:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14:0
PRECNT
0x0000
RWH
0
1
2
3
4
5
6
8
9
10
11
12
PRECNT RWH 0x0000 7
Reset
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Description
Pre-Counter Value
Gives access to the Pre-counter value of the RTCC.
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11.5.3 RTCC_CNT - Counter Value Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
2
1
0
1
0
3
2
4
5
6
7
8
9
10
11
12
13
14
15
16
CNT RWH 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
CNT
0x00000000
RWH
Counter Value
Gives access to the main counter value of the RTCC. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = CALENDAR.
11.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register
Name
3
4
5
6
7
0x0000
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CNTLSB
R
Access
PRECNT R
Reset
0x00000 23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Bit
Name
Reset
Access
Description
31:15
CNTLSB
0x00000
R
Counter Value
Gives access to the 17 LSBs of the main counter, CNT. Register will be read as zero when RTCC_CTRL_CNTMODE =
CALENDAR.
14:0
PRECNT
0x0000
R
Pre-Counter Value
Gives access to the pre-counter, PRECNT. Register will be read as zero when RTCC_CTRL_CNTMODE = CALENDAR.
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11.5.5 RTCC_TIME - Time of day register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Bit
Name
Reset
31:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:20
HOURT
0x0
RWH
0
1
3
2
RWH 0x0
SECU
SECT
4
RWH 0x0 5
6
7
8
9
11
12
14
15
16
17
18
10
RWH 0x0
MINU
Name
RWH 0x0 13
Access
MINT
Reset
HOURU RWH 0x0
19
20
21
HOURT RWH 0x0
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Description
Hours, tens.
Shows the tens part of the hour counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
19:16
HOURU
0x0
RWH
Hours, units.
Shows the unit part of the hour counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14:12
MINT
0x0
RWH
Minutes, tens.
Shows the tens part of the minute counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
11:8
MINU
0x0
RWH
Minutes, units.
Shows the unit part of the minute counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:4
SECT
0x0
RWH
Seconds, tens.
Shows the tens part of the second counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
3:0
SECU
0x0
RWH
Seconds, units.
Shows the unit part of the second counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
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11.5.6 RTCC_DATE - Date register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Bit
Name
Reset
31:27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
DAYOW
0x0
RWH
0
1
2
DAYOMU RWH 0x0
3
4
5
RWH 0x0
DAYOMT
6
7
8
9
10
MONTHU RWH 0x0
11
12
0
MONTHT RWH
13
14
15
16
17
18
RWH 0x0
19
20
21
22
RWH 0x0
Access
YEARU
Name
YEART
23
24
26
27
DAYOW
Access
RWH 0x0 25
Reset
28
29
30
0x014
Bit Position
31
Offset
Description
Day of week.
Shows the day of week counter. Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE =
NORMAL.
23:20
YEART
0x0
RWH
Year, tens.
Shows the tens part of the year counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
19:16
YEARU
0x0
RWH
Year, units.
Shows the unit part of the year counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
15:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12
MONTHT
0
RWH
Month, tens.
Shows the tens part of the month counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
11:8
MONTHU
0x0
RWH
Month, units.
Shows the unit part of the month counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:4
DAYOMT
0x0
RWH
Day of month, tens.
Shows the tens part of the day of month counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
3:0
DAYOMU
0x0
RWH
Day of month, units.
Shows the unit part of the day of month counter. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
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11.5.7 RTCC_IF - RTCC Interrupt Flags
Access
0
R
OF
0
1
R
CC0
0
2
3
R
CC1
0
R
CC2
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
MONTHTICK
0
R
0
4
R
OSCFAIL
0
5
0
R
CNTTICK
6
0
R
MINTICK
7
0
R
HOURTICK
8
0
R
DAYTICK
9
0
R
10
DAYOWOF
Name
0
Access
MONTHTICK R
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Description
Month tick
Set each time the month counter increments.
9
DAYOWOF
0
R
Day of week overflow
Set each time the day of week counter overflows.
8
DAYTICK
0
R
Day tick
Set each time the day counter increments.
7
HOURTICK
0
R
Hour tick
Set each time the hour counter increments.
6
MINTICK
0
R
Minute tick
Set each time the minute counter increments.
5
CNTTICK
0
R
Main counter tick
Set each time the main counter is updated.
4
OSCFAIL
0
R
Oscillator failure Interrupt Flag
Set when an oscillator failure has been detected.
3
CC2
0
R
Channel 2 Interrupt Flag
Set when a channel 2 event has occurred.
2
CC1
0
R
Channel 1 Interrupt Flag
Set when a channel 1 event has occurred.
1
CC0
0
R
Channel 0 Interrupt Flag
Set when a channel 0 event has occurred.
0
OF
0
R
Overflow Interrupt Flag
Set when a RTCC overflow has occurred.
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11.5.8 RTCC_IFS - Interrupt Flag Set Register
Access
0
W1 0
OF
1
W1 0
CC0
2
W1 0
CC1
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
MONTHTICK
0
W1
3
W1 0
CC2
4
W1 0
OSCFAIL
5
W1 0
CNTTICK
W1 0
MINTICK
6
W1 0
HOURTICK
7
W1 0
DAYTICK
8
9
W1 0
Name
DAYOWOF
Access
10
Reset
MONTHTICK W1 0
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Description
Set MONTHTICK Interrupt Flag
Write 1 to set the MONTHTICK interrupt flag
9
DAYOWOF
0
W1
Set DAYOWOF Interrupt Flag
Write 1 to set the DAYOWOF interrupt flag
8
DAYTICK
0
W1
Set DAYTICK Interrupt Flag
Write 1 to set the DAYTICK interrupt flag
7
HOURTICK
0
W1
Set HOURTICK Interrupt Flag
Write 1 to set the HOURTICK interrupt flag
6
MINTICK
0
W1
Set MINTICK Interrupt Flag
Write 1 to set the MINTICK interrupt flag
5
CNTTICK
0
W1
Set CNTTICK Interrupt Flag
Write 1 to set the CNTTICK interrupt flag
4
OSCFAIL
0
W1
Set OSCFAIL Interrupt Flag
Write 1 to set the OSCFAIL interrupt flag
3
CC2
0
W1
Set CC2 Interrupt Flag
W1
Set CC1 Interrupt Flag
W1
Set CC0 Interrupt Flag
W1
Set OF Interrupt Flag
Write 1 to set the CC2 interrupt flag
2
CC1
0
Write 1 to set the CC1 interrupt flag
1
CC0
0
Write 1 to set the CC0 interrupt flag
0
OF
0
Write 1 to set the OF interrupt flag
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11.5.9 RTCC_IFC - Interrupt Flag Clear Register
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0
(R)W1 0
OF
1
(R)W1 0
CC0
2
(R)W1 0
CC1
3
(R)W1 0
CC2
4
(R)W1 0
OSCFAIL
5
(R)W1 0
CNTTICK
(R)W1 0
MINTICK
6
(R)W1 0
HOURTICK
7
(R)W1 0
DAYTICK
8
9
(R)W1 0
11
12
13
14
15
16
17
18
19
20
21
DAYOWOF
Name
10
Access
MONTHTICK (R)W1 0
Reset
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
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Bit
Name
Reset
Access
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
MONTHTICK
0
(R)W1
Description
Clear MONTHTICK Interrupt Flag
Write 1 to clear the MONTHTICK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
9
DAYOWOF
0
(R)W1
Clear DAYOWOF Interrupt Flag
Write 1 to clear the DAYOWOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
8
DAYTICK
0
(R)W1
Clear DAYTICK Interrupt Flag
Write 1 to clear the DAYTICK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
7
HOURTICK
0
(R)W1
Clear HOURTICK Interrupt Flag
Write 1 to clear the HOURTICK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
6
MINTICK
0
(R)W1
Clear MINTICK Interrupt Flag
Write 1 to clear the MINTICK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
5
CNTTICK
0
(R)W1
Clear CNTTICK Interrupt Flag
Write 1 to clear the CNTTICK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
4
OSCFAIL
0
(R)W1
Clear OSCFAIL Interrupt Flag
Write 1 to clear the OSCFAIL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
3
CC2
0
(R)W1
Clear CC2 Interrupt Flag
Write 1 to clear the CC2 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
2
CC1
0
(R)W1
Clear CC1 Interrupt Flag
Write 1 to clear the CC1 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
1
CC0
0
(R)W1
Clear CC0 Interrupt Flag
Write 1 to clear the CC0 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
0
OF
0
(R)W1
Clear OF Interrupt Flag
Write 1 to clear the OF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
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RTCC - Real Time Counter and Calendar
11.5.10 RTCC_IEN - Interrupt Enable Register
Access
0
RW 0
OF
1
RW 0
CC0
2
RW 0
CC1
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
MONTHTICK
0
RW
3
RW 0
CC2
4
RW 0
OSCFAIL
5
RW 0
CNTTICK
RW 0
MINTICK
6
RW 0
HOURTICK
7
RW 0
DAYTICK
8
9
RW 0
Name
DAYOWOF
Access
10
Reset
MONTHTICK RW 0
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Description
MONTHTICK Interrupt Enable
Enable/disable the MONTHTICK interrupt
9
DAYOWOF
0
RW
DAYOWOF Interrupt Enable
Enable/disable the DAYOWOF interrupt
8
DAYTICK
0
RW
DAYTICK Interrupt Enable
RW
HOURTICK Interrupt Enable
Enable/disable the DAYTICK interrupt
7
HOURTICK
0
Enable/disable the HOURTICK interrupt
6
MINTICK
0
RW
MINTICK Interrupt Enable
RW
CNTTICK Interrupt Enable
RW
OSCFAIL Interrupt Enable
RW
CC2 Interrupt Enable
RW
CC1 Interrupt Enable
RW
CC0 Interrupt Enable
RW
OF Interrupt Enable
Enable/disable the MINTICK interrupt
5
CNTTICK
0
Enable/disable the CNTTICK interrupt
4
OSCFAIL
0
Enable/disable the OSCFAIL interrupt
3
CC2
0
Enable/disable the CC2 interrupt
2
CC1
0
Enable/disable the CC1 interrupt
1
CC0
0
Enable/disable the CC0 interrupt
0
OF
0
Enable/disable the OF interrupt
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RTCC - Real Time Counter and Calendar
11.5.11 RTCC_STATUS - Status register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11.5.12 RTCC_CMD - Command Register
3
2
1
0
3
2
1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
CLRSTATUS W1 0
Reset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
CLRSTATUS
0
W1
Description
Clear RTCC_STATUS register.
Clear BUMODETS in RTCC_STATUS.
11.5.13 RTCC_SYNCBUSY - Synchronization Busy Register
4
5
6
7
8
9
10
11
0
Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
CMD R
Access
Name
Bit
Name
Reset
Access
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
CMD
0
R
Description
CMD Register Busy
Set when the value written to CMD is being synchronized.
4:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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RTCC - Real Time Counter and Calendar
11.5.14 RTCC_POWERDOWN - Retention RAM power-down register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
3
2
1
0
3
2
1
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
RAM RW 0
Reset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
RAM
0
RW
Description
Retention RAM power-down
Shut off power to the Retention RAM. Once it is powered down, it cannot be powered up again
11.5.15 RTCC_LOCK - Configuration Lock Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
4
5
6
7
8
LOCKKEY RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x038
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
LOCKKEY
0x0000
RWH
Description
Configuration Lock Key
Write any other value than the unlock code to lock RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, RTCC_TIME,
RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN, and RTCC_CCx_XXX registers from editing. Write the unlock code to
unlock. When reading the register, bit 0 is set when the lock is enabled.
Mode
Value
Description
UNLOCKED
0
All registers are unlocked
LOCKED
1
Registers are locked
LOCK
0
Lock registers
UNLOCK
0xAEE8
Unlock all RTCC registers
Read Operation
Write Operation
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RTCC - Real Time Counter and Calendar
11.5.16 RTCC_EM4WUEN - Wake Up Enable
0
1
2
EM4WU RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
EM4WU
0
RW
Description
EM4 Wake-up enable
Write 1 to enable wake-up request, write 0 to disable wake-up request.
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RTCC - Real Time Counter and Calendar
11.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
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0
1
RW
MODE
0x0
2
3
RW
CMOA
0x0
4
5
0x0
RW
ICEDGE
6
7
8
0x0
RW
PRSSEL
9
10
12
11
0
RW
COMPBASE
13
15
COMPMASK RW 0x00 14
Name
16
17
0
RW
18
19
20
21
Access
DAYCC
Reset
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
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RTCC - Real Time Counter and Calendar
Bit
Name
Reset
Access
31:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17
DAYCC
0
RW
Description
Day Capture/Compare selection
Select whether day of week, or day of month is subject for Capture/Compare.
16:12
Value
Mode
Description
0
MONTH
Day of month is selected for Capture/Compare.
1
WEEK
Day of week is selected for Capture/Compare.
COMPMASK
0x00
RW
Capture compare channel comparison mask.
The COMPMASK most significant bits of the compare value will not be subject to comparison.
11
COMPBASE
0
RW
Capture compare channel comparison base.
Configure comparison base for compare channel
Value
Mode
Description
0
CNT
RTCC_CCx_CCV
is
compared
with
RTCC_CNT
register.
RTCC_CCx_TIME/DATE compare with RTCC_TIME/DATE in calendar
mode.
1
PRECNT
Least significant bits of RTCC_CCx_CCV are compared with PRECNT.
10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:6
PRSSEL
0x0
RW
Compare/Capture Channel PRS Input Channel Selection
Select PRS input channel for Compare/Capture channel.
5:4
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected as input
1
PRSCH1
PRS Channel 1 selected as input
2
PRSCH2
PRS Channel 2 selected as input
3
PRSCH3
PRS Channel 3 selected as input
4
PRSCH4
PRS Channel 4 selected as input
5
PRSCH5
PRS Channel 5 selected as input
6
PRSCH6
PRS Channel 6 selected as input
7
PRSCH7
PRS Channel 7 selected as input
8
PRSCH8
PRS Channel 8 selected as input
9
PRSCH9
PRS Channel 9 selected as input
10
PRSCH10
PRS Channel 10 selected as input
11
PRSCH11
PRS Channel 11 selected as input
ICEDGE
0x0
RW
Input Capture Edge Select
These bits control which edges the PRS edge detector triggers on.
Value
Mode
Description
0
RISING
Rising edges detected
1
FALLING
Falling edges detected
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RTCC - Real Time Counter and Calendar
Bit
3:2
Name
Reset
Access
2
BOTH
Both edges detected
3
NONE
No edge detection, signal is left as it is
CMOA
0x0
RW
Description
Compare Match Output Action
Select output action on compare match.
1:0
Value
Mode
Description
0
PULSE
A single clock cycle pulse is generated on output
1
TOGGLE
Toggle output on compare match
2
CLEAR
Clear output on compare match
3
SET
Set output on compare match
MODE
0x0
RW
CC Channel Mode
These bits select the mode for Compare/Capture channel.
Value
Mode
Description
0
OFF
Compare/Capture channel turned off
1
INPUTCAPTURE
Input capture
2
OUTPUTCOMPARE
Output compare
11.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CCV RWH 0x00000000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
CCV
0x00000000
RWH
Capture/Compare Value
Shows the Capture/Compare Value for the channel. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = CALENDAR.
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RTCC - Real Time Counter and Calendar
11.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Bit
Name
Reset
31:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:20
HOURT
0x0
RWH
0
1
2
RWH 0x0
SECU
3
4
RWH 0x0 5
SECT
6
7
8
9
11
12
14
15
16
17
18
10
RWH 0x0
MINU
Name
RWH 0x0 13
Access
MINT
Reset
HOURU RWH 0x0
19
20
21
HOURT RWH 0x0
22
23
24
25
26
27
28
29
30
0x048
Bit Position
31
Offset
Description
Hours, tens.
Shows the tens part of the Capture/Compare value for hours. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
19:16
HOURU
0x0
RWH
Hours, units.
Shows the unit part of the Capture/Compare value for hours. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14:12
MINT
0x0
RWH
Minutes, tens.
Shows the tens part of the Capture/Compare value for minutes. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
11:8
MINU
0x0
RWH
Minutes, units.
Shows the unit part of the Capture/Compare value for minutes. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:4
SECT
0x0
RWH
Seconds, tens.
Shows the tens part of the Capture/Compare value for seconds. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
3:0
SECU
0x0
RWH
Seconds, units.
Shows the unit part of the Capture/Compare value for seconds. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
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RTCC - Real Time Counter and Calendar
11.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Name
Reset
31:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12
MONTHT
0
0
1
2
RWH 0x0
3
4
5
RWH 0x0
6
7
8
9
Bit
RWH
DAYU
Name
DAYT
Access
10
MONTHU RWH 0x0
11
MONTHT RWH
0
Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x04C
Bit Position
31
Offset
Description
Month, tens.
Shows the tens part of the Capture/Compare value for months. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
11:8
MONTHU
0x0
RWH
Month, units.
Shows the unit part of the Capture/Compare value for months. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:4
DAYT
0x0
RWH
Day of month/week, tens.
Shows the tens part of the Capture/Compare value for days. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
3:0
DAYU
0x0
RWH
Day of month/week, units.
Shows the unit part of the Capture/Compare value for days. Register can not be written and will be read as zero when
RTCC_CTRL_CNTMODE = NORMAL.
11.5.21 RTCC_RETx_REG - Retention register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REG RW 0xXXXXXXXX
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x104
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
Description
31:0
REG
0xXXXXXXX
X
RW
General Purpose Retention Register
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WDOG - Watchdog Timer
12. WDOG - Watchdog Timer
Quick Facts
What?
0 1 2 3
4
The WDOG (Watchdog Timer) resets the system in
case of a fault condition, and can be enabled in all
energy modes as long as the low frequency clock
source is available.
Why?
Counter value
Watchdog clear
System reset
Timeout period
If a software failure or external event renders the
MCU unresponsive, a Watchdog timeout will reset
the system to a known, safe state.
How?
Time
An enabled Watchdog Timer implements a configurable timeout period. If the CPU fails to re-start the
Watchdog Timer before it times out, a full system reset will be triggered. The Watchdog consumes insignificant power, and allows the device to remain safely in low energy modes for up to 256 seconds at a
time.
12.1 Introduction
The purpose of the watchdog timer is to generate a reset in case of a system failure to increase application reliability. The failure can be
caused by a variety of events, such as an ESD pulse or a software failure.
12.2 Features
• Clock input from selectable oscillators
• Internal 32 kHz RC oscillator
• Internal 1 kHz RC oscillator
• External 32.768 kHz XTAL oscillator
• Configurable timeout period from 9 to 256k watchdog clock cycles
• Individual selection to keep running or freeze when entering EM2 DeepSleep or EM3 Stop
• Selection to keep running or freeze when entering debug mode
• Selection to block the CPU from entering Energy Mode 4
• Selection to block the CMU from disabling the selected watchdog clock
• Configurable warning interrupt at 25%,50%, or 75% of the timeout period
• Configurable window interrupt at 12.5%,25%,37.5%,50%,62.5%,75%,87.5% of the timeout period
• Timeout interrupt
• PRS as a watchdog clear
• Interrupt for the event where a PRS rising edge is absent before a software reset
12.3 Functional Description
The watchdog is enabled by setting the EN bit in WDOGn_CTRL. When enabled, the watchdog counts up to the period value configured through the PERSEL field in WDOGn_CTRL. If the watchdog timer is not cleared to 0 (by writing a 1 to the CLEAR bit in
WDOGn_CMD) before the period is reached, the chip is reset. If a timely clear command is issued, the timer starts counting up from 0
again. The watchdog can optionally be locked by writing the LOCK bit in WDOGn_CTRL. Once locked, it cannot be disabled or reconfigured by software.
When the EN bit in WDOGn_CTRL is cleared to 0, the watchdog counter is reset.
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WDOG - Watchdog Timer
12.3.1 Clock Source
Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOGn_CTRL. The corresponding clocks
must be enabled in the CMU. The SWOSCBLOCK bit in WDOGn_CTRL can be written to prevent accidental disabling of the selected
clocks. Also, setting this bit will automatically start the selected oscillator source when the watchdog is enabled. The PERSEL field in
WDOGn_CTRL is used to divide the selected watchdog clock, and the timeout for the watchdog timer can be calculated with the formula:
TTIMEOUT = (23+PERSEL + 1) / f
where f is the frequency of the selected clock.
When the watchdog is enabled, it is recommended to clear the watchdog before changing PERSEL.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
12.3.2 Debug Functionality
The watchdog timer can either keep running or be frozen when the device is halted by a debugger. This configuration is done through
the DEBUGRUN bit in WDOGn_CTRL. When code execution is resumed, the watchdog will continue counting where it left off.
12.3.3 Energy Mode Handling
The watchdog timer can be configured to either keep on running or freeze when entering EM2 DeepSleep or EM3 Stop. The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in WDOGn_CTRL. When the watchdog has been
frozen and is re-entering an energy mode where it is running, the watchdog timer will continue counting where it left off. For the watchdog there is no difference between EM0 Active and EM1 Sleep. The watchdog does not run in EM4 Hibernate/Shutoff. If EM4BLOCK in
WDOGn_CTRL is set, the CPU will be prevented from entering EM4 Hibernate/Shutoff by software request.
Note:
If the WDOG is clocked by the LFXO or LFRCO, writing the SWOSCBLOCK bit will prevent the CPU from entering EM3 Stop. When
running from the ULFRCO, writing the SWOSCBLOCK bit will prevent the CPU from entering EM4 Hibernate/Shutoff.
12.3.4 Register access
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 4.3 Access to Low Energy Peripherals (Asynchronous Registers) for a description on how to perform register accesses to Low Energy Peripherals. Note that clearing the EN bit in WDOGn_CTRL will reset the
WDOG module, which will halt any ongoing register synchronization.
Note:
Never write to the WDOG registers when it is disabled, except to enable the watchdog by setting the EN bitfield in WDOGn_CTRL.
12.3.5 Warning Interrupt
The watchdog implements a warning interrupt which can be configured to occur at approximately 25%, 50%, or 75% of the timeout
period through the WARNSEL field of the WDOGn_CTRL register.This interrupt can be used to wake up the cpu for clearing the watchdog. The warning point for the watchdog timer can be calculated with the formula:
TWARNING = (23+PERSEL) * (WARNSEL / 4) + 1) / f,
where f is the frequency of the selected clock.
When the watchdog is enabled, it is recommended to clear the watchdog before changing WARNSEL.
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WDOG - Watchdog Timer
12.3.6 Window Interrupt
This interrupt occurs when the watchdog is cleared below a certain threshold. This threshold is given by the formula:
TWARNING = (23+PERSEL) * (WINSEL/8) + 1)/f,
where f is the frequency of the selected clock.
This value will be approximately 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, or 87.5% of the timeout value based on the WINSEL field of
the WDOGn_CTRL. Figure 12.1 WDOG Warning, Window, and Timeout on page 311 illustrates the warning, the window, and the timeout interrupts. Also, it shows where the prs rising edge needs to happen. The prs edge detection feature is discussed later.
Counter value
Watchdog clear
System reset
Timeout period
Warning Irq
Legal Window
Time
PRS Event
Figure 12.1 WDOG Warning, Window, and Timeout
When the watchdog is enabled, it is recommended to clear the watchdog before changing WINSEL.
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WDOG - Watchdog Timer
12.3.7 PRS as Watchdog Clear
The first PRS channel (selected by register WDOGn_PCH0_PRSCTRL) can be used to clear the watchdog counter. To enable this feature, CLRSRC must be set to 1. Figure 12.2 PRS Clearing WDOG on page 312 shows how the PRS channel takes over the wdog clear
function. Clearing the WDOG with the PRS is mutually exclusive of clearing the WDT by software.
Counter value
PRS clear
Timeout Irq
Timeout period
Warning Irq
Legal Window
Time
Figure 12.2 PRS Clearing WDOG
12.3.8 PRS Rising Edge Monitoring
PRS channels can be used to monitor multiple processes. If enabled, every time the watch dog timer is cleared the PRS channels are
checked and any channel which has not seen an event can trigger an interrupt.
Counter value
PRS[0]
wdog clear
Time
Time
PRS[1] PRS[2]
PRS[0] PRS[1]
Figure 12.3 PRS Edge Monitoring in WDOG
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WDOG - Watchdog Timer
12.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
WDOG_CTRL
RW
Control Register
0x004
WDOG_CMD
W1
Command Register
0x008
WDOG_SYNCBUSY
R
Synchronization Busy Register
0x00C
WDOGn_PCH0_PRSCTRL
RW
PRS Control Register
0x010
WDOGn_PCH1_PRSCTRL
RW
PRS Control Register
0x01C
WDOG_IF
R
Watchdog Interrupt Flags
0x020
WDOG_IFS
W1
Interrupt Flag Set Register
0x024
WDOG_IFC
(R)W1
Interrupt Flag Clear Register
0x028
WDOG_IEN
RW
Interrupt Enable Register
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WDOG - Watchdog Timer
12.5 Register Description
12.5.1 WDOG_CTRL - Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
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0
RW
EN
0
1
RW
DEBUGRUN
0
2
3
RW
EM2RUN
0
RW
EM3RUN
0
4
RW
LOCK
0
5
0
RW
EM4BLOCK
6
0
SWOSCBLOCK RW
7
8
9
10
RW 0xF
PERSEL
11
12
13
RW 0x0
CLKSEL
14
15
16
17
RW 0x0
WARNSEL
18
19
20
21
22
23
24
RW 0x0 25
WINSEL
26
27
28
29
30
RW
CLRSRC
0
RW
Name
Reset
0
Access
WDOGRSTDIS
0x000
Bit Position
31
Offset
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WDOG - Watchdog Timer
Bit
Name
Reset
Access
Description
31
WDOGRSTDIS
0
RW
Watchdog Reset Disable
Disable watchdog reset output.
30
Value
Mode
Description
0
EN
A timeout will cause a watchdog reset
1
DIS
A timeout will not cause a watchdog reset
CLRSRC
0
RW
Watchdog Clear Source
Select watchdog clear source.
Value
Mode
Description
0
SW
A write to the clear bit will clear the watchdog counter
1
PCH0
A rising edge on the PRS Channel0 will clear the watchdog counter
29:27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
WINSEL
0x0
RW
Watchdog Illegal Window Select
Select watchdog illegal limit.
Value
Description
0
Disabled.
1
Window limit is 12.5% of
the Timeout.
2
Window limit is 25.0% of
the Timeout.
3
Window limit is 37.5% of
the Timeout.
4
Window limit is 50.0% of
the Timeout.
5
Window limit is 62.5% of
the Timeout.
6
Window limit is 75.0% of
the Timeout.
7
Window limit is 87.5% of
the Timeout.
23:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
WARNSEL
0x0
RW
Watchdog Timeout Period Select
Select watchdog warning timeout period.
Value
Description
0
Disabled.
1
Warning timeout is 25%
of the Timeout.
2
Warning timeout is 50%
of the Timeout.
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WDOG - Watchdog Timer
Bit
Name
Reset
Access
3
Warning timeout is 75%
of the Timeout.
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:12
CLKSEL
0x0
RW
Description
Watchdog Clock Select
Selects the WDOG oscillator, i.e. the clock on which the watchdog will run.
11:8
Value
Mode
Description
0
ULFRCO
ULFRCO
1
LFRCO
LFRCO
2
LFXO
LFXO
PERSEL
0xF
RW
Watchdog Timeout Period Select
Select watchdog timeout period.
Value
Description
0
Timeout period of 9
watchdog clock cycles.
1
Timeout period of 17
watchdog clock cycles.
2
Timeout period of 33
watchdog clock cycles.
3
Timeout period of 65
watchdog clock cycles.
4
Timeout period of 129
watchdog clock cycles.
5
Timeout period of 257
watchdog clock cycles.
6
Timeout period of 513
watchdog clock cycles.
7
Timeout period of 1k
watchdog clock cycles.
8
Timeout period of 2k
watchdog clock cycles.
9
Timeout period of 4k
watchdog clock cycles.
10
Timeout period of 8k
watchdog clock cycles.
11
Timeout period of 16k
watchdog clock cycles.
12
Timeout period of 32k
watchdog clock cycles.
13
Timeout period of 64k
watchdog clock cycles.
14
Timeout period of 128k
watchdog clock cycles.
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WDOG - Watchdog Timer
Bit
Name
Reset
Access
15
Timeout period of 256k
watchdog clock cycles.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
SWOSCBLOCK
0
RW
Description
Software Oscillator Disable Block
Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it
is not already running.
5
Value
Description
0
Software is allowed to disable the selected WDOG oscillator. See CMU
for detailed description. Note that also CMU registers are lockable.
1
Software is not allowed to disable the selected WDOG oscillator.
EM4BLOCK
0
RW
Energy Mode 4 Block
Set to disallow EM4 entry by software.
4
Value
Description
0
EM4 can be entered by software. See EMU for detailed description.
1
EM4 cannot be entered by software.
LOCK
0
RW
Configuration lock
Set to lock the watchdog configuration. This bit can only be cleared by reset.
3
Value
Description
0
Watchdog configuration can be changed.
1
Watchdog configuration cannot be changed.
EM3RUN
0
RW
Energy Mode 3 Run Enable
Set to keep watchdog running in EM3.
2
Value
Description
0
Watchdog timer is frozen in EM3.
1
Watchdog timer is running in EM3.
EM2RUN
0
RW
Energy Mode 2 Run Enable
Set to keep watchdog running in EM2.
1
Value
Description
0
Watchdog timer is frozen in EM2.
1
Watchdog timer is running in EM2.
DEBUGRUN
0
RW
Debug Mode Run Enable
Set to keep watchdog running in debug mode.
Value
Description
0
Watchdog timer is frozen in debug mode.
1
Watchdog timer is running in debug mode.
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WDOG - Watchdog Timer
Bit
Name
Reset
Access
Description
0
EN
0
RW
Watchdog Timer Enable
Set to enabled watchdog timer.
12.5.2 WDOG_CMD - Command Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
0
1
2
CLEAR W1 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
CLEAR
0
W1
Description
Watchdog Timer Clear
Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout.
Value
Mode
Description
0
UNCHANGED
Watchdog timer is unchanged.
1
CLEARED
Watchdog timer is cleared to 0.
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WDOG - Watchdog Timer
12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
PCH1_PRSCTRL
0
R
0
0
R
CTRL
1
0
R
CMD
2
3
0
Name
0
Access
PCH0_PRSCTRL R
Reset
PCH1_PRSCTRL R
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Description
PCH1_PRSCTRL Register Busy
Set when the value written to PCH1_PRSCTRL is being synchronized.
2
PCH0_PRSCTRL
0
R
PCH0_PRSCTRL Register Busy
Set when the value written to PCH0_PRSCTRL is being synchronized.
1
CMD
0
R
CMD Register Busy
Set when the value written to CMD is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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WDOG - Watchdog Timer
12.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Name
Access
Bit
Name
Reset
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8
PRSMISSRSTEN
0
RW
0
1
2
RW 0x0
PRSSEL
Access
3
4
5
6
7
8
PRSMISSRSTEN RW
0
Reset
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Description
PRS missing event will trigger a watchdog reset
When set, a PRS missing event will trigger a watchdog reset.
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
PRSSEL
0x0
RW
PRS Channel PRS Select
These bits select the PRS input for the PRS channel.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected as input
1
PRSCH1
PRS Channel 1 selected as input
2
PRSCH2
PRS Channel 2 selected as input
3
PRSCH3
PRS Channel 3 selected as input
4
PRSCH4
PRS Channel 4 selected as input
5
PRSCH5
PRS Channel 5 selected as input
6
PRSCH6
PRS Channel 6 selected as input
7
PRSCH7
PRS Channel 7 selected as input
8
PRSCH8
PRS Channel 8 selected as input
9
PRSCH9
PRS Channel 9 selected as input
10
PRSCH10
PRS Channel 10 selected as input
11
PRSCH11
PRS Channel 11 selected as input
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WDOG - Watchdog Timer
12.5.5 WDOG_IF - Watchdog Interrupt Flags
Access
0
0
Reset
31:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
PEM1
0
R
TOUT
1
0
2
WARN R
Name
R
3
0
R
Bit
0
R
WIN
Name
PEM0
4
0
Access
R
Reset
PEM1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Description
PRS Channel One Event Missing Interrupt Flag
Set when a wdog clear happens before a prs event has been detected on PRS channel one.
3
PEM0
0
R
PRS Channel Zero Event Missing Interrupt Flag
Set when a wdog clear happens before a prs event has been detected on PRS channel zero.
2
WIN
0
R
Wdog Window Interrupt Flag
Set when a wdog clear happens below the window limit value.
1
WARN
0
R
Wdog Warning Timeout Interrupt Flag
Set when a wdog warning timeout has occurred.
0
TOUT
0
R
Wdog Timeout Interrupt Flag
Set when a wdog timeout has occurred.
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WDOG - Watchdog Timer
12.5.6 WDOG_IFS - Interrupt Flag Set Register
Access
1
0
WARN W1 0
TOUT
Name
Reset
31:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
PEM1
0
W1 0
2
W1 0
Bit
3
W1 0
WIN
4
5
6
7
8
9
10
PEM0
Name
W1 0
Access
PEM1
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Description
W1
Set PEM1 Interrupt Flag
W1
Set PEM0 Interrupt Flag
W1
Set WIN Interrupt Flag
W1
Set WARN Interrupt Flag
W1
Set TOUT Interrupt Flag
Write 1 to set the PEM1 interrupt flag
3
PEM0
0
Write 1 to set the PEM0 interrupt flag
2
WIN
0
Write 1 to set the WIN interrupt flag
1
WARN
0
Write 1 to set the WARN interrupt flag
0
TOUT
0
Write 1 to set the TOUT interrupt flag
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WDOG - Watchdog Timer
12.5.7 WDOG_IFC - Interrupt Flag Clear Register
Access
1
0
WARN (R)W1 0
TOUT
Name
Reset
31:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
PEM1
0
(R)W1
(R)W1 0
2
(R)W1 0
Bit
3
(R)W1 0
WIN
4
5
6
7
8
9
10
PEM0
Name
(R)W1 0
Access
PEM1
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Description
Clear PEM1 Interrupt Flag
Write 1 to clear the PEM1 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
3
PEM0
0
(R)W1
Clear PEM0 Interrupt Flag
Write 1 to clear the PEM0 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
2
WIN
0
(R)W1
Clear WIN Interrupt Flag
Write 1 to clear the WIN interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
1
WARN
0
(R)W1
Clear WARN Interrupt Flag
Write 1 to clear the WARN interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
0
TOUT
0
(R)W1
Clear TOUT Interrupt Flag
Write 1 to clear the TOUT interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
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WDOG - Watchdog Timer
12.5.8 WDOG_IEN - Interrupt Enable Register
Access
1
0
WARN RW 0
TOUT
Name
Reset
31:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
PEM1
0
RW 0
2
RW 0
Bit
3
RW 0
WIN
4
5
6
7
8
9
10
PEM0
Name
RW 0
Access
PEM1
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Description
RW
PEM1 Interrupt Enable
RW
PEM0 Interrupt Enable
RW
WIN Interrupt Enable
RW
WARN Interrupt Enable
RW
TOUT Interrupt Enable
Enable/disable the PEM1 interrupt
3
PEM0
0
Enable/disable the PEM0 interrupt
2
WIN
0
Enable/disable the WIN interrupt
1
WARN
0
Enable/disable the WARN interrupt
0
TOUT
0
Enable/disable the TOUT interrupt
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PRS - Peripheral Reflex System
13. PRS - Peripheral Reflex System
Quick Facts
What?
0 1 2 3
4
The PRS (Peripheral Reflex System) allows configurable, fast, and autonomous communication between peripherals.
Why?
Timer
PRS
Ch
ADC
DMA
PRS
Ch
Events and signals from one peripheral can be used
as input signals or triggers by other peripherals. Besides reducing software overhead and thus current
consumption, this reduces latency and ensures predictable timing.
How?
Without CPU intervention the peripherals can send
Reflex signals (both pulses and level) to each other
in single- or chained steps. The peripherals can be
set up to perform actions based on the incoming Reflex signals. This results in improved system performance and reduced energy consumption.
13.1 Introduction
The Peripheral Reflex System (PRS) is a network allowing direct communication between different peripheral modules without involving
the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex signals through reflex
channels to consumer peripherals which perform actions depending on the Reflex signals received. The format for the Reflex signals is
not given, but edge triggers and other functionality can be applied by the PRS.
13.2 Features
• 12 Configurable Reflex Channels
• Each channel can be connected to any producing peripheral, including the PRS channels
• Consumers can choose which channel to listen to
• Selectable edge detector (Rising, falling and both edges)
• Configurable AND and OR between channels
• Optional channel invert
• PRS can generate event to CPU
• Two independent DMA requests based on PRS channels
• Software controlled channel output
• Configurable level
• Triggered pulses
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PRS - Peripheral Reflex System
13.3 Functional Description
An overview of the PRS module is shown in Figure 13.1 PRS Overview on page 326. The PRS contains 12 Reflex channels. All channels can select any Reflex signal offered by the producers. The consumers can choose which PRS channel to listen to and perform
actions based on the Reflex signals routed through that channel. The Reflex signals can be both edge signals and level signals.
APB Interface
SIGSEL[2:0]
SOURCESEL[5:0]
EDSEL[1:0]
SWPULSE[n]
APB bus
SWLEVEL[n]
Reg
Signals from
producer
peripherals
Signals to
consumer
peripherals
Figure 13.1 PRS Overview
13.3.1 Channel Functions
Different functions can be applied to a reflex signal within the PRS. Each channel includes an edge detector to enable generation of
pulse signals from level signals. The PRS channels can also be manually triggered by writing to PRS_SWPULSE or PRS_SWLEVEL.
SWLEVEL[n] is a programmable level for each channel and holds the value it is programmed to. Setting SWPULSE[n] will cause the
PRS channel to ouput a one HFBUSCLK cycle high pulse. The SWLEVEL[n] and SWPULSE[n] signals are then XOR'ed with the selected input from the producers to form the output signal sent to the consumers listening to the channel. For example, when SWLEVEL[n]
is set, if a producer produces a signal of 1, this will cause a channel output of 0.
13.3.1.1 Asynchronous Mode
Reflex channels can operate in two modes, synchronous or asynchronous. In synchronous mode reflex signals are clocked on the
HFCLK, and can be used by any reflex consumer. However, this will not work in EM2/EM3, since the HFCLK will be turned off.
Asynchronous reflex channels are not clocked on HFCLK, and can be used even in EM2/EM3. However, the asynchronous mode can
only be used by a subset of the reflex consumers.
The asynchronous reflex signals generated by the producers are indicated in the SIGSEL field in PRS_CHx_CTRL. The consumers
capable of utilizing asynchronous reflex signals include the LEUART and the PCNT. The USART can also consume some particular
asynchronous signals. Please refer to the respective modules for details on how to use the PRS.
Note: If a Reflex channel with ASYNC set is used in a consumer not supporting asynchronous reflexes, the behaviour is undefined
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PRS - Peripheral Reflex System
13.3.1.2 Edge Detection and Clock Domains
Using EDSEL in PRS_CHx_CTRL, edge detection can be applied to a PRS signal. When edge detection is enabled, changes in the
PRS input will result in a pulse on the PRS channel. This requires that ASYNC in PRS_CHx_CTRL is disabled. Signals on the PRS
input also has to be at least one HFBUSCLK period wide in order to be detected properly. This applies to all cases when ASYNC is not
used in the PRS.
For communication between peripherals on different prescaled clocks, e.g. between peripherals on HFBUSCLK and HFPERCLK, there
are two options. For level signals, no action is needed, but software must make sure that the level signals are held long enough for the
destination domain to detect them. For pulse signals, edge detection and stretch should be enabled. When edge detection and stretch
are enabled on a PRS source, the output on the PRS channel is held long enough for the destination domain to detect the pulse. This
also works if there are multiple destination domains running at different frequencies.
13.3.1.3 Configurable PRS Logic
Each PRS channel has three logic functions that can be used by themselves or in combination. The selected PRS source can be
AND'ed with the next PRS channel output, OR'ed with the previous PRS channel output and inverted. This is shown in Figure 13.1 PRS
Overview on page 326. The order of the functions is important. If OR and AND are enabled at the same time, AND is applied first, and
then OR.
PRS[i-1]
ORPREV
INV
PRS[0]
PRS[N-1]
PRS[i]
Signals from
producer
peripherals
ANDNEXT
PRS[i+1]
Figure 13.2 Configurable PRS Logic
In addition to the logic functions that can combine a PRS channel with one of its neighbors, a PRS channel can also select any other
PRS channel as input. This can allow relatively complex logic functions to be created.
13.3.2 Producers
Through SOURCESEL in PRS_CHx_CTRL, each PRS channel selects signal producers. Each producer outputs one or more signals
which can be selected by setting the SIGSEL field in PRS_CHx_CTRL. Setting the SOURCESEL bits to 0 (Off) leads to a constant 0
output from the input mux. An overview of the available producers can be found in the SOURCESEL and SIGSEL fields in
PRS_CHx_CTRL.
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PRS - Peripheral Reflex System
13.3.3 Consumers
Consumer peripherals (Listed in Table 13.1 Reflex Consumers on page 328) can be set to listen to a PRS channel and perform an
action based on the signal received on that channel. Most consumers expect pulse input, while some can handle level inputs as well.
Table 13.1. Reflex Consumers
Module
Reflex Input
Input Format
TIMER
Compare/Capture Channel
Pulse / Level
Alternate Input for DTI
Level
Alternate Input for DTI Fault 0
Level
Alternate Input for DTI Fault 1
Level
RX/TX Trigger
Pulse
Alternate Input for IrDA
Level
Alternate Input for RX
Level
Alternate Input for CLK
Level
Single Sample Trigger
Pulse
Scan Sequence Trigger
Pulse
IDAC
Alternate Input for OUTMODE
Level
CMU
Alternate Input for Calibration Up-Counter
Level
Alternate Input for Calibration Down-Counter
Level
LEUART
Alternate Input for RX
Level
PCNT
Compare/Clear Trigger
Pulse/Level
Alternate Input for S0IN
Level
Alternate Input for S1IN
Level
WDOG
Peripheral Watchdog
Pulse
LETIMER
Start LETIMER
Pulse
Stop LETIMER
Pulse
Clear LETIMER
Pulse
RTCC
Compare/Capture Channel
Pulse/Level
PRS
Set Event
Pulse
DMA Request 0
Pulse
DMA Request 1
Pulse
USART
ADC
13.3.4 Event on PRS
The PRS can be used to send events to the MCU. This is very useful in combination with the Wait For Event (WFE) instruction. A single
PRS channel can be selected for this using SEVONPRSSEL in PRS_CTRL, and the feature is enabled by setting SEVONPRS in the
same register.
Using SEVONPRS, one can e.g. set up a timer to trigger an event to the MCU periodically, every time letting the MCU pass through a
WFE instruction in its program. This can help in performance-critical sections where timing is known, and the goal is to wait for an
event, then execute some code, then wait for an event, then execute some code and so on.
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PRS - Peripheral Reflex System
13.3.5 DMA Request on PRS
Up to two independent DMA requests can be generated by the PRS. The PRS signals triggering the DMA requests are selected with
the DMAREQxSEL fields in DMA_CTRL. The DMA requests are cleared on write to the DMAREQxSEL fields and when the DMA services the requests. The requests are set whenever the selected PRS signals are high.
The selected PRS signals must have ASYNC cleared when they are used as inputs to the DMA. Edge detection in the PRS can be
enabled to only trigger transfers on edges.
13.3.6 Example
The example below (illustrated in Figure 13.3 TIMER0 overflow starting ADC0 single conversions through PRS channel 5. on page
329) shows how to set up ADC0 to start single conversions every time TIMER0 overflows (one HFPERCLK cycle high pulse), using
PRS channel 5:
• Set SOURCESEL in PRS_CH5_CTRL to TIMER0 as input to PRS channel 5.
• Set SIGSEL in PRS_CH5_CTRL to select the overflow signal (from TIMER0).
• Configure ADC0 with the desired conversion set-up.
• Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal.
• Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion.
• Start TIMER0 with the desired TOP value, an overflow PRS signal is output automatically on overflow.
Note that the ADC results needs to be fetched either by the CPU or DMA.
PRS
TIMER0
ADC0
Overflow
Start single conv.
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
Figure 13.3 TIMER0 overflow starting ADC0 single conversions through PRS channel 5.
13.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
PRS_SWPULSE
W1
Software Pulse Register
0x004
PRS_SWLEVEL
RW
Software Level Register
0x008
PRS_ROUTEPEN
RW
I/O Routing Pin Enable Register
0x010
PRS_ROUTELOC0
RW
I/O Routing Location Register
0x014
PRS_ROUTELOC1
RW
I/O Routing Location Register
0x018
PRS_ROUTELOC2
RW
I/O Routing Location Register
0x020
PRS_CTRL
RW
Control Register
0x024
PRS_DMAREQ0
RW
DMA Request 0 Register
0x028
PRS_DMAREQ1
RW
DMA Request 1 Register
0x030
PRS_PEEK
R
PRS Channel Values
0x040
PRS_CH0_CTRL
RW
Channel Control Register
0x044
PRS_CH1_CTRL
RW
Channel Control Register
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PRS - Peripheral Reflex System
13.5 Register Description
13.5.1 PRS_SWPULSE - Software Pulse Register
Access
0
W1 0
CH0PULSE
1
W1 0
CH1PULSE
2
W1 0
CH2PULSE
3
W1 0
CH3PULSE
4
W1 0
CH4PULSE
5
W1 0
W1 0
CH6PULSE
CH5PULSE
W1 0
CH7PULSE
6
W1 0
CH8PULSE
7
9
W1 0
CH9PULSE
8
10
12
13
14
CH10PULSE W1 0
Name
11
Access
CH11PULSE W1 0
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
Bit
Name
Reset
Description
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
CH11PULSE
0
W1
Channel 11 Pulse Generation
0
W1
Channel 10 Pulse Generation
0
W1
Channel 9 Pulse Generation
0
W1
Channel 8 Pulse Generation
0
W1
Channel 7 Pulse Generation
0
W1
Channel 6 Pulse Generation
0
W1
Channel 5 Pulse Generation
0
W1
Channel 4 Pulse Generation
0
W1
Channel 3 Pulse Generation
0
W1
Channel 2 Pulse Generation
0
W1
Channel 1 Pulse Generation
0
W1
Channel 0 Pulse Generation
See bit 0.
10
CH10PULSE
See bit 0.
9
CH9PULSE
See bit 0.
8
CH8PULSE
See bit 0.
7
CH7PULSE
See bit 0.
6
CH6PULSE
See bit 0.
5
CH5PULSE
See bit 0.
4
CH4PULSE
See bit 0.
3
CH3PULSE
See bit 0.
2
CH2PULSE
See bit 0.
1
CH1PULSE
See bit 0.
0
CH0PULSE
Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL
register and the selected PRS input signal to generate the channel output.
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PRS - Peripheral Reflex System
13.5.2 PRS_SWLEVEL - Software Level Register
Access
0
RW 0
CH0LEVEL
1
RW 0
CH1LEVEL
2
RW 0
CH2LEVEL
3
RW 0
CH3LEVEL
4
RW 0
CH4LEVEL
5
RW 0
RW 0
CH6LEVEL
CH5LEVEL
RW 0
CH7LEVEL
6
RW 0
CH8LEVEL
7
9
RW 0
CH9LEVEL
8
10
Name
CH10LEVEL RW 0
Access
11
12
Reset
CH11LEVEL RW 0
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Bit
Name
Reset
Description
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
CH11LEVEL
0
RW
Channel 11 Software Level
0
RW
Channel 10 Software Level
0
RW
Channel 9 Software Level
0
RW
Channel 8 Software Level
0
RW
Channel 7 Software Level
0
RW
Channel 6 Software Level
0
RW
Channel 5 Software Level
0
RW
Channel 4 Software Level
0
RW
Channel 3 Software Level
0
RW
Channel 2 Software Level
0
RW
Channel 1 Software Level
0
RW
Channel 0 Software Level
See bit 0.
10
CH10LEVEL
See bit 0.
9
CH9LEVEL
See bit 0.
8
CH8LEVEL
See bit 0.
7
CH7LEVEL
See bit 0.
6
CH6LEVEL
See bit 0.
5
CH5LEVEL
See bit 0.
4
CH4LEVEL
See bit 0.
3
CH3LEVEL
See bit 0.
2
CH2LEVEL
See bit 0.
1
CH1LEVEL
See bit 0.
0
CH0LEVEL
The value in this register is XOR'ed with the corresponding bit in the SWPULSE register and the selected PRS input signal
to generate the channel output.
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PRS - Peripheral Reflex System
13.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register
Access
0
RW 0
CH0PEN
1
RW 0
CH1PEN
2
RW 0
CH2PEN
Bit
Name
Reset
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
CH11PEN
0
RW
3
RW 0
CH3PEN
4
RW 0
CH4PEN
5
RW 0
RW 0
CH6PEN
CH5PEN
RW 0
CH7PEN
6
RW 0
CH8PEN
7
9
RW 0
CH9PEN
8
10
12
CH10PEN RW 0
Name
11
Access
CH11PEN RW 0
Reset
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Description
CH11 Pin Enable
When set, GPIO output from PRS channel 11 is enabled
10
CH10PEN
0
RW
CH10 Pin Enable
When set, GPIO output from PRS channel 10 is enabled
9
CH9PEN
0
RW
CH9 Pin Enable
When set, GPIO output from PRS channel 9 is enabled
8
CH8PEN
0
RW
CH8 Pin Enable
When set, GPIO output from PRS channel 8 is enabled
7
CH7PEN
0
RW
CH7 Pin Enable
When set, GPIO output from PRS channel 7 is enabled
6
CH6PEN
0
RW
CH6 Pin Enable
When set, GPIO output from PRS channel 6 is enabled
5
CH5PEN
0
RW
CH5 Pin Enable
When set, GPIO output from PRS channel 5 is enabled
4
CH4PEN
0
RW
CH4 Pin Enable
When set, GPIO output from PRS channel 4 is enabled
3
CH3PEN
0
RW
CH3 Pin Enable
When set, GPIO output from PRS channel 3 is enabled
2
CH2PEN
0
RW
CH2 Pin Enable
When set, GPIO output from PRS channel 2 is enabled
1
CH1PEN
0
RW
CH1 Pin Enable
When set, GPIO output from PRS channel 1 is enabled
0
CH0PEN
0
RW
CH0 Pin Enable
When set, GPIO output from PRS channel 0 is enabled
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PRS - Peripheral Reflex System
13.5.4 PRS_ROUTELOC0 - I/O Routing Location Register
0
1
2
3
CH0LOC RW 0x00
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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CH1LOC RW 0x00
Name
CH2LOC RW 0x00
Access
CH3LOC RW 0x00
Reset
30
0x010
Bit Position
31
Offset
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:24
CH3LOC
0x00
RW
Description
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
23:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:16
CH2LOC
0x00
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
CH1LOC
0x00
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
CH0LOC
0x00
RW
Description
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
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PRS - Peripheral Reflex System
13.5.5 PRS_ROUTELOC1 - I/O Routing Location Register
0
1
2
3
CH4LOC RW 0x00
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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CH5LOC RW 0x00
Name
CH6LOC RW 0x00
Access
CH7LOC RW 0x00
Reset
30
0x014
Bit Position
31
Offset
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EFM32JG1 Reference Manual
PRS - Peripheral Reflex System
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:24
CH7LOC
0x00
RW
Description
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
23:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:16
CH6LOC
0x00
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
Description
17
LOC17
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
CH5LOC
0x00
Location 17
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
CH4LOC
0x00
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
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PRS - Peripheral Reflex System
13.5.6 PRS_ROUTELOC2 - I/O Routing Location Register
0
1
2
3
CH8LOC
RW 0x00
4
5
6
7
8
9
10
11
RW 0x00
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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CH9LOC
Name
CH10LOC RW 0x00
Access
CH11LOC RW 0x00
Reset
30
0x018
Bit Position
31
Offset
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EFM32JG1 Reference Manual
PRS - Peripheral Reflex System
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:24
CH11LOC
0x00
RW
Description
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
23:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:16
CH10LOC
0x00
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
CH9LOC
0x00
RW
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
CH8LOC
0x00
RW
Description
I/O Location
Decides the location of the channel I/O pin
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
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PRS - Peripheral Reflex System
13.5.7 PRS_CTRL - Control Register
Name
Bit
Name
Reset
Access
31:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4:1
SEVONPRSSEL
0x0
RW
0
0
RW
Access
SEVONPRS
Reset
1
2
3
SEVONPRSSEL RW 0x0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Description
SEVONPRS PRS Channel Select
Selects PRS channel for SEVONPRS
0
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
SEVONPRS
0
RW
Set Event on PRS
When set, an event is generated to the CPU when the PRS channel selected by SEVONPRSSEL is high
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PRS - Peripheral Reflex System
13.5.8 PRS_DMAREQ0 - DMA Request 0 Register
0
1
2
3
4
5
6
7
8
PRSSEL RW 0x0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:6
PRSSEL
0x0
RW
Description
DMA Request 0 PRS Channel Select
Selects PRS channel for DMA request 0 from the PRS. Request is cleared on DMAREQ0 write
5:0
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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PRS - Peripheral Reflex System
13.5.9 PRS_DMAREQ1 - DMA Request 1 Register
0
1
2
3
4
5
6
7
8
PRSSEL RW 0x0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:6
PRSSEL
0x0
RW
Description
DMA Request 1 PRS Channel Select
Selects PRS channel for DMA request 1 from the PRS. Request is cleared on DMAREQ1 write
5:0
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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PRS - Peripheral Reflex System
13.5.10 PRS_PEEK - PRS Channel Values
Access
0
R
CH0VAL
0
1
R
CH1VAL
0
2
3
R
CH2VAL
0
R
CH3VAL
0
4
R
CH4VAL
0
5
0
R
CH5VAL
6
0
R
CH6VAL
7
0
R
CH7VAL
8
0
R
CH8VAL
9
0
R
CH9VAL
10
0
CH10VAL R
Name
11
12
Access
0
Reset
CH11VAL R
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Bit
Name
Reset
Description
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
CH11VAL
0
R
Channel 11 Current Value
0
R
Channel 10 Current Value
0
R
Channel 9 Current Value
0
R
Channel 8 Current Value
0
R
Channel 7 Current Value
0
R
Channel 6 Current Value
0
R
Channel 5 Current Value
0
R
Channel 4 Current Value
0
R
Channel 3 Current Value
0
R
Channel 2 Current Value
0
R
Channel 1 Current Value
0
R
Channel 0 Current Value
See bit 0.
10
CH10VAL
See bit 0.
9
CH9VAL
See bit 0.
8
CH8VAL
See bit 0.
7
CH7VAL
See bit 0.
6
CH6VAL
See bit 0.
5
CH5VAL
See bit 0.
4
CH4VAL
See bit 0.
3
CH3VAL
See bit 0.
2
CH2VAL
See bit 0.
1
CH1VAL
See bit 0.
0
CH0VAL
When ASYNC = 0, sample the current output value of channel 0. Any enabled edge detection will not be visible. This value
may be one or two clock delayed. When ASYNC = 1, no value is returned
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PRS - Peripheral Reflex System
13.5.11 PRS_CHx_CTRL - Channel Control Register
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0
1
SIGSEL
RW
0x0
2
3
4
5
6
7
8
9
10
12
SOURCESEL RW 0x00 11
13
14
15
16
17
18
19
20
21
0x0
RW
EDSEL
22
23
24
25
RW
STRETCH
0
26
RW
INV
0
27
RW
ORPREV
0
28
RW
Name
ANDNEXT
0
RW
29
30
Access
ASYNC
Reset
0
0x040
Bit Position
31
Offset
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
30
ASYNC
0
RW
Description
Asynchronous reflex
Set to enable asynchronous mode of this reflex signal
29
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
28
ANDNEXT
0
RW
And Next
Channel output is AND'ed with the next channel output
27
ORPREV
0
RW
Or Previous
Channel output is OR'ed with the previous channel output
26
INV
0
RW
Invert Channel
0
RW
Stretch Channel Output
Invert channel output
25
STRETCH
Stretches channel output to ensure that the target clock domain sees it.
24:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:20
EDSEL
0x0
RW
Edge Detect Select
Select edge detection.
Value
Mode
Description
0
OFF
Signal is left as it is
1
POSEDGE
A one HFPERCLK cycle pulse is generated for every positive edge of
the incoming signal
2
NEGEDGE
A one HFPERCLK clock cycle pulse is generated for every negative
edge of the incoming signal
3
BOTHEDGES
A one HFPERCLK clock cycle pulse is generated for every edge of the
incoming signal
19:15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14:8
SOURCESEL
0x00
RW
Source Select
Select input source to PRS channel.
Value
Mode
Description
0b0000000
NONE
No source selected
0b0000001
PRSL
Peripheral Reflex System
0b0000010
PRSH
Peripheral Reflex System
0b0000110
ACMP0
Analog Comparator 0
0b0000111
ACMP1
Analog Comparator 1
0b0001000
ADC0
Analog to Digital Converter 0
0b0010000
USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0b0010001
USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0b0011100
TIMER0
Timer 0
0b0011101
TIMER1
Timer 1
0b0101001
RTCC
Real-Time Counter and Calendar
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
0b0110000
GPIOL
General purpose Input/Output
0b0110001
GPIOH
General purpose Input/Output
0b0110100
LETIMER0
Low Energy Timer 0
0b0110110
PCNT0
Pulse Counter 0
0b0111100
CRYOTIMER
CryoTimer
0b0111101
CMU
Clock Management Unit
7:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2:0
SIGSEL
0x0
RW
Description
Signal Select
Select signal input to PRS channel.
Value
Mode
Description
OFF
Channel input selection is turned off
0b000
PRSCH0
PRS channel 0 PRSCH0 (Asynchronous)
0b001
PRSCH1
PRS channel 1 PRSCH1 (Asynchronous)
0b010
PRSCH2
PRS channel 2 PRSCH2 (Asynchronous)
0b011
PRSCH3
PRS channel 3 PRSCH3 (Asynchronous)
0b100
PRSCH4
PRS channel 4 PRSCH4 (Asynchronous)
0b101
PRSCH5
PRS channel 5 PRSCH5 (Asynchronous)
0b110
PRSCH6
PRS channel 6 PRSCH6 (Asynchronous)
0b111
PRSCH7
PRS channel 7 PRSCH7 (Asynchronous)
0b000
PRSCH8
PRS channel 8 PRSCH8 (Asynchronous)
0b001
PRSCH9
PRS channel 9 PRSCH9 (Asynchronous)
0b010
PRSCH10
PRS channel 10 PRSCH10 (Asynchronous)
0b011
PRSCH11
PRS channel 11 PRSCH11 (Asynchronous)
ACMP0OUT
Analog comparator output ACMP0OUT (Asynchronous)
ACMP1OUT
Analog comparator output ACMP1OUT (Asynchronous)
0b000
ADC0SINGLE
ADC single conversion done ADC0SINGLE
0b001
ADC0SCAN
ADC scan conversion done ADC0SCAN
SOURCESEL
=
0b000000 (NONE)
0bxxx
SOURCESEL =
0b0000001 (PRS)
SOURCESEL =
0b0000010 (PRS)
SOURCESEL
=
0b0000110 (ACMP0)
0b000
SOURCESEL
=
0b0000111 (ACMP1)
0b000
SOURCESEL
=
0b0001000 (ADC0)
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
Description
SOURCESEL =
0b0010000
(USART0)
0b000
USART0IRTX
USART 0 IRDA out USART0IRTX
0b001
USART0TXC
USART 0 TX complete USART0TXC
0b010
USART0RXDATAV
USART 0 RX Data Valid USART0RXDATAV
0b011
USART0RTS
USART 0 RTS USART0RTS
0b101
USART0TX
USART 0 TX USART0TX
0b110
USART0CS
USART 0 CS USART0CS
0b001
USART1TXC
USART 1 TX complete USART1TXC
0b010
USART1RXDATAV
USART 1 RX Data Valid USART1RXDATAV
0b011
USART1RTS
USART 0 RTS USART1RTS
0b101
USART1TX
USART 1 TX USART1TX
0b110
USART1CS
USART 1 CS USART1CS
0b000
TIMER0UF
Timer 0 Underflow TIMER0UF
0b001
TIMER0OF
Timer 0 Overflow TIMER0OF
0b010
TIMER0CC0
Timer 0 Compare/Capture 0 TIMER0CC0
0b011
TIMER0CC1
Timer 0 Compare/Capture 1 TIMER0CC1
0b100
TIMER0CC2
Timer 0 Compare/Capture 2 TIMER0CC2
0b000
TIMER1UF
Timer 1 Underflow TIMER1UF
0b001
TIMER1OF
Timer 1 Overflow TIMER1OF
0b010
TIMER1CC0
Timer 1 Compare/Capture 0 TIMER1CC0
0b011
TIMER1CC1
Timer 1 Compare/Capture 1 TIMER1CC1
0b100
TIMER1CC2
Timer 1 Compare/Capture 2 TIMER1CC2
0b101
TIMER1CC3
Timer 1 Compare/Capture 3 TIMER1CC3
0b001
RTCCCCV0
RTCC Compare 0 RTCCCCV0 (Asynchronous)
0b010
RTCCCCV1
RTCC Compare 1 RTCCCCV1 (Asynchronous)
0b011
RTCCCCV2
RTCC Compare 2 RTCCCCV2 (Asynchronous)
0b000
GPIOPIN0
GPIO pin 0 GPIOPIN0 (Asynchronous)
0b001
GPIOPIN1
GPIO pin 1 GPIOPIN1 (Asynchronous)
SOURCESEL =
0b0010001
(USART1)
SOURCESEL
=
0b0011100 (TIMER0)
SOURCESEL
=
0b0011101 (TIMER1)
SOURCESEL
=
0b0101001 (RTCC)
SOURCESEL
=
0b0110000 (GPIO)
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PRS - Peripheral Reflex System
Bit
Name
Reset
Access
Description
0b010
GPIOPIN2
GPIO pin 2 GPIOPIN2 (Asynchronous)
0b011
GPIOPIN3
GPIO pin 3 GPIOPIN3 (Asynchronous)
0b100
GPIOPIN4
GPIO pin 4 GPIOPIN4 (Asynchronous)
0b101
GPIOPIN5
GPIO pin 5 GPIOPIN5 (Asynchronous)
0b110
GPIOPIN6
GPIO pin 6 GPIOPIN6 (Asynchronous)
0b111
GPIOPIN7
GPIO pin 7 GPIOPIN7 (Asynchronous)
0b000
GPIOPIN8
GPIO pin 8 GPIOPIN8 (Asynchronous)
0b001
GPIOPIN9
GPIO pin 9 GPIOPIN9 (Asynchronous)
0b010
GPIOPIN10
GPIO pin 10 GPIOPIN10 (Asynchronous)
0b011
GPIOPIN11
GPIO pin 11 GPIOPIN11 (Asynchronous)
0b100
GPIOPIN12
GPIO pin 12 GPIOPIN12 (Asynchronous)
0b101
GPIOPIN13
GPIO pin 13 GPIOPIN13 (Asynchronous)
0b110
GPIOPIN14
GPIO pin 14 GPIOPIN14 (Asynchronous)
0b111
GPIOPIN15
GPIO pin 15 GPIOPIN15 (Asynchronous)
0b000
LETIMER0CH0
LETIMER CH0 Out LETIMER0CH0 (Asynchronous)
0b001
LETIMER0CH1
LETIMER CH1 Out LETIMER0CH1 (Asynchronous)
0b000
PCNT0TCC
Triggered compare match PCNT0TCC (Asynchronous)
0b001
PCNT0UFOF
Counter overflow or underflow PCNT0UFOF (Asynchronous)
0b010
PCNT0DIR
Counter direction PCNT0DIR (Asynchronous)
CRYOTIMERPERIOD
CRYOTIMER Output CRYOTIMERPERIOD (Asynchronous)
0b000
CMUCLKOUT0
Clock Output 0 CMUCLKOUT0 (Asynchronous)
0b001
CMUCLKOUT1
Clock Output 1 CMUCLKOUT1 (Asynchronous)
SOURCESEL
=
0b0110001 (GPIO)
SOURCESEL
=
0b0110100 (LETIMER0)
SOURCESEL
=
0b0110110 (PCNT0)
SOURCESEL
=
0b0111100 (CRYOTIMER)
0b000
SOURCESEL =
0b0111101 (CMU)
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PCNT - Pulse Counter
14. PCNT - Pulse Counter
Quick Facts
What?
0 1 2 3
4
The Pulse Counter (PCNT) decodes incoming pulses. The module has a quadrature mode which may
be used to decode the speed and direction of a mechanical shaft. PCNT can operate in EM0 ActiveEM3 Stop.
Reload value
0
Interrupt
Quadrature code
Why?
The PCNT generates an interrupt after a specific
number of pulses (or rotations), eliminating the need
for timing- or I/O interrupts and CPU processing to
measure pulse widths, etc.
How?
PCNT uses the LFACLK or may be externally
clocked from a pin. The module incorporates an 16bit up/down-counter to keep track of incoming pulses
or rotations.
14.1 Introduction
The Pulse Counter (PCNT) can be used for counting incoming pulses on a single input or to decode quadrature encoded inputs. It can
run from the internal LFACLK (EM0 Active-EM2 DeepSleep) while counting pulses on the PCNTn_S0IN pin or using this pin as an external clock source (EM0 Active-EM3 Stop) that runs both the PCNT counter and register access.
14.2 Features
•
•
•
•
•
•
•
•
•
•
•
16-bit counter with reload register
Auxiliary counter for counting a single direction
Single input oversampling up/down counter mode (EM0 Active-EM2 DeepSleep)
Externally clocked single input pulse up/down counter mode (EM0 Active-EM3 Stop)
Quadrature decoder modes
• Externally clocked quadrature decoder 1X mode (EM0 Active-EM3 Stop)
• Oversampling quadrature decoder 1X, 2X and 4X modes. (EM0 Active-EM2 DeepSleep)
Interrupt on counter underflow and overflow
Interrupt when a direction change is detected (quadrature decoder mode only)
Optional pulse width filter
Optional input inversion/edge detect select
PRS S0IN and S1IN input
Asynchronously triggered compare and clear
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PCNT - Pulse Counter
14.3 Functional Description
An overview of the PCNT module is shown in Figure 14.1 PCNT Overview on page 352.
CMU (conceptual)
LFACLK
Clock
switch
Triggered compare
and clear control
PCNTnCLK
0
1
TCCMODE != DISABLED
CLKPCNT
S0PRS Input
PC
OVR_SINGLE
Pulse Width
Filter
EXTCLK_SINGLE
Count
Enable
Analog de-glitch filter
IN
S1
_
Tn
N
PC
IN
S0
_
Tn
N
Edge
detector
Inverter &
Input logic
AUXCNT
1
Inverter &
Input logic
OverSampling
Clk
Quad decoder
Pulse Width
Filter
Peripheral bus
EXTCLK_QUAD
ExtClk
Quad decoder
OVR_QUADDEC
TOP
TOPB
Count
Enable
CNT
FILT
S1PRS Input
Figure 14.1 PCNT Overview
14.3.1 Pulse Counter Modes
The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked single input counter mode (EXTCLKSINGLE), externally clocked quadrature decoder mode (EXTCLKQUAD) and oversampling quadrature decoder modes(OVSQUAD1X, OVSQUAD2X and OVSQUAD4X). The following sections describe operation of each of these modes and how they are enabled. Input timing constraints are described in 14.3.6 Clock Sources and 14.3.7 Input Filter.
14.3.1.1 Single Input Oversampling Mode
This mode is enabled by writing OVSSINGLE to the MODE field in the PCNTn_CTRL register and disabled by writing DISABLE to the
same field. LFACLK is configured from the registers in the Clock Management Unit (CMU), 10. CMU - Clock Management Unit .
The optional pulse width filter is enabled by setting the FILT bit in the PCNTn_CTRL register. Additionally, the PCNTn_S0IN input may
be inverted, so that falling edges are counted, by setting the EDGE bit in the PCNTn_CTRL register.
If S1CDIR is cleared, PCNTn_S0IN is the only observed input in this mode. The PCNTn_S0IN input is sampled by the LFACLK and the
number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT. The counter may be configured to count
down by setting the CNTDIR bit in PCNTn_CTRL. Default is to count up.
The counting direction can also be controlled externally in this mode by setting S1CDIR in PCNTn_CTRL. This will make the input value
on PCNTn_S1IN decide the direction counted on a PCNTn_S0IN edge. If PCNTn_S1IN is high, the count is done according to CNTDIR
in PCNTn_CTRL. If low, the count direction is opposite.
14.3.1.2 Externally Clocked Single Input Counter Mode
This mode is enabled by writing EXTCLKSINGLE to the MODE field in the PCNTn_CTRL register and disabled by writing DISABLE to
the same field. The external pin clock source must be configured from the registers in the CMU (10. CMU - Clock Management Unit ).
Positive edges on PCNTn_S0IN are used to clock the counter. Similar to the oversampled mode, PCNTn_S1IN is used to determine
the count direction if S1CDIR in PCNTn_CTRL is set. If not, CNTDIR in PCNTn_CTRL solely defines count direction. As the LFACLK is
not used in this mode, the PCNT module can operate in EM3 Stop.
The digital pulse width filter is not available in this mode. The analog de-glitch filter in the GPIO pads is capable of removing some
unwanted noise. However, this mode may be susceptible to spikes and unintended pulses from devices such as mechanical switches,
and is therefore most suited to take input from electronic sensors etc. that generate single wire pulses.
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PCNT - Pulse Counter
14.3.1.3 Quadrature decoder modes
Two different types of quadrature decoding is supported in pulse counter, the externally clocked (Asynchronous) quadrature decoding
and the oversampling(Synchronous) quardrature decoding. The externally clocked mode supports 1X quadrature decoding whereas the
oversampling mode supports 1X, 2X and 4X quadrature decoding. These modes are described in detail in 14.3.1.4 Externally Clocked
Quadrature Decoder Mode and 14.3.1.5 Oversampling Quadrature Decoder Mode .
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PCNT - Pulse Counter
14.3.1.4 Externally Clocked Quadrature Decoder Mode
This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field.
The external pin clock source must be configured from the registers in the CMU, (10. CMU - Clock Management Unit ).
Both edges on PCNTn_S0IN pin are used to sample PCNTn_S1IN pin, in order to decode the quadrature code. Consequently, this
mode does not depend on the internal LFACLK and may be operated in EM3 Stop. A quadrature coded signal contains information
about the relative speed and direction of a rotating shaft as illustrated by Figure 14.2 PCNT Quadrature Coding on page 354, hence
the direction of the counter register PCNTn_CNT is controlled automatically.
Clockwise direction
Reset
1 cycle/sector, 4 states
00
10
11
01
X
X
PCNTn_S0IN
PCNTn_S1IN
PCNTn_CNT
Counter clockwise
direction
0
0
1
2
PCNTn_TOP
PCNTn_TOP-1
1 cycle/sector, 4 states
00
01
11
10
X
X
PCNTn_S0IN
PCNTn_S1IN
PCNTn_CNT
0
0
X = sensor position
Figure 14.2 PCNT Quadrature Coding
If PCNTn_S0IN leads PCNTn_S1IN in phase, the direction is clockwise, and if it lags in phase the direction is counter-clockwise. Default behavior is illustrated by Figure 14.2 PCNT Quadrature Coding on page 354.
The counter direction may be read from the DIR bit in the PCNTn_STATUS register. Additionally, the DIRCNG interrupt in the
PCNTn_IF register is generated when a direction change is detected. When a change is detected, the DIR bit in the PCNTn_STATUS
register must be read to determine the current new direction.
Note:
The sector disc illustrated in the figure may be finer grained in some systems. Typically, they may generate 2-4 PCNTn_S0IN wave
periods per 360° rotation.
The direction of the quadrature code and control of the counter is generated by the simple binary function outlined by Table 14.1 PCNT
QUAD Mode Counter Control Function on page 355. Note that this function also filters some invalid inputs that may occur when the
shaft changes direction or temporarily toggles direction.
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PCNT - Pulse Counter
Table 14.1. PCNT QUAD Mode Counter Control Function
Inputs
Control/Status
S1IN posedge
S1IN negedge
Count Enable
CNTDIR status bit
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
Note:
PCNTn_S1IN is sampled on both edges of PCNTn_S0IN.
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PCNT - Pulse Counter
14.3.1.5 Oversampling Quadrature Decoder Mode
There are three Oversampling Quadrature Decoder Modes supported, 1X , 2X and 4X.These modes are enabled by writing OVSQUAD1X, OVSQUAD2X and OVSQUAD4X respectively to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the
same field. The clock source must be configured to LFACLK for these modes from the registers in the CMU, (10. CMU - Clock Management Unit ).
The optional pulse width filter is enabled by setting the FILT bit in the PCNTn_CTRL register. The filter applies to both inputs
PCNTn_S0IN and PCNTn_S1IN. The filter length is configured by FILTLEN in PCNTn_OVSCFG register.
Based on the modes selected, the decoder updates the counter on different events. In the OVSQUAD1X mode, the counter is updated
on the rising edge of the PCNTn_S0IN input when counting up, and on the negedge of the PCNTn_S0IN input when counting down. In
the OVSQUAD2X mode, the counter is updated on both edges of PCNTn_S0IN input. In the OVSQUAD4X mode the counter is updated on both edges of both inputs PCNTn_S0IN and PCNTn_S1IN. Table 14.2 PCNT OVSQUAD 1X, 2X and 4X Mode Counter Control
Function on page 356 outlines the increment or decrement of the counter based on the Quadrature Mode selected.
Note:
The decoding behavior of OVSQUAD1X mode is slightly different compared to EXTCLKQUAD mode(also 1X mode). In the EXTCLKQUAD mode, the counter is updated only on the posedge of S0IN input. However, in the OVSQUAD1X mode, the counter is updated on the posedge of S0IN when counting up and on the negedge of S0IN when counting down.
Table 14.2. PCNT OVSQUAD 1X, 2X and 4X Mode Counter Control Function
Direction
Clockwise
Counter Clockwise
Previous State
Next State
OVSQUAD MODE
S1IN
S0IN
S1IN
S0IN
1X
2X
4X
0
0
0
1
+1
+1
+1
0
1
1
1
1
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
1
0
+1
+1
+1
+1
-1
-1
-1
-1
-1
-1
-1
Figure 14.3 PCNT State transitions for different Oversampling Quadrature Decoder Modes on page 357 illustrates the different states
of the quadrature input and the state transitions that updates the counter for the different modes. Each cycle of the input states results
in 1 update, 2 updates and 4 updates of the counter for OVSQUAD1X, OVSQUAD2X and OVSQUAD4X modes respectively.
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PCNT - Pulse Counter
Relationship between inputs and its state
STATE
S1IN
S0IN
S0
0
0
S1
0
1
S2
1
1
S3
1
0
S0
‘b00
S0
‘b00
+1
+1
-1
-1
-1
+1
-1
S1
‘b01
-1
-1
+1
+1
S2
‘b11
+1
S2
‘b11
OVSQUAD2X mode
Transitions between States S0
and S1 and between S3 and S2
updates the counter
OVSQUAD1X mode
Transitions between States S0
and S1 updates the counter
-1
S3
‘b10
S1
‘b01
+1
+1
S2
‘b11
-1
-1
+1
-1
S3
‘b10
S1
‘b01
+1
+1
-1
-1
S3
‘b10
S0
‘b00
+1
OVSQUAD4X mode
All state transitions updates the
counter
Figure 14.3 PCNT State transitions for different Oversampling Quadrature Decoder Modes
The counter direction can be read from the DIR bit in PCNTn_STATUS register. Additionally, the DIRCNG interrupt in the PCNTn_IF is
generated when the direction change is detected. When a change is detected, the DIR bit in the PCNTn_STATUS register must be read
to determine the new direction.
In the oversampling quadrature decoder modes, the maximum input toggle frequency supported is 8KHz. For frequencies of 8KHz and
higher, incorrect decoding occurs. The different decoding modes and the counter updates are futher illustrated by Figure 14.4 PCNT
Oversampling Quadrature Decoder 1X mode on page 357, Figure 14.5 PCNT Oversampling Quadrature Decoder 2X mode on page
358 and Figure 14.6 PCNT Oversampling Quadrature Decoder 4X mode on page 358.
Period > 125 us
S0IN
S1IN
CNT
3
4
5
6
6
5
4
3
Figure 14.4 PCNT Oversampling Quadrature Decoder 1X mode
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PCNT - Pulse Counter
Period > 125 us
S0IN
S1IN
CNT
3
4
5
6
8
7
8
7
6
5
4
3
2
Figure 14.5 PCNT Oversampling Quadrature Decoder 2X mode
Period > 125 us
S0IN
S1IN
CNT
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
Figure 14.6 PCNT Oversampling Quadrature Decoder 4X mode
The above modes, by default are prone to flutter effects in the inputs PCNTn_S0IN and PCNTn_S1IN. When this occurs, the counter
changes directions rapidly causing DIRCNG interrupts and unnecessarily waking the core. To prevent this, set FLUTTERRM in
PCNTn_OVSCFG register. When enabled, flutter is removed, thus preventing unnecessary wakeup of the core. The flutter removal logic works by preventing update of the counter value if the wheel keeps changing direction as a result of flutter. The counter is only updated if the current and previous state transition of the rotation are in the same direction. These state transitions are quadrature decoder
mode specific. The highlighted state trasitions in Figure 14.3 PCNT State transitions for different Oversampling Quadrature Decoder
Modes on page 357 are the ones considered for the different quadrature decoder modes. Figure 14.7 PCNT Oversampling Quadrature
Decoder with Flutter Removal on page 358 shows how the counter is updated for the different quadrature decoder modes with flutter
removal FLUTTERRM enabled in PCNTn_OVSCFG.
S0IN Flutter
S1IN Flutter
S0IN
S1IN
STATES
S0
S1
CNTQUAD4X
0
1
CNTQUAD2X
0
1
CNTQUAD1X
0
1
S2
2
S3
3
S0
S1
S2
S3
S0
4
5
6
7
8
2
3
2
4
S1
S0
9
S1
S0
S3
8
5
3
S2
S1
S0
7
6
5
4
S3
S0
S3
S0
4
3
2
S1
5
S2
6
S3
7
4
S0
8
S1
9
5
3
Figure 14.7 PCNT Oversampling Quadrature Decoder with Flutter Removal
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PCNT - Pulse Counter
14.3.2 Hysteresis
By default the pulse counter wraps to 0 when passing the configured top value, and wraps to the top value when counting down from 0.
On these events, a system will likely want to wake up to store and track the overflow count. This is fine if the pulse counter is tracking a
monotonic value or a value that does not change directions frequently. If you have the latter however, and the counter changes
directions around the overflow/underflow point, the system will have to wake up a lot to keep track of the rotations, causing high current
consumptions
To solve this, the pulse counter has a way of introducing hysteresis to the counter. When HYST in PCNTn_CTRL is set, the pulse counter will always wrap to TOP/2 on underflows and overflows. This takes the counter away from the area where it might overflow or underflow, removing the problem. Figure 14.8 PCNT Hysteresis behavior of Counter on page 359 illustrates the hysteresis behavior.
COUNTER
MAX VAL
TOP
Overflow wrap
underflow continue cnt
Overflow continue cnt
TOP/2
Overflow continue cnt
underflow continue cnt
Underflow warp
MIN VAL
Figure 14.8 PCNT Hysteresis behavior of Counter
Given a starting value of 0 for the counter, the absolute count value when hysteresis is enabled can be calculated with the equations
Figure 14.8 Absolute position with hysteresis and even TOP value on page 359 or Figure 14.9 Absolute position with hysteresis and
odd TOP value on page 359, depending on whether the TOP value is even or odd.
CNTabs = CNT - UFCNT x (TOP/2+1) + OFCNT x (TOP/2+1)
Equation: Absolute position with hysteresis and even TOP value
CNTabs = CNT - UFCNT x (TOP/2+1) + OFCNT x (TOP/2+2)
Equation: Absolute position with hysteresis and odd TOP value
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PCNT - Pulse Counter
14.3.3 Auxiliary counter
To be able to keep explicit track of counting in one direction in addition to the regular counter which counts both up and down, the
auxiliary counter can be used. The pulse counter can for instance be configured to keep track of the absolute rotation of the wheel, and
at the same time the auxiliary counter can keep track of how much the wheel has reversed.
The auxiliary counter is enabled by configuring AUXCNTEV in PCNTn_CTRL. It will always count up, but it can be configured whether it
should count up on up-events, down-events or both, keeping track of rotation either way or general movement. The value of the auxiliary counter can be read from the PCNTn_AUXCNT register.
Overflows on the auxiliary counter happen when the auxiliary counter passes the top value of the pulse counter, configured in
PCNTn_TOP. In that event, the AUXOF interrupt flag is set, and the auxiliary counter wraps to 0.
As the auxiliary counter, the main counter can be configured to count only on certain events. This is done through CNTEV in
PCNTn_CTRL, and it is possible like for the auxiliary counter, to make the main counter count on only up and down events. The difference between the counters is that where the auxiliary counter will only count up, the main counter will count up or down depending on
the direction of the count event.
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PCNT - Pulse Counter
14.3.4 Triggered compare and clear
The pulse counter features triggered compare and clear. When enabled, a configurable trigger will induce a comparison between the
main counter, PCNT_CNT, and the top value, PCNT_TOP. After the comparison, the counter is cleared. The trigger for a compare and
clear event is configured in the TCCMODE bit-field in PCNT_CTRL. There are two options, LFA and PRS. If LFA is selected, the pulse
counter will be compared with the top value, and cleared every 2N LFA clock cycle. N is configured in TCCPRESC in PCNT_CTRL. If a
PRS trigger is selected, the active PRS channel is configured in TCCPRSSEL in PCNT_CTRL. The PRS input can be inverted by setting TCCPRSPOL, triggering the compare and clear on the negative edge of the PRS input. The PRS input can also be used as a gate
for the pulse counter clock. This is enabled by setting PRSGATEEN in PCNT_CTRL.
Note:
When PRSGATEEN is set, the clock to the entire pulse counter will be gated by the PRS input, meaning that register writes will not take
effect while the gated clock is inactive.
Comparison with PCNT_TOP can be performed in three ways; range, greater than or equal, and less than or equal. TCCCOMP in
PCNT_CTRL configures comparison mode. Upon a compare match, the TCC interrupt is set, and the PRS output from the pulse counter is set. The PRS output will remain set until the next compare and clear event. Triggered compare and clear is intended for use when
the pulse counter is configured to count up. In this mode, PCNT_CNT will not wrap to 0 when hitting PCNT_TOP, it will keep counting.
In addition, the counter will not overflow, it will rather stop counting, just setting the overflow interrupt flag.
Figure 14.11 PCNT Triggered compare and clear on page 361 shows an overview of the control circuitry for triggered compare and
clear. The control circuitry includes two positive edge detectors (PED) and glitch filters, used to generate clocks for the pulse counter.
The two clock outputs are mutually exclusive: If both edge detectors receive a pulse at the same time, the output pulse from one of
them will be postponed until the other edge detectors output pulse has completed.
DISABLED
CLKPCNT
Triggered compare and clear control
PCNTnCLK
PED and gltich
filter
LFA or PRS
clear
CNT
>=TOP[7:0]
&&
<= TOP[15:8]
PRSGATEEN
TCCMODE
<=TOP
LTOE
GTOE
RANGE
TCCCOMP
PRS in
PRS
TCCPRSPOL
LFACLK
>=TOP
PED and gltich
filter
Prescaler
Compare match
TCC PRS out
TCC interrupt
LFA
TCCMODE
TCCPRESC
Figure 14.11 PCNT Triggered compare and clear
Note:
TCCMODE, TCCPRESC, PRSGATEEN, TCCPRSPOL, and TCCPRSSEL in PCNT_CTRL should only be altered when
PCNT_CTRL_RSTEN is set.
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PCNT - Pulse Counter
14.3.5 Register Access
The counter-clock domain may be clocked externally. To update the counter-clock domain registers from software in this mode, 2-3
clock pulses on the external clock are needed to synchronize accesses to the externally clocked domain. Clock source switching is
controlled from the registers in the CMU (10. CMU - Clock Management Unit ).
When the RSTEN bit in the PCNTn_CTRL register is set to 1, the PCNT clock domain is asynchronously held in reset. The reset is
synchronously released two PCNT clock edges after the RSTEN bit in the PCNTn_CTRL register is cleared by software. This asynchronous reset restores the reset values in PCNTn_TOP, PCNTn_CNT and other control registers in the PCNT clock domain.
CNTRSTEN works in a similar manner as RSTEN, but only resetting the counter, CNT. Note that the counter is also reset by RSTEN.
AUXCNTRSTEN works in a similar manner as RSTEN, but only resetting the auxiliary counter, AUXCNT. Note that the auxiliary counter
is also reset by RSTEN.
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 4.3 Access to Low Energy Peripherals (Asynchronous Registers) for a description on how to perform register accesses to Low Energy Peripherals.
Note:
PCNTn_TOP and PCNTn_CNT are read-only registers. When writing to PCNTn_TOPB, make sure that the counter value,
PCNTn_CNT, can not exceed the value written to PCNTn_TOPB within two clock cycles.
14.3.6 Clock Sources
The 32 kHz LFACLK is one of two possible clock sources. The clock select register is described in 10. CMU - Clock Management Unit .
The default clock source is the LFACLK.
This PCNT module may also use PCNTn_S0IN as an external clock to clock the counter (EXTCLKSINGLE mode) and to sample
PCNTn_S1IN (EXTCLKQUAD mode). Setup, hold and max frequency constraints for PCNTn_S0IN and PCNTn_S1IN for these modes
are specified in the device datasheet.
To use this module, the LE interface clock must be enabled in CMU_HFBUSCLKEN0, in addition to the module clock in
CMU_PCNTCTRL.
Note:
PCNT Clock Domain Reset, RSTEN, should be set when changing clock source for PCNT. If changing to an external clock source, the
clock pin has to be enabled as input prior to de-asserting RSTEN. Changing clock source without asserting RSTEN results in undefined
behaviour.
14.3.7 Input Filter
An optional pulse width filter is available in OVSSINGLE and OVSQUAD modes, when LFACLK is selected as a clock source for the
Pulse Counter in CMU 10. CMU - Clock Management Unit . The filter is enabled by writing 1 to the FILT bit in the PCNTn_CTRL register. When enabled, the high and low periods of PCNTn_S0IN and PCNTn_S1IN must be stable for a programmable number of consecutive clock cycles before the edge is passed to the edge detector. The filter length should be programmed in FILTLEN field of the
PCNTn_OVSCFG register.
The filter length is given by Figure 14.12 PCNT Input Filter length Equation on page 362:
Filter length = (FILTLEN + 5) LFACLK cycles
Equation: PCNT Input Filter length Equation
The maximum filter length configured is 260 LFACLK cycles.
In EXTCLKSINGLE and EXTCLKQUAD mode, there is no digital pulse width filter available.
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PCNT - Pulse Counter
14.3.8 Edge Polarity
The edge polarity can be set by configuring the EDGE bit in the PCNTn_CTRL register. When this bit is cleared, the pulse counter
counts positive edges of PCNTn_S0IN input and when set counts negative edges in OVSSINGLE mode. Also, in the OVSSINGLE and
EXTCLKSINGLE modes, when this bit is set, PCNTn_S1IN input is inverted In OVSQUAD 1X-4X modes this bit inverts both inputs.
Note:
The EDGE bit in PCNTn_CTRL has no effect in EXTCLKQUAD mode.
14.3.9 PRS and S0IN,S1IN Inputs
It is possible to receive input from PRS on both S0IN and S1IN by setting S0PRSEN or S1PRSEN in PCNTn_INPUT. The PRS channel
used can be selected using S0PRSSEL and S1PRSSEL in PCNTn_INPUT.
In the Oversampling quadrature decoder modes, the input frequency should be less than 8KHz to ensure correct functionality.
PCNT module generates three PRS outputs the TCC PRS output, the CNT OF/UF PRS output and the CNT DIR PRS output. The TCC
PRS is generated on compare match of TCC event. The CNT OF/UF combined PRS is generated when the counter overflow or underflows. The CNT DIR PRS is a level PRS and indicates the current direction of count of counter CNT
Note:
S0PRSEN,S1PRSEN,S0PRSSEL,S1PRSSEL should only be altered when PCNT_CTRL_RSTEN is set.
14.3.10 Interrupts
The interrupt generated by PCNT uses the PCNTn_INT interrupt vector. Software must read the PCNTn_IF register to determine which
module interrupt that generated the vector invocation.
14.3.10.1 Underflow and Overflow Interrupts
The underflow interrupt flag (UF) is set when the counter counts down from 0. I.e. when the value of the counter is 0 and a new pulse is
received. The PCNTn_CNT register is loaded with the PCNTn_TOP value after this event.
The overflow interrupt flag (OF) is set when the counter counts up from the PCNTn_TOP (reload) value. I.e. if PCNTn_CNT =
PCNTn_TOP and a new pulse is received. The PCNTn_CNT register is loaded with the value 0 after this event.
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PCNT - Pulse Counter
14.3.10.2 Direction Change Interrupt
The PCNTn_PCNT module sets the DIRCNG interrupt flag (PCNTn_IF register) for EXTCLKQUAD and OVSQUAD1X-4X modes when
the direction of the quadrature code changes. The behavior of this interrupt in the EXTCLKQUAD mode is illustrated by Figure
14.13 PCNT Direction Change Interrupt (DIRCNG) Generation on page 364.
X
X
Standard async
handshake
interface
Invalid pulse generated when
the shaft changes direction
PCNTn_S0IN
PCNTn_S1IN
Interrupt
PCNTn_CNT
n
n+1
n+2
n+3
n+2
Delay from the shaft physically
changed direction until the
counter direction is changed
and the interrupt is generated
Figure 14.13 PCNT Direction Change Interrupt (DIRCNG) Generation
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PCNT - Pulse Counter
14.3.11 Cascading Pulse Counters
When two or more Pulse Counters are available, it is possible to cascade them. For example two 16-bit Pulse Counters can be cascaded to form a 32-bit pulse counter. This can be done with the help of the CNT UF/OF PRS and CNT DIR PRS ouputs. The figure Figure
14.14 PCNT Cascading to two 16-bit PCNT to form a 32-bit PCNT on page 365 illustrates this structure.
PCNT1(MSB)
PCNT0(LSB)
[31:16]
EXTCLK SINLGE MODE
[15:0
PRS CHANNELS
OVSSINGLE MODE /
EXTCLKSINGLE MODE /
EXTCLKQUAD MODE /
OVSQUAD1X /
OVSQUAD2X /
OVSQUAD4X
prs_ufof
prs_dir
PRS
Combinational
Matrix
PRS
enable
and
input
select
S0IN
PCNT Core
S1IN
Figure 14.14 PCNT Cascading to two 16-bit PCNT to form a 32-bit PCNT
For cascading of Pulse Counters to work, the PCNT1 according to the figure Figure 14.14 PCNT Cascading to two 16-bit PCNT to form
a 32-bit PCNT on page 365 should be programmed in EXTCLKSINGLE mode and its S0IN and S1IN inputs should be configured to
prs_ufof and prs_dir of PCNT0 respectively. In addition to this, a strict programming sequence needs to be followed to ensure both
PCNTs are in sync with each other.
• Configure PCNT0 registers. eg. PCNT0_INPUT,PCNT0_CTRL,PCNT0_OVSCFG etc.
• Wait for PCNT0_SYCNBUSY to be cleared to ensure the registers are synchronized to the asynchronous clock domain.
• Hold PCNT0 in sw reset by setting PCNT0_CTRL_RSTEN.
• Configure PCNT1_CTRL to EXTCLKSINLE mode with S1CDIR and CNTDIR bit set. Configure INPUT to accept "prs_ufof" and
"prs_dir" of PCNT0 on S0IN and S1IN respectively.
• Wait for PCNTn_SYCNBUSY to be cleared to ensure the registers are synchronized to the asynchronous clock domain. Use three
PRS_SWPULSE on the S0IN prs channel to ensure this synchronization.
• Hold PCNT1 in sw reset by setting PCNT1_CTRL_RSTEN.
• Clear PCNT1_CTRL_RSTEN and synchronize it by asserting two PRS_SWPULSE on the S0IN input.
• Finally clear PCNT0_CTRL_RSTEN and start counting.
Note:
When PCNTn_CTRL_RSTEN bit is set, TOP value in the Pulse Counter gets cleared. Therefore, in order to update TOP value while
PCNTn_CTRL_RSTEN is set, assert PCNTn_CTRL_TOPBHFEN. This will update TOP value with TOPB value even without having to
syncrhonize the TOPB value. This only works if PCNTn_CTRL_TOPBHFEN and TOPB is configured while PCNTn_CTRL_RSTEN is
set.
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PCNT - Pulse Counter
14.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
PCNTn_CTRL
RW
Control Register
0x004
PCNTn_CMD
W1
Command Register
0x008
PCNTn_STATUS
R
Status Register
0x00C
PCNTn_CNT
R
Counter Value Register
0x010
PCNTn_TOP
R
Top Value Register
0x014
PCNTn_TOPB
RW
Top Value Buffer Register
0x018
PCNTn_IF
R
Interrupt Flag Register
0x01C
PCNTn_IFS
W1
Interrupt Flag Set Register
0x020
PCNTn_IFC
(R)W1
Interrupt Flag Clear Register
0x024
PCNTn_IEN
RW
Interrupt Enable Register
0x02C
PCNTn_ROUTELOC0
RW
I/O Routing Location Register
0x040
PCNTn_FREEZE
RW
Freeze Register
0x044
PCNTn_SYNCBUSY
R
Synchronization Busy Register
0x064
PCNTn_AUXCNT
R
Auxiliary Counter Value Register
0x068
PCNTn_INPUT
RW
PCNT Input Register
0x06C
PCNTn_OVSCFG
RW
Oversampling Config Register
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PCNT - Pulse Counter
14.5 Register Description
14.5.1 PCNTn_CTRL - Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
0
RW 0x0 1
MODE
2
3
0
RW
FILT
4
0
RW
RSTEN
5
0
RW
CNTRSTEN
6
0
AUXCNTRSTEN RW
7
0
RW
DEBUGHALT
8
0
RW
HYST
9
0
RW
S1CDIR
10
11
RW 0x0
CNTEV
12
13
RW 0x0
AUXCNTEV
14
0
RW
15
CNTDIR
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0
RW
EDGE
16
17
RW 0x0
TCCMODE
18
19
20
RW 0x0
TCCPRESC
21
22
23
RW 0x0
TCCCOMP
24
0
RW
PRSGATEEN
25
0
RW
26
27
28
29
30
TCCPRSPOL
0
RW 0x0
Name
TCCPRSSEL
Access
RW
Reset
TOPBHFSEL
0x000
Bit Position
31
Offset
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EFM32JG1 Reference Manual
PCNT - Pulse Counter
Bit
Name
Reset
Access
Description
31
TOPBHFSEL
0
RW
TOPB High frequency value select
Apply High frequency value of TOPB to TOP register. Should be used only when RSTEN in PCNTn_CTRL is set
30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:26
TCCPRSSEL
0x0
RW
TCC PRS Channel Select
Select PRS channel used as compare and clear trigger.
25
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected.
1
PRSCH1
PRS Channel 1 selected.
2
PRSCH2
PRS Channel 2 selected.
3
PRSCH3
PRS Channel 3 selected.
4
PRSCH4
PRS Channel 4 selected.
5
PRSCH5
PRS Channel 5 selected.
6
PRSCH6
PRS Channel 6 selected.
7
PRSCH7
PRS Channel 7 selected.
8
PRSCH8
PRS Channel 8 selected.
9
PRSCH9
PRS Channel 9 selected.
10
PRSCH10
PRS Channel 10 selected.
11
PRSCH11
PRS Channel 11 selected.
TCCPRSPOL
0
RW
TCC PRS polarity select
Configure which edge on the PRS input is used to trigger a compare and clear event
24
Value
Mode
Description
0
RISING
Rising edge on PRS trigger compare and clear event.
1
FALLING
Falling edge on PRS trigger compare and clear event.
PRSGATEEN
0
RW
PRS gate enable
When set, the clock input to the pulse counter will be gated when the selected PRS input is the inverse of TCCPRSPOL.
23:22
TCCCOMP
0x0
RW
Triggered compare and clear compare mode
Selects the mode for comparison upon a compare and clear event.
Value
Mode
Description
0
LTOE
Compare match if PCNT_CNT is less than, or equal to PCNT_TOP.
1
GTOE
Compare match if PCNT_CNT is greater than or equal to PCNT_TOP.
2
RANGE
Compare match if PCNT_CNT is less than, or equal to
PCNT_TOP[15:8]], and greater than, or equal to PCNT_TOP[7:0].
21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
20:19
TCCPRESC
0x0
RW
Set the LFA prescaler for triggered compare and clear
Selects the prescaler value for LFA compare and clear events
Value
Mode
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PCNT - Pulse Counter
Bit
Name
Reset
Access
0
DIV1
Compare and clear event each LFA cycle.
1
DIV2
Compare and clear performed on every other LFA cycle.
2
DIV4
Compare and clear performed on every 4th LFA cycle.
3
DIV8
Compare and clear performed on every 8th LFA cycle.
18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
TCCMODE
0x0
RW
Description
Sets the mode for triggered compare and clear
Selects whether compare and clear should be triggered on each LFA clock, or from PRS
15
Value
Mode
Description
0
DISABLED
Triggered compare and clear not enabled.
1
LFA
Compare and clear performed on each (optionally prescaled) LFA clock
cycle.
2
PRS
Compare and clear performed on positive PRS edges.
EDGE
0
RW
Edge Select
Determines the polarity of the incoming edges. This bit should be written when PCNT is in DISABLE mode, otherwise the
behavior is unpredictable. This bit used only in OVSSINGLE, EXTCLKSINGLE and OVSQUAD1X-4X modes.
14
Value
Mode
Description
0
POS
Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE
mode. Does not invert PCNTn_S1IN input in OVSSINGLE and EXTCLKSINGLE modes
1
NEG
Negative edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode. Inverts the PCNTn_S1IN input in OVSSINGLE and EXTCLKSINGLE modes
CNTDIR
0
RW
Non-Quadrature Mode Counter Direction Control
The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EXTCLKQUAD mode as the direction is automatically detected.
13:12
Value
Mode
Description
0
UP
Up counter mode.
1
DOWN
Down counter mode.
AUXCNTEV
0x0
RW
Controls when the auxiliary counter counts
Selects whether the auxiliary counter responds to up-count events, down-count events or both
11:10
Value
Mode
Description
0
NONE
Never counts.
1
UP
Counts up on up-count events.
2
DOWN
Counts up on down-count events.
3
BOTH
Counts up on both up-count and down-count events.
CNTEV
0x0
RW
Controls when the counter counts
Selects whether the regular counter responds to up-count events, down-count events or both
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PCNT - Pulse Counter
Bit
9
Name
Reset
Access
Value
Mode
Description
0
BOTH
Counts up on up-count and down on down-count events.
1
UP
Only counts up on up-count events.
2
DOWN
Only counts down on down-count events.
3
NONE
Never counts.
S1CDIR
0
RW
Description
Count direction determined by S1
S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes. When S1 is high, the count direction is given by CNTDIR, and when S1 is low, the count direction is the opposite
8
HYST
0
RW
Enable Hysteresis
When hysteresis is enabled, the PCNT will always overflow and underflow to TOP/2.
7
DEBUGHALT
0
RW
Debug Mode Halt Enable
Set to halt the PCNT in debug mode only in OVSSINGLE and OVSQUAD modes. When in EXTCLKSINGLE or EXTCLKQUAD modes debughalt does not halt the Pulse Counter.
6
Value
Description
0
PCNT is running in debug mode.
1
PCNT is frozen in debug mode.
AUXCNTRSTEN
0
RW
Enable AUXCNT Reset
The auxiliary counter, AUXCNT, is asynchronously held in reset when this bit is set. The reset is synchronously released
two PCNT clock edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing
the bit without pending for SYNCBUSY bit.
5
CNTRSTEN
0
RW
Enable CNT Reset
The counter, CNT, is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock
edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit without
pending for SYNCBUSY bit. This action clears the counter to its reset value
4
RSTEN
0
RW
Enable PCNT Clock Domain Reset
The PCNT clock domain is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT
clock edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit
without pending for SYNCBUSY bit.
3
FILT
0
RW
Enable Digital Pulse Width Filter
The filter passes all high and low periods that are at least (FILTLEN+5) clock cycles wide. This filter is only available in
OVSSINGLE,OVSQUAD1X-4X modes.
2:0
MODE
0x0
RW
Mode Select
Selects the mode of operation. The corresponding clock source must be selected from the CMU.
Value
Mode
Description
0
DISABLE
The module is disabled.
1
OVSSINGLE
Single input LFACLK oversampling mode (available in EM0-EM2).
2
EXTCLKSINGLE
Externally clocked single input counter mode (available in EM0-EM3).
3
EXTCLKQUAD
Externally clocked quadrature decoder mode (available in EM0-EM3).
4
OVSQUAD1X
LFACLK oversampling quadrature decoder 1X mode (available in EM0EM2).
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PCNT - Pulse Counter
Bit
Name
Reset
Access
Description
5
OVSQUAD2X
LFACLK oversampling quadrature decoder 2X mode (available in EM0EM2).
6
OVSQUAD4X
LFACLK oversampling quadrature decoder 4X mode (available in EM0EM2).
14.5.2 PCNTn_CMD - Command Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
LTOPBIM W1 0
Name
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
LTOPBIM
0
W1
0
1
1
Access
W1 0
2
2
Reset
LCNTIM
3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Description
Load TOPB Immediately
This bit has no effect since TOPB is not buffered and it is loaded directly into TOP.
0
LCNTIM
0
W1
Load CNT Immediately
Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
14.5.3 PCNTn_STATUS - Status Register
0
Reset
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
DIR R
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
DIR
0
R
Description
Current Counter Direction
Current direction status of the counter. This bit is valid in EXTCLKQUAD mode only.
Value
Mode
Description
0
UP
Up counter mode (clockwise in EXTCLKQUAD mode with the NEDGE
bit in PCNTn_CTRL set to 0).
1
DOWN
Down counter mode.
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PCNT - Pulse Counter
14.5.4 PCNTn_CNT - Counter Value Register
3
2
1
0
3
2
1
0
4
5
6
7
8
0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Reset
CNT R
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
CNT
0x0000
R
Description
Counter Value
Gives read access to the counter.
14.5.5 PCNTn_TOP - Top Value Register
4
5
6
7
8
0x00FF
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Reset
TOP R
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
TOP
0x00FF
R
Description
Counter Top Value
When counting down, this value is reloaded into PCNTn_CNT when counting past 0. When counting up, 0 is written to the
PCNTn_CNT register when counting past this value.
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PCNT - Pulse Counter
14.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
0
1
2
3
4
5
6
7
8
TOPB RW 0x00FF
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x014
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
TOPB
0x00FF
RW
Description
Counter Top Buffer
Loaded automatically to TOP when written.
14.5.7 PCNTn_IF - Interrupt Flag Register
Access
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
OQSTERR
0
0
0
R
1
UF
31:6
0
2
R
Reset
R
3
OF
Name
0
R
DIRCNG
Bit
0
R
AUXOF
4
0
5
R
Name
TCC
Access
0
Reset
OQSTERR R
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Description
Oversampling Quadrature State Error Interrupt
Set in the Oversampling Quardrature Mode when incorrect state transition occurs
4
TCC
0
R
Triggered compare Interrupt Read Flag
R
Overflow Interrupt Read Flag
Set upon triggered compare match
3
AUXOF
0
Set when an Auxiliary CNT overflow occurs
2
DIRCNG
0
R
Direction Change Detect Interrupt Flag
Set when the count direction changes. Set in EXTCLKQUAD mode only.
1
OF
0
R
Overflow Interrupt Read Flag
R
Underflow Interrupt Read Flag
Set when a CNT overflow occurs
0
UF
0
Set when a CNT underflow occurs
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PCNT - Pulse Counter
14.5.8 PCNTn_IFS - Interrupt Flag Set Register
Access
W1 0
UF
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
OQSTERR
0
W1
0
W1 0
OF
Reset
1
W1 0
DIRCNG
Name
2
W1 0
AUXOF
Bit
3
4
W1 0
6
7
8
9
TCC
Name
5
Access
OQSTERR W1 0
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Description
Set OQSTERR Interrupt Flag
Write 1 to set the OQSTERR interrupt flag
4
TCC
0
W1
Set TCC Interrupt Flag
W1
Set AUXOF Interrupt Flag
W1
Set DIRCNG Interrupt Flag
Write 1 to set the TCC interrupt flag
3
AUXOF
0
Write 1 to set the AUXOF interrupt flag
2
DIRCNG
0
Write 1 to set the DIRCNG interrupt flag
1
OF
0
W1
Set OF Interrupt Flag
W1
Set UF Interrupt Flag
Write 1 to set the OF interrupt flag
0
UF
0
Write 1 to set the UF interrupt flag
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PCNT - Pulse Counter
14.5.9 PCNTn_IFC - Interrupt Flag Clear Register
Access
(R)W1 0
UF
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
OQSTERR
0
(R)W1
0
(R)W1 0
OF
Reset
1
(R)W1 0
DIRCNG
Name
2
(R)W1 0
AUXOF
Bit
3
4
(R)W1 0
6
7
8
TCC
Name
5
Access
OQSTERR (R)W1 0
Reset
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Description
Clear OQSTERR Interrupt Flag
Write 1 to clear the OQSTERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
4
TCC
0
(R)W1
Clear TCC Interrupt Flag
Write 1 to clear the TCC interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
3
AUXOF
0
(R)W1
Clear AUXOF Interrupt Flag
Write 1 to clear the AUXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
2
DIRCNG
0
(R)W1
Clear DIRCNG Interrupt Flag
Write 1 to clear the DIRCNG interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
1
OF
0
(R)W1
Clear OF Interrupt Flag
Write 1 to clear the OF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
0
UF
0
(R)W1
Clear UF Interrupt Flag
Write 1 to clear the UF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
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PCNT - Pulse Counter
14.5.10 PCNTn_IEN - Interrupt Enable Register
Access
RW 0
UF
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
OQSTERR
0
RW
0
RW 0
OF
Reset
1
RW 0
DIRCNG
Name
2
RW 0
AUXOF
Bit
3
4
RW 0
6
7
8
9
TCC
Name
5
Access
OQSTERR RW 0
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Description
OQSTERR Interrupt Enable
Enable/disable the OQSTERR interrupt
4
TCC
0
RW
TCC Interrupt Enable
RW
AUXOF Interrupt Enable
RW
DIRCNG Interrupt Enable
RW
OF Interrupt Enable
RW
UF Interrupt Enable
Enable/disable the TCC interrupt
3
AUXOF
0
Enable/disable the AUXOF interrupt
2
DIRCNG
0
Enable/disable the DIRCNG interrupt
1
OF
0
Enable/disable the OF interrupt
0
UF
0
Enable/disable the UF interrupt
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PCNT - Pulse Counter
14.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register
Name
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5
S0INLOC RW 0x00
Access
S1INLOC RW 0x00
Reset
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
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EFM32JG1 Reference Manual
PCNT - Pulse Counter
Bit
Name
Reset
Access
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
S1INLOC
0x00
RW
Description
I/O Location
Defines the location of the PCNT S1IN input pin.
7:6
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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PCNT - Pulse Counter
Bit
Name
Reset
Access
Description
5:0
S0INLOC
0x00
RW
I/O Location
Defines the location of the PCNT S0IN input pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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PCNT - Pulse Counter
14.5.12 PCNTn_FREEZE - Freeze Register
REGFREEZE RW 0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
REGFREEZE
0
RW
Description
Register Update Freeze
When set, the update of the PCNT clock domain is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value
Mode
Description
0
UPDATE
Each write access to a PCNT register is updated into the Low Frequency domain as soon as possible.
1
FREEZE
The PCNT clock domain is not updated with the new written value.
14.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
OVSCFG
0
R
0
0
R
CTRL
1
0
R
CMD
2
0
3
0
Name
R
Access
TOPB
Reset
OVSCFG R
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Description
OVSCFG Register Busy
Set when the value written to OVSCFG is being synchronized.
2
TOPB
0
R
TOPB Register Busy
Set when the value written to TOPB is being synchronized.
1
CMD
0
R
CMD Register Busy
Set when the value written to CMD is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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PCNT - Pulse Counter
14.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register
0
1
2
3
4
5
6
7
8
0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x064
Bit Position
31
Offset
Reset
AUXCNT R
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
AUXCNT
0x0000
R
Description
Auxiliary Counter Value
Gives read access to the auxiliary counter.
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PCNT - Pulse Counter
14.5.15 PCNTn_INPUT - PCNT Input Register
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0
1
2
S0PRSSEL RW 0x0
3
4
5
0
RW
S0PRSEN
6
7
9
8
S1PRSSEL RW 0x0
Name
10
12
11
0
RW
13
14
15
16
17
18
19
20
21
Access
S1PRSEN
Reset
22
23
24
25
26
27
28
29
30
0x068
Bit Position
31
Offset
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EFM32JG1 Reference Manual
PCNT - Pulse Counter
Bit
Name
Reset
Access
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
S1PRSEN
0
RW
Description
S1IN PRS Enable
When set, the PRS channel is selected as input to S1IN.
10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:6
S1PRSSEL
0x0
RW
S1IN PRS Channel Select
Select PRS channel as input to S1IN.
5
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected.
1
PRSCH1
PRS Channel 1 selected.
2
PRSCH2
PRS Channel 2 selected.
3
PRSCH3
PRS Channel 3 selected.
4
PRSCH4
PRS Channel 4 selected.
5
PRSCH5
PRS Channel 5 selected.
6
PRSCH6
PRS Channel 6 selected.
7
PRSCH7
PRS Channel 7 selected.
8
PRSCH8
PRS Channel 8 selected.
9
PRSCH9
PRS Channel 9 selected.
10
PRSCH10
PRS Channel 10 selected.
11
PRSCH11
PRS Channel 11 selected.
S0PRSEN
0
RW
S0IN PRS Enable
When set, the PRS channel is selected as input to S0IN.
4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
S0PRSSEL
0x0
RW
S0IN PRS Channel Select
Select PRS channel as input to S0IN.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected.
1
PRSCH1
PRS Channel 1 selected.
2
PRSCH2
PRS Channel 2 selected.
3
PRSCH3
PRS Channel 3 selected.
4
PRSCH4
PRS Channel 4 selected.
5
PRSCH5
PRS Channel 5 selected.
6
PRSCH6
PRS Channel 6 selected.
7
PRSCH7
PRS Channel 7 selected.
8
PRSCH8
PRS Channel 8 selected.
9
PRSCH9
PRS Channel 9 selected.
10
PRSCH10
PRS Channel 10 selected.
11
PRSCH11
PRS Channel 11 selected.
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PCNT - Pulse Counter
Bit
Name
Reset
Access
Description
14.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Name
Access
Bit
Name
Reset
31:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12
FLUTTERRM
0
RW
0
1
2
3
4
RW 0x00
FILTLEN
FLUTTERRM RW
Access
5
6
7
8
9
10
11
12
13
0
Reset
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x06C
Bit Position
31
Offset
Description
Flutter Remove
When set, removes flutter from Quaddecoder inputs S0IN and S1IN. Available only in OVSQUAD1X-4X modes
11:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
FILTLEN
0x00
RW
Configure filter length for inputs S0IN and S1IN
Used only in OVSINGLE,OVSQUAD1X-4X modes.To use this first enable FILT in PCNTn_CTRL register. Filter length =
(FILTLEN + 5) LFACLK cycles
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I2C - Inter-Integrated Circuit Interface
15. I2C - Inter-Integrated Circuit Interface
Quick Facts
What?
0 1 2 3
4
The I2C interface allows communication on I2Cbuses with the lowest energy consumption possible.
Why?
Gecko Device
I2C master/slave
SCL
SDA
VDD
Other I2C
master
Other I2C
slave
I2C
EEPROM
I2C is a popular serial bus that enables communication with a number of external devices using only
two I/O pins.
How?
With the help of DMA, the I2C interface allows I2C
communication with minimal CPU intervention. Address recognition is available in all energy modes
(except EM4), allowing the MCU to wait for data on
the I2C-bus with sub-µA current consumption.
15.1 Introduction
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates all the
way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system. The interface provided to software by the I2C module allows precise control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in all energy modes (except EM4).
15.2 Features
• True multi-master capability
• Support for different bus speeds
• Standard-mode (Sm) bit rate up to 100 kbit/s
• Fast-mode (Fm) bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+) bit rate up to 1 Mbit/s
• Arbitration for both master and slave (allows SMBus ARP)
• Clock synchronization and clock stretching
• Hardware address recognition
• 7-bit masked address
• General call address
• Active in all energy modes (except EM4)
• 10-bit address support
• Error handling
• Clock low timeout
• Clock high timeout
• Arbitration lost
• Bus error detection
• Separate receive/ transmit 2-level buffers, with additional separate shift registers
• Full DMA support
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I2C - Inter-Integrated Circuit Interface
15.3 Functional Description
An overview of the I2C module is shown in Figure 15.1 I2C Overview on page 386.
Peripheral Bus
I2Cn_SDA
I2Cn_SCL
I2C Control and
Status
Transmit Buffer
(2-level FIFO)
Receive Buffer
(2-level FIFO)
Symbol
Generator
Transmit
Shift Register
Receive
Shift Register
Receive
Controller
Clock Generator
Pin
Ctrl
Address
Recognizer
Figure 15.1 I2C Overview
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I2C - Inter-Integrated Circuit Interface
15.3.1 I2C-Bus Overview
The I2C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in Figure 15.2 I2C-Bus
Example on page 387. As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple
masters transmit data at the same time without data loss.
VDD
I2C master
#1
I2C master
#2
I2C slave
#1
I2C slave
#2
I2C slave
#3
Rp
SDA
SCL
Figure 15.2 I2C-Bus Example
Each device on the bus is addressable by a unique address, and an I2C master can address all the devices on the bus, including other
masters.
Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a function of the maximal rise-time tr
for the given bus speed, and the estimated bus capacitance Cb as shown in Figure 15.2 I2C Pull-up Resistor Equation on page 387.
Rp(max) = (tr/0.8473) x Cb.
Equation: I2C Pull-up Resistor Equation
The maximal rise times for 100 kHz, 400 kHz and 1 MHz I2C are 1 µs, 300 ns and 120 ns respectively.
Note:
The GPIO drive strength can be used to control slew rate.
Note:
If Vdd drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines low.
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I2C - Inter-Integrated Circuit Interface
15.3.1.1 START and STOP Conditions
START and STOP conditions are used to initiate and stop transactions on the I2C-bus. All transactions on the bus begin with a START
condition (S) and end with a STOP condition (P). As shown in Figure 15.4 I2C START and STOP Conditions on page 388, a START
condition is generated by pulling the SDA line low while SCL is high, and a STOP condition is generated by pulling the SDA line high
while SCL is high.
SDA
SCL
S
P
START condition
STOP condition
Figure 15.4 I2C START and STOP Conditions
The START and STOP conditions are easily identifiable bus events as they are the only conditions on the bus where a transition is
allowed on SDA while SCL is high. During the actual data transmission, SDA is only allowed to change while SCL is low, and must be
stable while SCL is high. One bit is transferred per clock pulse on the I2C-bus as shown in Figure 15.5 I2C Bit Transfer on I2C-Bus on
page 388.
SDA
SCL
Data change
allowed
Data stable
Data change
allowed
Figure 15.5 I2C Bit Transfer on I2C-Bus
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15.3.1.2 Bus Transfer
When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The
master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the
slave (R/W bit set to 1) or write to the slave (R/W bit set to 0).
After the 7-bit address and the R/W bit, the master releases the bus, allowing the slave to acknowledge the request. During the next bitperiod, the slave pulls SDA low (ACK) if it acknowledges the request, or keeps it high if it does not acknowledge it (NACK).
Following the address acknowledge, either the slave or master transmits data, depending on the value of the R/W bit. After every 8 bits
(one byte) transmitted on the SDA line, the transmitter releases the line to allow the receiver to transmit an ACK or a NACK. Both the
data and the address are transmitted with the most significant bit first.
The number of bytes in a bus transfer is unrestricted. The master ends the transmission after a (N)ACK by sending a STOP condition
on the bus. After a STOP condition, any master wishing to initiate a transfer on the bus can try to gain control of it. If the current master
wishes to make another transfer immediately after the current, it can start a new transfer directly by transmitting a repeated START
condition (Sr) instead of a STOP followed by a START.
Examples of I2C transfers are shown in Figure 15.6 I2C Single Byte Write to Slave on page 389, Figure 15.7 I2C Double Byte Read
from Slave on page 389, and Figure 15.8 I2C Single Byte Write, then Repeated Start and Single Byte Read on page 389. The identifiers used are:
• ADDR - Address
• DATA - Data
• S - Start bit
• Sr - Repeated start bit
• P - Stop bit
• W/R - Read(1)/Write(0)
• A - ACK
• N - NACK
S
ADDR
W A
DATA
A
P
Figure 15.6 I2C Single Byte Write to Slave
S
ADDR
R
A
DATA
A
DATA
N
P
Figure 15.7 I2C Double Byte Read from Slave
S
ADDR
W A
DATA
A Sr
ADDR
R
A
DATA
N
P
Figure 15.8 I2C Single Byte Write, then Repeated Start and Single Byte Read
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15.3.1.3 Addresses
I2C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains
the address of the slave that the master wants to contact. In the 7-bit address space, several addresses are reserved. These addresses
are summarized in Table 15.1 I2C Reserved I2C Addresses on page 390, and include a General Call address which can be used to
broadcast a message to all slaves on the I2C-bus.
Table 15.1. I2C Reserved I2C Addresses
I2C Address
R/W
Description
0000-000
0
General Call address
0000-000
1
START byte
0000-001
X
Reserved for the C-Bus format
0000-010
X
Reserved for a different bus format
0000-011
X
Reserved for future purposes
0000-1XX
X
Reserved for future purposes
1111-1XX
X
Reserved for future purposes
1111-0XX
X
10 Bit slave addressing mode
15.3.1.4 10-bit Addressing
To address a slave using a 10-bit address, two bytes are required to specify the address instead of one. The seven first bits of the first
byte must then be 1111 0XX, where XX are the two most significant bits of the 10-bit address. As with 7-bit addresses, the eighth bit of
the first byte determines whether the master wishes to read from or write to the slave. The second byte contains the eight least significant bits of the slave address.
When a slave receives a 10-bit address, it must acknowledge both the address bytes if they match the address of the slave.
When performing a master transmitter operation, the master transmits the two address bytes and then the remaining data, as shown in
Figure 15.9 I2C Master Transmitter/Slave Receiver with 10-bit Address on page 390.
S
ADDR (1st 7 bits)
W A
Addr (2nd byte)
A
DATA
A
P
Figure 15.9 I2C Master Transmitter/Slave Receiver with 10-bit Address
When performing a master receiver operation however, the master first transmits the two address bytes in a master transmitter operation, then sends a repeated START followed by the first address byte and then receives data from the addressed slave. The slave addressed by the 10-bit address in the first two address bytes must remember that it was addressed, and respond with data if the address
transmitted after the repeated start matches its own address. An example of this (with one byte transmitted) is shown in Figure
15.10 I2C Master Receiver/Slave Transmitter with 10-bit Address on page 390.
S
ADDR (1st 7 bits)
W A
Addr (2nd byte)
A Sr
ADDR (1st 7 bits)
R
A
DATA
N
P
Figure 15.10 I2C Master Receiver/Slave Transmitter with 10-bit Address
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15.3.1.5 Arbitration, Clock Synchronization, Clock Stretching
Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to
drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be
able to do so due to the open-drain bus configuration. Both devices sample the bus, and the one that was unable to drive the bus in the
desired direction detects the collision and backs off, letting the other device continue communication on the bus undisturbed.
Clock synchronization is a means of synchronizing the clock outputs from several masters driving the bus at once, and is a requirement
for effective arbitration.
Slaves on the bus are allowed to force the clock output on the bus low in order to pause the communication on the bus and give themselves time to process data or perform any real-time tasks they might have. This is called clock stretching.
Arbitration is supported by the I2C module for both masters and slaves. Clock synchronization and clock stretching is also supported.
15.3.2 Enable and Reset
The I2C is enabled by setting the EN bit in the I2Cn_CTRL register. Whenever this bit is cleared, the internal state of the I2C is reset,
terminating any ongoing transfers.
Note:
When enabling the I2C, the ABORT command or the Bus Idle Timeout feature must be applied prior to use even if the BUSY flag is not
set.
15.3.3 Safely Disabling and Changing Slave Configuration
The I2C slave is partially asynchronous, and some precautions are necessary to always ensure a safe slave disable or slave configuration change. These measures should be taken, if (while the slave is enabled) the user cannot guarantee that an address match will not
occur at the exact time of slave disable or slave configuration change.
Worst case consequences for an address match while disabling slave or changing configuration is that the slave may end up in an
undefined state. To reset the slave back to a known state, the EN bit in I2Cn_CTRL must be reset. This should be done regardless of
whether the slave is going to be re-enabled or not.
15.3.4 Clock Generation
The SCL signal generated by the I2C master determines the maximum transmission rate on the bus. The clock is generated as a division of the peripheral clock, and is given by the following equation:
fSCL = fHFPERCLK/(((Nlow + Nhigh) x (DIV + 1)) + 8),
Equation: I2C Maximum Transmission Rate
Nlow and Nhigh in combination with the synchronization cycles (discussed below) specify the number of prescaled clock cycles in the low
and high periods of the clock signal respectively. The worst case low and high periods of the signal are:
Thigh >= ((Nhigh) x (DIV + 1) + 4)/fHFPERCLK,
Tlow >= (Nlow x (DIV + 1) + 4)/fHFPERCLK.
Equation: I2C High and Low Cycles Equations
In worst case, Thigh and Tlow can be 1 fHFPERCLK cycle longer than the number found by above equations due to synchronization uncertainity (i.e., if the synchronization takes 3 fHFPERCLK cycles instead of 2). Similarly, in the worst case the number 8 in the denominator in
fSCL equation can be 9 (if the synchronization cycles were 3 instead of 2 in Thigh or Tlow) or 10 (if synchronization cycles were 3 in both
Thigh and Tlow). The values of Nlow and Nhigh and thus the ratio between the high and low parts of the clock signal is controlled by
CLHR in the I2Cn_CTRL register.
Note:
DIV must be set to 1 during slave mode operation.
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15.3.5 Arbitration
Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value
on SDA is sensed every time the I2C module attempts to change its value. If the sensed value is different than the value the I2C module
tried to output, it is interpreted as a simultaneous transmission by another device, and that the I2C module has lost arbitration.
Whenever arbitration is lost, the ARBLOST interrupt flag in I2Cn_IF is set, any lines held are released, and the I2C device goes idle. If
an I2C master loses arbitration during the transmission of an address, another master may be trying to address it. The master therefore
receives the rest of the address, and if the address matches the slave address of the master, the master goes into either slave transmitter or slave receiver mode.
Note:
Arbitration can be lost both when operating as a master and when operating as a slave.
15.3.6 Buffers
15.3.6.1 Transmit Buffer and Shift Register
The I2C transmitter has a 2-level FIFO transmit buffer and a transmit shift register as shown in Figure 15.1 I2C Overview on page 386.
A byte is loaded into the transmit buffer by writing to I2Cn_TXDATA or 2 bytes can be loaded simultaneously in the transmit buffer by
writing to I2Cn_TXDOUBLE. Figure 15.13 I2C Transmit Buffer Operation on page 392 shows the basics of the transmit buffer. When
the transmit shift register is empty and ready for new data, the byte from the transmit buffer is then loaded into the shift register. The
byte is then kept in the shift register until it is transmitted. When a byte has been transmitted, a new byte is loaded into the shift register
(if available in the transmit buffer). If the transmit buffer is empty, then the shift register also remains empty. The TXC flag in I2Cn_STATUS and the TXC interrupt flags in I2Cn_IF are then set, signaling that the transmit shift register is out of data. TXC is cleared when
new data becomes available, but the TXC interrupt flag must be cleared by software.
Peripheral bus
TXDATA
TX buffer element 1
TXDOUBLE
TX buffer element 0
Shift register
Figure 15.13 I2C Transmit Buffer Operation
The TXBL flags in the I2Cn_STATUS and I2Cn_IF are used to indicate the level of the transmit buffer. TXBIL in I2Cn_CTRL controls the
level at which these flag bits are set. If TXBIL is cleared, the flags are set whenever the transmit buffer becomes empty (used when
transmitting using I2Cn_TXDOUBLE). If TXBIL is set, the flags are set whenever the transmit buffer goes from full to half-empty or empty (used when transmitting with I2Cn_TXDATA). Both the TXBL status flag and the TXBL interrupt flag are cleared automatically when
the condition becomes false.
If an attempt is made to write more bytes to the transmit buffer than the space available, the TXOF interrupt flag in I2Cn_IF is set,
indicating the overflow. The data already in the buffer remains preserved, and no new data is written.
The transmit buffer and the transmit shift register can be cleared by setting command bit CLEARTX in I2Cn_CMD. This will prevent the
I2C module from transmitting the data in the buffer and the shift register, and will make them available for new data. Any byte currently
being transmitted will not be aborted. Transmission of this byte will be completed.
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15.3.6.2 Receive Buffer and Shift Register
The I2C receiver uses a 2-level FIFO receive buffer and a receive shift register as shown in Figure 15.14 I2C Receive Buffer Operation
on page 393. When a byte has been fully received by the receive shift register, it is loaded into the receive buffer if there is room for it,
making the shift register empty to receive another byte. Otherwise, the byte waits in the shift register until space becomes available in
the buffer.
Peripheral bus
RX buffer element 0
RXDATA
RXDOUBLE
RX buffer element 1
Shift register
Figure 15.14 I2C Receive Buffer Operation
When a byte becomes available in the receive buffer, the RXDATAV in I2Cn_STATUS and RXDATAV interrupt flag in I2Cn_IF are set.
When the buffer becomes full, RXFULL in the I2Cn_STATUS and I2Cn_IF are set. The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true. This also goes for the RXDATAV interrupt flag, but the RXFULL
interrupt flag must be cleared by software. When the RXFULL flag is set, notifying that the buffer is full, space is still available in the
receive shift register for one more byte.
The data can be fetched from the buffer in two ways. I2Cn_RXDATA gives access to the received byte (if two bytes are received then
the one received first is fetched first). I2Cn_RXDOUBLE makes it possible to read the two received bytes simultaneously. If an attempt
is made to read more bytes from the buffer than available, the RXUF interrupt flag in I2Cn_IF is set to signal the underflow, and the data
read from the buffer is undefined.
When using I2Cn_RXDOUBLE to pick data, AUTOACK in I2Cn_CTRL should be set to 1. This ensures that an ACK is automatically
sent out after the first byte is received so that the reception of the next byte can begin. In order to stop receiving data bytes, a NACK
must be sent out through the I2Cn_CMD register.
I2Cn_RXDATAP and I2Cn_RXDOUBLEP can be used to read data from the receive buffer without removing it from the buffer. The
RXUF interrupt flag in I2Cn_IF will never be set as a result of reading from I2Cn_RXDATAP and I2Cn_RXDOUBLEP, but the data read
through I2Cn_RXDATAP when the receive buffer is empty is still undefined.
Once a transaction is complete (STOP sent or received), the receive buffer needs to be flushed (all received data must be read) before
starting a new transaction.
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15.3.7 Master Operation
A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2Cn_CMD. The
command schedules a START condition, and makes the I2C module generate a start condition whenever the bus becomes free.
The I2C-bus is considered busy whenever another device on the bus transmits a START condition. Until a STOP condition is detected,
the bus is owned by the master issuing the START condition. The bus is considered free when a STOP condition is transmitted on the
bus. After a STOP is detected, all masters that have data to transmit send a START condition and begin transmitting data. Arbitration
ensures that collisions are avoided.
When the START condition has been transmitted, the master must transmit a slave address (ADDR) with an R/W bit on the bus. If this
address is available in the transmit buffer, the master transmits it immediately, but if the buffer is empty, the master holds the I2C-bus
while waiting for software to write the address to the transmit buffer.
After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the
R/W bit (bit 0 in the address byte). If the bit was cleared, the master has entered a master transmitter role, where it now transmits data
to the slave. If the bit was set, it has entered a master receiver role, where it now should receive data from the slave. In either case, an
unlimited number of bytes can be transferred in one direction during the transmission.
At the end of the transmission, the master either transmits a repeated START condition (Sr) if it wishes to continue with another transfer, or transmits a STOP condition (P) if it wishes to release the bus. When operating in the master mode, HFPERCLK frequency must
be higher than 2 MHz for Standard-mode, 9 MHz for Fast-mode, and 20 MHz for Fast-mode Plus.
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15.3.7.1 Master State Machine
The master state machine is shown in Figure 15.15 I2C Master State Machine on page 395. A master operation starts in the far left of
the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when
arriving at the right side of the state machine.
Branches in the path through the state machine are the results of bus events and choices made by software, either directly or indirectly.
The dotted lines show where I2C-specific interrupt flags are set along the path and the full-drawn circles show places where interaction
may be required by software to let the transmission proceed.
Master transmitter
0/1
57
Waiting
for idle
Idle/busy
S
97
ADDR W
A
D7
DATA
A
DF
Bus state/event
9F
Transmitted by self
Sr
Repeated START condition
A
ACK
ADDR R
57
Arb. lost
START
condition
ADDR W
Sr
N
S
N
0
N
Received from slave
P
P
STOP
condition
1
Master receiver
93
ADDR R
A
B3
DATA
A
NACK
Slave address + write
(R/W bit cleared)
Slave address + read
(R/W bit set)
9B
P
0
Sr
57
N
N
Bus state (STATE)
X
Arb. lost
1
Arbitration lost
Interrupt flag set
Interaction required. Waitstates inserted until manual
or automatic interaction has
been performed
Go to state
ADDR R
Arb. lost, ADDR match
73
Slave transmitter
ADDR W
Arb. lost, ADDR match
71
Slave receiver
ADDR X
Arb. lost, no match
1
Bus reset
P
0
Figure 15.15 I2C Master State Machine
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15.3.7.2 Interactions
Whenever the I2C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the
BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I2C module. This
state can be read from the I2Cn_STATE register.
As an example, Table 15.3 I2C Master Transmitter on page 398 shows the different states the I2C goes through when operating as a
Master Transmitter, i.e., a master that transmits data to a slave. As seen in the table, when a start condition has been transmitted, a
requirement is that there is an address and an R/W bit in the transmit buffer. If the transmit buffer is empty, then the BUSHOLD interrupt
flag is set, and the bus is held until data becomes available in the buffer. While waiting for the address, I2Cn_STATE has a value 0x57,
which can be used to identify exactly what the I2C module is waiting for.
Note:
The bus would never stop at state 0x57 if the address was available in the transmit buffer.
The different interactions used by the I2C module are listed in Table 15.2 I2C Interactions in Prioritized Order on page 396 in a prioritized order. If the I2C module is in such a state that multiple courses of action are possible, then the action chosen is the one that has
the highest priority. For example, after sending out a START, if an address is present in the buffer and a STOP is also pending, then the
I2C will send out the STOP since it has the higher priority.
Table 15.2. I2C Interactions in Prioritized Order
Interaction
Priority
Software action
Automatically continues if
STOP*
1
Set the STOP command bit in
I2Cn_CMD
PSTOP is set (STOP pending)
in I2Cn_STATUS
ABORT
2
Set the ABORT command bit in
I2Cn_CMD
Never, the transmission is aborted
CONT*
3
Set the CONT command bit in
I2Cn_CMD
PCONT is set in I2Cn_STATUS
(CONT pending)
NACK*
4
Set the NACK command bit in
I2Cn_CMD
PNACK is set in I2Cn_STATUS
(NACK pending)
ACK*
5
Set the ACK command bit in
I2Cn_CMD
AUTOACK is set in I2Cn_CTRL
or PACK is set in I2Cn_STATUS
(ACK pending)
ADDR+W -> TXDATA
6
Write an address to the transmit Address is available in transmit
buffer with the R/W bit set
buffer with R/W bit set
ADDR+R -> TXDATA
7
Write an address to the transmit Address is available in transmit
buffer with the R/W bit cleared
buffer with R/W bit cleared
START*
8
Set the START command bit in
I2Cn_CMD
PSTART is set in I2Cn_STATUS
(START pending)
TXDATA/ TXDOUBLE
9
Write data to the transmit buffer
Data is available in transmit buffer
RXDATA/ RXDOUBLE
10
Read data from receive buffer
Space is available in receive
buffer
None
11
No interaction is required
The commands marked with a * in Table 15.2 I2C Interactions in Prioritized Order on page 396 can be issued before an interaction is
required. When such a command is issued before it can be used/consumed by the I2C module, the command is set in a pending state,
which can be read from the STATUS register. A pending START command can for instance be identified by PSTART having a high
value.
Whenever the I2C module requires an interaction, it checks the pending commands. If one or a combination of these can fulfill an interaction, they are consumed by the module and the transmission continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get
an interaction from software. The pending status of a command goes low when it is consumed.
When several interactions are possible from a set of pending commands, the interaction with the highest priority, i.e., the interaction
closest to the top of Table 15.2 I2C Interactions in Prioritized Order on page 396 is applied to the bus.
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Pending commands can be cleared by setting the CLEARPC command bit in I2Cn_CMD.
15.3.7.3 Automatic ACK Interaction
When receiving addresses and data, an ACK command in I2Cn_CMD is normally required after each received byte. When AUTOACK
is set in I2Cn_CTRL, an ACK is always pending, and the ACK-pending bit PACK in I2Cn_STATUS is thus always set, even after an
ACK has been consumed. This is used when data is picked using I2Cn_RXDOUBLE and can also be used with I2Cn_RXDATA in order
to reduce the amount of software interaction required during a transfer.
15.3.7.4 Reset State
After a reset, the state of the I2C-bus is unknown. To avoid interrupting transfers on the I2C-bus after a reset of the I2C module or the
entire MCU, the I 2C-bus is assumed to be busy when coming out of a reset, and the BUSY flag in I2Cn_STATUS is thus set. To be able
to carry through master operations on the I2C-bus, the bus must be idle.
The bus goes idle when a STOP condition is detected on the bus, but on buses with little activity, the time before the I2C module detects that the bus is idle can be significant. There are two ways of assuring that the I2C module gets out of the busy state.
• Use the ABORT command in I2Cn_CMD. When the ABORT command is issued, the I2C module is instructed that the bus is idle.
The I2C module can then initiate master operations.
• Use the Bus Idle Timeout. When SCL has been high for a long period of time, it is very likely that the bus is idle. Set BITO in
I2Cn_CTRL to an appropriate timeout period and set GIBITO in I2Cn_CTRL. If activity has not been detected on the bus within the
timeout period, the bus is then automatically assumed idle, and master operations can be initiated.
Note:
If operating in slave mode, the above approach is not necessary.
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15.3.7.5 Master Transmitter
To transmit data to a slave, the master must operate as a master transmitter. Table 15.3 I2C Master Transmitter on page 398 shows
the states the I2C module goes through while acting as a master transmitter. Every state where an interaction is required has the possible interactions listed, along with the result of the interactions. The table also shows which interrupt flags are set in the different states.
The interrupt flags enclosed in parenthesis may be set. If the BUSHOLD interrupt in I2Cn_IF is set, the module is waiting for an interaction, and the bus is frozen. The value of I2Cn_STATE will be equal to the values given in the table when the BUSHOLD interrupt flag is
set, and can be used to determine which interaction is required to make the transmission continue.
The interrupt flag START in I2Cn_IF is set when the I2C module transmits the START.
A master operation is started by issuing a START command by setting START in I2Cn_CMD. ADDR+W, i.e., the address of the slave +
the R/W bit is then required by the I2C module. If this is not available in the transmit buffer, then the bus is held and the BUSHOLD
interrupt flag is set. The value of I2Cn_STATE will then be 0x57. As seen in the table, the I2C module also stops in this state if the
address is not available after a repeated start condition.
To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits and the least significant bit cleared
(ADDR+W). This address will then be transmitted, and the slave will reply with an ACK or a NACK. If no slave replies to the address,
the response will also be NACK. If the address was acknowledged, the master now has four choices. It can send data by placing it in
I2Cn_TXDATA/ I2Cn_TXDOUBLE (the master should check the TXBL interrupt flag before writing to the transmit buffer), this data is
then transmitted. The master can also stop the transmission by sending a STOP, it can send a repeated start by sending START, or it
can send a STOP and then a START as soon as possible. If the master wishes to make another transfer immediately after the current,
the preferred way is to start a new transfer directly by transmitting a repeated START instead of a STOP followed by a START. This is
so because if a STOP is sent out, then any master wishing to initiate a transfer on the bus can try to gain control of it.
If a NACK was received, the master has to issue a CONT command in addition to providing data in order to continue transmission. This
is not standard I2C, but is provided for flexibility. The rest of the options are similar to when an ACK was received.
If a new byte was transmitted, an ACK or NACK is received after the transmission of the byte, and the master has the same options as
for when the address was sent.
The master may lose arbitration at any time during transmission. In this case, the ARBLOST interrupt flag in I2Cn_IF is set. If the arbitration was lost during the transfer of an address, and SLAVE in I2Cn_CTRL is set, the master then checks which address was transmitted. If it was the address of the master, then the master goes to slave mode.
After a master has transmitted a START and won any arbitration, it owns the bus until it transmits a STOP. After a STOP, the bus is
released, and arbitration decides which bus master gains the bus next. The MSTOP interrupt flag in I2Cn_IF is set when a STOP condition is transmitted by the master.
Table 15.3. I2C Master Transmitter
I2Cn_STATE
Description
I2Cn_IF
Required interaction
Response
0x57
Start transmitted
START interrupt flag
(BUSHOLD interrupt
flag)
ADDR+W ->
TXDATA
ADDR+W will be sent
STOP
STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
ADDR+W ->
TXDATA
ADDR+W will be sent
STOP
STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
0x57
-
Repeated start transmitted
ADDR+W transmitted
START interrupt flag
(BUSHOLD interrupt
flag)
TXBL interrupt flag
(TXC interrupt flag)
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I2Cn_STATE
Description
I2Cn_IF
Required interaction
Response
0x97
ADDR+W transmitted,
ACK received
ACK interrupt flag
(BUSHOLD interrupt
flag)
TXDATA
DATA will be sent
STOP
STOP will be sent. Bus will be released
START
Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a
START will be sent when the bus becomes idle
CONT +
TXDATA
DATA will be sent
STOP
STOP will be sent. Bus will be released
START
Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a
START will be sent when the bus becomes idle
0x9F
ADDR+W transmitted,NACK received
NACK (BUSHOLD interrupt flag)
-
Data transmitted
TXBL interrupt flag
(TXC interrupt flag)
None
0xD7
Data transmitted,ACK
received
ACK interrupt flag
(BUSHOLD interrupt
flag)
TXDATA
DATA will be sent
STOP
STOP will be sent. Bus will be released
START
Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a
START will be sent when the bus becomes idle
0xDF
-
Data transmitted,NACK NACK(BUSHOLD inter- CONT +
received
rupt flag)
TXDATA
Stop transmitted
MSTOP interrupt flag
STOP
STOP will be sent. Bus will be released
START
Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a
START will be sent when the bus becomes idle
None
START
-
Arbitration lost
DATA will be sent
START will be sent when bus becomes idle
ARBLOST interrupt flag None
START
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15.3.7.6 Master Receiver
To receive data from a slave, the master must operate as a master receiver, see Table 15.4 I2C Master Receiver on page 400. This is
done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The address byte loaded into the data register thus has to contain the 7-bit slave address in the 7 most significant bits of the byte, and have
the least significant bit set.
When the address has been transmitted, the master receives an ACK or a NACK. If an ACK is received, the ACK interrupt flag in
I2Cn_IF is set, and if space is available in the receive shift register, reception of a byte from the slave begins. If the receive buffer and
shift register is full however, the bus is held until data is read from the receive buffer or another interaction is made. Note that the STOP
and START interactions have a higher priority than the data-available interaction, so if a STOP or START command is pending, the
highest priority interaction will be performed, and data will not be received from the slave.
If a NACK was received, the CONT command in I2Cn_CMD has to be issued in order to continue receiving data, even if there is space
available in the receive buffer and/or shift register.
After a data byte has been received the master must ACK or NACK the received byte. If an ACK is pending or AUTOACK in
I2Cn_CTRL is set, an ACK is sent automatically and reception continues if space is available in the receive buffer.
If a NACK is sent, the CONT command must be used in order to continue transmission. If an ACK or NACK is issued along with a
START or STOP or both, then the ACK/NACK is transmitted and the reception is ended. If START in I2Cn_CMD is set alone, a repeated start condition is transmitted after the ACK/NACK. If STOP in I2Cn_CMD is set, a stop condition is sent regardless of whether
START is set. If START is set in this case, it is set as pending.
As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag
in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the correct conditions.
Table 15.4. I2C Master Receiver
I2Cn_STATE
Description
I2Cn_IF
Required interaction
Response
0x57
START transmitted
START interrupt flag
(BUSHOLD interrupt
flag)
ADDR+R ->
TXDATA
ADDR+R will be sent
STOP
STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
ADDR+R ->
TXDATA
ADDR+R will be sent
STOP
STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
0x57
Repeated START trans- START interrupt
mitted
flag(BUSHOLD interrupt flag)
-
ADDR+R transmitted
TXBL interrupt flag
(TXC interrupt flag)
0x93
ADDR+R transmitted,
ACK received
ACK interrupt flag(BUS- RXDATA
HOLD)
STOP
0x9B
ADDR+R transmitted,NACK received
NACK(BUSHOLD)
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None
Start receiving
STOP will be sent and the bus released
START
Repeated START will be sent
STOP +
START
STOP will be sent and the bus released. Then a
START will be sent when the bus becomes idle
CONT +
RXDATA
Continue, start receiving
STOP
STOP will be sent and the bus released
START
Repeated START will be sent
STOP +
START
STOP will be sent and the bus released. Then a
START will be sent when the bus becomes idle
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I2Cn_STATE
Description
I2Cn_IF
Required interaction
Response
0xB3
Data received
RXDATA interrupt
flag(BUSHOLD interrupt flag)
ACK + RXDATA
ACK will be transmitted, reception continues
NACK +
CONT +
RXDATA
NACK will be transmitted, reception continues
ACK/NACK +
STOP
ACK/NACK will be sent and the bus will be released.
ACK/NACK +
START
ACK/NACK will be sent, and then a repeated
start condition.
ACK/NACK +
STOP +
START
ACK/NACK will be sent and the bus will be released. Then a START will be sent when the bus
becomes idle
-
Stop received
MSTOP interrupt flag
None
START
-
Arbitration lost
START will be sent when bus becomes idle
ARBLOST interrupt flag None
START
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15.3.8 Bus States
The I2Cn_STATE register can be used to determine which state the I2C module and the I2C bus are in at a given time. The register
consists of the STATE bit-field, which shows which state the I2C module is at in any ongoing transmission, and a set of single-bits,
which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I2C module waiting for a software response.
The possible values of the STATE field are summarized in Table 15.5 I2C STATE Values on page 402. When this field is cleared, the
I2C module is not a part of any ongoing transmission. The remaining status bits in the I2Cn_STATE register are listed in Table 15.6 I2C
Transmission Status on page 402.
Table 15.5. I2C STATE Values
Mode
Value
Description
IDLE
0
No transmission is being performed by this module.
WAIT
1
Waiting for idle. Will send a start condition as soon as the bus is idle.
START
2
Start being transmitted
ADDR
3
Address being transmitted or has been received
ADDRACK
4
Address ACK/NACK being transmitted or received
DATA
5
Data being transmitted or received
DATAACK
6
Data ACK/NACK being transmitted or received
Table 15.6. I2C Transmission Status
Bit
Description
BUSY
Set whenever there is activity on the bus. Whether or not this module is responsible for
the activity cannot be determined by this byte.
MASTER
Set when operating as a master. Cleared at all other times.
TRANSMITTER
Set when operating as a transmitter; either a master transmitter or a slave transmitter.
Cleared at all other times
BUSHOLD
Set when the bus is held by this I2C module because an action is required by software.
NACK
Only valid when bus is held and STATE is ADDRACK or DATAACK. In that case it is set
if a NACK was received. In all other cases, the bit is cleared.
Note:
I2Cn_STATE reflects the internal state of the I2C module, and therefore only held constant as long as the bus is held, i.e., as long as
BUSHOLD in I2Cn_STATUS is set.
15.3.9 Slave Operation
The I2C module operates in master mode by default. To enable slave operation, i.e., to allow the device to be addressed as an I2C
slave, the SLAVE bit in I2Cn_CTRL must be set. In this case the I2C module operates in a mixed mode, both capable of starting transmissions as a master, and being addressed as a slave. When operating in the slave mode, HFPERCLK frequency must be higher than
2 MHz for Standard-mode, 5 MHz for Fast-mode, and 14 MHz for Fast-mode Plus.
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15.3.9.1 Slave State Machine
The slave state machine is shown in Figure 15.16 I2C Slave State Machine on page 403. The dotted lines show where I2C-specific
interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission proceed.
Slave transmitter
0/1
73
Idle/busy
S
ADDR R
D5
A
DATA
A
DD
Bus state/event
P
0
Sr
41
N
Transmitted by self
N
Received from master
Arb. lost
Bus state (STATE)
Slave receiver
71
ADDR W
Interrupt flag set
1
B1
A
DATA
Interaction required. Clockstretching applied until
manual or automatic
interaction has been
performed
A
P
0
Sr
41
Arb. lost
1
N
N
X
Go to state
Figure 15.16 I2C Slave State Machine
15.3.9.2 Address Recognition
The I2C module provides automatic address recognition for 7-bit addresses. 10-bit address recognition is not fully automatic, but can be
assisted by the 7-bit address comparator as shown in 15.3.11 Using 10-bit Addresses. Address recognition is supported in all energy
modes (except EM4).
The slave address, i.e., the address which the I2C module should be addressed with, is defined in the I2Cn_SADDR register. In addition
to the address, a mask must be specified, telling the address comparator which bits of an incoming address to compare with the address defined in I2Cn_SADDR. The mask is defined in I2Cn_SADDRMASK, and for every zero in the mask, the corresponding bit in the
slave address is treated as a don’t-care, i.e., the 0-masked bits are ignored.
An incoming address that fails address recognition is automatically replied to with a NACK. Since only the bits defined by the mask are
checked, a mask with a value 0x00 will result in all addresses being accepted. A mask with a value 0x7F will only match the exact
address defined in I2Cn_SADDR, while a mask 0x70 will match all addresses where the three most significant bits in I2Cn_SADDR and
the incoming address are equal.
If GCAMEN in I2Cn_CTRL is not set, the start-byte, i.e., the general call address with the R/W bit set is ignored unless it is included in
the defined slave address and and the address mask.
When an address is accepted by the address comparator, the decision of whether to ACK or NACK the address is passed to software.
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15.3.9.3 Slave Transmitter
When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected.
After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the
receive shift register for the address, the bus will be held by the slave until room is available in the shift register. Transmission then
continues and the address is loaded into the shift register. If this address does not pass address recognition, it is automatically
NACK’ed by the slave, and the slave goes to an idle state. The address byte is in this case discarded, making the shift register ready
for a new address. It is not loaded into the receive buffer.
If the address was accepted and the R/W bit was set (R), indicating that the master wishes to read from the slave, the slave now goes
into the slave transmitter mode. Software interaction is now required to decide whether the slave wants to acknowledge the request or
not. The accepted address byte is loaded into the receive buffer like a regular data byte. If no valid interaction is pending, the bus is
held until the slave responds with a command. The slave can reject the request with a single NACK command.
The slave will in that case go to an idle state, and wait for the next start condition. To continue the transmission, the slave must make
sure data is loaded into the transmit buffer and send an ACK. The loaded data will then be transmitted to the master, and an ACK or
NACK will be received from the master.
Data transmission can also continue after a NACK if a CONT command is issued along with the NACK. This is not standard I2C however.
If the master responds with an ACK, it may expect another byte of data, and data should be made available in the transmit buffer. If
data is not available, the bus is held until data is available.
If the response is a NACK however, this is an indication of that the master has received enough bytes and wishes to end the transmission. The slave now automatically goes idle, unless CONT in I2Cn_CMD is set and data is available for transmission. The latter is not
standard I2C.
The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag in I2Cn_IF is set when the master transmits a STOP condition. If the transmission is ended with a repeated START, then the SSTOP interrupt flag is not set.
Note:
The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is participating in the transmission or not, as long as
SLAVE in I2Cn_CTRL is set and a STOP condition is detected
If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the bus is released and the slave
goes idle.
See Table 15.7 I2C Slave Transmitter on page 404 for more information.
Table 15.7. I2C Slave Transmitter
I2Cn_STATE
Description
I2Cn_IF
Required interaction
Response
0x41
Repeated START received
RSTART interrupt flag
(BUSHOLD interrupt
flag)
RXDATA
Receive and compare address
0x75
ADDR + R received
ADDR interrupt flag
ACK + TXDA- ACK will be sent, then DATA
TA
RXDATA interrupt flag
NACK
NACK will be sent, slave goes idle
(BUSHOLD interrupt
flag)
NACK +
CONT +
TXDATA
NACK will be sent, then DATA.
-
Data transmitted
TXBL interrupt flag
(TXC interrupt flag)
None
0xD5
Data transmitted, ACK
received
ACK interrupt flag
(BUSHOLD interrupt
flag)
TXDATA
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I2Cn_STATE
Description
0xDD
-
-
Required interaction
Response
Data transmitted, NACK NACK interrupt flag
received
(BUSHOLD interrupt
flag)
None
The slave goes idle
CONT +
TXDATA
DATA will be transmitted
Stop received
None
The slave goes idle
START
START will be sent when bus becomes idle
Arbitration lost
I2Cn_IF
SSTOP interrupt flag
ARBLOST interrupt flag None
START
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15.3.9.4 Slave Receiver
A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted
by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiver mode.
To receive data from the master, the slave should respond to the address with an ACK and make sure space is available in the receive
buffer. Transmission will then continue, and the slave will receive a byte from the master.
If a NACK is sent without a CONT, the transmission is ended for the slave, and it goes idle. If the slave issues both the NACK and
CONT commands and has space available in the receive buffer, it will be open for continuing reception from the master.
When a byte has been received from the master, the slave must ACK or NACK the byte. The responses here are the same as for the
reception of the address byte.
The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag is set when the master transmits
a STOP condition. If the transmission is ended with a repeated START, then the SSTOP interrupt flag in I2Cn_IF is not set.
Note:
The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is participating in the transmission or not, as long as
SLAVE in I2Cn_CTRL is set and a STOP condition is detected
If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the bus is released and the slave
goes idle.
See Table 15.8 I2C - Slave Receiver on page 406 for more information.
Table 15.8. I2C - Slave Receiver
I2Cn_STATE
Description
I2Cn_IF
Required interaction
Response
-
Repeated START received
RSTART interrupt flag
(BUSHOLD interrupt
flag)
RXDATA
Receive and compare address
0x71
ADDR + W received
ADDR interrupt flag
RXDATA interrupt flag
(BUSHOLD interrupt
flag)
ACK +
RXDATA
ACK will be sent and data will be received
NACK
NACK will be sent, slave goes idle
NACK +
CONT +
RXDATA
NACK will be sent and DATA will be received.
ACK +
RXDATA
ACK will be sent and data will be received
NACK
NACK will be sent and slave will go idle
NACK +
CONT +
RXDATA
NACK will be sent and data will be received
None
The slave goes idle
START
START will be sent when bus becomes idle
0xB1
-
-
Data received
Stop received
Arbitration lost
RXDATA interrupt flag
(BUSHOLD interrupt
flag)
SSTOP interrupt flag
ARBLOST interrupt flag None
START
The slave goes idle
START will be sent when the bus becomes idle
15.3.10 Transfer Automation
The I2C can be set up to complete transfers with a minimal amount of interaction.
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15.3.10.1 DMA
DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, software is thus relieved of moving data to and from memory after each transferred byte.
15.3.10.2 Automatic ACK
When AUTOACK in I2Cn_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority
interactions are pending.
15.3.10.3 Automatic STOP
A STOP can be generated automatically on two conditions. These apply only to the master transmitter.
If AUTOSN in I2Cn_CTRL is set, the I2C module ends a transmission by transmitting a STOP condition when operating as a master
transmitter and a NACK is received.
If AUTOSE in I2Cn_CTRL is set, the I2C module always ends a transmission when there is no more data in the transmit buffer. If data
has been transmitted on the bus, the transmission is ended after the (N)ACK has been received by the slave. If a START is sent when
no data is available in the transmit buffer and AUTOSE is set, then the STOP condition is sent immediately following the START. Software must thus make sure data is available in the transmit buffer before the START condition has been fully transmitted if data is to be
transferred.
15.3.11 Using 10-bit Addresses
When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of
the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be given on all 10-bit addresses where the two
most significant bits are correct.
When receiving an address match, the slave must acknowledge the address and receive the first data byte. This byte contains the second part of the 10-bit address. If it matches the address of the slave, the slave should ACK the byte to continue the transmission, and if
it does not match, the slave should NACK it.
When the master is operating as a master transmitter, the data bytes will follow after the second address byte. When the master is
operating as a master receiver however, a repeated START condition is sent after the second address byte. The address sent after this
repeated START is equal to the first of the address bytes transmitted previously, but now with the R/W byte set, and only the slave that
found a match on the entire 10-bit address in the previous message should ACK this address. The repeated start should take the master into a master receiver mode, and after the single address byte sent this time around, the slave begins transmission to the master.
15.3.12 Error Handling
Note:
The setting of GCAMEN and SLAVE fields in the I2Cn_CTRL register and the registers I2Cn_SADDR and I2Cn_ROUTELOC0 are considered static. This means that these need to be set before an I2C transaction starts and need to stay stable during the entire transaction.
15.3.12.1 ABORT Command
Some bus errors may require software intervention to be resolved. The I2C module provides an ABORT command, which can be set in
I2Cn_CMD, to help resolve bus errors.
When the bus for some reason is locked up and the I2C module is in the middle of a transmission it cannot get out of, or for some other
reason the I2C wants to abort a transmission, the ABORT command can be used.
Setting the ABORT command will make the I2C module discard any data currently being transmitted or received, release the SDA and
SCL lines and go to an idle mode. ABORT effectively makes the I2C module forget about any ongoing transfers.
15.3.12.2 Bus Reset
A bus reset can be performed by setting the START and STOP commands in I2Cn_CMD while the transmit buffer is empty. A START
condition will then be transmitted, immediately followed by a STOP condition. A bus reset can also be performed by transmitting a
START command with the transmit buffer empty and AUTOSE set.
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15.3.12.3 I2C-Bus Errors
An I2C-bus error occurs when a START or STOP condition is misplaced, which happens when the value on SDA changes while SCL is
high during bit-transmission on the I2C-bus. If the I2C module is part of the current transmission when a bus error occurs, any data
currently being transmitted or received is discarded, SDA and SCL are released, the BUSERR interrupt flag in I2Cn_IF is set to indicate
the error, and the module automatically takes a course of action as defined in Table 15.9 I2C Bus Error Response on page 408.
Table 15.9. I2C Bus Error Response
In a master/slave operation
Misplaced START
Misplaced STOP
Treated as START. Receive address.
Go idle. Perform any pending actions.
15.3.12.4 Bus Lockup
A lockup occurs when a master or slave on the I2C-bus has locked the SDA or SCL at a low value, preventing other devices from putting high values on the bus, and thus making communication on the bus impossible.
Many slave-only devices operating on an I2C-bus are not capable of driving SCL low, but in the rare case that SCL is stuck LOW, the
advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in order to
make them release SCL.
When SDA is stuck low and SCL is free, a master should send 9 clock pulses on SCL while tristating the SDA. This procedure is performed in the GPIO module after clearing the I2C_ROUTE register and disabling the I2C module. The device that held the bus low
should release it sometime within those 9 clocks. If not, use the same approach as for when SCL is stuck, resetting and possibly cycling
power to the slaves.
Lockup of SDA can be detected by keeping count of the number of continuous arbitration losses during address transmission. If arbitration is also lost during the transmission of a general call address, i.e., during the transmission of the STOP condition, which should
never happen during normal operation, this is a good indication of SDA lockup.
Detection of SCL lockups can be done using the timeout functionality defined in 15.3.12.6 Clock Low Timeout
15.3.12.5 Bus Idle Timeout
When SCL has been high for a significant amount of time, this is a good indication of that the bus is idle. On an SMBus system, the bus
is only allowed to be in this state for a maximum of 50 µs before the bus is considered idle.
The bus idle timeout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the middle of a transmission. The
timeout can be configured in BITO, and when the bus has been idle for the given amount of time, the BITO interrupt flag in I2Cn_IF is
set. The bus can also be set idle automatically on a bus idle timeout. This is enabled by setting GIBITO in I2Cn_CTRL.
When the bus idle timer times out, it wraps around and continues counting as long as its condition is true. If the bus is not set idle using
GIBITO or the ABORT command in I2Cn_CMD, this will result in periodic timeouts.
Note:
This timeout will be generated even if SDA is held low.
The bus idle timeout is active as long as the bus is busy, i.e., BUSY in I2Cn_STATUS is set. The timeout can be used to get the I2C
module out of the busy-state it enters when reset, see 15.3.7.4 Reset State.
15.3.12.6 Clock Low Timeout
The clock timeout, which can be configured in CLTO in I2Cn_CTRL, starts counting whenever SCL goes low, and times out if SCL does
not go high within the configured timeout. A clock low timeout results in CLTOIF in I2Cn_IF being set, allowing software to take action.
When the timer times out, it wraps around and continues counting as long as SCL is low. An SCL lockup will thus result in periodic clock
low timeouts as long as SCL is low.
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15.3.12.7 Clock Low Error
The I2C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications
are identical. A case may arise when (before an arbitration has been decided upon) the I2C module decides to send out a repeated
START or a STOP condition while the other device is still sending data. In the I2C protocol specifications, such a combination results in
an undefined condition. The I2C deals with this by generating a clock low error. This means that if the I2C is transmitting a repeated
START or a STOP condition and another device (another master or a misbehaving slave) pulls SCL low before the I2C sends out the
START/STOP condition on SDA, a clock low error is generated. The CLERR interrupt flag is then set in the I2Cn_IF register, any held
lines are released and the I2C device goes to idle.
15.3.13 DMA Support
The I2C module has full DMA support. A request for the DMA controller to write to the I2C transmit buffer can come from TXBL (transmit
buffer has room for more data). The DMA controller can write to the transmit buffer using the I2Cn_TXDATA or the I2Cn_TXDOUBLE
register. In order to write to the I2Cn_TXDOUBLE register (i.e., transferring 2 bytes simultaneously to the transmit buffer using the
DMA), DMA_USEBURSTS needs to be set to 1 for the selected DMA channel. This ensures that the transfer is made to the transmit
buffer only when both buffer elements are empty. For performing a DMA write to the I2Cn_TXDATA register, DMA_USEBURSTC needs
to be set to 1 for the selected DMA channel. This ensures that a DMA transfer is made even when the transmit buffer is half-empty.
A request for the DMA controller to read from the I2C receive buffer can come from RXDATAV (data available in the receive buffer). To
receive from I2Cn_RXDOUBLE (i.e., receive only when both buffer elements are full), DMA_USEBURSTS needs to be set to 1 for the
selected DMA channel. In order to receive from I2Cn_RXDATA through the DMA, DMA_USEBURSTC needs to be set to 1. This ensures that the data gets picked up even when the receive buffer is half-full.
15.3.14 Interrupts
The interrupts generated by the I2C module are combined into one interrupt vector, I2C_INT. If I2C interrupts are enabled, an interrupt
will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.
15.3.15 Wake-up
The I2C receive section can be active all the way down to energy mode EM3 Stop, and can wake up the CPU on address interrupt. All
address match modes are supported.
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15.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
I2Cn_CTRL
RW
Control Register
0x004
I2Cn_CMD
W1
Command Register
0x008
I2Cn_STATE
R
State Register
0x00C
I2Cn_STATUS
R
Status Register
0x010
I2Cn_CLKDIV
RW
Clock Division Register
0x014
I2Cn_SADDR
RW
Slave Address Register
0x018
I2Cn_SADDRMASK
RW
Slave Address Mask Register
0x01C
I2Cn_RXDATA
R(a)
Receive Buffer Data Register
0x020
I2Cn_RXDOUBLE
R(a)
Receive Buffer Double Data Register
0x024
I2Cn_RXDATAP
R
Receive Buffer Data Peek Register
0x028
I2Cn_RXDOUBLEP
R
Receive Buffer Double Data Peek Register
0x02C
I2Cn_TXDATA
W
Transmit Buffer Data Register
0x030
I2Cn_TXDOUBLE
W
Transmit Buffer Double Data Register
0x034
I2Cn_IF
R
Interrupt Flag Register
0x038
I2Cn_IFS
W1
Interrupt Flag Set Register
0x03C
I2Cn_IFC
(R)W1
Interrupt Flag Clear Register
0x040
I2Cn_IEN
RW
Interrupt Enable Register
0x044
I2Cn_ROUTEPEN
RW
I/O Routing Pin Enable Register
0x048
I2Cn_ROUTELOC0
RW
I/O Routing Location Register
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I2C - Inter-Integrated Circuit Interface
15.5 Register Description
15.5.1 I2Cn_CTRL - Control Register
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0
0
RW
EN
1
0
RW
SLAVE
2
0
AUTOACK RW
3
0
RW
AUTOSE
4
0
RW
AUTOSN
5
0
RW
ARBDIS
6
0
RW
GCAMEN
7
0
RW
TXBIL
8
9
RW 0x0
CLHR
10
11
12
13
RW 0x0
BITO
14
16
18
19
20
21
15
0
RW
GIBITO
Name
RW 0x0 17
Access
CLTO
Reset
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
31:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18:16
CLTO
0x0
RW
Description
Clock Low Timeout
Use to generate a timeout when CLK has been low for the given amount of time. Wraps around and continues counting
when the timeout is reached. The timeout value can be calculated by
timeout = PCC/(fSCL x (Nlow + Nhigh))
15
Value
Mode
Description
0
OFF
Timeout disabled
1
40PCC
Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 50us timeout.
2
80PCC
Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 100us timeout.
3
160PCC
Timeout after 160 prescaled clock cycles. In standard mode at 100
kHz, this results in a 200us timeout.
4
320PCC
Timeout after 320 prescaled clock cycles. In standard mode at 100
kHz, this results in a 400us timeout.
5
1024PCC
Timeout after 1024 prescaled clock cycles. In standard mode at 100
kHz, this results in a 1280us timeout.
GIBITO
0
RW
Go Idle on Bus Idle Timeout
When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated.
Value
Description
0
A bus idle timeout has no effect on the bus state.
1
A bus idle timeout tells the I2C module that the bus is idle, allowing new
transfers to be initiated.
14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:12
BITO
0x0
RW
Bus Idle Timeout
Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When
in a bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value
defined by BITO, it sets the BITO interrupt flag. The BITO interrupt flag will then be set periodically as long as SCL remains
high. The bus idle timeout is active as long as BUSY is set. It is thus stopped automatically on a timeout if GIBITO is set. It
is also stopped a STOP condition is detected and when the ABORT command is issued. The timeout is activated whenever
the bus goes BUSY, i.e. a START condition is detected. The timeout value can be calculated by
timeout = PCC/(fSCL x (Nlow + Nhigh))
Value
Mode
Description
0
OFF
Timeout disabled
1
40PCC
Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 50us timeout.
2
80PCC
Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 100us timeout.
3
160PCC
Timeout after 160 prescaled clock cycles. In standard mode at 100
kHz, this results in a 200us timeout.
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Bit
Name
Reset
Access
11:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:8
CLHR
0x0
RW
Description
Clock Low High Ratio
Determines the ratio between the low and high parts of the clock signal generated on SCL as master.
7
Value
Mode
Description
0
STANDARD
The ratio between low period and high period counters (Nlow:Nhigh) is
4:4
1
ASYMMETRIC
The ratio between low period and high period counters (Nlow:Nhigh) is
6:3
2
FAST
The ratio between low period and high period counters (Nlow:Nhigh) is
11:6
TXBIL
0
RW
TX Buffer Interrupt Level
Determines the interrupt and status level of the transmit buffer.
6
Value
Mode
Description
0
EMPTY
TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty.
1
HALFFULL
TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer
becomes full.
GCAMEN
0
RW
General Call Address Match Enable
Set to enable address match on general call in addition to the programmed slave address.
5
Value
Description
0
General call address will be NACK'ed if it is not included by the slave
address and address mask.
1
When a general call address is received, a software response is required.
ARBDIS
0
RW
Arbitration Disable
A master or slave will not release the bus upon losing arbitration.
4
Value
Description
0
When a device loses arbitration, the ARB interrupt flag is set and the
bus is released.
1
When a device loses arbitration, the ARB interrupt flag is set, but communication proceeds.
AUTOSN
0
RW
Automatic STOP on NACK
Write to 1 to make a master transmitter send a STOP when a NACK is received from a slave.
Value
Description
0
Stop is not automatically sent if a NACK is received from a slave.
1
The master automatically sends a STOP if a NACK is received from a
slave.
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
3
AUTOSE
0
RW
Automatic STOP when Empty
Write to 1 to make a master transmitter send a STOP when no more data is available for transmission.
2
Value
Description
0
A stop must be sent manually when no more data is to be transmitted.
1
The master automatically sends a STOP when no more data is available for transmission.
AUTOACK
0
RW
Automatic Acknowledge
Set to enable automatic acknowledges.
1
Value
Description
0
Software must give one ACK command for each ACK transmitted on
the I2C bus.
1
Addresses that are not automatically NACK'ed, and all data is automatically acknowledged.
SLAVE
0
RW
Addressable as Slave
Set this bit to allow the device to be selected as an I2C slave.
0
Value
Description
0
All addresses will be responded to with a NACK
1
Addresses matching the programmed slave address or the general call
address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK.
EN
0
RW
I2C Enable
Use this bit to enable or disable the I2C module.
Value
Description
0
The I2C module is disabled. And its internal state is cleared
1
The I2C module is enabled.
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I2C - Inter-Integrated Circuit Interface
15.5.2 I2Cn_CMD - Command Register
Access
5
4
3
2
1
0
W1 0
W1 0
W1 0
W1 0
W1 0
W1 0
ABORT
CONT
NACK
ACK
STOP
START
6
8
9
10
CLEARTX W1 0
Name
7
Access
CLEARPC W1 0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Bit
Name
Reset
Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
CLEARPC
0
W1
Clear Pending Commands
W1
Clear TX
Set to clear pending commands.
6
CLEARTX
0
Set to clear transmit buffer and shift register. Will not abort ongoing transfer.
5
ABORT
0
W1
Abort transmission
Abort the current transmission making the bus go idle. When used in combination with STOP, a STOP condition is sent as
soon as possible before aborting the transmission. The stop condition is subject to clock synchronization.
4
CONT
0
W1
Continue transmission
Set to continue transmission after a NACK has been received.
3
NACK
0
W1
Send NACK
Set to transmit a NACK the next time an acknowledge is required.
2
ACK
0
W1
Send ACK
Set to transmit an ACK the next time an acknowledge is required.
1
STOP
0
W1
Send stop condition
Set to send stop condition as soon as possible.
0
START
0
W1
Send start condition
Set to send start condition as soon as possible. If a transmission is ongoing and not owned, the start condition will be sent
as soon as the bus is idle. If the current transmission is owned by this module, a repeated start condition will be sent. Use
in combination with a STOP command to automatically send a STOP, then a START when the bus becomes idle.
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I2C - Inter-Integrated Circuit Interface
15.5.3 I2Cn_STATE - State Register
Access
4
3
2
1
0
0
0
0
0
1
R
TRANSMITTER R
R
R
NACKED
MASTER
BUSY
5
R
STATE
Name
BUSHOLD
R
Access
0x0 6
Reset
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Bit
Name
Reset
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:5
STATE
0x0
R
Description
Transmission State
The state of any current transmission. Cleared if the I2C module is idle.
4
Value
Mode
Description
0
IDLE
No transmission is being performed.
1
WAIT
Waiting for idle. Will send a start condition as soon as the bus is idle.
2
START
Start transmitted or received
3
ADDR
Address transmitted or received
4
ADDRACK
Address ack/nack transmitted or received
5
DATA
Data transmitted or received
6
DATAACK
Data ack/nack transmitted or received
BUSHOLD
0
R
Bus Held
Set if the bus is currently being held by this I2C module.
3
NACKED
0
R
Nack Received
Set if a NACK was received and STATE is ADDRACK or DATAACK.
2
TRANSMITTER
0
R
Transmitter
Set when operating as a master transmitter or a slave transmitter. When cleared, the system may be operating as a master
receiver, a slave receiver or the current mode is not known.
1
MASTER
0
R
Master
Set when operating as an I2C master. When cleared, the system may be operating as an I2C slave.
0
BUSY
1
R
Bus Busy
Set when the bus is busy. Whether the I2C module is in control of the bus or not has no effect on the value of this bit. When
the MCU comes out of reset, the state of the bus is not known, and thus BUSY is set. Use the ABORT command or a bus
idle timeout to force the I2C module out of the BUSY state.
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I2C - Inter-Integrated Circuit Interface
15.5.4 I2Cn_STATUS - Status Register
Access
0
R
PSTART
0
1
R
PSTOP
0
2
3
R
PACK
0
R
PNACK
Bit
Name
Reset
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9
RXFULL
0
R
0
4
R
PCONT
0
5
0
R
PABORT
6
0
R
TXC
7
1
R
TXBL
Name
8
0
RXDATAV R
9
0
10
RXFULL
Access
R
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Description
RX FIFO Full
Set when the receive buffer is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room
for one more frame in the receive shift register.
8
RXDATAV
0
R
RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
7
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
6
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.
5
PABORT
0
R
Pending abort
An abort is pending and will be transmitted as soon as possible.
4
PCONT
0
R
Pending continue
A continue is pending and will be transmitted as soon as possible.
3
PNACK
0
R
Pending NACK
A not-acknowledge is pending and will be transmitted as soon as possible.
2
PACK
0
R
Pending ACK
An acknowledge is pending and will be transmitted as soon as possible.
1
PSTOP
0
R
Pending STOP
A stop condition is pending and will be transmitted as soon as possible.
0
PSTART
0
R
Pending START
A start condition is pending and will be transmitted as soon as possible.
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I2C - Inter-Integrated Circuit Interface
15.5.5 I2Cn_CLKDIV - Clock Division Register
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
DIV
0x000
RW
0
31:9
0
Access
1
Reset
1
Name
2
Bit
3
Name
2
Access
3
Reset
DIV RW 0x000 4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Description
Clock Divider
Specifies the clock divider for the I2C. Note that DIV must be 1 or higher when slave is enabled.
15.5.6 I2Cn_SADDR - Slave Address Register
Access
Name
Access
5
6
7
8
9
10
11
12
13
ADDR RW 0x00 4
Reset
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x014
Bit Position
31
Offset
Bit
Name
Reset
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:1
ADDR
0x00
RW
Description
Slave address
Specifies the slave address of the device.
0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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15.5.7 I2Cn_SADDRMASK - Slave Address Mask Register
Reset
Access
Name
Access
Bit
Name
Reset
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:1
MASK
0x00
RW
0
1
2
3
MASK RW 0x00 4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Description
Slave Address Mask
Specifies the significant bits of the slave address. Setting the mask to 0x00 will match all addresses, while setting it to 0x7F
will only match the exact address specified by ADDR.
0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads)
0
1
2
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Reset
RXDATA R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
RXDATA
0x00
R
Description
RX Data
Use this register to read from the receive buffer. Buffer is emptied on read access.
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15.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads)
1
0
0
3
4
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:8
RXDATA1
0x00
R
1
Access
2
Name
2
RXDATA1 R
Access
RXDATA0 R
Reset
0x00
5
6
7
8
9
10
11
12
0x00
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Description
RX Data 1
Second byte read from buffer. Buffer is emptied on read access.
7:0
RXDATA0
0x00
R
RX Data 0
First byte read from buffer. Buffer is emptied on read access.
15.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Reset
RXDATAP R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
RXDATAP
0x00
R
Description
RX Data Peek
Use this register to read from the receive buffer. Buffer is not emptied on read access.
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15.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register
1
0
0
3
4
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:8
RXDATAP1
0x00
R
1
Access
2
Name
2
RXDATAP1 R
Access
RXDATAP0 R
Reset
0x00
5
6
7
8
9
10
11
12
0x00
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Description
RX Data 1 Peek
Second byte read from buffer. Buffer is not emptied on read access.
7:0
RXDATAP0
0x00
R
RX Data 0 Peek
First byte read from buffer. Buffer is not emptied on read access.
15.5.12 I2Cn_TXDATA - Transmit Buffer Data Register
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
Reset
TXDATA W
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TXDATA
0x00
W
Description
TX Data
Use this register to write a byte to the transmit buffer.
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15.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register
TXDATA1 W
Access
Name
Access
0
1
2
3
4
0x00
6
7
8
9
5
TXDATA0 W
Reset
10
11
12
0x00
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Bit
Name
Reset
Description
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:8
TXDATA1
0x00
W
TX Data
W
TX Data
Second byte to write to buffer.
7:0
TXDATA0
0x00
First byte to write to buffer.
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15.5.14 I2Cn_IF - Interrupt Flag Register
0
R
START
0
1
R
RSTART
0
2
3
R
ADDR
0
R
TXC
0
4
R
TXBL
1
5
0
R
RXDATAV
6
0
R
ACK
7
0
R
NACK
8
0
R
MSTOP
9
0
R
ARBLOST
10
0
R
BUSERR
11
0
BUSHOLD R
12
0
R
TXOF
13
0
R
RXUF
14
0
R
BITO
15
0
R
CLTO
16
0
R
SSTOP
17
0
R
RXFULL
18
Name
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0
R
19
20
21
Access
CLERR
Reset
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
31:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18
CLERR
0
R
Description
Clock Low Error Interrupt Flag
Set when the clock is pulled low before a START or a STOP condition could be transmitted.
17
RXFULL
0
R
Receive Buffer Full Interrupt Flag
Set when the receive buffer becomes full.
16
SSTOP
0
R
Slave STOP condition Interrupt Flag
Set when a STOP condition has been received. Will be set regardless of the slave being involved in the transaction or not.
15
CLTO
0
R
Clock Low Timeout Interrupt Flag
Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register.
14
BITO
0
R
Bus Idle Timeout Interrupt Flag
Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register.
13
RXUF
0
R
Receive Buffer Underflow Interrupt Flag
Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty. It is also
set when data is read through the I2Cn_RXDOUBLE while the buffer is not full.
12
TXOF
0
R
Transmit Buffer Overflow Interrupt Flag
Set when data is written to the transmit buffer while the transmit buffer is full.
11
BUSHOLD
0
R
Bus Held Interrupt Flag
Set when the bus becomes held by the I2C module.
10
BUSERR
0
R
Bus Error Interrupt Flag
Set when a bus error is detected. The bus error is resolved automatically, but the current transfer is aborted.
9
ARBLOST
0
R
Arbitration Lost Interrupt Flag
R
Master STOP Condition Interrupt Flag
Set when arbitration is lost.
8
MSTOP
0
Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP
condition, then the MSTOP interrupt flag is not set.
7
NACK
0
R
Not Acknowledge Received Interrupt Flag
R
Acknowledge Received Interrupt Flag
R
Receive Data Valid Interrupt Flag
Set when a NACK has been received.
6
ACK
0
Set when an ACK has been received.
5
RXDATAV
0
Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read.
4
TXBL
1
R
Transmit Buffer Level Interrupt Flag
Set when the transmit buffer becomes empty. Cleared automatically when new data is written to the transmit buffer.
3
TXC
0
R
Transfer Completed Interrupt Flag
Set when the transmit shift register becomes empty and there is no more data in the transmit buffer.
2
ADDR
0
R
Address Interrupt Flag
Set when incoming address is accepted, i.e. own address or general call address is received.
1
RSTART
0
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R
Repeated START condition Interrupt Flag
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
Set when a repeated start condition is detected.
0
START
0
R
START condition Interrupt Flag
Set when a start condition is successfully transmitted.
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I2C - Inter-Integrated Circuit Interface
15.5.15 I2Cn_IFS - Interrupt Flag Set Register
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0
W1 0
START
1
W1 0
RSTART
2
W1 0
ADDR
3
W1 0
TXC
W1 0
ACK
4
W1 0
NACK
5
W1 0
MSTOP
6
W1 0
ARBLOST
7
10
W1 0
BUSERR
8
11
BUSHOLD W1 0
9
12
W1 0
TXOF
13
W1 0
RXUF
14
W1 0
BITO
15
W1 0
CLTO
16
W1 0
SSTOP
17
W1 0
18
19
20
21
RXFULL
Name
W1 0
Access
CLERR
Reset
22
23
24
25
26
27
28
29
30
0x038
Bit Position
31
Offset
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
31:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18
CLERR
0
W1
Set CLERR Interrupt Flag
W1
Set RXFULL Interrupt Flag
Write 1 to set the CLERR interrupt flag
17
RXFULL
0
Write 1 to set the RXFULL interrupt flag
16
SSTOP
0
W1
Set SSTOP Interrupt Flag
W1
Set CLTO Interrupt Flag
W1
Set BITO Interrupt Flag
W1
Set RXUF Interrupt Flag
W1
Set TXOF Interrupt Flag
W1
Set BUSHOLD Interrupt Flag
Write 1 to set the SSTOP interrupt flag
15
CLTO
0
Write 1 to set the CLTO interrupt flag
14
BITO
0
Write 1 to set the BITO interrupt flag
13
RXUF
0
Write 1 to set the RXUF interrupt flag
12
TXOF
0
Write 1 to set the TXOF interrupt flag
11
BUSHOLD
0
Write 1 to set the BUSHOLD interrupt flag
10
BUSERR
0
W1
Set BUSERR Interrupt Flag
Write 1 to set the BUSERR interrupt flag
9
ARBLOST
0
W1
Set ARBLOST Interrupt Flag
Write 1 to set the ARBLOST interrupt flag
8
MSTOP
0
W1
Set MSTOP Interrupt Flag
W1
Set NACK Interrupt Flag
W1
Set ACK Interrupt Flag
Write 1 to set the MSTOP interrupt flag
7
NACK
0
Write 1 to set the NACK interrupt flag
6
ACK
0
Write 1 to set the ACK interrupt flag
5:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
TXC
0
W1
Set TXC Interrupt Flag
W1
Set ADDR Interrupt Flag
W1
Set RSTART Interrupt Flag
Write 1 to set the TXC interrupt flag
2
ADDR
0
Write 1 to set the ADDR interrupt flag
1
RSTART
0
Write 1 to set the RSTART interrupt flag
0
START
0
W1
Set START Interrupt Flag
Write 1 to set the START interrupt flag
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0x03C
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(R)W1 0
(R)W1 0
(R)W1 0
MSTOP
NACK
ACK
(R)W1 0
(R)W1 0
ARBLOST
START
(R)W1 0
BUSERR
(R)W1 0
BUSHOLD (R)W1 0
RSTART
(R)W1 0
TXOF
(R)W1 0
(R)W1 0
RXUF
(R)W1 0
10
(R)W1 0
BITO
ADDR
11
(R)W1 0
CLTO
TXC
12
(R)W1 0
SSTOP
0
1
2
3
4
5
6
7
8
9
13
14
15
16
Offset
17
(R)W1 0
18
19
20
21
RXFULL
Name
(R)W1 0
Access
CLERR
Reset
22
23
24
25
26
27
28
29
30
31
I2C - Inter-Integrated Circuit Interface
EFM32JG1 Reference Manual
15.5.16 I2Cn_IFC - Interrupt Flag Clear Register
Bit Position
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
31:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18
CLERR
0
(R)W1
Description
Clear CLERR Interrupt Flag
Write 1 to clear the CLERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
17
RXFULL
0
(R)W1
Clear RXFULL Interrupt Flag
Write 1 to clear the RXFULL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
16
SSTOP
0
(R)W1
Clear SSTOP Interrupt Flag
Write 1 to clear the SSTOP interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
15
CLTO
0
(R)W1
Clear CLTO Interrupt Flag
Write 1 to clear the CLTO interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
14
BITO
0
(R)W1
Clear BITO Interrupt Flag
Write 1 to clear the BITO interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
13
RXUF
0
(R)W1
Clear RXUF Interrupt Flag
Write 1 to clear the RXUF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
12
TXOF
0
(R)W1
Clear TXOF Interrupt Flag
Write 1 to clear the TXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
11
BUSHOLD
0
(R)W1
Clear BUSHOLD Interrupt Flag
Write 1 to clear the BUSHOLD interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
10
BUSERR
0
(R)W1
Clear BUSERR Interrupt Flag
Write 1 to clear the BUSERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
9
ARBLOST
0
(R)W1
Clear ARBLOST Interrupt Flag
Write 1 to clear the ARBLOST interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
8
MSTOP
0
(R)W1
Clear MSTOP Interrupt Flag
Write 1 to clear the MSTOP interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
7
NACK
0
(R)W1
Clear NACK Interrupt Flag
Write 1 to clear the NACK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
6
ACK
0
(R)W1
Clear ACK Interrupt Flag
Write 1 to clear the ACK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
5:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
TXC
0
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(R)W1
Clear TXC Interrupt Flag
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
Write 1 to clear the TXC interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
2
ADDR
0
(R)W1
Clear ADDR Interrupt Flag
Write 1 to clear the ADDR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
1
RSTART
0
(R)W1
Clear RSTART Interrupt Flag
Write 1 to clear the RSTART interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
0
START
0
(R)W1
Clear START Interrupt Flag
Write 1 to clear the START interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
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0x040
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RW 0
START
RW 0
ACK
RW 0
RW 0
NACK
RSTART
RW 0
MSTOP
RW 0
RW 0
ARBLOST
RW 0
RW 0
BUSERR
ADDR
BUSHOLD RW 0
TXC
RW 0
TXOF
RW 0
RW 0
RXUF
TXBL
10
RW 0
BITO
RW 0
11
RW 0
CLTO
RXDATAV
12
RW 0
SSTOP
0
1
2
3
4
5
6
7
8
9
13
14
15
16
Offset
17
RW 0
18
19
20
21
RXFULL
Name
RW 0
Access
CLERR
Reset
22
23
24
25
26
27
28
29
30
31
I2C - Inter-Integrated Circuit Interface
EFM32JG1 Reference Manual
15.5.17 I2Cn_IEN - Interrupt Enable Register
Bit Position
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
31:19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18
CLERR
0
RW
CLERR Interrupt Enable
RW
RXFULL Interrupt Enable
RW
SSTOP Interrupt Enable
RW
CLTO Interrupt Enable
RW
BITO Interrupt Enable
RW
RXUF Interrupt Enable
RW
TXOF Interrupt Enable
RW
BUSHOLD Interrupt Enable
Enable/disable the CLERR interrupt
17
RXFULL
0
Enable/disable the RXFULL interrupt
16
SSTOP
0
Enable/disable the SSTOP interrupt
15
CLTO
0
Enable/disable the CLTO interrupt
14
BITO
0
Enable/disable the BITO interrupt
13
RXUF
0
Enable/disable the RXUF interrupt
12
TXOF
0
Enable/disable the TXOF interrupt
11
BUSHOLD
0
Enable/disable the BUSHOLD interrupt
10
BUSERR
0
RW
BUSERR Interrupt Enable
RW
ARBLOST Interrupt Enable
RW
MSTOP Interrupt Enable
RW
NACK Interrupt Enable
RW
ACK Interrupt Enable
RW
RXDATAV Interrupt Enable
RW
TXBL Interrupt Enable
RW
TXC Interrupt Enable
RW
ADDR Interrupt Enable
RW
RSTART Interrupt Enable
RW
START Interrupt Enable
Enable/disable the BUSERR interrupt
9
ARBLOST
0
Enable/disable the ARBLOST interrupt
8
MSTOP
0
Enable/disable the MSTOP interrupt
7
NACK
0
Enable/disable the NACK interrupt
6
ACK
0
Enable/disable the ACK interrupt
5
RXDATAV
0
Enable/disable the RXDATAV interrupt
4
TXBL
0
Enable/disable the TXBL interrupt
3
TXC
0
Enable/disable the TXC interrupt
2
ADDR
0
Enable/disable the ADDR interrupt
1
RSTART
0
Enable/disable the RSTART interrupt
0
START
0
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
Enable/disable the START interrupt
15.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
SCLPEN
0
RW
0
2
SDAPEN RW 0
Name
1
Access
SCLPEN RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Description
SCL Pin Enable
When set, the SCL pin of the I2C is enabled.
0
SDAPEN
0
RW
SDA Pin Enable
When set, the SDA pin of the I2C is enabled.
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I2C - Inter-Integrated Circuit Interface
15.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register
Name
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5
SDALOC RW 0x00
Access
SCLLOC RW 0x00
Reset
22
23
24
25
26
27
28
29
30
0x048
Bit Position
31
Offset
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EFM32JG1 Reference Manual
I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
SCLLOC
0x00
RW
Description
I/O Location
Decides the location of the I2C SCL pin.
7:6
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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I2C - Inter-Integrated Circuit Interface
Bit
Name
Reset
Access
Description
5:0
SDALOC
0x00
RW
I/O Location
Decides the location of the I2C SDA pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16. USART - Universal Synchronous Asynchronous Receiver/Transmitter
Quick Facts
What?
0 1 2 3
4
The USART handles high-speed UART, SPI-bus,
SmartCards, and IrDA communication.
Why?
DMA
controller
Serial communication is frequently used in embedded systems and the USART allows efficient communication with a wide range of external devices.
RAM
How?
USART
RX/
MISO
TX/
MOSI
IrDA SmartCards
USART
SPI
The USART has a wide selection of operating
modes, frame formats and baud rates. The multiprocessor mode allows the USART to remain idle
when not addressed. Triple buffering and DMA support makes high data-rates possible with minimal
CPU intervention and it is possible to transmit and
receive large frames while the MCU remains in EM1
Sleep.
CLK
µC
CS
16.1 Introduction
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, and IrDA devices.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.2 Features
•
•
•
•
•
Asynchronous and synchronous (SPI) communication
Full duplex and half duplex
Separate TX/RX enable
Separate receive / transmit multiple entry buffers, with additional separate shift registers
Programmable baud rate, generated as an fractional division from the peripheral clock (HFPERCLKUSARTn)
• Max bit-rate
• SPI master mode, peripheral clock rate/2
• SPI slave mode, peripheral clock rate/8
• UART mode, peripheral clock rate/16, 8, 6, or 4
• Asynchronous mode supports
• Majority vote baud-reception
• False start-bit detection
• Break generation/detection
• Multi-processor mode
• Synchronous mode supports
• All 4 SPI clock polarity/phase configurations
• Master and slave mode
• Data can be transmitted LSB first or MSB first
• Configurable number of data bits, 4-16 (plus the parity bit, if enabled)
• HW parity bit generation and check
• Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2
• HW collision detection
• Multi-processor mode
• IrDA modulator on USART0
• SmartCard (ISO7816) mode
• I2S mode
• Separate interrupt vectors for receive and transmit interrupts
• Loopback mode
• Half duplex communication
• Communication debugging
• PRS RX input
• 8 bit Timer
• Hardware Flow Control
• Automatic Baud Rate Detection
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.3 Functional Description
An overview of the USART module is shown in Figure 16.1 USART Overview on page 439.
USn_CTS
Peripheral Bus
USn_RTS
USn_CS
UART Control
and status
TX Buffer
(2-level FIFO)
RX Buffer
(2-level FIFO)
!RXBLOCK
U(S)n_TX
Pin
ctrl
IrDA
modulator
TX Shift Register
RX Shift Register
USn_CLK
TIMECMP0
Timer
U(S)n_RX
PRS inputs
TIMECMP1
TIMECMP2
Baud rate
generator
Auto Baud
Detection
IrDA
demodulator
Figure 16.1 USART Overview
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.3.1 Modes of Operation
The USART operates in either asynchronous or synchronous mode.
In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both
the master and slave sample and transmit data according to this clock. Both master and slave modes are supported by the USART. The
synchronous communication mode is compatible with the Serial Peripheral Interface Bus (SPI) standard.
In asynchronous mode, no separate clock signal is transmitted with the data on the bus. The USART receiver thus has to determine
where to sample the data on the bus from the actual data. To make this possible, additional synchronization bits are added to the data
when operating in asynchronous mode, resulting in a slight overhead.
Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported
protocols in Table 16.1 USART Asynchronous vs. Synchronous Mode on page 440. Full duplex and half duplex communication is supported in both asynchronous and synchronous mode.
Table 16.1. USART Asynchronous vs. Synchronous Mode
SYNC
Communication Mode
Supported Protocols
0
Asynchronous
RS-232, RS-485 (w/external driver), IrDA, ISO 7816
1
Synchronous
SPI, MicroWire, 3-wire
Table 16.2 USART Pin Usage on page 440 explains the functionality of the different USART pins when the USART operates in different
modes. Pin functionality enclosed in square brackets is optional, and depends on additional configuration parameters. LOOPBK and
MASTER are discussed in 16.3.2.14 Local Loopback and 16.3.3.3 Master Mode respectively.
Table 16.2. USART Pin Usage
SYNC
LOOPBK
MASTER
0
0
0
Pin functionality
U(S)n_TX (MOSI)
U(S)n_RX (MISO)
USn_CLK
USn_CS
x
Data out
Data in
-
[Driver enable]
1
x
Data out/in
-
-
[Driver enable]
1
0
0
Data in
Data out
Clock in
Slave select
1
0
1
Data out
Data in
Clock out
[Auto slave select]
1
1
0
Data out/in
-
Clock in
Slave select
1
1
1
Data out/in
-
Clock out
[Auto slave select]
16.3.2 Asynchronous Operation
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.3.2.1 Frame Format
The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity
bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a
frame, and is used for synchronization. Following the start bit are 4 to 16 data bits and an optional parity bit. Finally, a number of stopbits, where the line is driven high, end the frame. An example frame is shown in Figure 16.2 USART Asynchronous Frame Format on
page 441.
Frame
Stop or idle
Start or idle
S
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Stop
Figure 16.2 USART Asynchronous Frame Format
The number of data bits in a frame is set by DATABITS in USARTn_FRAME, see Table 16.3 USART Data Bits on page 441, and the
number of stop-bits is set by STOPBITS in USARTn_FRAME, see Table 16.4 USART Stop Bits on page 441. Whether or not a parity
bit should be included, and whether it should be even or odd is defined by PARITY, also in USARTn_FRAME. For communication to be
possible, all parties of an asynchronous transfer must agree on the frame format being used.
Table 16.3. USART Data Bits
DATA BITS [3:0]
Number of Data bits
0001
4
0010
5
0011
6
0100
7
0101
8 (Default)
0110
9
0111
10
1000
11
1001
12
1010
13
1011
14
1100
15
1101
16
Table 16.4. USART Stop Bits
STOP BITS [1:0]
Number of Stop bits
00
0.5
01
1 (Default)
10
1.5
11
2
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a
frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first.
The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver
can be inverted by setting RXINV in USARTn_CTRL. These bits affect the entire frame, not only the data bits. An inverted frame has a
low idle state, a high start-bit, inverted data and parity bits, and low stop-bits.
16.3.2.2 Parity bit Calculation and Handling
When parity bits are enabled, hardware automatically calculates and inserts any parity bits into outgoing frames, and verifies the received parity bits in incoming frames. This is true for both asynchronous and synchronous modes, even though it is mostly used in
asynchronous communication. The possible parity modes are defined in Table 16.5 USART Parity Bits on page 442. When even parity
is chosen, a parity bit is inserted to make the number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the
total number of high bits odd.
Table 16.5. USART Parity Bits
STOP BITS [1:0]
Description
00
No parity bit (Default)
01
Reserved
10
Even parity
11
Odd parity
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16.3.2.3 Clock Generation
The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is
given by Figure 16.3 USART Baud Rate on page 443
br = fHFPERCLK/(oversample x (1 + USARTn_CLKDIV/256))
Equation: USART Baud Rate
where fHFPERCLK is the peripheral clock (HFPERCLKUSARTn) frequency and oversample is the oversampling rate as defined by OVS in
USARTn_CTRL, see Table 16.6 USART Oversampling on page 443.
Table 16.6. USART Oversampling
OVS [1:0]
oversample
00
16
01
8
10
6
11
4
The USART has a fractional clock divider to allow the USART clock to be controlled more accurately than what is possible with a standard integral divider.
The clock divider used in the USART is a 20-bit value, with a 15-bit integral part and an 5-bit fractional part. The fractional part is configured in the lower 5 bits of DIV in USART_CLKDIV. The lowest achievable baud rate at 32 MHz is about 61 bauds/sec.
Fractional clock division is implemented by distributing the selected fraction over thirty two baud periods. The fractional part of the divider tells how many of these periods should be extended by one peripheral clock cycle.
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated by using Figure 16.4 USART Desired Baud
Rate on page 443:
USARTn_CLKDIV = 256 x (fHFPERCLK/(oversample x brdesired) - 1)
Equation: USART Desired Baud Rate
Table 16.7 USART Baud Rates @ 4MHz Peripheral Clock with 20 bit CLKDIV on page 443 shows a set of desired baud rates and how
accurately the USART is able to generate these baud rates when running at a 4 MHz peripheral clock, using 16x or 8x oversampling.
Table 16.7. USART Baud Rates @ 4MHz Peripheral Clock with 20 bit CLKDIV
USARTn_OVS =00
Desired baud
Actual baud rate
rate [baud/s] USARTn_CLKDIV/256
Error %
(to 32nd position)
[baud/s]
USARTn_CLKDIV/256
(to 32nd position)
Actual baud rate
Error %
[baud/s]
600
415,6563
600,015
0,003
832,3438
599,9925
-0,001
1200
207,3438
1199,94
-0,005
415,6563
1200,03
0,003
2400
103,1563
2400,24
0,010
207,3438
2399,88
-0,005
4800
51,09375
4799,04
-0,020
103,1563
4800,48
0,010
9600
25,03125
9603,842
0,040
51,09375
9598,08
-0,020
14400
16,375
14388,49
-0,080
33,71875
14401,44
0,010
19200
12,03125
19184,65
-0,080
25,03125
19207,68
0,040
28800
7,6875
28776,98
-0,080
16,375
28776,98
-0,080
38400
5,5
38461,54
0,160
12,03125
38369,3
-0,080
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USARTn_OVS =00
Desired baud
Actual baud rate
rate [baud/s] USARTn_CLKDIV/256
Error %
(to 32nd position)
[baud/s]
USARTn_OVS =01
USARTn_CLKDIV/256
(to 32nd position)
Actual baud rate
Error %
[baud/s]
57600
3,34375
57553,96
-0,080
7,6875
57553,96
-0,080
76800
2,25
76923,08
0,160
5,5
76923,08
0,160
115200
1,15625
115942
0,644
3,34375
115107,9
-0,080
230400
0,09375
228571,4
-0,794
1,15625
231884,1
0,644
16.3.2.4 Auto Baud Detection
Setting AUTOBAUDEN in USARTn_CLKDIV uses the first frame received to automatically set the baud rate provided that it contains
0x55 (IrDA uses 0x00). AUTOBAUDEN can be used in a simple LIN configuration to auto detect the SYNC byte. The receiver will
measure the number of local clock cycles between the beginning of the START bit and the beginning of the 8th data bit. The DIV field in
USARTn_CLKDIV will be overwritten with the new value. The OVS in USARTn_CTRL and the +1 count of the Baud Rate equation are
already factored into the result that gets written into the DIV field. To restart autobaud detection, clear AUTOBAUDEN and set it high
again. Since the auto baud detection is done over 8 baud times, only the upper 3 bits of the fractional part of the clock divider are
populated.
16.3.2.5 Data Transmission
Asynchronous data transmission is initiated by writing data to the transmit buffer using one of the methods described in 16.3.2.6 Transmit Buffer Operation. When the transmission shift register is empty and ready for new data, a frame from the transmit buffer is loaded
into the shift register, and if the transmitter is enabled, transmission begins. When the frame has been transmitted, a new frame is loaded into the shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to an idle state,
waiting for a new frame to become available.
Transmission is enabled through the command register USARTn_CMD by setting TXEN, and disabled by setting TXDIS in the same
command register. When the transmitter is disabled using TXDIS, any ongoing transmission is aborted, and any frame currently being
transmitted is discarded. When disabled, the TX output goes to an idle state, which by default is a high value. Whether or not the transmitter is enabled at a given time can be read from TXENS in USARTn_STATUS.
When the USART transmitter is enabled and there is no data in the transmit shift register or transmit buffer, the TXC flag in
USARTn_STATUS and the TXC interrupt flag in USARTn_IF are set, signaling that the transmission is complete. The TXC status flag is
cleared when a new frame becomes available for transmission, but the TXC interrupt flag must be cleared by software.
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16.3.2.6 Transmit Buffer Operation
The transmit-buffer is a multiple entry FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA,
USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buffer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer. If 9-bit frames are used, the 9th bit of the frames will in
these cases be set to the value of BIT8DV in USARTn_CTRL.
To set the 9th bit directly and/or use transmission control, USARTn_TXDATAX and USARTn_TXDOUBLEX must be used.
USARTn_TXDATAX allows 9 data bits to be written, as well as a set of control bits regarding the transmission of the written frame.
Every frame in the buffer is stored with 9 data bits and additional transmission control bits. USARTn_TXDOUBLEX allows two frames,
complete with control bits to be written at once. When data is written to the transmit buffer using USARTn_TXDATAX and
USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the
9th bits that are transmitted if 9-bit frames are used. Figure 16.5 USART Transmit Buffer Operation on page 445 shows the basics of
the transmit buffer when DATABITS in USARTn_FRAME is configured to less than 10 bits.
Peripheral Bus
TXDOUBLE,
TXDOUBLEX
TX buffer element 1
Write CTRL
TX buffer element 0
Write CTRL
TXDATA,
TXDATAX
Shift register
Write CTRL
Figure 16.5 USART Transmit Buffer Operation
When writing more frames to the transmit buffer than there is free space for, the TXOF interrupt flag in USARTn_IF will be set, indicating the overflow. The data already in the transmit buffer is preserved in this case, and no data is written.
In addition to the interrupt flag TXC in USARTn_IF and status flag TXC in USARTn_STATUS which are set when the transmission is
complete, TXBL in USARTn_STATUS and the TXBL interrupt flag in USARTn_IF are used to indicate the level of the transmit buffer.
TXBIL in USARTn_CTRL controls the level at which these bits are set. If TXBIL is cleared, they are set whenever the transmit buffer
becomes empty, and if TXBIL is set, they are set whenever the transmit buffer goes from full to half-full or empty. Both the TXBL status
flag and the TXBL interrupt flag are cleared automatically when their condition becomes false.
There is a TXIDLE status bit in USARTn_STATUS to provide an indication of when the transmitter is idle. The combined count of TX
buffer element 0, TX buffer element 1, and TX shift register is called TXBUFCNT in USARTn_STATUS. For large frames, the count is
only of TX buffer entry 0 and the TX shifter register.
The transmit buffer, including the transmit shift register can be cleared by setting CLEARTX in USARTn_CMD. This will prevent the
USART from transmitting the data in the buffer and shift register, and will make them available for new data. Any frame currently being
transmitted will not be aborted. Transmission of this frame will be completed.
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16.3.2.7 Frame Transmission Control
The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of
the written frame. The following options are available:
• Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver
that supports break detection detects this state, allowing it to be used e.g. for framing of larger data packets. The line is driven high
before the next frame is transmitted so the next start condition can be identified correctly by the recipient. Continuous breaks lasting
longer than a USART frame are thus not supported by the USART. GPIO can be used for this.
• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame has been fully transmitted.
• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has been fully transmitted. It is enabled
in time to detect a start-bit directly after the last stop-bit has been transmitted.
• Unblock receiver after transmission: If UBRXAT is set, the receiver is unblocked and RXBLOCK is cleared after the frame has been
fully transmitted.
• Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been fully transmitted, tristating the transmitter output. Tristating of the output can also be performed automatically by setting AUTOTRI. If AUTOTRI is set TXTRI is always
read as 0.
Note:
When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure. Generation of a break in SmartCard mode with repeat enabled will cause the USART to detect a NACK on every
frame.
16.3.2.8 Data Reception
Data reception is enabled by setting RXEN in USARTn_CMD. When the receiver is enabled, it actively samples the input looking for a
transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins if the
receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making
the shift register ready for another frame of data, and the receiver starts looking for another start baud. If the receive buffer is full, the
received frame remains in the shift register until more space in the receive buffer is available. If an incoming frame is detected while
both the receive buffer and the receive shift register are full, the data in the shift register is overwritten, and the RXOF interrupt flag in
USARTn_IF is set to indicate the buffer overflow.
The receiver can be disabled by setting the command bit RXDIS in USARTn_CMD. Any frame currently being received when the receiver is disabled is discarded. Whether or not the receiver is enabled at a given time can be read out from RXENS in USARTn_STATUS.
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16.3.2.9 Receive Buffer Operation
When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in
USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are
set. The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true. This also
goes for the RXDATAV interrupt flag, but the RXFULL interrupt flag must be cleared by software. When the RXFULL flag is set, notifying
that the buffer is full, space is still available in the receive shift register for one more frame.
Data can be read from the receive buffer in a number of ways. USARTn_RXDATA gives access to the 8 least significant bits of the
received frame, and USARTn_RXDOUBLE makes it possible to read the 8 least significant bits of two frames at once, pulling two
frames from the buffer. To get access to the 9th, most significant bit, USARTn_RXDATAX must be used. This register also contains
status information regarding the frame. USARTn_RXDOUBLEX can be used to get two frames complete with the 9th bits and status
bits.
When a frame is read from the receive buffer using USARTn_RXDATA or USARTn_RXDATAX, the frame is pulled out of the buffer,
making room for a new frame. USARTn_RXDOUBLE and USARTn_RXDOUBLEX pull two frames out of the buffer. If an attempt is
done to read more frames from the buffer than what is available, the RXUF interrupt flag in USARTn_IF is set to signal the underflow,
and the data read from the buffer is undefined.
Frames can be read from the receive buffer without removing the data by using USARTn_RXDATAXP and USARTn_RXDOUBLEXP.
USARTn_RXDATAXP gives access the first frame in the buffer with status bits, while USARTn_RXDOUBLEXP gives access to both
frames with status bits. The data read from these registers when the receive buffer is empty is undefined. If the receive buffer contains
one valid frame, the first frame in USARTn_RXDOUBLEXP will be valid. No underflow interrupt is generated by a read using these
registers, i.e. RXUF in USARTn_IF is never set as a result of reading from USARTn_RXDATAXP or USARTn_RXDOUBLEXP.
The basic operation of the receive buffer when DATABITS in USARTn_FRAME is configured to less than 10 bits is shown in Figure
16.6 USART Receive Buffer Operation on page 447.
Peripheral Bus
RXDOUBLE
RXDOUBLEX
RXDOUBLEXP
RX buffer element 0
Status
RX buffer element 1
Status
RXDATA,
RXDATAX,
RXDATAXP
Shift register
Status
Figure 16.6 USART Receive Buffer Operation
The receive buffer, including the receive shift register can be cleared by setting CLEARRX in USARTn_CMD. Any frame currently being
received will not be discarded.
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16.3.2.10 Blocking Incoming Data
When using hardware frame recognition, as detailed in 16.3.2.20 Multi-Processor Mode and 16.3.2.21 Collision Detection, it is necessary to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer.
This is accomplished by blocking incoming data.
Incoming data is blocked as long as RXBLOCK in USARTn_STATUS is set. When blocked, frames received by the receiver will not be
loaded into the receive buffer, and software is not notified by the RXDATAV flag in USARTn_STATUS or the RXDATAV interrupt flag in
USARTn_IF at their arrival. For data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully received by the receiver. RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by setting RXBLOCKDIS also in
USARTn_CMD. There is one exception where data is loaded into the receive buffer even when RXBLOCK is set. This is when an address frame is received when operating in multi-processor mode. See 16.3.2.20 Multi-Processor Mode for more information.
Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in USARTn_IF being set while
RXBLOCK in USARTn_STATUS is set. Hardware recognition is not applied to these erroneous frames, and they are silently discarded.
Note:
If a frame is received while RXBLOCK in USARTn_STATUS is cleared, but stays in the receive shift register because the receive buffer
is full, the received frame will be loaded into the receive buffer when space becomes available even if RXBLOCK is set at that time.
The overflow interrupt flag RXOF in USARTn_IF will be set if a frame in the receive shift register, waiting to be loaded into the receive
buffer is overwritten by an incoming frame even though RXBLOCK in USARTn_STATUS is set.
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16.3.2.11 Clock Recovery and Filtering
The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling
mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors.
When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate
generator is synchronized with the incoming frame.
For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity. These
samples are aimed at the middle of the bit-periods, as visualized in Figure 16.7 USART Sampling of Start and Data Bits on page 449.
With OVS=0 in USARTn_CTRL, the start and data bits are thus sampled at locations 8, 9 and 10 in the figure, locations 4, 5 and 6 for
OVS=1 and locations 3, 4, and 5 for OVS=2. The value of a sampled bit is determined by majority vote. If two or more of the three bitsamples are high, the resulting bit value is high. If the majority is low, the resulting bit value is low.
Majority vote is used for all oversampling modes except 4x oversampling. In this mode, a single sample is taken at position 3 as shown
in Figure 16.7 USART Sampling of Start and Data Bits on page 449.
Majority vote can be disabled by setting MVDIS in USARTn_CTRL.
If the value of the start bit is found to be high, the reception of the frame is aborted, filtering out false start bits possibly generated by
noise on the input.
Start bit
0
0
OVS = 3
OVS = 2
OVS = 1
OVS = 0
Idle
0
0
0
1
1
1
1
2
3
4
2
5
6
7
3
2
4
3
2
8
Bit 0
9 10 11 12 13 14 15 16 1
5
4
3
6
7
5
8
6
4
1
1
1
2
3
4
2
5
6
7
3
2
4
3
2
8
9 10 11 12 13
5
4
3
6
7
5
4
Figure 16.7 USART Sampling of Start and Data Bits
If the baud rate of the transmitter and receiver differ, the location each bit is sampled will be shifted towards the previous or next bit in
the frame. This is acceptable for small errors in the baud rate, but for larger errors, it will result in transmission errors.
When the number of stop bits is 1 or more, stop bits are sampled like the start and data bits as seen in Figure 16.8 USART Sampling of
Stop Bits when Number of Stop Bits are 1 or More on page 450. When a stop bit has been detected by sampling at positions 8, 9 and
10 for normal mode, or 4, 5 and 6 for smart mode, the USART is ready for a new start bit. As seen in Figure 16.8 USART Sampling of
Stop Bits when Number of Stop Bits are 1 or More on page 450, a stop-bit of length 1 normally ends at c, but the next frame will be
received correctly as long as the start-bit comes after position a for OVS=0 and OVS=3, and b for OVS=1 and OVS=2.
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a
7
OVS = 3
8
6
4
c
1 stop bit
13 14 15 16 1
OVS = 2
OVS = 1
OVS = 0
n’th bit
b
1
2
3
4
2
1
1
5
Idle or start bit
6
7
3
2
4
3
2
8
9 10 0/1 X
5
4
3
6
X
X
0/1
5
X
X
0/1
0/1
X
1
1
Figure 16.8 USART Sampling of Stop Bits when Number of Stop Bits are 1 or More
When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices. In this case, the stop-bit is not
sampled, and no framing error is generated in the receiver if the stop-bit is not generated. The line must still be driven high before the
next start bit however for the USART to successfully identify the start bit.
16.3.2.12 Parity Error
When parity bits are enabled, a parity check is automatically performed on incoming frames. When a parity error is detected in an incoming frame, the data parity error bit PERR in the frame is set, as well as the interrupt flag PERR in USARTn_IF. Frames with parity
errors are loaded into the receive buffer like regular frames.
PERR can be accessed by reading the frame from the receive buffer using the USARTn_RXDATAX, USARTn_RXDATAXP,
USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers.
If ERRSTX in USARTn_CTRL is set, the transmitter is disabled on received parity and framing errors. If ERRSRX in USARTn_CTRL is
set, the receiver is disabled on parity and framing errors.
16.3.2.13 Framing Error and Break Detection
A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0. This can be the result of noise
and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
When a framing error is detected in an incoming frame, the framing error bit FERR in the frame is set. The interrupt flag FERR in
USARTn_IF is also set. Frames with framing errors are loaded into the receive buffer like regular frames.
FERR can be accessed by reading the frame from the receive buffer using the USARTn_RXDATAX, USARTn_RXDATAXP,
USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers.
If ERRSTX in USARTn_CTRL is set, the transmitter is disabled on parity and framing errors. If ERRSRX in USARTn_CTRL is set, the
receiver is disabled on parity and framing errors.
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16.3.2.14 Local Loopback
The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option however. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in Figure 16.9 USART Local
Loopback on page 451. This is useful for debugging, as the USART can receive the data it transmits, but it is also used to allow the
USART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the U(S)n_TX
pin must be enabled as an output in the GPIO.
LOOBPK = 0
LOOBPK = 1
µC
µC
USART
USART
TX
U(S)n_TX
TX
U(S)n_TX
RX
U(S)n_RX
RX
U(S)n_RX
Figure 16.9 USART Local Loopback
16.3.2.15 Asynchronous Half Duplex Communication
When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same
time. In half duplex mode, data is only sent in one direction at a time. There are several possible half duplex setups, as described in the
following sections.
16.3.2.16 Single Data-link
In this setup, the USART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in USARTn_CTRL,
which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the USART
transmitter does not drive the line when receiving data, as this would corrupt the data on the line.
When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. This is done by
setting the command bit TXTRIEN in USARTn_CMD, which tristates the transmitter. Before transmitting data, the command bit TXTRIDIS, also in USARTn_CMD, must be set to enable transmitter output again. Whether or not the output is tristated at a given time can be
read from TXTRI in USARTn_STATUS. If TXTRI is set when transmitting data, the data is shifted out of the shift register, but is not put
out on U(S)n_TX.
When operating a half duplex data bus, it is common to have a bus master, which first transmits a request to one of the bus slaves, then
receives a reply. In this case, the frame transmission control bits, which can be set by writing to USARTn_TXDATAX, can be used to
make the USART automatically disable transmission, tristate the transmitter and enable reception when the request has been transmitted, making it ready to receive a response from the slave.
The timer, 16.3.10 Timer, can also be used to add delay between the RX and TX frames so that the interrupt service routine has time to
process data that was just received before transmitting more data. Also hardware flow control is another method to insert time for processing the frame. RTS and CTS can be used to halt either the link partner's transmitter or the local transmitter. See the section on
hardware flow control,16.3.4 Hardware Flow Control, for more details.
Tristating the transmitter can also be performed automatically by the USART by using AUTOTRI in USARTn_CTRL. When AUTOTRI is
set, the USART automatically tristates U(S)n_TX whenever the transmitter is idle, and enables transmitter output when the transmitter
goes active. If AUTOTRI is set TXTRI is always read as 0.
Note:
Another way to tristate the transmitter is to enable wired-and or wired-or mode in GPIO. For wired-and mode, outputting a 1 will be the
same as tristating the output, and for wired-or mode, outputting a 0 will be the same as tristating the output. This can only be done on
buses with a pull-up or pull-down resistor respectively.
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16.3.2.17 Single Data-link with External Driver
Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and
instead of tristating the transmitter when receiving data, the external driver must be disabled.
This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART. If AUTOCS in USARTn_CTRL is set, the USn_CS output is automatically activated a configurable number of baud periods before the transmitter starts transmitting data, and deactivated a configurable number of baud periods after the last bit has been transmitted and there
is no more data in the transmit buffer to transmit. The number of baud periods are controlled by CSSETUP and CSHOLD in
USARTn_TIMING. This feature can be used to turn the external driver on when transmitting data, and turn it off when the data has been
transmitted.
The timer, 16.3.10 Timer, can also be used to configure CSSETUP and CSHOLD values between 1 to 256 baud-times by using
TCMPVAL0, TCMPVAL1, or TCMPVAL2 for the TX sequencer.
USn_CS is immediately deasserted when the transmitter becomes disabled.
Figure 16.10 USART Half Duplex Communication with External Driver on page 452 shows an example configuration where USn_CS is
used to automatically enable and disable an external driver.
µC
USART
CS
TX
RX
Figure 16.10 USART Half Duplex Communication with External Driver
The USn_CS output is active low by default, but its polarity can be changed with CSINV in USARTn_CTRL. AUTOCS works regardless
of which mode the USART is in, so this functionality can also be used for automatic chip/slave select when in synchronous mode (e.g.
SPI).
16.3.2.18 Two Data-links
Some limited devices only support half duplex communication even though two data links are available. In this case software is responsible for making sure data is not transmitted when incoming data is expected.
TXARXnEN in USARTn_TRIGCTRL may be used to automatically start transmission after the end of the RX frame plus any TXSTDELAY and CSSETUP delay in USARTn_TIMING. For enabling the receiver either use RXENAT in USARTn_TXDATAX or RXATXnEN in
USARTn_TRIGCTRL.
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16.3.2.19 Large Frames
As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when
working with USART-frames of 10 or more data bits.
To transmit such a frame, at least two elements must be available in the transmit buffer. If only one element is available, the USART will
wait for the second element before transmitting the combined frame. Both the elements making up the frame are consumed when
transmitting such a frame.
When using large frames, the 9th bits in the buffers are unused. For an 11 bit frame, the 8 least significant bits are thus taken from the
first element in the buffer, and the 3 remaining bits are taken from the second element as shown in Figure 16.11 USART Transmission
of Large Frames on page 453. The first element in the transmit buffer, i.e. element 0 in Figure 16.11 USART Transmission of Large
Frames on page 453 is the first element written to the FIFO, or the least significant byte when writing two bytes at a time using
USARTn_TXDOUBLE.
Peripheral Bus
TX buffer element 1
0
1
2
TX buffer element 0
0
1
2
3
4
6
7
0
1
2
Write CTRL
5
6
Write CTRL
7
Shift register
0
1
2
3
4
5
Write CTRL
Figure 16.11 USART Transmission of Large Frames
As shown in Figure 16.11 USART Transmission of Large Frames on page 453, frame transmission control bits are taken from the second element in FIFO.
The two buffer elements can be written at the same time using the USARTn_TXDOUBLE or USARTn_TXDOUBLEX register. The
TXDATAX0 bitfield then refers to buffer element 0, and TXDATAX1 refers to buffer element 1.
Peripheral Bus
TX buffer element 1
0
1
2
TX buffer element 0
0
1
2
3
4
5
6
7
Shift register
2
1
0
7
6
5
4
3
2
1
0
Figure 16.12 USART Transmission of Large Frames, MSBF
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Figure 16.12 USART Transmission of Large Frames, MSBF on page 453 illustrates the order of the transmitted bits when an 11 bit
frame is transmitted with MSBF set. If MSBF is set and the frame is smaller than 10 bits, only the contents of transmit buffer 0 will be
transmitted.
When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer
elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive
buffer, and the remaining bits are loaded into the second element, as shown in Figure 16.13 USART Reception of Large Frames on
page 454. The first byte read from the buffer thus contains the 8 least significant bits. Set BYTESWAP to reverse the order.
The status bits are loaded into both elements of the receive buffer. The frame is not moved from the receive shift register before there
are two free spaces in the receive buffer.
Peripheral Bus
RX buffer element 0
Status
0
1
2
RX buffer element 1
Status
0
1
2
7
0
1
3
4
5
6
7
Shift register
0
Status
1
2
3
4
5
6
2
Figure 16.13 USART Reception of Large Frames
The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or USARTn_RXDOUBLEX register. RXDATA0
then refers to buffer element 0 and RXDATA1 refers to buffer element 1.
Large frames can be used in both asynchronous and synchronous modes.
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16.3.2.20 Multi-Processor Mode
To simplify communication between multiple processors, the USART supports a special multi-processor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address.
When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of MPAB in USARTn_CTRL is identified as an address frame. When an address frame is detected, the MPAF interrupt flag in USARTn_IF is set, and the address frame is
loaded into the receive register. This happens regardless of the value of RXBLOCK in USARTn_STATUS.
Multi-processor mode is enabled by setting MPM in USARTn_CTRL, and the value of the 9th bit in address frames can be set in MPAB.
Note that the receiver must be enabled for address frames to be detected. The receiver can be blocked however, preventing data from
being loaded into the receive buffer while looking for address frames.
Figure 16.14 USART Multi-processor Mode Example on page 455 explains basic usage of the multi-processor mode:
1. All slaves enable multi-processor mode and, enable and block the receiver. They will now not receive data unless it is an address
frame. MPAB in USARTn_CTRL is set to identify frames with the 9th bit high as address frames.
2.
The master sends a frame containing the address of a slave and with the 9th bit set
3. All slaves receive the address frame and get an interrupt. They can read the address from the receive buffer. The selected slave
unblocks the receiver to start receiving data from the master.
4.
The master sends data with the 9th bit cleared
5. Only the slave with RX enabled receives the data. When transmission is complete, the slave blocks the receiver and waits for a
new address frame.
Figure 16.14 USART Multi-processor Mode Example
When a slave has received an address frame and wants to receive the following data, it must make sure the receiver is unblocked
before the next frame has been completely received in order to prevent data loss.
BIT8DV in USARTn_CTRL can be used to specify the value of the 9th bit without writing to the transmit buffer with USARTn_TXDATAX
or USARTn_TXDOUBLEX, giving higher efficiency in multi-processor mode, as the 9th bit is only set when writing address frames, and
8-bit writes to the USART can be used when writing the data frames.
16.3.2.21 Collision Detection
The USART supports a basic form of collision detection. When the receiver is connected to the output of the transmitter, either by using
the LOOPBK bit in USARTn_CTRL or through an external connection, this feature can be used to detect whether data transmitted on
the bus by the USART did get corrupted by a simultaneous transmission by another device on the bus.
For collision detection to be enabled, CCEN in USARTn_CTRL must be set, and the receiver enabled. The data sampled by the receiver is then continuously compared with the data output by the transmitter. If they differ, the CCF interrupt flag in USARTn_IF is set. The
collision check includes all bits of the transmitted frames. The CCF interrupt flag is set once for each bit sampled by the receiver that
differs from the bit output by the transmitter. When the transmitter output is disabled, i.e. the transmitter is tristated, collisions are not
registered.
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16.3.2.22 SmartCard Mode
In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop-bits (guard time), the 7816 data
frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard
time to indicate a parity error. This NAK can for instance be used by the transmitter to re-transmit the frame. SmartCard mode is a half
duplex asynchronous mode, so the transmitter must be tristated whenever not transmitting data.
To enable SmartCard mode, set SCMODE in USARTn_CTRL, set the number of databits in a frame to 8, and configure the number of
stopbits to 1.5 by writing to STOPBITS in USARTn_FRAME.
The SmartCard mode relies on half duplex communication on a single line, so for it to work, both the receiver and transmitter must work
on the same line. This can be achieved by setting LOOPBK in USARTn_CTRL or through an external connection. The TX output
should be configured as open-drain in the GPIO module.
When no parity error is identified by the receiver, the data frame is as shown in Figure 16.15 USART ISO 7816 Data Frame Without
Error on page 456. The frame consists of 8 data bits, a parity bit, and 2 stop bits. The transmitter does not drive the output line during
the guard time.
ISO 7816 Frame without error
Stop or idle
Start or idle
S
0
1
3
2
4
6
5
Stop
P
7
Figure 16.15 USART ISO 7816 Data Frame Without Error
If a parity error is detected by the receiver, it pulls the line I/O line low after half a stop bit, see Figure 16.16 USART ISO 7816 Data
Frame With Error on page 456. It holds the line low for one bit-period before it releases the line. In this case, the guard time is extended by one bit period before a new transmission can start, resulting in a total of 3 stop bits.
ISO 7816 Frame with error
Start or idle
Stop or idle
S
0
1
2
3
4
5
6
7
P
Stop
NAK
Stop
Figure 16.16 USART ISO 7816 Data Frame With Error
On a parity error, the NAK is generated by hardware. The NAK generated by the receiver is sampled as the stop-bit of the frame. Because of this, parity errors when in SmartCard mode are reported with both a parity error and a framing error.
When transmitting a T0 frame, the USART receiver on the transmitting side samples position 16, 17 and 18 in the stop-bit to detect the
error signal when in 16x oversampling mode as shown in Figure 16.17 USART SmartCard Stop Bit Sampling on page 457. Sampling
at this location places the stop-bit sample in the middle of the bit-period used for the error signal (NAK).
If a NAK is transmitted by the receiver, it will thus appear as a framing error at the transmitter, and the FERR interrupt flag in
USARTn_IF will be set. If SCRETRANS USARTn_CTRL is set, the transmitter will automatically retransmit a NACK’ed frame. The
transmitter will retransmit the frame until it is ACK’ed by the receiver. This only works when the number of databits in a frame is configured to 8.
Set SKIPPERRF in USARTn_CTRL to make the receiver discard frames with parity errors. The PERR interrupt flag in USARTn_IF is
set when a frame is discarded because of a parity error.
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1/2 stop bit
13 14 15 16 1
7
OVS = 3
OVS = 2
OVS = 1
OVS = 0
P
8
6
4
2
1
1
1
3
4
5
2
NAK or stop
6
7
3
2
4
3
2
8
Stop
9 10 11 12 13 14 15 16 17 18 X
5
4
3
6
7
5
8
6
4
9
X
10
7
5
X
X
X
X
8
X
X
x
x
Figure 16.17 USART SmartCard Stop Bit Sampling
For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one
of the timers. See the ISO 7816 specification for more info on this clock signal.
SmartCard T1 mode is also supported. The T1 frame format used is the same as the asynchronous frame format with parity bit enabled
and one stop bit. The USART must then be configured to operate in asynchronous half duplex mode.
16.3.3 Synchronous Operation
Most of the features in asynchronous mode are available in synchronous mode. Multi-processor mode can be enabled for 9-bit frames,
loopback is available and collision detection can be performed.
16.3.3.1 Frame Format
The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the communication. Parity bits cannot be used in synchronous mode.
The USART supports frame lengths of 4 to 16 bits per frame. Larger frames can be simulated by transmitting multiple smaller frames,
i.e. a 22 bit frame can be sent using two 11-bit frames, and a 21 bit frame can be generated by transmitting three 7-bit frames. The
number of bits in a frame is set using DATABITS in USARTn_FRAME.
The frames in synchronous mode are by default transmitted with the least significant bit first like in asynchronous mode. The bit-order
can be reversed by setting MSBF in USARTn_CTRL.
The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver
can be inverted by setting RXINV, also in USARTn_CTRL.
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16.3.3.2 Clock Generation
The bit-rate in synchronous mode is given by Figure 16.18 USART Synchronous Mode Bit Rate on page 458. As in the case of asynchronous operation, the clock division factor have a 15-bit integral part and a 5-bit fractional part.
br = fHFPERCLK/(2 x (1 + USARTn_CLKDIV/256))
Equation: USART Synchronous Mode Bit Rate
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated using Figure 16.19 USART Synchronous
Mode Clock Division Factor on page 458
USARTn_CLKDIV = 256 x (fHFPERCLK/(2 x brdesired) - 1)
Equation: USART Synchronous Mode Clock Division Factor
When the USART operates in master mode, the highest possible bit rate is half the peripheral clock rate. When operating in slave mode
however, the highest bit rate is an eighth of the peripheral clock:
• Master mode: brmax = fHFPERCLK/2
• Slave mode: brmax = fHFPERCLK/8
On every clock edge data on the data lines, MOSI and MISO, is either set up or sampled. When CLKPHA in USARTn_CTRL is cleared,
data is sampled on the leading clock edge and set-up is done on the trailing edge. If CLKPHA is set however, data is set-up on the
leading clock edge, and sampled on the trailing edge. In addition to this, the polarity of the clock signal can be changed by setting
CLKPOL in USARTn_CTRL, which also defines the idle state of the clock. This results in four different modes which are summarized in
Table 16.8 USART SPI Modes on page 458. Figure 16.18 USART SPI Timing on page 458 shows the resulting timing of data set-up
and sampling relative to the bus clock.
Table 16.8. USART SPI Modes
SPI mode
CLKPOL
CLKPHA
Leading edge
Trailing edge
0
0
0
Rising, sample
Falling, set-up
1
0
1
Rising, set-up
Falling, sample
2
1
0
Falling, sample
Rising, set-up
3
1
1
Falling, set-up
Rising, sample
CLKPOL = 0
USn_CLK
CLKPOL = 1
USn_CS
CLKPHA = 0
0
X
1
2
3
4
5
6
7
X
USn_TX/
USn_RX
CLKPHA = 1
X
0
1
2
3
4
5
6
7
X
Figure 16.18 USART SPI Timing
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If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available. If
CPHA=0, TXUF is set if data is not available in the transmit buffer three HFPERCLK cycles prior to the first sample clock edge. The
RXDATAV flag is updated on the last sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first
sample clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on
the first setup clock edge of the succeeding frame, or when CS is deasserted.
16.3.3.3 Master Mode
When in master mode, the USART is in full control of the data flow on the synchronous bus. When operating in full duplex mode, the
slave cannot transmit data to the master without the master transmitting to the slave. The master outputs the bus clock on USn_CLK.
Communication starts whenever there is data in the transmit buffer and the transmitter is enabled. The USART clock then starts, and
the master shifts bits out from the transmit shift register using the internal clock.
When there are no more frames in the transmit buffer and the transmit shift register is empty, the clock stops, and communication ends.
When the receiver is enabled, it samples data using the internal clock when the transmitter transmits data. Operation of the RX and TX
buffers is as in asynchronous mode.
16.3.3.4 Operation of USn_CS Pin
When operating in master mode, the USn_CS pin can have one of two functions, or it can be disabled.
If USn_CS is configured as an output, it can be used to automatically generate a chip select for a slave by setting AUTOCS in
USARTn_CTRL. If AUTOCS is set, USn_CS is activated before a transmission begins, and deactivated after the last bit has been transmitted and there is no more data in the transmit buffer.
The time between when CS is asserted and the first bit is transmitted can be controlled using the USART Timer and with CSSETUP in
USARTn_TIMING. Any of the three comparators can be used to set this delay. If new data is ready for transmission before CS is deasserted, the data is sent without deasserting CS in between. CSHOLD in USARTn_TIMING keeps CS asserted after the end of frame for
the number of baud-times specified.
By default, USn_CS is active low, but its polarity can be inverted by setting CSINV in USARTn_CTRL.
When USn_CS is configured as an input, it can be used by another master that wants control of the bus to make the USART release it.
When USn_CS is driven low, or high if CSINV is set, the interrupt flag SSM in USARTn_IF is set, and if CSMA in USARTn_CTRL is set,
the USART goes to slave mode.
16.3.3.5 AUTOTX
A synchronous master is required to transmit data to a slave in order to receive data from the slave. In some cases, only a few words
are transmitted and a lot of data is then received from the slave. In that case, one solution is to keep feeding the TX with data to transmit, but that consumes system bandwidth. Instead AUTOTX can be used.
When AUTOTX in USARTn_CTRL is set, the USART transmits data as long as there is available space in the RX shift register for the
chosen frame size. This happens even though there is no data in the TX buffer. The TX underflow interrupt flag TXUF in USARTn_IF is
set on the first word that is transmitted which does not contain valid data.
During AUTOTX the USART will always send the previous sent bit, thus reducing the number of transitions on the TX output. So if the
last bit sent was a 0, 0's will be sent during AUTOTX and if the last bit sent was a 1, 1's will be sent during AUTOTX.
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16.3.3.6 Slave Mode
When the USART is in slave mode, data transmission is not controlled by the USART, but by an external master. The USART is therefore not able to initiate a transmission, and has no control over the number of bytes written to the master.
The output and input to the USART are also swapped when in slave mode, making the receiver take its input from USn_TX (MOSI) and
the transmitter drive USn_RX (MISO).
To transmit data when in slave mode, the slave must load data into the transmit buffer and enable the transmitter. The data will remain
in the USART until the master starts a transmission by pulling the USn_CS input of the slave low and transmitting data. For every frame
the master transmits to the slave, a frame is transferred from the slave to the master. After a transmission, MISO remains in the same
state as the last bit transmitted. This also applies if the master transmits to the slave and the slave TX buffer is empty.
If the transmitter is enabled in synchronous slave mode and the master starts transmission of a frame, the underflow interrupt flag
TXUF in USARTn_IF will be set if no data is available for transmission to the master.
If the slave needs to control its own chip select signal, this can be achieved by clearing CSPEN in the ROUTE register. The internal
chip select signal can then be controlled through CSINV in the CTRL register. The chip select signal will be CSINV inverted, i.e. if
CSINV is cleared, the chip select is active and vice versa.
16.3.3.7 Synchronous Half Duplex Communication
Half duplex communication in synchronous mode is very similar to half duplex communication in asynchronous mode as detailed in
16.3.2.15 Asynchronous Half Duplex Communication. The main difference is that in this mode, the master must generate the bus clock
even when it is not transmitting data, i.e. it must provide the slave with a clock to receive data. To generate the bus clock, the master
should transmit data with the transmitter tristated, i.e. TXTRI in USARTn_STATUS set, when receiving data. If 2 bytes are expected
from the slave, then transmit 2 bytes with the transmitter tristated, and the slave uses the generated bus clock to transmit data to the
master. TXTRI can be set by setting the TXTRIEN command bit in USARTn_CMD.
Note:
When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled) during data reception if the slave is to transmit
data in the current transfer.
16.3.3.8 I2S
I2S is a synchronous format for transmission of audio data. The frame format is 32-bit, but since data is always transmitted with MSB
first, an I2S device operating with 16-bit audio may choose to only process the 16 msb of the frame, and only transmit data in the 16
msb of the frame.
In addition to the bit clock used for regular synchronous transfers, I2S mode uses a separate word clock. When operating in mono
mode, with only one channel of data, the word clock pulses once at the start of each new word. In stereo mode, the word clock toggles
at the start of new words, and also gives away whether the transmitted word is for the left or right audio channel; A word transmitted
while the word clock is low is for the left channel, and a word transmitted while the word clock is high is for the right.
When operating in I2S mode, the CS pin is used as a the word clock. In master mode, this is automatically driven by the USART, and in
slave mode, the word clock is expected from an external master.
16.3.3.9 Word Format
The general I2S word format is 32 bits wide, but the USART also supports 16-bit and 8-bit words. In addition to this, it can be specified
how many bits of the word should actually be used by the USART. These parameters are given by FORMAT in USARTn_I2SCTRL.
As an example, configuring FORMAT to using a 32-bit word with 16-bit data will make each word on the I2S bus 32-bits wide, but when
receiving data through the USART, only the 16 most significant bits of each word can be read out of the USART. Similarly, only the 16
most significant bits have to be written to the USART when transmitting. The rest of the bits will be transmitted as zeroes.
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16.3.3.10 Major Modes
The USART supports a set of different I2S formats as shown in Table 16.9 USART I2S Modes on page 461, but it is not limited to these
modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e. one data stream instead of two which is the default. JUSTIFY aligns data within a word on the I2S bus, either left
or right which can bee seen in figures Figure 16.23 USART Left-justified I2S waveform on page 462 and Figure 16.24 USART Rightjustified I2S waveform on page 462. Finally, DELAY specifies whether a new I2S word should be started directly on the edge of the
word-select signal, or one bit-period after the edge.
Table 16.9. USART I2S Modes
Mode
MONO
JUSTIFY
DELAY
CLKPOL
Regular I2S
0
0
1
0
Left-Justified
0
0
0
1
Right-Justified
0
1
0
1
Mono
1
0
0
0
The regular I2S waveform is shown in Figure 16.21 USART Standard I2S waveform on page 461 and Figure 16.22 USART Standard
I2S waveform (reduced accuracy) on page 461. The first figure shows a waveform transmitted with full accuracy. The wordlength can
be configured to 32-bit, 16-bit or 8-bit using FORMAT in USARTn_I2SCTRL. In the second figure, I2S data is transmitted with reduced
accuracy, i.e. the data transmitted has less bits than what is possible in the bus format.
Note that the msb of a word transmitted in regular I2S mode is delayed by one cycle with respect to word select
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX
LSB
MSB
Right channel
LSB
Left channel
MSB
Right channel
Figure 16.21 USART Standard I2S waveform
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX
Right channel
MSB
LSB
Left channel
MSB
Right channel
Figure 16.22 USART Standard I2S waveform (reduced accuracy)
A left-justified stream is shown in Figure 16.23 USART Left-justified I2S waveform on page 462. Note that the MSB comes directly after
the edge on the word-select signal in contradiction to the regular I2S waveform where it comes one bit-period after.
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USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX
MSB
LSB
Right channel
MSB
Left channel
Right channel
Figure 16.23 USART Left-justified I2S waveform
A right-justified stream is shown in Figure 16.24 USART Right-justified I2S waveform on page 462. The left and right justified streams
are equal when the data-size is equal to the word-width.
USn_CLK
USn_TX/
USn_RX
LSB
MSB
Right channel
LSB
Left channel
Right channel
Figure 16.24 USART Right-justified I2S waveform
In mono-mode, the word-select signal pulses at the beginning of each word instead of toggling for each word. Mono I2S waveform is
shown in Figure 16.25 USART Mono I2S waveform on page 462.
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX
MSB
Right channel
LSB
Left channel
MSB
Right channel
Figure 16.25 USART Mono I2S waveform
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16.3.3.11 Using I2S Mode
When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all
modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in
USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.
The USART does not have separate TX and RX buffers for left and right data, so when using I2S in stereo mode, the application must
keep track of whether the buffers contain left or right data. This can be done by observing TXBLRIGHT, RXDATAVRIGHT and RXFULLRIGHT in USARTn_STATUS. TXBLRIGHT tells whether TX is expecting data for the left or right channel. It will be set with TXBL if right
data is expected. The receiver will set RXDATAVRIGHT if there is at least one right element in the buffer, and RXFULLRIGHT if the
buffer is full of right elements.
When using I2S with DMA, separate DMA requests can be used for left and right data by setting DMASPLIT in USARTn_I2SCTRL.
In both master and slave mode the USART always starts transmitting on the LEFT channel after being enabled. In master mode, the
transmission will stop if TX becomes empty. In that case, TXC is set. Continuing the transmission in this case will make the data-stream
continue where it left off. To make the USART start on the LEFT channel after going empty, disable and re-enable TX.
16.3.4 Hardware Flow Control
Hardware flow control can be used to hold off the link partner's transmission until RX buffer space is available. Use RTSPEN and
CTSPEN in USARTn_ROUTEPEN to allocate the hardware flow control to GPIOs. RTS is an out going signal which indicates that RX
buffer space is available to receive a frame. The link partner is being requested to send its data when RTS is asserted. CTS is an incoming signal to stop the next TX data from going out. When CTS is negated, the frame currently being transmitted is completed before
stopping. CTS indicates that the link partner has RX buffer space available, and the local transmitter is clear to send. Also use CTSEN
in USARTn_CTLX to enable the CTS input into the TX sequencer. For debug use set DBGHALT in USARTn_CTRLX which will force
the RTS to request one frame from the link partner when the CPU core single steps.
16.3.5 Debug Halt
When DBGHALT in USART_CTRLX is clear, RTS is only dependent on the RX buffer having space available to receive data. Incoming
data is always received until both the RX buffer is full and the RX shift register is full regardless of the state of DBGHALT or chip halt.
Additional incoming data is discarded. When DBGHALT is set, RTS deasserts on RX buffer full or when chip halt is high. However, a
low pulse detected on chip halt will keep RTS asserted when no frame is being received. At the start of frame reception, RTS will deassert if chip halt is high and DBGHALT is set. This behavior allows single stepping to pulse the chip halt low for a cycle, and receive the
next frame. The link partner must stop transmitting when RTS is deasserted, or the RX buffer could overflow. All data in the transmit
buffer is sent out even when chip halt is asserted; therefore, the DMA will need to be set to stop sending the USART TX data during
chip halt.
16.3.6 PRS-triggered Transmissions
If a transmission must be started on an event with very little delay, the PRS system can be used to trigger the transmission. The PRS
channel to use as a trigger can be selected using TSEL in USARTn_TRIGCTRL. When a positive edge is detected on this signal, the
receiver is enabled if RXTEN in USARTn_TRIGCTRL is set, and the transmitter is enabled if TXTEN in USARTn_TRIGCTRL is set.
Only one signal input is supported by the USART.
The AUTOTX feature can also be enabled via PRS. If an external SPI device sets a pin high when there is data to be read from the
device, this signal can be routed to the USART through the PRS system and be used to make the USART clock data out of the external
device. If AUTOTXTEN in USARTn_TRIGCTRL is set, the USART will transmit data whenever the PRS signal selected by TSEL is high
given that there is enough room in the RX buffer for the chosen frame size. Note that if there is no data in the TX buffer when using
AUTOTX, the TX underflow interrupt will be set.
AUTOTXTEN can also be combined with TXTEN to make the USART transmit a command to the external device prior to clocking out
data. To do this, disable TX using the TXDIS command, load the TX buffer with the command and enable AUTOTXTEN and TXTEN.
When the selected PRS input goes high, the USART will now transmit the loaded command, and then continue clocking out while both
the PRS input is high and there is room in the RX buffer
16.3.7 PRS RX Input
The USART can be configured to receive data directly from a PRS channel by setting RXPRS in USARTn_INPUT. The PRS channel
used is selected using RXPRSSEL in USARTn_INPUT. This way, for example, a differential RX signal can be input to the ACMP and
the output routed via PRS to the USART.
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16.3.8 PRS CLK Input
The USART can be configured to receive clock directly from a PRS channel by setting CLKPRS in USARTn_INPUT. The PRS channel
used is selected using CLKPRSSEL in USARTn_INPUT. This is useful in synchronous slave mode and can together with RX PRS input
be used to input data from PRS.
16.3.9 DMA Support
The USART has full DMA support. The DMA controller can write to the transmit buffer using the registers USARTn_TXDATA,
USARTn_TXDATAX, USARTn_TXDOUBLE and USARTn_TXDOUBLEX, and it can read from the receive buffer using the registers
USARTn_RXDATA, USARTn_RXDATAX, USARTn_RXDOUBLE and USARTn_RXDOUBLEX. This enables single byte transfers, 9 bit
data + control/status bits, double byte and double byte + control/status transfers both to and from the USART.
A request for the DMA controller to read from the USART receive buffer can come from the following source:
• Data available in the receive buffer
• Data available in the receive buffer and data is for the RIGHT I2S channel. Only used in I2S mode.
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send.
• Transmit buffer has room for more data
• Transmit buffer has room for RIGHT I2S data. Only used in I2S mode
Even though there are two sources for write requests to the DMA, only one should be used at a time, since the requests from both
sources are cleared even though only one of the requests are used.
In some cases, it may be sensible to temporarily stop DMA access to the USART when an error such as a framing error has occurred.
This is enabled by setting ERRSDMA in USARTn_CTRL.
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16.3.10 Timer
In addition to the TX sequence timer, there is a versatile 8 bit timer that can generate up to three event pulses. These pulses can be
used to create timing for a variety of uses such as RX timeout, break detection, response timeout, and RX enable delay. Transmission
delay, CS setup, inter-character spacing, and CS hold use the TX sequence counter. The TX sequencer counter can use the three 8 bit
compare values or preset values for delays. There is one general counter with three comparators. Each comparator has a start source,
a stop source, a restart enable, and a timer compare value. The start source enables the comparator, resets the counter, and starts the
counter. If the counter is already running, the start source will reset the counter and restart it.
Any comparator could start the counter using the same start source but have different timing events programmed into TCMPVALn in
USARTn_TIMECMPn. The TCMP0, TCMP1, or TCMP2 events can be preempted by using the comparator stop source to disable the
comparator before the counter reaches TCMPVAL0, TCMPVAL1, or TCMPVAL2. If one comparator gets disabled while the other comparator is still enabled, the counter continues counting. By default the counter will count up to 256 and stop unless a RESTARTEN is set
in one of the USARTn_TIMECMPn registers. By using RESTARTEN and an interval programmed into TCMPVAL, an interval timer can
be set up. The TSTART field needs to be changed to DISABLE to stop the interval timer. The timer stops running once all of the comparators are disabled. If a comparator's start and stop sources both trigger the same cycle, the TCMPn event triggers, the comparator
stays enabled, and the counter begins counting from zero.
The TXDELAY, CSSETUP, ICS, and CSHOLD in USARTn_TIMING are used to program start of transmission delay, chip select setup
delay, inter-character space, and chip select hold delay. Either a preset value of 0, 1, 2, 3, or 7 can be used for any of these delays; or
the value in TCMPVALn may be used to set the delay. Using the preset values leaves the TCMPVALn free for other uses. The same
TCMPVALn may be used for multiple events that require the same timing. The transmit sequencer's counter can run in parallel with the
timer's counter. The counters and controls are shown in Figure 16.26 USART Timer Block Diagram on page 466.
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TIMECMP2
TIMECMP1
TIMECMP0
TCMPn
TXST
RXACT
RXACTN
TCMPVALn
TSTOP
GP_CNT[7:0]
clear
DISABLE
TXEOF
TXC
RXACT
RXEOF
TCMP
enable
TSTART
Compare
START_An
TCMPn
RESTARTEN
START_Bn
START_A2
START_B2
START_A1
START_B1
start
event
START_A0
START_B0
TXARX2EN
TCMP2
bit time
TCMPVAL2
TCMPVAL1
TCMPVAL0
8 bit
Counter
GP_CNT[7:0]
TXEOF
TXSEQ
TXC
TX Counter
TXARX1EN
TCMP1
TXST
TXENS
TX
TXARX0EN
TCMP0
RXSEQ
RX
RXATX2EN
TCMP2
RXATX1EN
TCMP1
RXEOF
RXENS
RXATX0EN
TCMP0
Figure 16.26 USART Timer Block Diagram
The following sections will go into more details on programming the various usage cases.
Table 16.10. USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn
Application
TSTARTn
Response Timeout
TCMPVALn
Other
TSTART0 = TXEOF TSTOP0 = RXACT
TCMPVAL0
= 0x08
TCMP0 in USARTn_IEN
Receiver Timeout
TSTART1 = RXEOF TSTOP1 = RXACT
TCMPVAL1
= 0x08
TCMP1 in USARTn_IEN
Large Receiver Timeout
TSTART1 =
RXEOF, TCMP1
TCMPVAL1
= 0xFF
TCMP1 in USARTn_IEN; TIMERRESTARTED in USARTn_STATUS; RESTART1EN in
USARTn_TIMECMP1
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TSTOPn
TSTOP1 = RXACT
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Application
TSTARTn
TSTOPn
Break Detect
TSTART1 = RXACT TSTOP1 =
RXACTN
TCMPVALn
Other
TCMPVAL1
= 0x0C
TCMP1 in USARTn_IEN
TX delayed start of transmission and TSTART0 = DISACS setup
BLE, TSTART1 =
DISABLE
TSTOP0 = TCMP0,
TSTOP1 = TCMP1
TCMPVAL0
= 0x04,
TCMPVAL1
= 0x02
TXDELAY = TCMP0, CSSETUP =
TCMP1 in USARTn_TIMING; AUTOCS in USARTn_CTRL
TX inter-character spacing
TSTART2 = DISABLE
TSTOP2 = TCMP2
TCMPVAL2
= 0x03
ICS = TCMP2 in USARTn_TIMING;
AUTOCS in USARTn_CTRL
TX Chip Select End Delay
TSTART1 = DISABLE
TSTOP1 = TCMP1
TCMPVAL1
= 0x04
CSHOLD = TCMP1 in
USARTn_TIMING; AUTOCS in
USARTn_CTRL
Response Delay
TSTART1 = RXEOF TSTOP1 = TCMP1
TCMPVAL1
= 0x08
TXARX1EN in USARTn_TRIGCTRL
Combined TX and RX Example
TSTART1 =
RXEOF, TSTART0
= TXEOF
TSTOP1 = TCMP1,
TSTOP0 = TCMP0
TCMPVAL1
= 0x1C,
TCMPVAL0
= 0x10
TXARX1EN, RXATX0EN in
USARTn_TRIGCTRL; CSSETUP =
0x7, CSHOLD = 0x3 in
USARTn_TIMING
Combined Delayed TX and Receiver TSTART0 =
TSTOP0 =
Timeout Example
TCMPVAL0,
RXACTN, TSTOP1
TSTART1 = RXEOF = RXACT
TCMPVAL0
= 0x20,
TCMPVAL1
= 0x0C
TXARX0EN in
USARTn_TRIGCTRL; TCMP0 in
USARTn_IEN
Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 shows some examples of how
the USART timer can be programmed for various applications. The following sections will describe more details for each applications
shown in the table.
16.3.10.1 Response Timeout
Response Timeout is when a UART master sends a frame and expects the slave to respond within a certain number of baud-times.
Refer to Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 for specific register settings. Comparator 0 will be looking for TX end of frame to use as the timer start source. For this example, a receiver start of frame
RXACT has not been detected for 8 baud-times, and the TCMP0 interrupt in USARTn_IF is set. If an RX start bit is detected before the
8 baud-times, comparator 0 is disabled before the TCMP0 event can trigger.
TC
M
Pn
IN
T
TX
RX
RESPONSE TIMEOUT
Figure 16.27 USART Response Timeout
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16.3.10.2 RX Timeout
TC
RX
M
Pn
IN
T
A receiver timeout function can be implemented by using the RX end of frame to start comparator 1 and look for the RX start bit RXACT
to disable the comparator. See Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466
for details on setting up this example. As long as the next RX start bit occurs before the counter reaches the comparator 1 value
TCMPVAL1, the interrupt will not get set. In this example the RX Timeout was set to 8 baud-times. To get an RX timeout larger than 256
baud-times, RESTART1EN in USARTn_TIMER can used to restart the counter when it reaches TCMPVAL1. By setting TCMPVAL1 in
USARTn_TIMING to 0xFF, an interrupt will be generated after 256 baud-times. An interrupt service routine can then increment a memory location until the desired timeout is reached. Once the RX start bit is detected, comparator 1 will be disabled. If TIMERRESTARTED
in USARTn_STATUS is clear, the TCMP1 interrupt is the first interrupt after RXEOF.
RX
RECEIVER TIMEOUT
Figure 16.28 USART RX Timeout
16.3.10.3 Break Detect
M
Pn
IN
T
LIN bus and half-duplex UARTs can take advantage of the timer configured for break detection where RX is held low for a number of
baud-times to indicate a break condition. Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on
page 466 shows the settings for this mode. Each time RX is active (default of low) such as for a start bit, the timer begins counting. If
the counter reaches 12 baud-times before RX goes to inactive RXACTN (default of high), an interrupt is asserted.
TC
RX
BREAK DETECT
Figure 16.29 USART Break Detection
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16.3.10.4 TX Start Delay
Some applications may require a delay before the start of transmission. This example in Figure 16.30 USART TXSEQ Timing on page
469 shows the TXSEQ timer used to delay the start of transmission by 4 baud times before the start of CS, and by 2 baud times with
CS asserted. See Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 for details on
how to configure this mode. The TX sequencer could be enabled on PRS and start the TXSEQ counter running for 4 baud times as
programmed in TCMPVAL0. Then CS is asserted for 2 baud times before the transmitter begins sending TX data. TXDELAY in
USARTn_TIMING is the initial delay before any CS assertion, and CSSETUP is the delay during CS assertion. There are several small
preset timing values such as 1, 2, 3, or 7 that can be used for some of the TX sequencer timing which leaves TCMPVAL0, TCMPVAL1,
and TCMPVAL2 free for other uses.
TX_DELAY
TX
TX
SETUP
CS
TX
ICS
HOLD
Figure 16.30 USART TXSEQ Timing
16.3.10.5 Inter-Character Space
In addition to delaying the start of frame transmission, it is sometimes necessary to also delay the time between each transmit character
(inter-character space). After the first transmission, the inter-character space will delay the start of all subsequent transmissions until
the transmit buffer is empty. See Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466
for details on setting up this example. For this example in Figure 16.30 USART TXSEQ Timing on page 469 ICS is set to TCMP2 in
USARTn_TIMING. To keep CS asserted during the inter-character space, set AUTOCS in USARTn_CTRL. There are a few small preset timing values provided for TX sequence timing. Using these preset timing values can free up the TCMPVALn for other uses. For this
example, the inter-character space is set to 0x03 and a preset value could be used.
16.3.10.6 TX Chip Select End Delay
The assertion of CS can be extended after the final character of the frame by using CSHOLD in USARTn_TIMING. See Table
16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 for details on setting up this example.
AUTOCS in USARTn_CTRL needs to be set to extend the CS assertion after the last TX character is transmitted as shown in Figure
16.30 USART TXSEQ Timing on page 469.
16.3.10.7 Response Delay
A response delay can be used to hold off the transmitter until a certain number of baud-times after the RX frame. See Table
16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 for details on setting up this example.
TXARX1EN in USARTn_TRIGCTRL tells the TX sequencer to trigger after RX EOF plus tcmp1val baud times.
TX
EN
S
RX
TX
RESPONSE DELAY
Figure 16.31 USART Response Delay
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16.3.10.8 Combined TX and RX Example
This example describes how to alternate between TX and RX frames. This has a 28 baud-time space after RX and a 16 baud-time
space after TX. The TSTART1 in USARTn_TIMECMP1 is set to RXEOF which uses the the receiver end of frame to start the timer. The
TSTOP1 is set to TCMP1 to generate an event after 28 baud times. Set TXARX1EN in USARTn_TRIGCTRL, and the transmitter is
held off until 28 baud times. TCMPVAL in USARTn_TIMECMP1 is set to 0x1C for 28 baud times. By setting TSTART0 in
USARTn_TIMECMP0 to TXEOF, the timer will be started after the transmission has completed. RXATX0EN in USARTn_TRIGCTRL is
used to delay enabling of the receiver until 16 baud times after the transmitter has completed. Write 0x10 into TCMPVAL of
USARTn_TIMECMP0 for a 16 baud time delay. CS is also asserted 7 baud-times before start of transmission by setting CSSETUP to
0x7 in USARTn_TIMING. To keep CS asserted for 3 baud-times after transmission completes, CSHOLD is set to 0x3 in USARTn_TIMING. See Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 for details on setting
up this example.
16.3.10.9 Combined TX delay and RX break detect
This example describes how to delay TX transmission after an RX frame and how to have a break condition signal an interrupt. See
Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 466 for details on setting up this example. The TX delay is set up by using transmit after RX, TXARX0EN in USARTn_TRIGCTRL to start the timer. TSTART0 in
USARTn_TIMECMP0 is set to RXEOF which enables the transitter of the timer delay. For this example TCMPVAL in
USARTn_TIMECMP0 is set to 0x20 to create a 32 baud-time delay between the end of the RX frame and the start of the TX frame. The
break detect is configured by setting TSTART1 to RXACT to detect the start bit, and setting TSTOP1 to RXACTN to detect RX going
high. In this case the interrupt asserts after RX stays low for 12 baud-times, so TCMPVAL1 is set to 0x0C.
16.3.10.10 Other Stop Conditions
There is also a timer stop on TX start using the TXST setting in TSTOP of USARTn_TIMECMPn. This can be used to see that the DMA
has not written to the TXBUFFER for a given time.
16.3.11 Interrupts
The interrupts generated by the USART are combined into two interrupt vectors. Interrupts related to reception are assigned to one
interrupt vector, and interrupts related to transmission are assigned to the other. Separating the interrupts in this way allows different
priorities to be set for transmission and reception interrupts.
The transmission interrupt vector groups the transmission-related interrupts generated by the following interrupt flags:
• TXC
• TXBL
• TXOF
• CCF
• TXIDLE
The reception interrupt on the other hand groups the reception-related interrupts, triggered by the following interrupt flags:
• RXDATAV
• RXFULL
• RXOF
• RXUF
• PERR
• FERR
• MPAF
• SSM
• TCMPn
If USART interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in USART_IF and their corresponding bits
in USART_IEN are set.
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16.3.12 IrDA Modulator/ Demodulator
The IrDA modulator on USART0 implements the physical layer of the IrDA specification, which is necessary for communication over
IrDA. The modulator takes the signal output from the USART module, and modulates it before it leaves USART0. In the same way, the
input signal is demodulated before it enters the actual USART module. The modulator is only available on USART0, and implements
the original Rev. 1.0 physical layer and one high speed extension which supports speeds from 2.4 kbps to 1.152 Mbps.
The data from and to the USART is represented in a NRZ (Non Return to Zero) format, where the signal value is at the same level
through the entire bit period. For IrDA, the required format is RZI (Return to Zero Inverted), a format where a “1” is signalled by holding
the line low, and a “0” is signalled by a short high pulse. An example is given in Figure 16.32 USART Example RZI Signal for a given
Asynchronous USART Frame on page 471.
Idle
USART
(NRZ)
Idle
S
0
1
2
3
4
5
6
7
P
Stop
IrDA
(RZI)
Figure 16.32 USART Example RZI Signal for a given Asynchronous USART Frame
The IrDA module is enabled by setting IREN. The USART transmitter output and receiver input is then routed through the IrDA modulator.
The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL. Four pulse widths are available, each defined relative to the configured bit period as listed in Table 16.11 USART IrDA Pulse Widths on page 471.
Table 16.11. USART IrDA Pulse Widths
IRPW
Pulse width OVS=0
Pulse width OVS=1
Pulse width OVS=2
Pulse width OVS=3
00
1/16
1/8
1/6
1/4
01
2/16
2/8
2/6
N/A
10
3/16
3/8
N/A
N/A
11
4/16
N/A
N/A
N/A
By default, no filter is enabled in the IrDA demodulator. A filter can be enabled by setting IRFILT in USARTn_IRCTRL. When the filter is
enabled, an incoming pulse has to last for 4 consecutive clock cycles to be detected by the IrDA demodulator.
Note that by default, the idle value of the USART data signal is high. This means that the IrDA modulator generates negative pulses,
and the IrDA demodulator expects negative pulses. To make the IrDA module use RZI signalling, both TXINV and RXINV in
USARTn_CTRL must be set.
The IrDA module can also modulate a signal from the PRS system, and transmit a modulated signal to the PRS system. To use a PRS
channel as transmitter source instead of the USART, set IRPRSEN in USARTn_IRCTRL high. The channel is selected by configuring
IRPRSSEL in USARTn_IRCTRL.
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16.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
USARTn_CTRL
RW
Control Register
0x004
USARTn_FRAME
RW
USART Frame Format Register
0x008
USARTn_TRIGCTRL
RW
USART Trigger Control register
0x00C
USARTn_CMD
W1
Command Register
0x010
USARTn_STATUS
R
USART Status Register
0x014
USARTn_CLKDIV
RWH
Clock Control Register
0x018
USARTn_RXDATAX
R(a)
RX Buffer Data Extended Register
0x01C
USARTn_RXDATA
R(a)
RX Buffer Data Register
0x020
USARTn_RXDOUBLEX
R(a)
RX Buffer Double Data Extended Register
0x024
USARTn_RXDOUBLE
R(a)
RX FIFO Double Data Register
0x028
USARTn_RXDATAXP
R
RX Buffer Data Extended Peek Register
0x02C
USARTn_RXDOUBLEXP
R
RX Buffer Double Data Extended Peek Register
0x030
USARTn_TXDATAX
W
TX Buffer Data Extended Register
0x034
USARTn_TXDATA
W
TX Buffer Data Register
0x038
USARTn_TXDOUBLEX
W
TX Buffer Double Data Extended Register
0x03C
USARTn_TXDOUBLE
W
TX Buffer Double Data Register
0x040
USARTn_IF
R
Interrupt Flag Register
0x044
USARTn_IFS
W1
Interrupt Flag Set Register
0x048
USARTn_IFC
(R)W1
Interrupt Flag Clear Register
0x04C
USARTn_IEN
RW
Interrupt Enable Register
0x050
USARTn_IRCTRL
RW
IrDA Control Register
0x058
USARTn_INPUT
RW
USART Input Register
0x05C
USARTn_I2SCTRL
RW
I2S Control Register
0x060
USARTn_TIMING
RW
Timing Register
0x064
USARTn_CTRLX
RW
Control Register Extended
0x068
USARTn_TIMECMP0
RW
Used to generate interrupts and various delays
0x06C
USARTn_TIMECMP1
RW
Used to generate interrupts and various delays
0x070
USARTn_TIMECMP2
RW
Used to generate interrupts and various delays
0x074
USARTn_ROUTEPEN
RW
I/O Routing Pin Enable Register
0x078
USARTn_ROUTELOC0
RW
I/O Routing Location Register
0x07C
USARTn_ROUTELOC1
RW
I/O Routing Location Register
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0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW 0x0
RW
RW
RW
RW
RW
AUTOTX
BYTESWAP
SSSEARLY
ERRSTX
ERRSRX
ERRSDMA
BIT8DV
SKIPPERRF
SCRETRANS RW
RW
Name
MVDIS
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SCMODE
AUTOTRI
AUTOCS
CSINV
TXINV
RXINV
TXBIL
CSMA
MSBF
CLKPHA
CLKPOL
OVS
MPAB
MPM
CCEN
LOOPBK
SYNC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Offset
0
0
0
0
0
0
0
0
0
31
0x000
0
Access
RW
Reset
SMSDELAY
USART - Universal Synchronous Asynchronous Receiver/Transmitter
EFM32JG1 Reference Manual
16.5 Register Description
16.5.1 USARTn_CTRL - Control Register
Bit Position
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Bit
Name
Reset
Access
Description
31
SMSDELAY
0
RW
Synchronous Master Sample Delay
Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher
speeds
30
MVDIS
0
RW
Majority Vote Disable
Disable majority vote for 16x, 8x and 6x oversampling modes.
29
AUTOTX
0
RW
Always Transmit When RX Not Full
Transmits as long as RX is not full. If TX is empty, underflows are generated.
28
BYTESWAP
0
RW
Byteswap In Double Accesses
Set to switch the order of the bytes in double accesses.
Value
Description
0
Normal byte order
1
Byte order swapped
27:26
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
25
SSSEARLY
0
RW
Synchronous Slave Setup Early
Setup data on sample edge in synchronous slave mode to improve MOSI setup time
24
ERRSTX
0
RW
Disable TX On Error
When set, the transmitter is disabled on framing and parity errors (asynchronous mode only) in the receiver.
23
Value
Description
0
Received framing and parity errors have no effect on transmitter
1
Received framing and parity errors disable the transmitter
ERRSRX
0
RW
Disable RX On Error
When set, the receiver is disabled on framing and parity errors (asynchronous mode only).
22
Value
Description
0
Framing and parity errors have no effect on receiver
1
Framing and parity errors disable the receiver
ERRSDMA
0
RW
Halt DMA On Error
When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only).
21
Value
Description
0
Framing and parity errors have no effect on DMA requests from the
USART
1
DMA requests from the USART are blocked while the PERR or FERR
interrupt flags are set
BIT8DV
0
RW
Bit 8 Default Value
The default value of the 9th bit. If 9-bit frames are used, and an 8-bit write operation is done, leaving the 9th bit unspecified,
the 9th bit is set to the value of BIT8DV.
20
SKIPPERRF
0
RW
Skip Parity Error Frames
When set, the receiver discards frames with parity errors (asynchronous mode only). The PERR interrupt flag is still set.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
19
SCRETRANS
0
RW
SmartCard Retransmit
When in SmartCard mode, a NACK'ed frame will be kept in the shift register and retransmitted if the transmitter is still enabled.
18
SCMODE
0
RW
SmartCard Mode
Use this bit to enable or disable SmartCard mode.
17
AUTOTRI
0
RW
Automatic TX Tristate
When enabled, TXTRI is set by hardware whenever the transmitter is idle, and TXTRI is cleared by hardware when transmission starts.
16
Value
Description
0
The output on U(S)n_TX when the transmitter is idle is defined by
TXINV
1
U(S)n_TX is tristated whenever the transmitter is idle
AUTOCS
0
RW
Automatic Chip Select
When enabled, the output on USn_CS will be activated one baud-period before transmission starts, and deactivated when
transmission ends.
15
CSINV
0
RW
Chip Select Invert
Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller
as a slave.
14
Value
Description
0
Chip select is active low
1
Chip select is active high
TXINV
0
RW
Transmitter output Invert
The output from the USART transmitter can optionally be inverted by setting this bit.
13
Value
Description
0
Output from the transmitter is passed unchanged to U(S)n_TX
1
Output from the transmitter is inverted before it is passed to U(S)n_TX
RXINV
0
RW
Receiver Input Invert
Setting this bit will invert the input to the USART receiver.
12
Value
Description
0
Input is passed directly to the receiver
1
Input is inverted before it is passed to the receiver
TXBIL
0
RW
TX Buffer Interrupt Level
Determines the interrupt and status level of the transmit buffer.
Value
Mode
Description
0
EMPTY
TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty.
1
HALFFULL
TXBL and TXBLIF are set when the transmit buffer goes from full to
half-full or empty. TXBL is cleared when the buffer becomes full.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
11
CSMA
0
RW
Action On Slave-Select In Master Mode
This register determines the action to be performed when slave-select is configured as an input and driven low while in
master mode.
10
Value
Mode
Description
0
NOACTION
No action taken
1
GOTOSLAVEMODE
Go to slave mode
MSBF
0
Most Significant Bit First
RW
Decides whether data is sent with the least significant bit first, or the most significant bit first.
9
Value
Description
0
Data is sent with the least significant bit first
1
Data is sent with the most significant bit first
CLKPHA
0
RW
Clock Edge For Setup/Sample
Determines where data is set-up and sampled according to the bus clock when in synchronous mode.
8
Value
Mode
Description
0
SAMPLELEADING
Data is sampled on the leading edge and set-up on the trailing edge of
the bus clock in synchronous mode
1
SAMPLETRAILING
Data is set-up on the leading edge and sampled on the trailing edge of
the bus clock in synchronous mode
CLKPOL
0
Clock Polarity
RW
Determines the clock polarity of the bus clock used in synchronous mode.
Value
Mode
Description
0
IDLELOW
The bus clock used in synchronous mode has a low base value
1
IDLEHIGH
The bus clock used in synchronous mode has a high base value
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:5
OVS
0x0
RW
Oversampling
Sets the number of clock periods in a UART bit-period. More clock cycles gives better robustness, while less clock cycles
gives better performance.
4
Value
Mode
Description
0
X16
Regular UART mode with 16X oversampling in asynchronous mode
1
X8
Double speed with 8X oversampling in asynchronous mode
2
X6
6X oversampling in asynchronous mode
3
X4
Quadruple speed with 4X oversampling in asynchronous mode
MPAB
0
RW
Multi-Processor Address-Bit
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks
the frame as a multi-processor address frame.
3
MPM
0
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RW
Multi-Processor Mode
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame.
2
Value
Description
0
The 9th bit of incoming frames has no special function
1
An incoming frame with the 9th bit equal to MPAB will be loaded into
the receive buffer regardless of RXBLOCK and will result in the MPAB
interrupt flag being set
CCEN
0
RW
Collision Check Enable
Enables collision checking on data when operating in half duplex modus.
1
Value
Description
0
Collision check is disabled
1
Collision check is enabled. The receiver must be enabled for the check
to be performed
LOOPBK
0
RW
Loopback Enable
Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication.
0
Value
Description
0
The receiver is connected to and receives data from U(S)n_RX
1
The receiver is connected to and receives data from U(S)n_TX
SYNC
0
RW
USART Synchronous Mode
Determines whether the USART is operating in asynchronous or synchronous mode.
Value
Description
0
The USART operates in asynchronous mode
1
The USART operates in synchronous mode
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.2 USARTn_FRAME - USART Frame Format Register
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0
1
2
RW 0x5
3
4
6
7
8
9
RW 0x0
10
11
12
13
14
15
16
17
18
19
20
21
5
DATABITS
Name
PARITY
Access
STOPBITS RW 0x1
Reset
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:12
STOPBITS
0x1
RW
Description
Stop-Bit Mode
Determines the number of stop-bits used.
Value
Mode
Description
0
HALF
The transmitter generates a half stop bit. Stop-bits are not verified by
receiver
1
ONE
One stop bit is generated and verified
2
ONEANDAHALF
The transmitter generates one and a half stop bit. The receiver verifies
the first stop bit
3
TWO
The transmitter generates two stop bits. The receiver checks the first
stop-bit only
11:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
9:8
PARITY
0x0
RW
Parity-Bit Mode
Determines whether parity bits are enabled, and whether even or odd parity should be used. Only available in asynchronous mode.
Value
Mode
Description
0
NONE
Parity bits are not used
2
EVEN
Even parity are used. Parity bits are automatically generated and
checked by hardware.
3
ODD
Odd parity is used. Parity bits are automatically generated and checked
by hardware.
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
DATABITS
0x5
RW
Data-Bit Mode
This register sets the number of data bits in a USART frame.
Value
Mode
Description
1
FOUR
Each frame contains 4 data bits
2
FIVE
Each frame contains 5 data bits
3
SIX
Each frame contains 6 data bits
4
SEVEN
Each frame contains 7 data bits
5
EIGHT
Each frame contains 8 data bits
6
NINE
Each frame contains 9 data bits
7
TEN
Each frame contains 10 data bits
8
ELEVEN
Each frame contains 11 data bits
9
TWELVE
Each frame contains 12 data bits
10
THIRTEEN
Each frame contains 13 data bits
11
FOURTEEN
Each frame contains 14 data bits
12
FIFTEEN
Each frame contains 15 data bits
13
SIXTEEN
Each frame contains 16 data bits
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.3 USARTn_TRIGCTRL - USART Trigger Control register
0
1
2
3
4
RW
RXTEN
0
5
0
RW
TXTEN
6
0
AUTOTXTEN RW
7
0
RW
TXARX0EN
8
0
RW
TXARX1EN
9
0
RW
TXARX2EN
10
0
RW
RXATX0EN
12
11
0
RW
0
RW
RXATX1EN
13
14
15
RXATX2EN
Name
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16
17
19
20
21
18
RW 0x0
Access
TSEL
Reset
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:16
TSEL
0x0
RW
Description
Trigger PRS Channel Select
Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and
TXTEN.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
15:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
12
RXATX2EN
0
RW
Enable Receive Trigger after TX end of frame plus TCMPVAL2
baud-times
When set, a TX end of frame will trigger the receiver after a TCMPVAL2 baud-time delay
11
RXATX1EN
0
RW
Enable Receive Trigger after TX end of frame plus TCMPVAL1
baud-times
When set, a TX end of frame will trigger the receiver after a TCMPVAL1 baud-time delay
10
RXATX0EN
0
RW
Enable Receive Trigger after TX end of frame plus TCMPVAL0
baud-times
When set, a TX end of frame will trigger the receiver after a TCMPVAL0 baud-time delay
9
TXARX2EN
0
RW
Enable Transmit Trigger after RX End of Frame plus TCMP2VAL
When set, an RX end of frame will trigger the transmitter after TCMP2VAL bit times to force a minimum response delay
8
TXARX1EN
0
RW
Enable Transmit Trigger after RX End of Frame plus TCMP1VAL
When set, an RX end of frame will trigger the transmitter after TCMP1VAL bit times to force a minimum response delay
7
TXARX0EN
0
RW
Enable Transmit Trigger after RX End of Frame plus TCMP0VAL
When set, an RX end of frame will trigger the transmitter after TCMP0VAL bit times to force a minimum response delay
6
AUTOTXTEN
0
RW
AUTOTX Trigger Enable
When set, AUTOTX is enabled as long as the PRS channel selected by TSEL has a high value
5
TXTEN
0
RW
Transmit Trigger Enable
When set, the PRS channel selected by TSEL sets TXEN, enabling the transmitter on positive trigger edges.
4
RXTEN
0
RW
Receive Trigger Enable
When set, the PRS channel selected by TSEL sets RXEN, enabling the receiver on positive trigger edges.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
3:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16.5.4 USARTn_CMD - Command Register
Access
0
W1 0
RXEN
1
W1 0
RXDIS
2
W1 0
TXEN
Bit
Name
Reset
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
CLEARRX
0
W1
3
W1 0
TXDIS
4
W1 0
MASTEREN
5
W1 0
6
RXBLOCKEN
MASTERDIS
7
RXBLOCKDIS W1 0
W1 0
8
W1 0
TXTRIEN
9
W1 0
TXTRIDIS
10
W1 0
CLEARTX
Name
11
12
Access
W1 0
Reset
CLEARRX
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Description
Clear RX
Set to clear receive buffer and the RX shift register.
10
CLEARTX
0
W1
Clear TX
Set to clear transmit buffer and the TX shift register.
9
TXTRIDIS
0
W1
Transmitter Tristate Disable
Disables tristating of the transmitter output.
8
TXTRIEN
0
W1
Transmitter Tristate Enable
W1
Receiver Block Disable
Tristates the transmitter output.
7
RXBLOCKDIS
0
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
6
RXBLOCKEN
0
W1
Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
5
MASTERDIS
0
W1
Master Disable
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
4
MASTEREN
0
W1
Master Enable
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1.
To enable both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
3
TXDIS
0
W1
Transmitter Disable
W1
Transmitter Enable
W1
Receiver Disable
Set to disable transmission.
2
TXEN
0
Set to enable data transmission.
1
RXDIS
0
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
0
W1
Receiver Enable
Set to activate data reception on U(S)n_RX.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.5 USARTn_STATUS - USART Status Register
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0
R
RXENS
0
1
R
TXENS
0
2
3
R
0
R
RXBLOCK
MASTER
0
4
R
TXTRI
0
5
0
R
TXC
6
1
R
TXBL
7
0
R
RXDATAV
8
0
R
RXFULL
9
0
R
TXBDRIGHT
10
0
R
TXBSRIGHT
12
11
0
R
RXDATAVRIGHT
0
R
RXFULLRIGHT
13
1
R
TXIDLE
14
0
TIMERRESTARTED R
Name
15
16
17
0x0
R
18
19
20
21
Access
TXBUFCNT
Reset
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
TXBUFCNT
0x0
R
Description
TX Buffer Count
Count of TX buffer entry 0, entry 1, and TX shift register. For large frames, the count is only of TX buffer entry 0 and the TX
shifter register.
15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
14
TIMERRESTARTED
0
R
The USART Timer restarted itself
When the timer is restarting itself on each TCMP event, a TIMERRESTARTED value of 0x0 indicates the first TCMP event
in the sequence of multiple TCMP events. Any non TCMP timer start events will clear TIMERRESTARTED. When there is a
TCMP interrupt and TIMERRESTARTED is 0x0, an interrupt service routine can set a TCMP event counter variable in
memory to 0x1 to indicate the first TCMP interrupt of the sequence.
13
TXIDLE
1
R
TX Idle
0
R
RX Full of Right Data
Set when TX idle
12
RXFULLRIGHT
When set, the entire RX buffer contains right data. Only used in I2S mode
11
RXDATAVRIGHT
0
R
RX Data Right
When set, reading RXDATA or RXDATAX gives right data. Else left data is read. Only used in I2S mode
10
TXBSRIGHT
0
R
TX Buffer Expects Single Right Data
When set, the TX buffer expects at least a single right data. Else it expects left data. Only used in I2S mode
9
TXBDRIGHT
0
R
TX Buffer Expects Double Right Data
When set, the TX buffer expects double right data. Else it may expect a single right data or left data. Only used in I2S mode
8
RXFULL
0
R
RX FIFO Full
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one
more frame in the receive shift register.
7
RXDATAV
0
R
RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
6
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. If TXBIL is 0x0, TXBL is set whenever the transmit buffer is completely empty.
Otherwise TXBL is set whenever the TX Buffer becomes half full.
5
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer and shift register. Cleared
when data is written to the transmit buffer.
4
TXTRI
0
R
Transmitter Tristated
Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in USARTn_CTRL is set
this bit is always read as 0.
3
RXBLOCK
0
R
Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is
set at the instant the frame has been completely received.
2
MASTER
0
R
SPI Master Mode
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.
1
TXENS
0
R
Transmitter Enable Status
Set when the transmitter is enabled.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
0
RXENS
0
R
Receiver Enable Status
Set when the receiver is enabled.
16.5.6 USARTn_CLKDIV - Clock Control Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RWH 0x00000
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RW
Name
Bit
Name
Reset
Access
Description
31
AUTOBAUDEN
0
RW
AUTOBAUD detection enable
DIV
Access
AUTOBAUDEN
Reset
0
0x014
Bit Position
31
Offset
Detects the baud rate based on receiving a 0x55 frame (0x00 for IrDA). This is used in Asynchronous mode.
30:23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
22:3
DIV
0x00000
RWH
Fractional Clock Divider
Specifies the fractional clock divider for the USART. Setting AUTOBAUDEN in USARTn_CLKDIV will overwrite the DIV
field.
2:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads)
3
2
1
0
1
0
0x000 4
5
6
7
8
9
10
11
12
13
14
0
R
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
FERR
0
R
2
Access
3
Name
RXDATA R
FERR
R
Access
PERR
0
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Description
Data Framing Error
Set if data in buffer has a framing error. Can be the result of a break condition.
14
PERR
0
R
Data Parity Error
Set if data in buffer has a parity error (asynchronous mode only).
13:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
RXDATA
0x000
R
RX Data
Use this register to access data read from the USART. Buffer is cleared on read access.
16.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads)
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Reset
RXDATA R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
RXDATA
0x00
R
Description
RX Data
Use this register to access data read from USART. Buffer is cleared on read access. Only the 8 LSB can be read using this
register.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads)
FERR1
0
R
Data Framing Error 1
0
1
2
3
0x000 4
6
7
8
9
5
RXDATA0 R
31
R
Description
PERR0
Access
R
Reset
FERR0
Name
10
11
12
13
14
0
15
0
16
17
18
19
21
Bit
RXDATA1 R
R
Name
PERR1
0x000 20
22
23
24
25
26
27
28
29
30
R
0
Access
FERR1
Reset
0
0x020
Bit Position
31
Offset
Set if data in buffer has a framing error. Can be the result of a break condition.
30
PERR1
0
R
Data Parity Error 1
Set if data in buffer has a parity error (asynchronous mode only).
29:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24:16
RXDATA1
0x000
R
RX Data 1
R
Data Framing Error 0
Second frame read from buffer.
15
FERR0
0
Set if data in buffer has a framing error. Can be the result of a break condition.
14
PERR0
0
R
Data Parity Error 0
Set if data in buffer has a parity error (asynchronous mode only).
13:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
RXDATA0
0x000
R
RX Data 0
First frame read from buffer.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads)
1
0
0
3
4
1
Access
2
Name
2
RXDATA1 R
Access
RXDATA0 R
Reset
0x00
5
6
7
8
9
10
11
12
0x00
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Bit
Name
Reset
Description
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:8
RXDATA1
0x00
R
RX Data 1
R
RX Data 0
Second frame read from buffer.
7:0
RXDATA0
0x00
First frame read from buffer.
16.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register
Access
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
FERRP
0
R
3
0x000 4
RXDATAP R
5
6
7
8
9
10
11
12
13
14
0
R
PERRP
Name
R
Access
FERRP
0
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Description
Data Framing Error Peek
Set if data in buffer has a framing error. Can be the result of a break condition.
14
PERRP
0
R
Data Parity Error Peek
Set if data in buffer has a parity error (asynchronous mode only).
13:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
RXDATAP
0x000
R
RX Data Peek
Use this register to access data read from the USART.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register
Bit
Name
Reset
Access
Description
31
FERRP1
0
R
Data Framing Error 1 Peek
0
1
2
3
0x000 4
RXDATAP0 R
5
6
7
8
9
10
11
12
13
14
R
PERRP0
0
15
R
FERRP0
0
16
17
18
19
21
RXDATAP1 R
0x000 20
22
23
24
25
26
27
28
29
30
0
0
R
Name
PERRP1
Access
R
Reset
FERRP1
0x02C
Bit Position
31
Offset
Set if data in buffer has a framing error. Can be the result of a break condition.
30
PERRP1
0
R
Data Parity Error 1 Peek
Set if data in buffer has a parity error (asynchronous mode only).
29:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24:16
RXDATAP1
0x000
R
RX Data 1 Peek
R
Data Framing Error 0 Peek
Second frame read from FIFO.
15
FERRP0
0
Set if data in buffer has a framing error. Can be the result of a break condition.
14
PERRP0
0
R
Data Parity Error 0 Peek
Set if data in buffer has a parity error (asynchronous mode only).
13:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
RXDATAP0
0x000
R
RX Data 0 Peek
First frame read from FIFO.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register
Access
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
RXENAT
0
W
0
1
2
3
TXDATAX
W
0x000 4
5
6
7
8
9
10
12
11
0
0
W
13
0
14
0
W
W
UBRXAT
TXTRIAT
Name
TXBREAK W
RXENAT
W
Access
TXDISAT
0
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Description
Enable RX After Transmission
Set to enable reception after transmission.
14
TXDISAT
0
W
Clear TXEN After Transmission
Set to disable transmitter and release data bus directly after transmission.
13
TXBREAK
0
W
Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
12
TXTRIAT
0
W
Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
11
UBRXAT
0
W
Unblock RX After Transmission
Set to clear RXBLOCK after transmission, unblocking the receiver.
10:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
TXDATAX
0x000
W
TX Data
Use this register to write data to the USART. If TXEN is set, a transfer will be initiated at the first opportunity.
16.5.14 USARTn_TXDATA - TX Buffer Data Register
0
1
2
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
Reset
TXDATA W
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TXDATA
0x00
W
Description
TX Data
This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
31
RXENAT1
0
W
Enable RX After Transmission
0
1
2
3
5
6
7
8
9
0x000 4
Description
W
Access
TXDATA0
Reset
10
11
12
W
UBRXAT0
0
0
W
TXTRIAT0
13
0
TXBREAK0 W
14
0
W
TXDISAT0
15
0
W
Name
W
Bit
TXDATA1
RXENAT0
16
17
18
19
21
0x000 20
22
23
24
25
26
W
UBRXAT1
27
W
TXTRIAT1
0
TXBREAK1 W
28
0
W
Name
TXDISAT1
29
0
W
30
0
Access
RXENAT1
Reset
0
0x038
Bit Position
31
Offset
Set to enable reception after transmission.
30
TXDISAT1
0
W
Clear TXEN After Transmission
Set to disable transmitter and release data bus directly after transmission.
29
TXBREAK1
0
W
Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of USARTn_TXDATA.
28
TXTRIAT1
0
W
Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
27
UBRXAT1
0
W
Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
26:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24:16
TXDATA1
0x000
W
TX Data
W
Enable RX After Transmission
Second frame to write to FIFO.
15
RXENAT0
0
Set to enable reception after transmission.
14
TXDISAT0
0
W
Clear TXEN After Transmission
Set to disable transmitter and release data bus directly after transmission.
13
TXBREAK0
0
W
Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
12
TXTRIAT0
0
W
Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
11
UBRXAT0
0
W
Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
10:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
TXDATA0
0x000
W
TX Data
First frame to write to buffer.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register
TXDATA1 W
Access
Name
Access
0
1
2
3
4
0x00
6
7
8
9
5
TXDATA0 W
Reset
10
11
12
0x00
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Bit
Name
Reset
Description
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:8
TXDATA1
0x00
W
TX Data
W
TX Data
Second frame to write to buffer.
7:0
TXDATA0
0x00
First frame to write to buffer.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.17 USARTn_IF - Interrupt Flag Register
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0
R
TXC
0
1
R
TXBL
1
0
2
3
0
R
RXDATAV R
RXFULL
4
R
RXOF
0
5
0
R
RXUF
6
0
R
TXOF
7
0
R
TXUF
8
0
R
PERR
9
0
R
FERR
10
0
R
MPAF
11
12
R
0
0
R
CCF
SSM
13
0
R
TXIDLE
14
0
R
TCMP0
15
0
R
17
18
19
20
21
16
0
TCMP1
Name
R
Access
TCMP2
Reset
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
TCMP2
0
R
Description
Timer comparator 2 Interrupt Flag
Set when the timer reaches the comparator 2 value, TCMP2.
15
TCMP1
0
R
Timer comparator 1 Interrupt Flag
Set when the timer reaches the comparator 1 value, TCMP1.
14
TCMP0
0
R
Timer comparator 0 Interrupt Flag
Set when the Timer reaches the comparator 0 value, TCMP0.
13
TXIDLE
0
R
TX Idle Interrupt Flag
Set when TX goes idle. At this point, transmission has ended
12
CCF
0
R
Collision Check Fail Interrupt Flag
Set when a collision check notices an error in the transmitted data.
11
SSM
0
R
Slave-Select In Master Mode Interrupt Flag
Set when the device is selected as a slave when in master mode.
10
MPAF
0
R
Multi-Processor Address Frame Interrupt Flag
Set when a multi-processor address frame is detected.
9
FERR
0
R
Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
8
PERR
0
R
Parity Error Interrupt Flag
Set when a frame with a parity error (asynchronous mode only) is received while RXBLOCK is cleared.
7
TXUF
0
R
TX Underflow Interrupt Flag
Set when operating as a synchronous slave, no data is available in the transmit buffer when the master starts transmission
of a new frame.
6
TXOF
0
R
TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
5
RXUF
0
R
RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
4
RXOF
0
R
RX Overflow Interrupt Flag
Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.
3
RXFULL
0
R
RX Buffer Full Interrupt Flag
Set when the receive buffer becomes full.
2
RXDATAV
0
R
RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
1
TXBL
1
R
TX Buffer Level Interrupt Flag
Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals specified buffer level.
0
TXC
0
R
TX Complete Interrupt Flag
This interrupt is set after a transmission when both the TX buffer and shift register are empty.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.18 USARTn_IFS - Interrupt Flag Set Register
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0
W1 0
TXC
1
3
RXFULL W1 0
2
4
W1 0
RXOF
5
W1 0
W1 0
TXOF
RXUF
W1 0
TXUF
6
W1 0
PERR
7
W1 0
FERR
8
W1 0
MPAF
9
W1 0
10
12
W1 0
CCF
SSM
11
13
W1 0
TXIDLE
14
W1 0
TCMP0
15
W1 0
16
17
18
19
20
21
TCMP1
Name
W1 0
Access
TCMP2
Reset
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Preliminary Rev. 0.2 | 495
EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
TCMP2
0
W1
Set TCMP2 Interrupt Flag
W1
Set TCMP1 Interrupt Flag
W1
Set TCMP0 Interrupt Flag
W1
Set TXIDLE Interrupt Flag
W1
Set CCF Interrupt Flag
W1
Set SSM Interrupt Flag
W1
Set MPAF Interrupt Flag
W1
Set FERR Interrupt Flag
W1
Set PERR Interrupt Flag
W1
Set TXUF Interrupt Flag
W1
Set TXOF Interrupt Flag
W1
Set RXUF Interrupt Flag
W1
Set RXOF Interrupt Flag
W1
Set RXFULL Interrupt Flag
Write 1 to set the TCMP2 interrupt flag
15
TCMP1
0
Write 1 to set the TCMP1 interrupt flag
14
TCMP0
0
Write 1 to set the TCMP0 interrupt flag
13
TXIDLE
0
Write 1 to set the TXIDLE interrupt flag
12
CCF
0
Write 1 to set the CCF interrupt flag
11
SSM
0
Write 1 to set the SSM interrupt flag
10
MPAF
0
Write 1 to set the MPAF interrupt flag
9
FERR
0
Write 1 to set the FERR interrupt flag
8
PERR
0
Write 1 to set the PERR interrupt flag
7
TXUF
0
Write 1 to set the TXUF interrupt flag
6
TXOF
0
Write 1 to set the TXOF interrupt flag
5
RXUF
0
Write 1 to set the RXUF interrupt flag
4
RXOF
0
Write 1 to set the RXOF interrupt flag
3
RXFULL
0
Write 1 to set the RXFULL interrupt flag
2:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
TXC
0
W1
Set TXC Interrupt Flag
Write 1 to set the TXC interrupt flag
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.19 USARTn_IFC - Interrupt Flag Clear Register
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0
(R)W1 0
TXC
1
3
RXFULL (R)W1 0
2
4
(R)W1 0
RXOF
5
(R)W1 0
(R)W1 0
TXOF
RXUF
(R)W1 0
TXUF
6
(R)W1 0
PERR
7
(R)W1 0
FERR
8
(R)W1 0
MPAF
9
(R)W1 0
10
12
(R)W1 0
CCF
SSM
11
13
(R)W1 0
TXIDLE
14
(R)W1 0
TCMP0
15
(R)W1 0
16
17
18
19
20
21
TCMP1
Name
(R)W1 0
Access
TCMP2
Reset
22
23
24
25
26
27
28
29
30
0x048
Bit Position
31
Offset
Preliminary Rev. 0.2 | 497
EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
TCMP2
0
(R)W1
Description
Clear TCMP2 Interrupt Flag
Write 1 to clear the TCMP2 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
15
TCMP1
0
(R)W1
Clear TCMP1 Interrupt Flag
Write 1 to clear the TCMP1 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
14
TCMP0
0
(R)W1
Clear TCMP0 Interrupt Flag
Write 1 to clear the TCMP0 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
13
TXIDLE
0
(R)W1
Clear TXIDLE Interrupt Flag
Write 1 to clear the TXIDLE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
12
CCF
0
(R)W1
Clear CCF Interrupt Flag
Write 1 to clear the CCF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
11
SSM
0
(R)W1
Clear SSM Interrupt Flag
Write 1 to clear the SSM interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
10
MPAF
0
(R)W1
Clear MPAF Interrupt Flag
Write 1 to clear the MPAF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
9
FERR
0
(R)W1
Clear FERR Interrupt Flag
Write 1 to clear the FERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
8
PERR
0
(R)W1
Clear PERR Interrupt Flag
Write 1 to clear the PERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
7
TXUF
0
(R)W1
Clear TXUF Interrupt Flag
Write 1 to clear the TXUF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
6
TXOF
0
(R)W1
Clear TXOF Interrupt Flag
Write 1 to clear the TXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
5
RXUF
0
(R)W1
Clear RXUF Interrupt Flag
Write 1 to clear the RXUF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
4
RXOF
0
(R)W1
Clear RXOF Interrupt Flag
Write 1 to clear the RXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
3
RXFULL
0
(R)W1
Clear RXFULL Interrupt Flag
Write 1 to clear the RXFULL interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
2:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
TXC
0
(R)W1
Description
Clear TXC Interrupt Flag
Write 1 to clear the TXC interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.20 USARTn_IEN - Interrupt Enable Register
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2
1
RXDATAV RW 0
RW 0
RW 0
TXBL
TXC
0
3
RW 0
RXFULL
4
RW 0
RXOF
5
RW 0
RW 0
TXOF
RXUF
RW 0
TXUF
6
RW 0
PERR
7
RW 0
FERR
8
RW 0
MPAF
9
RW 0
10
12
RW 0
CCF
SSM
11
13
RW 0
TXIDLE
14
RW 0
TCMP0
15
RW 0
16
17
18
19
20
21
TCMP1
Name
RW 0
Access
TCMP2
Reset
22
23
24
25
26
27
28
29
30
0x04C
Bit Position
31
Offset
Preliminary Rev. 0.2 | 500
EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16
TCMP2
0
RW
TCMP2 Interrupt Enable
RW
TCMP1 Interrupt Enable
RW
TCMP0 Interrupt Enable
RW
TXIDLE Interrupt Enable
RW
CCF Interrupt Enable
RW
SSM Interrupt Enable
RW
MPAF Interrupt Enable
RW
FERR Interrupt Enable
RW
PERR Interrupt Enable
RW
TXUF Interrupt Enable
RW
TXOF Interrupt Enable
RW
RXUF Interrupt Enable
RW
RXOF Interrupt Enable
RW
RXFULL Interrupt Enable
RW
RXDATAV Interrupt Enable
RW
TXBL Interrupt Enable
RW
TXC Interrupt Enable
Enable/disable the TCMP2 interrupt
15
TCMP1
0
Enable/disable the TCMP1 interrupt
14
TCMP0
0
Enable/disable the TCMP0 interrupt
13
TXIDLE
0
Enable/disable the TXIDLE interrupt
12
CCF
0
Enable/disable the CCF interrupt
11
SSM
0
Enable/disable the SSM interrupt
10
MPAF
0
Enable/disable the MPAF interrupt
9
FERR
0
Enable/disable the FERR interrupt
8
PERR
0
Enable/disable the PERR interrupt
7
TXUF
0
Enable/disable the TXUF interrupt
6
TXOF
0
Enable/disable the TXOF interrupt
5
RXUF
0
Enable/disable the RXUF interrupt
4
RXOF
0
Enable/disable the RXOF interrupt
3
RXFULL
0
Enable/disable the RXFULL interrupt
2
RXDATAV
0
Enable/disable the RXDATAV interrupt
1
TXBL
0
Enable/disable the TXBL interrupt
0
TXC
0
Enable/disable the TXC interrupt
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.21 USARTn_IRCTRL - IrDA Control Register
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0
0
RW
IREN
1
2
RW 0x0
IRPW
3
0
RW
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
7
0
RW
IRFILT
Name
IRPRSEN
Access
IRPRSSEL RW 0x0
Reset
22
23
24
25
26
27
28
29
30
0x050
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11:8
IRPRSSEL
0x0
RW
Description
IrDA PRS Channel Select
A PRS can be used as input to the pulse modulator instead of TX. This value selects the channel to use.
7
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
IRPRSEN
0
RW
IrDA PRS Channel Enable
Enable the PRS channel selected by IRPRSSEL as input to IrDA module instead of TX.
6:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
IRFILT
0
RW
IrDA RX Filter
Set to enable filter on IrDA demodulator.
2:1
Value
Description
0
No filter enabled
1
Filter enabled. IrDA pulse must be high for at least 4 consecutive clock
cycles to be detected
IRPW
0x0
RW
IrDA TX Pulse Width
Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period.
0
Value
Mode
Description
0
ONE
IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1
1
TWO
IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1
2
THREE
IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1
3
FOUR
IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1
IREN
0
RW
Enable IrDA Module
Enable IrDA module and rout USART signals through it.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.22 USARTn_INPUT - USART Input Register
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0
1
2
RXPRSSEL
RW 0x0
3
4
5
6
7
0
RW
RXPRS
8
9
11
12
13
10
CLKPRSSEL RW 0x0
Name
14
15
0
RW
16
17
18
19
20
21
Access
CLKPRS
Reset
22
23
24
25
26
27
28
29
30
0x058
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
CLKPRS
0
RW
Description
PRS CLK Enable
When set, the PRS channel selected as input to CLK.
14:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11:8
CLKPRSSEL
0x0
RW
CLK PRS Channel Select
Select PRS channel as input to CLK.
7
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
RXPRS
0
RW
PRS RX Enable
When set, the PRS channel selected as input to RX.
6:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
RXPRSSEL
0x0
RW
RX PRS Channel Select
Select PRS channel as input to RX.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
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Access
Description
Preliminary Rev. 0.2 | 506
EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.23 USARTn_I2SCTRL - I2S Control Register
Access
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10:8
FORMAT
0x0
RW
0
0
RW
EN
1
0
RW
MONO
2
0
RW
JUSTIFY
3
0
DMASPLIT RW
4
0
RW
5
DELAY
Name
6
7
8
10
FORMAT
Access
RW 0x0 9
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x05C
Bit Position
31
Offset
Description
I2S Word Format
Configure the data-width used internally for I2S data
Value
Mode
Description
0
W32D32
32-bit word, 32-bit data
1
W32D24M
32-bit word, 32-bit data with 8 lsb masked
2
W32D24
32-bit word, 24-bit data
3
W32D16
32-bit word, 16-bit data
4
W32D8
32-bit word, 8-bit data
5
W16D16
16-bit word, 16-bit data
6
W16D8
16-bit word, 8-bit data
7
W8D8
8-bit word, 8-bit data
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
DELAY
0
RW
Delay on I2S data
Set to add a one-cycle delay between a transition on the word-clock and the start of the I2S word. Should be set for standard I2S format
3
DMASPLIT
0
RW
Separate DMA Request For Left/Right Data
When set DMA requests for right-channel data are put on the TXBLRIGHT and RXDATAVRIGHT DMA requests.
2
JUSTIFY
0
RW
Justification of I2S Data
Determines whether the I2S data is left or right justified
1
Value
Mode
Description
0
LEFT
Data is left-justified
1
RIGHT
Data is right-justified
MONO
0
RW
Stero or Mono
Switch between stereo and mono mode. Set for mono
0
EN
0
RW
Enable I2S Mode
Set the U(S)ART in I2S mode.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.24 USARTn_TIMING - Timing Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RW 0x0 17
TXDELAY
18
19
20
22
23
24
RW 0x0 25
26
27
28
30
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CSSETUP RW 0x0 21
Name
ICS
Access
RW 0x0 29
Reset
CSHOLD
0x060
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
30:28
CSHOLD
0x0
RW
Description
Chip Select Hold
Chip Select will be asserted after the end of frame transmission. When using TCMPn, normally set TIMECMPn_TSTART to
DISABLE to stop general timer and to prevent unwanted interrupts.
Value
Mode
Description
0
ZERO
Disable CS being asserted after the end of transmission
1
ONE
CS is asserted for 1 baud-times after the end of transmission
2
TWO
CS is asserted for 2 baud-times after the end of transmission
3
THREE
CS is asserted for 3 baud-times after the end of transmission
4
SEVEN
CS is asserted for 7 baud-times after the end of transmission
5
TCMP0
CS is asserted after the end of transmission for TCMPVAL0 baud-times
6
TCMP1
CS is asserted after the end of transmission for TCMPVAL1 baud-times
7
TCMP2
CS is asserted after the end of transmission for TCMPVAL2 baud-times
27
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
26:24
ICS
0x0
RW
Inter-character spacing
Inter-character spacing after each TX frame while the TX buffer is not empty. When using USART_TIMECMPn, normally
set TSTART to DISABLE to stop general timer and to prevent unwanted interrupts.
Value
Mode
Description
0
ZERO
There is no space between charcters
1
ONE
Create a space of 1 baud-times before start of transmission
2
TWO
Create a space of 2 baud-times before start of transmission
3
THREE
Create a space of 3 baud-times before start of transmission
4
SEVEN
Create a space of 7 baud-times before start of transmission
5
TCMP0
Create a space of before the start of transmission for TCMPVAL0
baud-times
6
TCMP1
Create a space of before the start of transmission for TCMPVAL1
baud-times
7
TCMP2
Create a space of before the start of transmission for TCMPVAL2
baud-times
23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
22:20
CSSETUP
0x0
RW
Chip Select Setup
Chip Select will be asserted before the start of frame transmission. When using USART_TIMECMPn, normally set TSTART
to DISABLE to stop general timer and to prevent unwanted interrupts.
Value
Mode
Description
0
ZERO
CS is not asserted before start of transmission
1
ONE
CS is asserted for 1 baud-times before start of transmission
2
TWO
CS is asserted for 2 baud-times before start of transmission
3
THREE
CS is asserted for 3 baud-times before start of transmission
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
4
SEVEN
CS is asserted for 7 baud-times before start of transmission
5
TCMP0
CS is asserted before the start of transmission for TCMPVAL0 baudtimes
6
TCMP1
CS is asserted before the start of transmission for TCMPVAL1 baudtimes
7
TCMP2
CS is asserted before the start of transmission for TCMPVAL2 baudtimes
19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18:16
TXDELAY
0x0
RW
Description
TX frame start delay
Number of baud-times to delay the start of frame transmission. When using USART_TIMECMPn, normally set TSTART to
DISABLE to stop general timer and to prevent unwanted interrupts.
15:0
Value
Mode
Description
0
DISABLE
Disable - TXDELAY in USARTn_CTRL can be used for legacy
1
ONE
Start of transmission is delayed for 1 baud-times
2
TWO
Start of transmission is delayed for 2 baud-times
3
THREE
Start of transmission is delayed for 3 baud-times
4
SEVEN
Start of transmission is delayed for 7 baud-times
5
TCMP0
Start of transmission is delayed for TCMPVAL0 baud-times
6
TCMP1
Start of transmission is delayed for TCMPVAL1 baud-times
7
TCMP2
Start of transmission is delayed for TCMPVAL2 baud-times
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.25 USARTn_CTRLX - Control Register Extended
Bit
Name
Reset
Access
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
RTSINV
0
RW
1
0
RW 0
CTSINV
DBGHALT RW 0
2
3
RW 0
Name
RW 0
Access
CTSEN
Reset
RTSINV
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x064
Bit Position
31
Offset
Description
RTS Pin Inversion
When set, the RTS pin polarity is inverted.
2
Value
Description
0
The USn_RTS pin is low true
1
The USn_RTS pin is high true
CTSEN
0
RW
CTS Function enabled
When set, frames in the TXBUFn will not be sent until link partner asserts CTS. Any data in the TX shift register will continue transmitting, the next TXBUFn data will not load into the TX shift register
1
Value
Description
0
Ingore CTS
1
Stop transmitting when CTS is negated
CTSINV
0
RW
CTS Pin Inversion
When set, the CTS pin polarity is inverted.
0
Value
Description
0
The USn_CTS pin is low true
1
The USn_CTS pin is high true
DBGHALT
0
RW
Debug halt
.
Value
Description
0
Continue to transmit until TX buffer is empty
1
Complete the transmission in the shift register and then halt transmission; also negate RTS to stop link partner's transmission during debug
HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple
frames instead of just transmitting one frame.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.26 USARTn_TIMECMP0 - Used to generate interrupts and various delays
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0
1
2
3
4
TCMPVAL
RW 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
0x0
RW
TSTART
18
19
20
21
0x0
RW
22
23
25
26
27
28
29
24
TSTOP
Name
0
Access
RESTARTEN RW
Reset
30
0x068
Bit Position
31
Offset
Preliminary Rev. 0.2 | 512
EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
RESTARTEN
0
RW
Description
Restart Timer on TCMP0
Each TCMP0 event will reset and restart the timer
Value
Description
0
Disable the timer restarting on TCMP0
1
Enable the timer restarting on TCMP0
23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
22:20
TSTOP
0x0
RW
Source used to disable comparator 0
Select the source which disables comparator 0
Value
Mode
Description
0
TCMP0
Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event
1
TXST
Comparator 0 is disabled at the start of transmission
2
RXACT
Comparator 0 is disabled on RX going going Active (default: low)
3
RXACTN
Comparator 0 is disabled on RX going Inactive
19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18:16
TSTART
0x0
RW
Timer start source
Source used to start comparator 0 and timer
Value
Mode
Description
0
DISABLE
Comparator 0 is disabled
1
TXEOF
Comparator 0 and timer are started at TX end of frame
2
TXC
Comparator 0 and timer are started at TX Complete
3
RXACT
Comparator 0 and timer are started at RX going Active (default: low)
4
RXEOF
Comparator 0 and timer are started at RX end of frame
15:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TCMPVAL
0x00
RW
Timer comparator 0.
When the timer equals TCMPVAL, this signals a TCMP0 event and sets the TCMP0 flag. This event can also be used to
enable various USART functionality. A value of 0x00 represents 256 baud times.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.27 USARTn_TIMECMP1 - Used to generate interrupts and various delays
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0
1
2
3
4
TCMPVAL
RW 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
0x0
RW
TSTART
18
19
20
21
0x0
RW
22
23
25
26
27
28
29
24
TSTOP
Name
0
Access
RESTARTEN RW
Reset
30
0x06C
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
RESTARTEN
0
RW
Description
Restart Timer on TCMP1
Each TCMP1 event will reset and restart the timer
Value
Description
0
Disable the timer restarting on TCMP1
1
Enable the timer restarting on TCMP1
23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
22:20
TSTOP
0x0
RW
Source used to disable comparator 1
Select the source which disables comparator 1
Value
Mode
Description
0
TCMP1
Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event
1
TXST
Comparator 1 is disabled at TX start TX Engine
2
RXACT
Comparator 1 is disabled on RX going going Active (default: low)
3
RXACTN
Comparator 1 is disabled on RX going Inactive
19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18:16
TSTART
0x0
RW
Timer start source
Source used to start comparator 1 and timer
Value
Mode
Description
0
DISABLE
Comparator 1 is disabled
1
TXEOF
Comparator 1 and timer are started at TX end of frame
2
TXC
Comparator 1 and timer are started at TX Complete
3
RXACT
Comparator 1 and timer are started at RX going going Active (default:
low)
4
RXEOF
Comparator 1 and timer are started at RX end of frame
15:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TCMPVAL
0x00
RW
Timer comparator 1.
When the timer equals TCMPVAL, this signals a TCMP1 event and sets the TCMP1 flag. This event can also be used to
enable various USART functionality. A value of 0x00 represents 256 baud times.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.28 USARTn_TIMECMP2 - Used to generate interrupts and various delays
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0
1
2
3
4
TCMPVAL
RW 0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
0x0
RW
TSTART
18
19
20
21
0x0
RW
22
23
25
26
27
28
29
24
TSTOP
Name
0
Access
RESTARTEN RW
Reset
30
0x070
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
24
RESTARTEN
0
RW
Description
Restart Timer on TCMP2
Each TCMP2 event will reset and restart the timer
Value
Description
0
Disable the timer restarting on TCMP2
1
Enable the timer restarting on TCMP2
23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
22:20
TSTOP
0x0
RW
Source used to disable comparator 2
Select the source which disables comparator 2
Value
Mode
Description
0
TCMP2
Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event
1
TXST
Comparator 2 is disabled at TX start TX Engine
2
RXACT
Comparator 2 is disabled on RX going going Active (default: low)
3
RXACTN
Comparator 2 is disabled on RX going Inactive
19
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
18:16
TSTART
0x0
RW
Timer start source
Source used to start comparator 2 and timer
Value
Mode
Description
0
DISABLE
Comparator 2 is disabled
1
TXEOF
Comparator 2 and timer are started at TX end of frame
2
TXC
Comparator 2 and timer are started at TX Complete
3
RXACT
Comparator 2 and timer are started at RX going going Active (default:
low)
4
RXEOF
Comparator 2 and timer are started at RX end of frame
15:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TCMPVAL
0x00
RW
Timer comparator 2.
When the timer equals TCMPVAL, this signals a TCMP2 event and sets the TCMP2 flag. This event can also be used to
enable various USART functionality. A value of 0x00 represents 256 baud times.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register
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RW 0
RW 0
TXPEN
RXPEN
0
2
RW 0
CSPEN
1
3
CLKPEN RW 0
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CTSPEN RW 0
Name
5
Access
RTSPEN RW 0
Reset
22
23
24
25
26
27
28
29
30
0x074
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
RTSPEN
0
RW
Description
RTS Pin Enable
When set, the RTS pin of the USART is enabled.
4
Value
Description
0
The USn_RTS pin is disabled
1
The USn_RTS pin is enabled
CTSPEN
0
RW
CTS Pin Enable
When set, the CTS pin of the USART is enabled.
3
Value
Description
0
The USn_CTS pin is disabled
1
The USn_CTS pin is enabled
CLKPEN
0
RW
CLK Pin Enable
When set, the CLK pin of the USART is enabled.
2
Value
Description
0
The USn_CLK pin is disabled
1
The USn_CLK pin is enabled
CSPEN
0
RW
CS Pin Enable
When set, the CS pin of the USART is enabled.
1
Value
Description
0
The USn_CS pin is disabled
1
The USn_CS pin is enabled
TXPEN
0
RW
TX Pin Enable
When set, the TX/MOSI pin of the USART is enabled
0
Value
Description
0
The U(S)n_TX (MOSI) pin is disabled
1
The U(S)n_TX (MOSI) pin is enabled
RXPEN
0
RW
RX Pin Enable
When set, the RX/MISO pin of the USART is enabled.
Value
Description
0
The U(S)n_RX (MISO) pin is disabled
1
The U(S)n_RX (MISO) pin is enabled
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register
0
1
2
3
RXLOC
RW 0x00
4
5
6
7
8
9
10
11
RW 0x00
TXLOC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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RW 0x00
Name
CSLOC
Access
CLKLOC RW 0x00
Reset
30
0x078
Bit Position
31
Offset
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EFM32JG1 Reference Manual
USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:24
CLKLOC
0x00
RW
Description
I/O Location
Decides the location of the USART CLK pin.
23:22
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
21:16
CSLOC
0x00
RW
I/O Location
Decides the location of the USART CS pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
TXLOC
0x00
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I/O Location
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
Decides the location of the USART TX pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
RXLOC
0x00
RW
I/O Location
Decides the location of the USART RX pin.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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Description
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
16.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register
Name
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5
CTSLOC RW 0x00
Access
RTSLOC RW 0x00
Reset
22
23
24
25
26
27
28
29
30
0x07C
Bit Position
31
Offset
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
RTSLOC
0x00
RW
Description
I/O Location
Decides the location of the USART RTS pin.
7:6
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
5:0
CTSLOC
0x00
RW
I/O Location
Decides the location of the USART CTS pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
Quick Facts
What?
0 1 2 3
4
The LEUART provides full UART communication using a low frequency 32.768 kHz clock, and has special features for communication without CPU intervention.
Why?
DMA
controller
RAM
It allows UART communication to be performed in
low energy modes, using only a few µA during active
communication and only 150 nA when waiting for incoming data.
How?
LEUART
RX
TX
A low frequency clock signal allows communication
with less energy. Using DMA, the LEUART can
transmit and receive data with minimal CPU intervention. Special UART-frames can be configured to
help control the data flow, further automating data
transmission.
17.1 Introduction
The unique Low Energy UART (LEUART) is a UART that allows two-way UART communication on a strict power budget. Only a 32.768
kHz clock is needed to allow UART communication up to 9600 baud.
Even when the EFM is in low energy mode EM2 DeepSleep (with most core functionality turned off), the LEUART can wait for an incoming UART frame while having an extremely low energy consumption. When a UART frame is completely received, the CPU can
quickly be woken up. Alternatively, multiple frames can be transferred via the Direct Memory Access (DMA) module into RAM memory
before waking up the CPU.
Received data can optionally be blocked until a configurable start frame is detected. A signal frame can be configured to generate an
interrupt indicating the end of a data transmission. The start frame and signal frame can be used in combination to handle higher level
communication protocols.
Similarly, data can be transmitted in EM2 DeepSleep either on a frame-by-frame basis with data from the CPU or through use of the
DMA.
The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimal software
overhead and low energy consumption.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.2 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low energy asynchronous serial communications
Full/half duplex communication
Separate TX / RX enable
Separate double buffered transmit buffer and receive buffer
Programmable baud rate, generated as a fractional division of the LFBCLK
• Supports baud rates from 300 baud to 9600 baud
Can use a high frequency clock source for even higher baud rates
Configurable number of data bits: 8 or 9 (plus parity bit, if enabled)
Configurable parity: off, even or odd
• HW parity bit generation and check
Configurable number of stop bits, 1 or 2
Capable of sleep-mode wake-up on received frame
• Either wake-up on any received byte or
• Wake up only on specified start and signal frames
Supports transmission and reception in EM0 Active, EM1 Sleep and EM2 DeepSleep with
• Full DMA support
• Specified start-frame can start reception automatically
IrDA modulator (pulse generator, pulse extender)
Multi-processor mode
Loopback mode
• Half duplex communication
• Communication debugging
PRS RX input
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3 Functional Description
An overview of the LEUART module is shown in Figure 17.1 LEUART Overview on page 530.
Peripheral Bus
TX Buffer
UART Control
and status
RX Buffer
!RXBLOCK
Start frame
(STARTFRAME)
=
Start frame interrupt
Signal frame interrupt
LEUn_TX
Pulse
gen
LEUn_RX
TX Shift Register
Signal frame
(SIGFRAME)
TX Baud rate
generator
RX Wakeup
SYNC
=
RX Shift Register
RX Baud rate
generator
Pulse
extend
Figure 17.1 LEUART Overview
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.1 Frame Format
The frame format used by the LEUART consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for
error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and
is used for synchronization. Following the start bit are 8 or 9 data bits and an optional parity bit. The data is transmitted with the least
significant bit first. Finally, a number of stop-bits, where the line is driven high, end the frame. The frame format is shown in Figure
17.2 LEUART Asynchronous Frame Format on page 531.
Frame
Stop or idle
Start or idle
S
0
1
2
3
4
5
6
7
[8]
[P]
Stop
Figure 17.2 LEUART Asynchronous Frame Format
The number of data bits in a frame is set by DATABITS in LEUARTn_CTRL, and the number of stop-bits is set by STOPBITS in
LEUARTn_CTRL. Whether or not a parity bit should be included, and whether it should be even or odd is defined by PARITY in
LEUARTn_CTRL. For communication to be possible, all parties of an asynchronous transfer must agree on the frame format being
used.
The frame format used by the LEUART can be inverted by setting INV in LEUARTn_CTRL. This affects the entire frame, resulting in a
low idle state, a high start-bit, inverted data and parity bits, and low stop-bits. INV should only be changed while the receiver is disabled.
17.3.1.1 Parity Bit Calculation and Handling
Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming frames. The possible parity
modes are defined in Table 17.1 LEUART Parity Bit on page 531. When even parity is chosen, a parity bit is inserted to make the
number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number of high bits odd. When parity bits
are disabled, which is the default configuration, the parity bit is omitted.
Table 17.1. LEUART Parity Bit
PARITY [1:0]
Description
00
No parity (default)
01
Reserved
10
Even parity
11
Odd parity
See 17.3.5.4 Parity Error for more information on parity bit handling.
17.3.2 Clock Source
The LEUART clock source is selected by the LFB bit field the CMU_LFCLKSEL register. The clock is prescaled by the LEUARTn bitfield in the CMU_LFBPRESC0 register and enabled by the LEUARTn bit in the CMU_LFBCLKEN0. See Figure 10.1 CMU Overview on
page 204 for a diagram of the clocking structure.
To use this module, the LE interface clock must be enabled in CMU_HFBUSCLKEN0, in addition to the module clock.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.3 Clock Generation
The LEUART clock defines the transmission and reception data rate. The clock generator employs a fractional clock divider to allow
baud rates that are not attainable by integral division of the 32.768 kHz clock that drives the LEUART.
The clock divider used in the LEUART is a 14-bit value, with a 9-bit integral part and a 5-bit fractional part. The baud rate of the
LEUART is given by :
br = fLEUARTn / (1 + LEUARTn_CLKDIV / 256)
Equation: LEUART Baud Rate Equation
where fLEUARTn is the clock frequency supplied to the LEUART. The value of LEUARTn_CLKDIV thus defines the baud rate of the
LEUART. The integral part of the divider is right-aligned in the upper 24 bits of LEUARTn_CLKDIV and the fractional part is left-aligned
in the lower 8 bits. The divider is thus a 256th of LEUARTn_CLKDIV as seen in the equation.
As an example let us assume fLEUART = 22.5Khz and the value of DIV in LEUARTn_CLKDIV is 0x0028 (LEUARTn_CLKDIV =
0x00000140). The baud rate = 22.5Khz/(1 + 0x140 / 256) = 22.5Khz / 2.25 = 10Khz.
For a desired baud rate brDESIRED, LEUARTn_CLKDIV can be calculated by using:
LEUARTn_CLKDIV = 256 x (fLEUARTn/brDESIRED - 1)
Equation: LEUART CLKDIV Equation
It's important to note that this equation results in a 32bit value for the LEUARTn_CLKDIV register but only bits [16:3] are valid and all
others must be 0. For example if we have a 32Khz clock and whish to achieve a baud rate of 10Khz the equation above results in a
LEUARTn_CLKDIV value of 0x233. However, the actual value of the register will be 0x230 since bits [2:0] cannot be set. This limits the
best achievable acuracy. In this example the actual baud rate wil be 32Khz / (1+ 0x230/255) = 10.039Khz instead of 32Khz /
(1+ 0x233/255) = 10.002Khz.
Table 17.2 LEUART Baud Rates on page 532 lists a set of desired baud rates and the closest baud rates reachable by the LEUART
with a 32.768 kHz clock source. It also shows the average baud rate error.
Table 17.2. LEUART Baud Rates
Desired baud rate
LEUARTn_CLKDIV
LEUARTn_CLKDIV/256
Actual baud rate
Error [%]
300
27704
108,21875
300,0217
0.01
600
13728
53,625
599,8719
-0.02
1200
6736
26,3125
1199,744
-0.02
2400
3240
12,65625
2399,487
-0.02
4800
1488
5,8125
4809,982
0.21
9600
616
2,40625
9619,963
0.21
17.3.4 Data Transmission
Data transmission is initiated by writing data to the transmit buffer using one of the methods described in 17.3.4.1 Transmit Buffer Operation. When the transmit shift register is empty and ready for new data, a frame from the transmit buffer is loaded into the shift register,
and if the transmitter is enabled, transmission begins. When the frame has been transmitted, a new frame is loaded into the shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to an idle state, waiting for a new frame
to become available. Transmission is enabled through the command register LEUARTn_CMD by setting TXEN, and disabled by setting
TXDIS. When the transmitter is disabled using TXDIS, any ongoing transmission is aborted, and any frame currently being transmitted
is discarded. When disabled, the TX output goes to an idle state, which by default is a high value. Whether or not the transmitter is
enabled at a given time can be read from TXENS in LEUARTn_STATUS. After a transmission, when there is no more data in the shift
register or transmit buffer, the TXC flag in LEUARTn_STATUS and the TXC interrupt flag in LEUARTn_IF are set, signaling that the
transmitter is idle. The TXC status flag is cleared when a new byte becomes available for transmission, but the TXC interrupt flag must
be cleared by software.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.4.1 Transmit Buffer Operation
A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX. Using LEUARTn_TXDATA
allows 8 bits to be written to the buffer. If 9 bit frames are used, the 9th bit will in that case be set to the value of BIT8DV in
LEUARTn_CTRL. To set the 9th bit directly and/or use transmission control, LEUARTn_TXDATAX must be used. When writing data to
the transmit buffer using LEUARTn_TXDATAX, the 9th bit written to LEUARTn_TXDATAX overrides the value in BIT8DV, and alone
defines the 9th bit that is transmitted if 9-bit frames are used.
If a write is attempted to the transmit buffer when it is not empty, the TXOF interrupt flag in LEUARTn_IF is set, indicating the overflow.
The data already in the buffer is in that case preserved, and no data is written.
In addition to the interrupt flag TXC in LEUARTn_IF and the status flag TXC in LEUARTn_STATUS which are set when the transmitter
becomes idle, TXBL in LEUARTn_STATUS and the TXBL interrupt flag in LEUARTn_IF are used to indicate the level of the transmit
buffer. Whenever the transmit buffer becomes empty, these flags are set high. Both the TXBL status flag and the TXBL interrupt flag are
cleared automatically when data is written to the transmit buffer.
There is also TXIDLE status in LEUART_STATUS which can be used to detect when the transmit state machine is in the idle state.
The transmit buffer, including the TX shift register can be cleared by setting command bit CLEARTX in LEUARTn_CMD. This will prevent the LEUART from transmitting the data in the buffer and shift register, and will make them available for new data. Any frame currently being transmitted will not be aborted. Transmission of this frame will be completed. An overview of the operation of the transmitter
is shown in Figure 17.5 LEUART Transmitter Overview on page 533.
TXDATA
TXENS
LEUn_TX
Transmit shift register
d0-d8
control
BIT8DV
d0 d1 d2 d3 d4 d5 d6 d7 d8
0
control
Transmit buffer
TXDATAX
Figure 17.5 LEUART Transmitter Overview
17.3.4.2 Frame Transmission Control
The transmission control bits, which can be written using LEUARTn_TXDATAX, affect the transmission of the written frame. The following options are available:
• Generate break: By setting TXBREAK, the output will be held low during the first stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g. for framing of larger data packets. The line is driven
high for one bit period before the next frame is transmitted so the next start condition can be identified correctly by the recipient.
Continuous breaks lasting longer than an UART frame are thus not supported by the LEUART. GPIO can be used for this. Note that
when AUTOTRI in LEUARTn_CTRL is used, the transmitter is not tristated before the high-bit after the break has been transmitted.
• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame has been fully transmitted.
• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has been fully transmitted. It is enabled
in time to detect a start-bit directly after the last stop-bit has been transmitted.
The transmission control bits in the LEUART cannot tristate the transmitter. This is performed automatically by hardware if AUTOTRI in
LEUARTn_CTRL is set. See 17.3.7 Half Duplex Communication for more information on half duplex operation.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.5 Data Reception
Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively samples the input looking for a
transition from high to low indicating the start bit of a new frame. When a start bit is found, reception of the new frame begins if the
receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making
the shift register ready for another frame of data, and the receiver starts looking for another start bit. If the receive buffer is full, the
received frame remains in the shift register until more space in the receive buffer is available.
If an incoming frame is detected while both the receive buffer and the receive shift register are full, the data in the receive shift register
is overwritten, and the RXOF interrupt flag in LEUARTn_IF is set to indicate the buffer overflow.
The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD. Any frame currently being received when the receiver is disabled is discarded. Whether or not the receiver is enabled at a given time can be read out from RXENS in LEUARTn_STATUS.
The receive buffer,can be cleared by setting command bit CLEARRX in LEUARTn_CMD. This will make it avaliable for new data. Any
frame currently being received will not be aborted and will become the first received frame when complete.
17.3.5.1 Receive Buffer Operation
When data becomes available in the receive buffer, the RXDATAV flag in LEUARTn_STATUS and the RXDATAV interrupt flag in
LEUARTn_IF are set. Both the RXDATAV status flag and the RXDATAV interrupt flag are cleared by hardware when data is no longer
available, i.e. when data has been read out of the buffer.
Data can be read from receive buffer using either LEUARTn_RXDATA or LEUARTn_RXDATAX. LEUARTn_RXDATA gives access to
the 8 least significant bits of the received frame, while LEUARTn_RXDATAX must be used to get access to the 9th, most significant bit.
The LEUARTn_RXDATAX register also contains status information regarding the frame.
When a frame is read from the receive buffer using LEUARTn_RXDATA or LEUARTn_RXDATAX, the frame is removed from the buffer,
making room for a new one. If an attempt is done to read more frames from the buffer than what is available, the RXUF interrupt flag in
LEUARTn_IF is set to signal the underflow, and the data read from the buffer is undefined.
Frames can also be read from the receive buffer without removing the data by using LEUARTn_RXDATAXP, which gives access to the
frame in the buffer including control bits. Data read from this register when the receive buffer is empty is undefined. No underflow interrupt is generated by a read using LEUARTn_RXDATAXP, i.e. the RXUF interrupt flag is never set as a result of reading from
LEUARTn_RXDATAXP.
An overview of the operation of the receiver is shown in Figure 17.6 LEUART Receiver Overview on page 534.
RXDATA
RXENS
LEUn_RX
!RXBLOCK
Receive shift register
d0-d8
status
d0 d1 d2 d3 d4 d5 d6 d7 d8
status
Receive buffer
RXDATAX
(RXDATAXP)
Figure 17.6 LEUART Receiver Overview
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.5.2 Blocking Incoming Data
When using hardware frame recognition, as detailed in 17.3.5.6 Programmable Start Frame, 17.3.5.7 Programmable Signal Frame, and
17.3.5.8 Multi-Processor Mode, it is necessary to be able to let the receiver sample incoming frames without passing the frames to
software by loading them into the receive buffer. This is accomplished by blocking incoming data.
Incoming data is blocked as long as RXBLOCK in LEUARTn_STATUS is set. When blocked, frames received by the receiver will not be
loaded into the receive buffer, and software is not notified by the RXDATAV bit in LEUARTn_STATUS or the RXDATAV interrupt flag in
LEUARTn_IF at their arrival. For data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully
received by the receiver. RXBLOCK is set by setting RXBLOCKEN in LEUARTn_CMD and disabled by setting RXBLOCKDIS also in
LEUARTn_CMD. There are two exceptions where data is loaded into the receive buffer even when RXBLOCK is set. The first is when
an address frame is received when in operating in multi-processor mode as shown in 17.3.5.8 Multi-Processor Mode. The other case is
when receiving a start-frame when SFUBRX in LEUARTn_CTRL is set; see 17.3.5.6 Programmable Start Frame
Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in LEUARTn_IF being set while
RXBLOCK is set. Hardware recognition is not applied to these erroneous frames, and they are silently discarded.
Note:
If a frame is received while RXBLOCK in LEUARTn_STATUS is cleared, but stays in the receive shift register because the receive buffer is full, the received frame will be loaded into the receive buffer when space becomes available even if RXBLOCK is set at that time.
The overflow interrupt flag RXOF in LEUARTn_IF will be set if a frame in the receive shift register, waiting to be loaded into the receive
buffer is overwritten by an incoming frame even though RXBLOCK is set.
17.3.5.3 Data Sampling
The receiver samples each incoming bit as close as possible to the middle of the bit-period. Except for the start-bit, only a single sample is taken of each of the incoming bits.
The length of a bit-period is given by 1 + LEUARTn_CLKDIV/256, as a number of 32.768 kHz clock periods. Let the clock cycle where a
start-bit is first detected be given the index 0. The optimal sampling point for each bit in the UART frame is then given by the following
equation:
Sopt(n) = n (1 + LEUARTn_CLKDIV/256) + CLKDIV/512
Equation: LEUART Optimal Sampling Point
where n is the bit-index.
Since samples are only done on the positive edges of the 32.768 kHz clock, the actual samples are performed on the closest positive
edge, i.e. the edge given by the following equation:
S(n) = floor(n x (1 + LEUARTn_CLKDIV/256) + LEUARTn_CLKDIV/512)
Equation: LEUART Actual Sampling Point
The sampling location will thus have jitter according to difference between Sopt and S. The start-bit is found at n=0, then follows the
data bits, any parity bit, and the stop bits.
If the value of the start-bit is found to be high, then the start-bit is discarded, and the receiver waits for a new start-bit.
17.3.5.4 Parity Error
When the parity bit is enabled, a parity check is automatically performed on incoming frames. When a parity error is detected in a
frame, the data parity error bit PERR in the frame is set, as well as the interrupt flag PERR. Frames with parity errors are loaded into
the receive buffer like regular frames.
PERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX register.
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17.3.5.5 Framing Error and Break Detection
A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and
baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
When a framing error is detected, the framing error bit FERR in the received frame is set. The interrupt flag FERR in LEUARTn_IF is
also set. Frames with framing errors are loaded into the receive buffer like regular frames.
FERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX or LEUARTn_RXDATAXP registers.
17.3.5.6 Programmable Start Frame
The LEUART can be configured to start receiving data when a special start frame is detected on the input. This can be useful when
operating in low energy modes, allowing other devices to gain the attention of the LEUART by transmitting a given frame.
When SFUBRX in LEUARTn_CTRL is set, an incoming frame matching the frame defined in LEUARTn_STARTFRAME will result in
RXBLOCK in LEUARTn_STATUS being cleared. This can be used to enable reception when a specified start frame is detected. If the
receiver is enabled and blocked, i.e. RXENS and RXBLOCK in LEUARTn_STATUS are set, the receiver will receive all incoming
frames, but unless an incoming frame is a start frame it will be discarded and not loaded into the receive buffer. When a start frame is
detected, the block is cleared, and frames received from that point, including the start frame, are loaded into the receive buffer.
An incoming start frame results in the STARTF interrupt flag in LEUARTn_IF being set, regardless of the value of SFUBRX in
LEUARTn_CTRL. This allows an interrupt to be made when the start frame is detected.
When 8 data-bit frame formats are used, only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming
frames. The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bits.
Note:
The receiver must be enabled for start frames to be detected. In addition, a start frame with a parity error or framing error is not detected as a start frame.
17.3.5.7 Programmable Signal Frame
As well as the configurable start frame, a special signal frame can be specified. When a frame matching the frame defined in
LEUARTn_SIGFRAME is detected by the receiver, the SIGF interrupt flag in LEUARTn_IF is set. As for start frame detection, the receiver must be enabled for signal frames to be detected.
One use of the programmable signal frame is to signal the end of a multi-frame message transmitted to the LEUART. An interrupt will
then be triggered when the packet has been completely received, allowing software to process it. Used in conjunction with the programmable start frame and DMA, this makes it possible for the LEUART to automatically begin the reception of a packet on a specified start
frame, load the entire packet into memory, and give an interrupt when reception of a packet has completed. The device can thus wait
for data packets in EM2 DeepSleep, and only be woken up when a packet has been completely received.
A signal frame with a parity error or framing error is not detected as a signal frame.
17.3.5.8 Multi-Processor Mode
To simplify communication between multiple processors and maintain compatibility with the USART, the LEUART supports a multi-processor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an
address.
When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of MPAB in LEUARTn_CTRL is
identified as an address frame. When an address frame is detected, the MPAF interrupt flag in LEUARTn_IF is set, and the address
frame is loaded into the receive register. This happens regardless of the value of RXBLOCK in LEUARTn_STATUS.
Multi-processor mode is enabled by setting MPM in LEUARTn_CTRL. The mode can be used in buses with multiple slaves, allowing
the slaves to be addressed using the special address frames. An addressed slave, which was previously blocking reception using
RXBLOCK, would then unblock reception, receive a message from the bus master, and then block reception again, waiting for the next
message. See the USART for a more detailed example.
Note:
The programmable start frame functionality can be used for automatic address matching, enabling reception on a correctly configured
incoming frame.
An address frame with a parity error or a framing error is not detected as an address frame.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.6 Loopback
The LEUART receiver samples LEUn_RX by default, and the transmitter drives LEUn_TX by default. This is not the only configuration
however. When LOOPBK in LEUARTn_CTRL is set, the receiver is connected to the LEUn_TX pin as shown in Figure 17.9 LEUART
Local Loopback on page 537. This is useful for debugging, as the LEUART can receive the data it transmits, but it is also used to
allow the LEUART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the
LEUn_TX pin must be enabled as an output in the GPIO.
LOOPBK = 0
LOOPBK = 1
µC
µC
LEUART
TX
LEUn_TX
LEUART
TX
LEUn_TX
RX
LEUn_RX
RX
LEUn_RX
Figure 17.9 LEUART Local Loopback
17.3.7 Half Duplex Communication
When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same
time. In half duplex mode, data is only sent in one direction at a time. There are several possible half duplex setups, as described in the
following sections.
17.3.7.1 Single Data-link
In this setup, the LEUART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in LEUARTn_CTRL,
which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the
LEUART transmitter does not drive the line when receiving data, as this would corrupt the data on the line.
When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. If AUTOTRI in
LEUARTn_CTRL is set, the LEUART automatically tristates LEUn_TX whenever the transmitter is inactive. It is then the responsibility
of the software protocol to make sure the transmitter is not transmitting data whenever incoming data is expected.
The transmitter can also be tristated from software by configuring the GPIO pin as an input and disabling the LEUART output on
LEUn_TX.
Note:
Another way to tristate the transmitter is to enable wired-and or wired-or mode in GPIO. For wired-and mode, outputting a 1 will be the
same as tristating the output, and for wired-or mode, outputting a 0 will be the same as tristating the output. This can only be done on
buses with a pull-up or pull-down resistor respectively.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.7.2 Single Data-link with External Driver
Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and
instead of Tristating the transmitter when receiving data, the external driver must be disabled. The USART has hardware support for
automatically turning the driver on and off. When using the LEUART in such a setup, the driver must be controlled by a GPIO. Figure
17.10 LEUART Half Duplex Communication with External Driver on page 538 shows an example configuration using an external driver.
µC
GPIO
LEUART
TX
RX
Figure 17.10 LEUART Half Duplex Communication with External Driver
17.3.7.3 Two Data-links
Some limited devices only support half duplex communication even though two data links are available. In this case software is responsible for making sure data is not transmitted when incoming data is expected.
17.3.8 Transmission Delay
By configuring TXDELAY in LEUARTn_CTRL, the transmitter can be forced to wait a number of bit-periods from when it is ready to
transmit data, to when it actually transmits the data. This delay is only applied to the first frame transmitted after the transmitter has
been idle. When transmitting frames back-to-back the delay is not introduced between the transmitted frames.
This is useful on half duplex buses, because the receiver always returns received frames to software during the first stop-bit. The bus
may still be driven for up to 3 bit periods, depending on the current frame format. Using the transmission delay, a transmission can be
started when a frame is received, and it is possible to make sure that the transmitter does not begin driving the output before the frame
on the bus is completely transmitted.
To route the UART TX and RX signals to a pin first select the desired pins using the RXLOC and TXLOC fields in the LEUARTn_ROUTELOC0 register. Then enable the connection using TXPEN and RXPEN in the LEUARTn_ROUTPEN register. See the device datasheet for mappings between UART locations (LOC0, LOC1, etc.) and device pins (PA0, PA1, etc.).
17.3.9 PRS RX Input
In addition to receiving data on an external pin the LEUART can be configured to receive data directly from a PRS channel by setting
RX_PRS in LEUARTn_INPUT. The PRS channel used can be selected using RX_PRS_SEL in LEUARTn_INPUT. See the PRS chapter
for more details on the PRS block.
For example the output of a comparator coudl be routed to the LEUART through the PRS to allow for recieving a signal with low peakto-peak voltage or a significant DC offset.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.10 DMA Support
The LEUART has full DMA support in energy modes EM0 Active – EM2 DeepSleep. The DMA controller can write to the transmit buffer
using the registers LEUARTn_TXDATA and LEUARTn_TXDATAX, and it can read from receive buffer using the registers
LEUARTn_RXDATA and LEUARTn_RXDATAX. This enables single byte transfers and 9 bit data + control/status bits transfers both to
and from the LEUART. The DMA will start up the HFRCO and run from this when it is waken by the LEUART in EM2. The HFRCO is
disabled once the transaction is done.
A request for the DMA controller to read from the receive buffer can come from one of the following sources:
• Receive buffer full
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send.
• Transmit buffer empty
In some cases, it may be sensible to temporarily stop DMA access to the LEUART when a parity or framing error has occurred. This is
enabled by setting ERRSDMA in LEUARTn_CTRL. When this bit is set, the DMA controller will not get requests from the receive buffer
if a framing error or parity error is detected in the received byte. The ERRSDMA bit applies only to the RX DMA.
When operating in EM2 DeepSleep, the DMA controller must be powered up in order to perform the transfer. This is automatically performed for read operations if RXDMAWU in LEUARTn_CTRL is set and for write operations if TXDMAWU in LEUARTn_CTRL is set. To
make sure the DMA controller still transfers bits to and from the LEUART in low energy modes, these bits must thus be configured
accordingly.
Note:
When RXDMAWU or TXDMAWU is set, the system will not be able to go to EM2 DeepSleep/EM3 Stop before all related LEUART DMA
requests have been processed. This means that if RXDMAWU is set and the LEUART receives a frame, the system will not be able to
go to EM2 DeepSleep/EM3 Stop before the frame has been read from the LEUART. In order for the system to go to EM2 during the last
byte transmission, LEUART_CTRL_TXDMAWU must be cleared in the DMA interrupt service routine. This is because TXBL will be high
during that last byte transfer.
17.3.11 Pulse Generator/ Pulse Extender
The LEUART has an optional pulse generator for the transmitter output, and a pulse extender on the receiver input. These are enabled
by setting PULSEEN in LEUARTn_PULSECTRL, and with INV in LEUARTn_CTRL set, they will change the output/input format of the
LEUART from NRZ to RZI as shown in Figure 17.11 LEUART - NRZ vs. RZI on page 539.
Idle
NRZ
Idle
S
0
1
2
3
4
5
6
7
P
Stop
RZI
Figure 17.11 LEUART - NRZ vs. RZI
If PULSEEN in LEUARTn_PULSECTRL is set while INV in LEUARTn_CTRL is cleared, the output waveform will look like RZI shown in
Figure 17.11 LEUART - NRZ vs. RZI on page 539, only inverted.
The width of the pulses from the pulse generator can be configured using PULSEW in LEUARTn_PULSECTRL. The generated pulse
width is PULSEW + 1 cycles of the 32.768 kHz clock, which makes pulse width from 31.25µs to 500µs possible.
Since the incoming signal is only sampled on positive clock edges, the width of the incoming pulses must be at least two 32.768 kHz
clock periods wide for reliable detection by the LEUART receiver. They must also be shorter than half a UART bit period.
At 2400 baud or lower, the pulse generator is able to generate RZI pulses compatible with the IrDA physical layer specification. The
external IrDA device must generate pulses of sufficient length for successful two-way communication.
PULSEFILT in the LEUARTn_PULSECTRL register can be used to extend the minimum receive pulse width from 2 clock periods to 3
clock periods.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.3.11.1 Interrupts
The interrupts generated by the LEUART are combined into one interrupt vector. If LEUART interrupts are enabled, an interrupt will be
made if one or more of the interrupt flags in LEUARTn_IF and their corresponding bits in LEUART_IEN are set.
17.3.12 Register access
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 4.3 Access to Low Energy Peripherals (Asynchronous Registers) for a description on how to perform register accesses to Low Energy Peripherals.
The registers LEUARTn_FREEZE and LEUARTn_SYNCBUSY are used for synchronization of this peripheral.
17.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
LEUARTn_CTRL
RW
Control Register
0x004
LEUARTn_CMD
W1
Command Register
0x008
LEUARTn_STATUS
R
Status Register
0x00C
LEUARTn_CLKDIV
RW
Clock Control Register
0x010
LEUARTn_STARTFRAME
RW
Start Frame Register
0x014
LEUARTn_SIGFRAME
RW
Signal Frame Register
0x018
LEUARTn_RXDATAX
R(a)
Receive Buffer Data Extended Register
0x01C
LEUARTn_RXDATA
R(a)
Receive Buffer Data Register
0x020
LEUARTn_RXDATAXP
R
Receive Buffer Data Extended Peek Register
0x024
LEUARTn_TXDATAX
W
Transmit Buffer Data Extended Register
0x028
LEUARTn_TXDATA
W
Transmit Buffer Data Register
0x02C
LEUARTn_IF
R
Interrupt Flag Register
0x030
LEUARTn_IFS
W1
Interrupt Flag Set Register
0x034
LEUARTn_IFC
(R)W1
Interrupt Flag Clear Register
0x038
LEUARTn_IEN
RW
Interrupt Enable Register
0x03C
LEUARTn_PULSECTRL
RW
Pulse Control Register
0x040
LEUARTn_FREEZE
RW
Freeze Register
0x044
LEUARTn_SYNCBUSY
R
Synchronization Busy Register
0x054
LEUARTn_ROUTEPEN
RW
I/O Routing Pin Enable Register
0x058
LEUARTn_ROUTELOC0
RW
I/O Routing Location Register
0x064
LEUARTn_INPUT
RW
LEUART Input Register
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5 Register Description
17.5.1 LEUARTn_CTRL - Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
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0
0
RW
AUTOTRI
1
0
RW
DATABITS
2
3
RW 0x0
PARITY
4
0
RW
STOPBITS
5
0
RW
INV
6
0
RW
ERRSDMA
7
0
RW
LOOPBK
8
0
RW
SFUBRX
9
0
RW
MPM
10
0
RW
MPAB
11
0
RW
BIT8DV
12
0
RXDMAWU RW
14
15
16
17
18
19
20
21
13
0
TXDMAWU RW
Name
RW 0x0
Access
TXDELAY
Reset
22
23
24
25
26
27
28
29
30
0x000
Bit Position
31
Offset
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:14
TXDELAY
0x0
RW
Description
TX Delay Transmission
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
13
Value
Mode
Description
0
NONE
Frames are transmitted immediately
1
SINGLE
Transmission of new frames are delayed by a single bit period
2
DOUBLE
Transmission of new frames are delayed by two bit periods
3
TRIPLE
Transmission of new frames are delayed by three bit periods
TXDMAWU
0
RW
TX DMA Wakeup
Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer.
12
Value
Description
0
While in EM2, the DMA controller will not get requests about space being available in the transmit buffer
1
DMA is available in EM2 for the request about space available in the
transmit buffer
RXDMAWU
0
RW
RX DMA Wakeup
Set to wake the DMA controller up when in EM2 and data is available in the receive buffer.
11
Value
Description
0
While in EM2, the DMA controller will not get requests about data being
available in the receive buffer
1
DMA is available in EM2 for the request about data in the receive buffer
BIT8DV
0
RW
Bit 8 Default Value
When 9-bit frames are transmitted, the default value of the 9th bit is given by BIT8DV. If TXDATA is used to write a frame,
then the value of BIT8DV is assigned to the 9th bit of the outgoing frame. If a frame is written with TXDATAX however, the
default value is overridden by the written value.
10
MPAB
0
RW
Multi-Processor Address-Bit
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks
the frame as a multi-processor address frame.
9
MPM
0
RW
Multi-Processor Mode
Set to enable multi-processor mode.
8
Value
Description
0
The 9th bit of incoming frames have no special function
1
An incoming frame with the 9th bit equal to MPAB will be loaded into
the receive buffer regardless of RXBLOCK and will result in the MPAB
interrupt flag being set
SFUBRX
0
RW
Start-Frame UnBlock RX
Clears RXBLOCK when the start-frame is found in the incoming data. The start-frame is loaded into the receive buffer.
Value
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
Bit
7
Name
Reset
Access
Description
0
Detected start-frames have no effect on RXBLOCK
1
When a start-frame is detected, RXBLOCK is cleared and the startframe is loaded into the receive buffer
LOOPBK
0
RW
Loopback Enable
Set to connect receiver to LEUn_TX instead of LEUn_RX.
6
Value
Description
0
The receiver is connected to and receives data from LEUn_RX
1
The receiver is connected to and receives data from LEUn_TX
ERRSDMA
0
RW
Clear RX DMA On Error
When set,RX DMA requests will be cleared on framing and parity errors.
5
Value
Description
0
Framing and parity errors have no effect on DMA requests from the
LEUART
1
RX DMA requests from the LEUART are disabled if a framing error or
parity error occurs.
INV
0
RW
Invert Input And Output
Set to invert the output on LEUn_TX and input on LEUn_RX.
4
Value
Description
0
A high value on the input/output is 1, and a low value is 0.
1
A low value on the input/output is 1, and a high value is 0.
STOPBITS
0
RW
Stop-Bit Mode
Determines the number of stop-bits used. Only used when transmitting data. The receiver only verifies that one stop bit is
present.
3:2
Value
Mode
Description
0
ONE
One stop-bit is transmitted with every frame
1
TWO
Two stop-bits are transmitted with every frame
PARITY
0x0
RW
Parity-Bit Mode
Determines whether parity bits are enabled, and whether even or odd parity should be used.
1
Value
Mode
Description
0
NONE
Parity bits are not used
2
EVEN
Even parity are used. Parity bits are automatically generated and
checked by hardware.
3
ODD
Odd parity is used. Parity bits are automatically generated and checked
by hardware.
DATABITS
0
RW
Data-Bit Mode
This register sets the number of data bits.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
Bit
0
Name
Reset
Access
Value
Mode
Description
0
EIGHT
Each frame contains 8 data bits
1
NINE
Each frame contains 9 data bits
AUTOTRI
0
RW
Description
Automatic Transmitter Tristate
When set, LEUn_TX is tristated whenever the transmitter is inactive.
Value
Description
0
LEUn_TX is held high when the transmitter is inactive. INV inverts the
inactive state.
1
LEUn_TX is tristated when the transmitter is inactive
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.2 LEUARTn_CMD - Command Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
5
4
3
2
1
0
RXBLOCKDIS W1 0
W1 0
W1 0
W1 0
W1 0
W1 0
RXBLOCKEN
TXDIS
TXEN
RXDIS
RXEN
6
W1 0
CLEARTX
Name
7
Access
W1 0
Reset
CLEARRX
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Bit
Name
Reset
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
CLEARRX
0
W1
Description
Clear RX
Set to clear receive buffer and the RX shift register.
6
CLEARTX
0
W1
Clear TX
Set to clear transmit buffer and the TX shift register.
5
RXBLOCKDIS
0
W1
Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
4
RXBLOCKEN
0
W1
Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
3
TXDIS
0
W1
Transmitter Disable
W1
Transmitter Enable
W1
Receiver Disable
Set to disable transmission.
2
TXEN
0
Set to enable data transmission.
1
RXDIS
0
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
0
W1
Receiver Enable
Set to activate data reception on LEUn_RX.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.3 LEUARTn_STATUS - Status Register
Access
Bit
Name
Reset
31:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6
TXIDLE
1
R
TX Idle
0
R
RX Data Valid
0
0
R
RXENS
1
0
R
TXENS
2
0
RXBLOCK R
3
0
R
TXC
4
1
R
5
0
TXBL
Name
R
TXIDLE
R
Access
RXDATAV
6
7
1
Reset
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x008
Bit Position
31
Offset
Description
Set when TX is idle
5
RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
4
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
3
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.
2
RXBLOCK
0
R
Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is
set at the instant the frame has been completely received.
1
TXENS
0
R
Transmitter Enable Status
R
Receiver Enable Status
Set when the transmitter is enabled.
0
RXENS
0
Set when the receiver is enabled. The receiver must be enabled for start frames, signal frames, and multi-processor address bit detection.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
0
1
2
3
4
5
6
7
8
9
10
DIV RW 0x0000
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
16:3
DIV
0x0000
RW
Description
Fractional Clock Divider
Specifies the fractional clock divider for the LEUART. Bits [7:3] are the franctional part and bits [16:8] are the integer part.
The total divider is ([16:8] + [7:3]/32). To make the math easier the total divider can also be calculated as '([16:8] + [7:0]/
256) where bits [0:2] will always be 0.
2:0
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Name
Access
Bit
Name
Reset
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
STARTFRAME
0x000
RW
0
1
2
3
5
6
7
8
9
10
11
12
13
14
STARTFRAME RW 0x000 4
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Description
Start Frame
When a frame matching STARTFRAME is detected by the receiver, STARTF interrupt flag is set, and if SFUBRX is set,
RXBLOCK is cleared. The start-frame is be loaded into the RX buffer.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
SIGFRAME
0x000
RW
0
31:9
0
Access
1
Reset
1
Name
2
Bit
3
Name
2
Access
3
Reset
SIGFRAME RW 0x000 4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x014
Bit Position
31
Offset
Description
Signal Frame
When a frame matching SIGFRAME is detected by the receiver, SIGF interrupt flag is set.
17.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads)
Access
0x000 4
RXDATA R
5
6
7
8
9
10
11
12
13
14
0
R
PERR
Name
R
Access
FERR
0
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
FERR
0
R
Description
Receive Data Framing Error
Set if data in buffer has a framing error. Can be the result of a break condition.
14
PERR
0
R
Receive Data Parity Error
Set if data in buffer has a parity error.
13:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
RXDATA
0x000
R
RX Data
Use this register to access data read from the LEUART. Buffer is cleared on read access.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads)
0
1
2
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Reset
RXDATA R
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
RXDATA
0x00
R
Description
RX Data
Use this register to access data read from LEUART. Buffer is cleared on read access. Only the 8 LSB can be read using
this register.
17.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register
Access
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
FERRP
0
R
0
1
2
3
0x000 4
RXDATAP R
5
6
7
8
9
10
11
12
13
14
0
R
PERRP
Name
R
Access
FERRP
0
Reset
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Description
Receive Data Framing Error Peek
Set if data in buffer has a framing error. Can be the result of a break condition.
14
PERRP
0
R
Receive Data Parity Error Peek
Set if data in buffer has a parity error.
13:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
RXDATAP
0x000
R
RX Data Peek
Use this register to access data read from the LEUART.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Bit
Name
Reset
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15
RXENAT
0
W
0
1
2
3
0x000 4
TXDATA
W
5
6
7
8
9
10
11
12
13
0
TXBREAK W
14
0
W
Name
TXDISAT
15
0
Access
W
Reset
RXENAT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Description
Enable RX After Transmission
Set to enable reception after transmission.
14
Value
Description
0
The receiver is not enabled after the frame has been transmitted
1
The receiver is enabled (setting RXENS) after the frame has been
transmitted
TXDISAT
0
W
Disable TX After Transmission
Set to disable transmitter directly after transmission has competed.
13
Value
Description
0
The transmitter is not disabled after the frame has been transmitted
1
The transmitter is disabled (clearing TXENS) after the frame has been
transmitted
TXBREAK
0
W
Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
Value
Description
0
The specified number of stop-bits are transmitted
1
Instead of the ordinary stop-bits, 0 is transmitted to generate a break. A
single stop-bit is generated after the break to allow the receiver to detect the start of the next frame
12:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
8:0
TXDATA
0x000
W
TX Data
Use this register to write data to the LEUART. If the transmitter is enabled, a transfer will be initiated at the first opportunity.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
0
1
2
3
4
0x00
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x028
Bit Position
31
Offset
Reset
TXDATA W
Access
Name
Bit
Name
Reset
Access
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7:0
TXDATA
0x00
W
Description
TX Data
This frame will be added to the transmit buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be
cleared.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.12 LEUARTn_IF - Interrupt Flag Register
Access
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
SIGF
0
0
0
R
TXC
1
1
R
TXBL
2
0
RXDATAV R
3
0
R
RXOF
4
0
R
RXUF
5
0
R
TXOF
6
R
PERR
0
7
R
FERR
0
8
R
MPAF
0
9
0
R
STARTF
Name
R
Access
SIGF
0
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
Description
R
Signal Frame Interrupt Flag
R
Start Frame Interrupt Flag
R
Multi-Processor Address Frame Interrupt Flag
Set when a signal frame is detected.
9
STARTF
0
Set when a start frame is detected.
8
MPAF
0
Set when a multi-processor address frame is detected.
7
FERR
0
R
Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
6
PERR
0
R
Parity Error Interrupt Flag
Set when a frame with a parity error is received while RXBLOCK is cleared.
5
TXOF
0
R
TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
4
RXUF
0
R
RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
3
RXOF
0
R
RX Overflow Interrupt Flag
Set when data is incoming while the receive shift register is full. The data previously in shift register is overwritten by the
new data.
2
RXDATAV
0
R
RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
1
TXBL
1
R
TX Buffer Level Interrupt Flag
Set when space becomes available in the transmit buffer for a new frame.
0
TXC
0
R
TX Complete Interrupt Flag
Set after a transmission when both the TX buffer and shift register are empty.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.13 LEUARTn_IFS - Interrupt Flag Set Register
Access
0
W1 0
TXC
1
2
3
W1 0
RXOF
4
W1 0
RXUF
5
W1 0
W1 0
PERR
TXOF
W1 0
FERR
6
8
W1 0
MPAF
7
9
STARTF W1 0
SIGF
Name
10
Access
W1 0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Bit
Name
Reset
Description
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
SIGF
0
W1
Set SIGF Interrupt Flag
W1
Set STARTF Interrupt Flag
Write 1 to set the SIGF interrupt flag
9
STARTF
0
Write 1 to set the STARTF interrupt flag
8
MPAF
0
W1
Set MPAF Interrupt Flag
W1
Set FERR Interrupt Flag
W1
Set PERR Interrupt Flag
W1
Set TXOF Interrupt Flag
W1
Set RXUF Interrupt Flag
W1
Set RXOF Interrupt Flag
Write 1 to set the MPAF interrupt flag
7
FERR
0
Write 1 to set the FERR interrupt flag
6
PERR
0
Write 1 to set the PERR interrupt flag
5
TXOF
0
Write 1 to set the TXOF interrupt flag
4
RXUF
0
Write 1 to set the RXUF interrupt flag
3
RXOF
0
Write 1 to set the RXOF interrupt flag
2:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
TXC
0
W1
Set TXC Interrupt Flag
Write 1 to set the TXC interrupt flag
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.14 LEUARTn_IFC - Interrupt Flag Clear Register
Access
0
(R)W1 0
1
2
TXC
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
SIGF
0
(R)W1
3
(R)W1 0
RXOF
4
(R)W1 0
RXUF
5
(R)W1 0
(R)W1 0
PERR
TXOF
(R)W1 0
FERR
6
8
(R)W1 0
MPAF
7
9
SIGF
Name
STARTF (R)W1 0
Access
10
Reset
(R)W1 0
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x034
Bit Position
31
Offset
Description
Clear SIGF Interrupt Flag
Write 1 to clear the SIGF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
9
STARTF
0
(R)W1
Clear STARTF Interrupt Flag
Write 1 to clear the STARTF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
8
MPAF
0
(R)W1
Clear MPAF Interrupt Flag
Write 1 to clear the MPAF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
7
FERR
0
(R)W1
Clear FERR Interrupt Flag
Write 1 to clear the FERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
6
PERR
0
(R)W1
Clear PERR Interrupt Flag
Write 1 to clear the PERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
5
TXOF
0
(R)W1
Clear TXOF Interrupt Flag
Write 1 to clear the TXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
4
RXUF
0
(R)W1
Clear RXUF Interrupt Flag
Write 1 to clear the RXUF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
3
RXOF
0
(R)W1
Clear RXOF Interrupt Flag
Write 1 to clear the RXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
2:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
TXC
0
(R)W1
Clear TXC Interrupt Flag
Write 1 to clear the TXC interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.15 LEUARTn_IEN - Interrupt Enable Register
Access
2
1
RXDATAV RW 0
RW 0
RW 0
TXBL
TXC
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
SIGF
0
0
3
RW 0
RXOF
4
RW 0
RXUF
5
RW 0
TXOF
6
RW 0
PERR
7
RW 0
FERR
8
RW 0
MPAF
9
RW 0
10
STARTF
Name
RW 0
Access
SIGF
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x038
Bit Position
31
Offset
Description
RW
SIGF Interrupt Enable
RW
STARTF Interrupt Enable
RW
MPAF Interrupt Enable
RW
FERR Interrupt Enable
RW
PERR Interrupt Enable
RW
TXOF Interrupt Enable
RW
RXUF Interrupt Enable
RW
RXOF Interrupt Enable
RW
RXDATAV Interrupt Enable
RW
TXBL Interrupt Enable
RW
TXC Interrupt Enable
Enable/disable the SIGF interrupt
9
STARTF
0
Enable/disable the STARTF interrupt
8
MPAF
0
Enable/disable the MPAF interrupt
7
FERR
0
Enable/disable the FERR interrupt
6
PERR
0
Enable/disable the PERR interrupt
5
TXOF
0
Enable/disable the TXOF interrupt
4
RXUF
0
Enable/disable the RXUF interrupt
3
RXOF
0
Enable/disable the RXOF interrupt
2
RXDATAV
0
Enable/disable the RXDATAV interrupt
1
TXBL
0
Enable/disable the TXBL interrupt
0
TXC
0
Enable/disable the TXC interrupt
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers).
Access
Name
Reset
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
PULSEFILT
0
0
1
2
RW 0x0
PULSEW
Bit
RW
3
4
0
RW
5
PULSEEN
Name
0
Access
PULSEFILT RW
Reset
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Description
Pulse Filter
Enable a one-cycle pulse filter for pulse extender
4
Value
Description
0
Filter is disabled. Pulses must be at least 2 cycles long for reliable detection.
1
Filter is enabled. Pulses must be at least 3 cycles long for reliable detection.
PULSEEN
0
RW
Pulse Generator/Extender Enable
Filter LEUART output through pulse generator and the LEUART input through the pulse extender.
3:0
PULSEW
0x0
RW
Pulse Width
Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.17 LEUARTn_FREEZE - Freeze Register
REGFREEZE RW 0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x040
Bit Position
31
Offset
Access
Name
Bit
Name
Reset
Access
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
0
REGFREEZE
0
RW
Description
Register Update Freeze
When set, the update of the LEUART logic from registers is postponed until this bit is cleared. Use this bit to update several
registers simultaneously.
Value
Mode
Description
0
UPDATE
Each write access to a LEUART register is updated into the Low Frequency domain as soon as possible.
1
FREEZE
The LEUART is not updated with the new written value.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
Access
Name
Reset
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
PULSECTRL
0
R
3
2
1
0
0
0
0
0
R
R
R
CLKDIV
CMD
CTRL
4
0
R
SIGFRAME
Bit
STARTFRAME R
5
0
R
6
0
R
TXDATA
TXDATAX
7
8
9
0
Name
R
Access
PULSECTRL
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x044
Bit Position
31
Offset
Description
PULSECTRL Register Busy
Set when the value written to PULSECTRL is being synchronized.
6
TXDATA
0
R
TXDATA Register Busy
Set when the value written to TXDATA is being synchronized.
5
TXDATAX
0
R
TXDATAX Register Busy
Set when the value written to TXDATAX is being synchronized.
4
SIGFRAME
0
R
SIGFRAME Register Busy
Set when the value written to SIGFRAME is being synchronized.
3
STARTFRAME
0
R
STARTFRAME Register Busy
Set when the value written to STARTFRAME is being synchronized.
2
CLKDIV
0
R
CLKDIV Register Busy
Set when the value written to CLKDIV is being synchronized.
1
CMD
0
R
CMD Register Busy
Set when the value written to CMD is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register
Bit
Name
Reset
Access
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
TXPEN
0
RW
0
2
RXPEN RW 0
Name
1
Access
TXPEN RW 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x054
Bit Position
31
Offset
Description
TX Pin Enable
When set, the TX pin of the LEUART is enabled.
0
Value
Description
0
The LEUn_TX pin is disabled
1
The LEUn_TX pin is enabled
RXPEN
0
RW
RX Pin Enable
When set, the RX pin of the LEUART is enabled.
Value
Description
0
The LEUn_RX pin is disabled
1
The LEUn_RX pin is enabled
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register
Name
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0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5
RXLOC RW 0x00
Access
TXLOC RW 0x00
Reset
22
23
24
25
26
27
28
29
30
0x058
Bit Position
31
Offset
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EFM32JG1 Reference Manual
LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
31:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
TXLOC
0x00
RW
Description
I/O Location
Decides the location of the LEUART TX pin. See the device datasheet for the mapping between location and physical pins.
7:6
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
Bit
Name
Reset
Access
Description
5:0
RXLOC
0x00
RW
I/O Location
Decides the location of the LEUART RX pin. See the device datasheet for the mapping between location and physical pins.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
17.5.21 LEUARTn_INPUT - LEUART Input Register
Name
Bit
Name
Reset
Access
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5
RXPRS
0
RW
0
1
2
RXPRSSEL RW 0x0
RW
RXPRS
Access
3
4
5
6
7
8
9
10
0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x064
Bit Position
31
Offset
Description
PRS RX Enable
When set, the PRS channel selected as input to RX.
4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3:0
RXPRSSEL
0x0
RW
RX PRS Channel Select
Select PRS channel as input to RX.
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected
1
PRSCH1
PRS Channel 1 selected
2
PRSCH2
PRS Channel 2 selected
3
PRSCH3
PRS Channel 3 selected
4
PRSCH4
PRS Channel 4 selected
5
PRSCH5
PRS Channel 5 selected
6
PRSCH6
PRS Channel 6 selected
7
PRSCH7
PRS Channel 7 selected
8
PRSCH8
PRS Channel 8 selected
9
PRSCH9
PRS Channel 9 selected
10
PRSCH10
PRS Channel 10 selected
11
PRSCH11
PRS Channel 11 selected
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TIMER - Timer/Counter
18. TIMER - Timer/Counter
Quick Facts
What?
0 1 2 3
4
The TIMER (Timer/Counter) keeps track of timing
and counts events, generates output waveforms and
triggers timed actions in other peripherals.
Why?
ADC
USART
PRS
How?
TIMER
Compare values
=
Most applications have activities that need to be
timed accurately with as little CPU intervention and
energy consumption as possible.
Output compare/PWM
The flexible 16-bit timer can be configured to provide
PWM waveforms with optional dead-time insertion
(e.g. motor control) or work as a frequency generator. The timer can also count events and control other peripherals through the PRS, which offloads the
CPU and reduces energy consumption.
Counter
Clock
Input capture
Capture values
18.1 Introduction
The 16-bit general purpose timer has 3 or 4 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM)
output. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.
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TIMER - Timer/Counter
18.2 Features
• 16-bit auto reload up/down counter
• Dedicated 16-bit reload register which serves as counter maximum
• 3 or 4 Compare/Capture channels
• Individually configurable as either input capture or output compare/PWM
• Multiple Counter modes
• Count up
• Count down
• Count up/down
• Quadrature Decoder
• Direction and count from external pins
• 2x Count Mode
• Counter control from PRS or external pin
• Start
• Stop
• Reload and start
• Inter-Timer connection
• Allows 32-bit counter mode
• Start/stop synchronization between several timers
• Input Capture
• Period measurement
• Pulse width measurement
• Two capture registers for each capture channel
• Capture on either positive or negative edge
• Capture on both edges
• Optional digital noise filtering on capture inputs
• Output Compare
• Compare output toggle/pulse on compare match
• Immediate update of compare registers
• PWM
• Up-count PWM
• Up/down-count PWM
• Predictable initial PWM output state (configured by SW)
• Buffered compare register to ensure glitch-free update of compare values
• Clock sources
• HFPERCLKTIMERn
• 10-bit Prescaler
• External pin
• Peripheral Reflex System
• Debug mode
• Configurable to either run or stop when processor is stopped (halt/breakpoint)
• Interrupts, PRS output and/or DMA request on:
• Underflow
• Overflow
• Compare/Capture event
• Dead-Time Insertion Unit (TIMER0 only)
• Complementary PWM outputs with programmable dead-time
• Dead-time is specified independently for rising and falling edge
• 10-bit prescaler
• 6-bit time value
• Outputs have configurable polarity
• Outputs can be set inactive individually by software.
• Configurable action on fault
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TIMER - Timer/Counter
• Set outputs inactive
• Clear output
• Tristate output
• Individual fault sources
• One or two PRS signals
• Debugger
• Support for automatic restart
• Core lockup
• Configuration lock
18.3 Functional Description
An overview of the TIMER module is shown in Figure 18.1 TIMER Block Overview on page 566 and it consists of a 16 bit up/down
counter with 3 Compare/Capture channels connected to pins TIMn_CC0, TIMn_CC1, and TIMn_CC2.
HFPERCLKTIMERn
Prescaler
CNTCLK
Counter
control
TIMERn_CNT
Note: For simplicity, all
TIMERn_CCx registers are
grouped together in the figure,
but they all have individual Input
Capture Registers
Update
condition
TIMERn_TOP
Quadrature
Decoder
=
Overflow
=0
Underflow
Input Capture
TIMn_CC0
Input logic
PRS inputs
TIMn_CC1
Input logic
PRS inputs
TIMn_CC2
Input logic
PRS inputs
Compare Match x
Edge
detect
Edge
detect
TnCCR1[15:0
TIMERn_CCx
TnCCR0[15:0
]
]
=
==
Edge
detect
Compare and
PWM config
TIMn_CC0
Compare and
PWM config
TIMn_CC1
Compare and
PWM config
TIMn_CC2
Figure 18.1 TIMER Block Overview
18.3.1 Counter Modes
The timer consists of a counter that can be configured to the following modes:
1. Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before counting up again.
2. Down-count: The counter starts at the value in TIMERn_TOP and counts down. When it reaches 0, it is reloaded with the value in
TIMERn_TOP.
3. Up/Down-count: The counter starts at 0 and counts up. When it reaches the value in TIMERn_TOP, it counts down until it reaches
0 and starts counting up again.
4. Quadrature Decoder: Two input channels where one determines the count direction, while the other pin triggers a clock event.
In addition, to the TIMER modes listed above, the TIMER also supports a 2x Count Mode. In this mode the counter increments/decrements by 2. The 2x Count Mode intended use is to generate 2x PWM frequency when the Compare/Capture channel is put in PWM
mode. The 2x Count Mode can be enabled by setting the X2CNT bitfield in the TIMERn_CTRL register.
The counter value can be read or written by software at any time by accessing the CNT field in TIMERn_CNT.
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TIMER - Timer/Counter
18.3.1.1 Events
Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up. In up-count mode and Quadrature
Decoder mode the next value is 0. In up/down-count mode, the next value is TIMERn_TOP-1.
Underflow is set when the counter value shifts from 0 to the next value when counting down. In down-count mode and Quadrature Decoder mode, the next value is TIMERn_TOP. In up/down-count mode the next value is 1.
An update event occurs on overflow in up-count mode and on underflow in down-count or up/down count mode. Additionally, an update
event also occurs on overflow and underflow in Quadrature Decoder Mode. This event is used to time updates of buffered values.
18.3.1.2 Operation
Figure 18.2 TIMER Hardware Timer/Counter Control on page 567 shows the hardware Timer/Counter control. Software can start or
stop the counter by setting the START or STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT) can always be written
by software to any 16-bit value.
It is also possible to control the counter through either an external pin or PRS input. This is done through the input logic for the Compare/Capture Channel 0. The Timer/Counter allows individual actions (start, stop, reload) to be taken for rising and falling input edges.
This is configured in the RISEA and FALLA fields in TIMERn_CTRL. The reload value is 0 in up-count and up/down-count mode and
TOP in down-count mode.
The RUNNING bit in TIMERn_STATUS indicates if the timer is running or not. If the SYNC bit in TIMERn_CTRL is set, the timer is
started/stopped/reloaded (external pin or PRS) when any of the other timers are started/stopped/reloaded.
The DIR bit in TIMERn_STATUS indicates the counting direction of the timer at any given time. The counter value can be read or written by software through the CNT field in TIMERn_CNT. In Up/Down-Count mode the count direction will be set to up if the CNT value is
written by software.
Counter
(Controlled by TIMERn_CTRL)
RISEA
FALLA
Start
Counter
Stop
Reload&Start
Compare/Capture channel 0
(Controlled by TIMERn_CC0_CTRL)
INSEL
ICEDGE
TIMn_CC0
Input
Capture 0
PRS channels
Filter
PRSSEL
FILT
Figure 18.2 TIMER Hardware Timer/Counter Control
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TIMER - Timer/Counter
18.3.1.3 Clock Source
The counter can be clocked from several sources, which are all synchronized with the peripheral clock (HFPERCLK). See Figure
18.3 TIMER Clock Selection on page 568.
Counter
(Controlled by TIMERn_CTRL)
HFPERCLKTIMERn
Compare/Capture channel 1
(Controlled by TIMERn_CC1_CTRL)
PRESC
CLKSEL
Counter
Prescaler
INSEL
ICEDGE
TIMn_CC1
Input
Capture 1
PRS channels
Filter
PRSSEL
FILT
Figure 18.3 TIMER Clock Selection
18.3.1.4 Peripheral Clock (HFPERCLK)
The peripheral clock (HFPERCLK) can be used as a source with a configurable prescale factor of 2^PRESC, where PRESC is an integer between 0 and 10, which is set in PRESC in TIMERn_CTRL. However, if 2x Count Mode is enabled and the Compare/Capture
channels are put in PWM mode, the CC output is updated on both clock edges so prescaling the peripheral clock will produce an incorrect result. The prescaler is stopped and reset when the timer is stopped.
18.3.1.5 Compare/ Capture Channel 1 Input
The timer can also be clocked by positive and/or negative edges on the Compare/Capture channel 1 input. This input can either come
from the TIMn_CC1 pin or one of the PRS channels. The input signal must not have a higher frequency than fHFPERCLK/3 when running
from a pin input or a PRS input with FILT enabled in TIMERn_CCx_CTRL. When running from PRS without FILT, the frequency can be
as high as fHFPERCLK. Note that when clocking the timer from the same pulse that triggers a start (through RISEA/FALLA in
TIMERn_CTRL), the starting pulse will not update the Counter Value.
18.3.1.6 Underflow/Overflow from Neighboring Timer
All timers are linked together (see Figure 18.4 TIMER Connections on page 568), allowing timers to count on overflow/underflow from
the lower numbered neighbouring timers to form a 32-bit or 48-bit timer. Note that all timers must be set to same count direction and
less significant timer(s) can only be set to count up or down.
Underflow
TIMER2
Overflow
Underflow
TIMER1
Overflow
TIMER0
Figure 18.4 TIMER Connections
18.3.1.7 One-Shot Mode
By default, the counter counts continuously until it is stopped. If the OSMEN bit is set in the TIMERn_CTRL register, however, the counter is disabled by hardware on the first update event (see 18.3.1.1 Events). Note that when the counter is running with CC1 as clock
source (0b01 in CLKSEL in TIMERn_CTRL) and OSMEN is set, a CC1 capture event will not take place on the update event (CC1
rising edge) that stops the timer.
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TIMER - Timer/Counter
18.3.1.8 Top Value Buffer
The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to
the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP
value is not set below the actual count value. The TOPBV flag in TIMERn_STATUS indicates whether the TIMERn_TOPB register contains data that has not yet been written to the TIMERn_TOP register (see Figure 18.5 TIMER TOP Value Update Functionality on page
569).
Note: When writing to TIMERn_TOP register directly, the TIMERn_TOPB register value will be invalidated and the TOPBV flag will be
cleared. This prevents TIMERn_TOP register from being immmediately updated by an existing vaild TIMERn_TOPB value during the
next update event.
APB Write (TOPB)
Load APB
Clear
TOPBV
Load TOPB
APB Write (TOP)
Load APB
TOP
APB Data
Set
Update event
TOPB
Figure 18.5 TIMER TOP Value Update Functionality
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TIMER - Timer/Counter
18.3.1.9 Quadrature Decoder
Quadrature Decoding mode is used to track motion and determine both rotation direction and position. The Quadrature Decoder uses
two input channels that are 90 degrees out of phase (see Figure 18.6 TIMER Quadrature Encoded Inputs on page 570).
Channel A
90°
Channel B
Forward rotation (Channel A leads Channel B)
Channel A
Channel B
90°
Backward rotation (Channel B leads Channel A)
Figure 18.6 TIMER Quadrature Encoded Inputs
In the timer these inputs are tapped from the Compare/Capture channel 0 (Channel A) and 1 (Channel B) inputs before edge detection.
The Timer/Counter then increments or decrements the counter, based on the phase relation between the two inputs. The Quadrature
Decoder Mode supports two channels, but if a third channel (Z-terminal) is available, this can be connected to an external interrupt and
trigger a counter reset from the interrupt service routine. By connecting a periodic signal from another timer as input capture on Compare/Capture Channel 2, it is also possible to calculate speed and acceleration.
Note: In Quadrature Decoder mode, overflow and underflow triggers an update event
Compare/Capture channel 0
(Controlled by TIMERn_CC0_CTRL)
INSEL
ICEDGE
TIMn_CC0
PRS channels
Input
Capture 0
Filter
Counter
(Controlled by TIMERn_CTRL)
PRSSEL
QDM
MODE
FILT
Ch A
Ch B
Compare/Capture channel 1
(Controlled by TIMERn_CC1_CTRL)
Quadrature
Decoder
Inc Counter
Dec
INSEL
ICEDGE
TIMn_CC1
PRS channels
Input
Capture 1
Filter
PRSSEL
FILT
Figure 18.7 TIMER Quadrature Decoder Configuration
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TIMER - Timer/Counter
The Quadrature Decoder can be set in either X2 or X4 mode, which is configured in the QDM bit in TIMERn_CTRL. See Figure
18.7 TIMER Quadrature Decoder Configuration on page 570
18.3.1.10 X2 Decoding Mode
In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 18.1 TIMER Counter Response in
X2 Decoding Mode on page 571 and Figure 18.8 TIMER X2 Decoding Mode on page 571.
Table 18.1. TIMER Counter Response in X2 Decoding Mode
Channel A
Channel B
Rising
Falling
0
Increment
Decrement
1
Decrement
Increment
Channel A
Channel B
CNT
4
3
5
6
8
7
8
7
6
5
4
3
2
Figure 18.8 TIMER X2 Decoding Mode
18.3.1.11 X4 Decoding Mode
In X4 Decoding mode, the counter increments or decrements on every edge of Channel A and Channel B, see Figure 18.9 TIMER X4
Decoding Mode on page 571 and Table 18.2 TIMER Counter Response in X4 Decoding Mode on page 571.
Table 18.2. TIMER Counter Response in X4 Decoding Mode
Opposite Channel
Channel A
Rising
Channel B
Falling
Rising
Falling
Channel A = 0
Decrement
Increment
Channel A = 1
Increment
Decrement
Channel B = 0
Increment
Decrement
Channel B = 1
Decrement
Increment
Channel A
Channel B
CNT
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
Figure 18.9 TIMER X4 Decoding Mode
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TIMER - Timer/Counter
18.3.1.12 TIMER Rotational Position
To calculate a position Figure 18.10 TIMER Rotational Position Equation on page 572 can be used.
pos° = (CNT/X x N) x 360°
Equation: TIMER Rotational Position Equation
where X = Encoding type and N = Number of pulses per revolution.
18.3.2 Compare/Capture Channels
The timer contains 3 Compare/Capture channels, which can be configured in the following modes:
1. Input Capture
2. Output Compare
3. PWM
18.3.2.1 Input Pin Logic
Each Compare/Capture channel can be configured as an input source for the Capture Unit or as external clock source for the timer (see
Figure 18.11 TIMER Input Pin Logic on page 572). Compare/Capture channels 0 and 1 are the inputs for the Quadrature Decoder
Mode. The input channel can be filtered before it is used, which requires the input to remain stable for 5 cycles in a row before the input
is propagated to the output.
INSEL
ICEDGE
TIMn_CCx
PRS channels
Input
Capture x
Filter
PRSSEL
FILT
Figure 18.11 TIMER Input Pin Logic
18.3.2.2 Compare/Capture Registers
The Compare/Capture channel registers are prefixed with TIMERn_CCx_, where the x stands for the channel number. Since the Compare/Capture channels serve three functions (input capture, compare, PWM), the behavior of the Compare/Capture registers
(TIMERn_CCx_CCV) and buffer registers (TIMERn_CCx_CCVB) change depending on the mode the channel is set in.
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TIMER - Timer/Counter
18.3.2.3 Input Capture
In Input Capture Mode, the counter value (TIMERn_CNT) can be captured in the Compare/Capture Register (TIMERn_CCx_CCV) (see
Figure 18.12 TIMER Input Capture on page 573). The CCPOL bits in TIMERn_STATUS indicate the polarity of the edge that triggered
the capture in TIMERn_CCx_CCV.
Input
z
y
n
TIMERn_CNT m
TIMERn_CCx_CCVB
TIMERn_CCx_CCV
m
prev. val
y
m
y
Read TIMERn_CCx_CCV
Figure 18.12 TIMER Input Capture
The Compare/Capture Buffer Register (TIMERn_CCx_CCVB) and the TIMERn_CCx_CCV register form double-buffered capture registers allowing two subsequent capture events to take place before a read-out is required. The first capture can always be read from
TIMERn_CCx_CCV, and reading this address will load the next capture value into TIMERn_CCx_CCV from TIMERn_CCx_CCVB if it
contains valid data. The CC value can be read without altering the FIFO contents by reading TIMERn_CCx_CCVP.
TIMERn_CCx_CCVB can also be read without altering the FIFO contents. The ICV flag in TIMERn_STATUS indicates if there is a valid
unread capture in TIMERn_CCx_CCV. In this mode, TIMERn_CCx_CCV is read-only.
In the case where a capture is triggered while both TIMERn_CCx_CCV and TIMERn_CCx_CCVB contain unread capture values, the
buffer overflow interrupt flag (ICBOF in TIMERn_IF) will be set. On overflow new capture values will overwrite the value in
TIMERn_CCx_CCVB and the value of TIMERn_CCx_CCV will remain unchanged. TIMERn_CCx_CCV will always contain the oldest
unread value and TIMERn_CCx_CCVB will always contain the newest value.
Note: In input capture mode, the timer will only trigger interrupts when it is running
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TIMER - Timer/Counter
18.3.2.4 Period/Pulse-Width Capture
Period and/or pulse-width capture can only be possible with Channel 0 (CC0), because this is the only channel that can start and stop
the timer. This can be done by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either external pin or PRS, see Figure 18.13 TIMER Period and/or Pulse width Capture on page 574. For period capture, the Compare/Capture
Channel should then be set to input capture on a rising edge of the same input signal. To capture the width of a high pulse, the Compare/Capture Channel should be set to capture on a falling edge of the input signal. To measure the low pulse-width of a signal, opposite polarities should be chosen.
CNT
0
Input
Clear&Start
Input Capture (frequency capture)
Input Capture (pulse-width capture)
Figure 18.13 TIMER Period and/or Pulse width Capture
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TIMER - Timer/Counter
18.3.2.5 Compare
Each Compare/Capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_CCV matches
the counter value, see Figure 18.14 TIMER Block Diagram Showing Comparison Functionality on page 575. In compare mode, each
compare channel can be configured to either set, clear or toggle the output on an event (compare match, overflow or underflow). The
output from each channel is represented as an alternative function on the port it is connected to, which needs to be enabled for the CC
outputs to propagate to the pins.
Update
Condition
CNTCLK
TIMERn_CNT
TIMERn_TOP
Note: For simplicity, all
TIMERn_CCx registers are
grouped together in the figure,
but they all have individual
Compare Register and logic
TnCCR1[15:0
TIMERn_CCx
TnCCR0[15:0
]
]
=
Overflow
=0
Underflow
Compare Match x
=
==
Compare and
PWM config
TIMn_CC0
Compare and
PWM config
TIMn_CC1
Compare and
PWM config
TIMn_CC2
Figure 18.14 TIMER Block Diagram Showing Comparison Functionality
The compare output is delayed by one cycle to allow for full 0% to 100% PWM generation. Each example contains a high detail diagram whcih specifies the exact timing of events durring Compare or PWM operation. If occurring in the same cycle, match action will
have priority over overflow or underflow action.
The input selected (through PRSSEL, INSEL and FILTSEL in TIMERn_CCx_CTRL) for the CC channel will also be sampled on compare match and the result is found in the CCPOL bits in TIMERn_STATUS. It is also possible to configure the CCPOL to always track
the inputs by setting ATI in TIMERn_CTRL.
The COIST bit in TIMERn_CCx_CTRL is the initial state of the compare/PWM output. The COIST bit can also be used as an initial
value to the compare outputs on a reload-start when RSSCOIST is set in TIMERn_CTRL. Also the resulting output can be inverted by
setting OUTINV in TIMERn_CCx_CTRL. It is recommended to turn off the CC channel before configuring the output state to avoid any
pulses on the output. The CC channel can be turned off by setting MODE to OFF in TIMER_CCx_CTRL.
COIST
OUTINV
Output
Compare/
PWM x
0
TIMn_CCx
1
Figure 18.15 TIMER Output Logic
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TIMER - Timer/Counter
18.3.2.6 Compare Mode Registers
When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Compare mode the output can be configured to toggle, clear or set on compare match, overflow, and underflow through the CMOA, COFOA
and CUFOA fields in TIMERn_CCx_CTRL. TIMERn_CCx_CCV can be accessd directly or through the buffer register
TIMERn_CCx_CCVB, see Figure 18.16 TIMER Output Compare/PWM Buffer Functionality Detail on page 576. When writing to the
buffer register, the value in TIMERn_CCx_CCVB will be written to TIMERn_CCx_CCV on the next update event. This functionality ensures glitch free PWM outputs. The CCVBV flag in TIMERn_STATUS indicates whether the TIMERn_CCx_CCVB register contains data
that has not yet been written to the TIMERn_CCx_CCV register. Note that when writing 0 to TIMERn_CCx_CCVB in up-down count
mode the CCV value is updated when the timer counts from 0 to 1. Thus, the compare match for the next period will not happen until
the timer reaches 0 again on the way down.
Load APB CCVB
APB Write (CCB)
APB Write (CC)
Set
Clear
CCVBV
Load CCB
Load APB
CCV
APB Data
Update event
Figure 18.16 TIMER Output Compare/PWM Buffer Functionality Detail
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TIMER - Timer/Counter
18.3.2.7 Frequency Generation (FRG)
Frequency generation (see Figure 18.17 TIMER Up-count Frequency Generation on page 577) can be achieved in compare mode by:
• Setting the counter in up-count mode
• Enabling buffering of the TOP value.
• Setting the CC channels overflow action to toggle
TIMERn_TOP
0
TIMERn_CCx_CCV
Figure 18.17 TIMER Up-count Frequency Generation
The output frequency is given by Figure 18.17 TIMER Up-count Frequency Generation Equation on page 577
fFRG = fHFPERCLK/ ( 2^(PRESC + 1) x (TOP + 1) x 2)
Equation: TIMER Up-count Frequency Generation Equation
The figure below provides cycle accurate timing and event genration information for frequency generation.
TIMERn_TOP = 4
3
2
1
0
TIMERn_CCx
TIMERn_CCx_CCV
Figure 18.18 TIMER Up-count Frequency Generation Detail
18.3.2.8 Pulse-Width Modulation (PWM)
In PWM mode, TIMERn_CCx_CCV is buffered to avoid glitches in the output. The settings in the Compare Output Action configuration
bits are ignored in PWM mode and PWM generation is only supported for up-count and up/down-count mode.
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TIMER - Timer/Counter
18.3.2.9 Up-count (Single-slope) PWM
If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope PWM output will be generated
(see Figure 18.20 TIMER Up-count PWM Generation on page 578). In up-count mode the PWM period is TOP+1 cycles and the
PWM output will be high for a number of cycles equal to TIMERn_CCx_CCV. This means that a constant high output is achieved by
setting TIMER_CCx to TOP+1 or higher. The PWM resolution (in bits) is then given by Figure 18.20 TIMER Up-count PWM Resolution
Equation on page 578.
TIMn_CCx
TIMERn_TOP
TIMERn_CCx_CCV
0
Compare match
Overflow
Buffer update
Figure 18.20 TIMER Up-count PWM Generation
RPWMup = log(TOP+1)/log(2)
Equation: TIMER Up-count PWM Resolution Equation
The PWM frequency is given by Figure 18.21 TIMER Up-count PWM Frequency Equation on page 578:
fPWMup/down = fHFPERCLK/ ( 2^PRESC x (TOP + 1))
Equation: TIMER Up-count PWM Frequency Equation
The high duty cycle is given by Figure 18.22 TIMER Up-count Duty Cycle Equation on page 578
DSup = CCVx/(TOP+1)
Equation: TIMER Up-count Duty Cycle Equation
The figure below provides cycle accurate timing and event genration information for up-count mode.
TIMn_CCx
TIMERn_TOP =
TIMERn_CCx_CCV =
4
3
2
1
0
TIMERn_CCx
Compare match
Overflow
Buffer update
Figure 18.21 TIMER Up-count PWM Generation Detail
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TIMER - Timer/Counter
18.3.2.10 2x Count Mode
When the timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the
closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure
18.25 TIMER CC out in 2x mode on page 579
Clock
0
2
4
0
2
4
0
0
2
4
0
2
4
0
CC Out
Top = 5
Top = 5
CC = 1
CC = 2
Figure 18.25 TIMER CC out in 2x mode
Figure 18.25 TIMER 2x PWM Resolution Equation on page 579.
RPWM2xmode = log(TOP/2+1)/log(2)
Equation: TIMER 2x PWM Resolution Equation
The PWM frequency is given by Figure 18.26 TIMER 2x Mode PWM Frequency Equation( Up-count) on page 579:
fPWM2xmode = fHFPERCLK/ floor(TOP/2)+1
Equation: TIMER 2x Mode PWM Frequency Equation( Up-count)
The high duty cycle is given by Figure 18.27 TIMER 2x Mode Duty Cycle Equation on page 579
DS2xmode = CCVx/((floor(TOP/2)+1)*2)
Equation: TIMER 2x Mode Duty Cycle Equation
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TIMER - Timer/Counter
18.3.2.11 Up/Down-count (Dual-slope) PWM
If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual slope PWM output will be generated
by Figure 18.29 TIMER Up/Down-count PWM Generation on page 580.The resolution (in bits) is given by Figure 18.29 TIMER Up/
Down-count PWM Resolution Equation on page 580.
TIMn_CCx
TIMERn_TOP
TIMERn_CCx_CCV
0
Compare match
Overflow
Buffer update
Figure 18.29 TIMER Up/Down-count PWM Generation
RPWMup/down = log(TOP+1)/log(2)
Equation: TIMER Up/Down-count PWM Resolution Equation
The PWM frequency is given by Figure 18.30 TIMER Up/Down-count PWM Frequency Equation on page 580:
fPWMup/down = fHFPERCLK/ ( 2^(PRESC+1) x TOP))
Equation: TIMER Up/Down-count PWM Frequency Equation
The high duty cycle is given by Figure 18.31 TIMER Up/Down-count Duty Cycle Equation on page 580
DSup/down = CCVx/TOP
Equation: TIMER Up/Down-count Duty Cycle Equation
The figure below provides cycle accurate timing and event genration information for up-count mode.
TIMn_CCx
TIMERn_TOP =
TIMERn_CCx_CCV =
4
3
2
1
0
TIMERn_CCx
Overflow
Compare match
Buffer update
Figure 18.30 TIMER Up/Down-count PWM Generation
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TIMER - Timer/Counter
18.3.2.12 2x Count Mode
When the timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down to
the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure
18.34 TIMER CC out in 2x mode on page 581
Clock
0
2
4
2
0
2
0
4
2
4
2
0
2
4
CC Out
Top = 5
Top = 5
CC = 1
CC = 2
Figure 18.34 TIMER CC out in 2x mode
Figure 18.34 TIMER 2x PWM Resolution Equation on page 581.
RPWM2xmode = log(TOP/2+1)/log(2)
Equation: TIMER 2x PWM Resolution Equation
The PWM frequency is given by Figure 18.35 TIMER 2x Mode PWM Frequency Equation( Up/Down-count) on page 581:
fPWM2xmode = fHFPERCLK/ (floor(TOP/2)*2)
Equation: TIMER 2x Mode PWM Frequency Equation( Up/Down-count)
The high duty cycle is given by two equations based on the CCVx values.Figure 18.36 TIMER 2x Mode Duty Cycle Equation for CCVx
= 1 or CCVx = even on page 581 and Figure 18.37 TIMER 2x Mode Duty Cycle Equation for all other CCVx = odd values on page
581
DS2xmode = (CCVx*2)/(floor(TOP/2)*4)
Equation: TIMER 2x Mode Duty Cycle Equation for CCVx = 1 or CCVx = even
DS2xmode = (CCVx*2 - CCVx)/(floor(TOP/2)*4)
Equation: TIMER 2x Mode Duty Cycle Equation for all other CCVx = odd values
18.3.2.13 Timer Configuration Lock
To prevent software errors from making changes to the timer configuration, a configuration lock is available similar to DTI configuration
Lock. Writing any value but 0xCE80 to LOCKKEY in TIMERn_LOCK results in TIMERn_CTRL, TIMERn_CMD, TIMERn_TOP,
TIMERn_CNT, TIMERn_CCx_CTRL and TIMERn_CCx_CCV being locked from writing. To unlock the registers, write 0xCE80 to LOCKKEY in TIMERn_LOCK. The value of TIMERn_LOCK is 1 when the lock is active, and 0 when the registers are unlocked.
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TIMER - Timer/Counter
18.3.3 Dead-Time Insertion Unit (TIMER0 only)
The Dead-Time Insertion Unit aims to make control of brushless DC (BLDC) motors safer and more efficient by introducing complementary PWM outputs with dead-time insertion and fault handling, see Figure 18.39 TIMER Dead-Time Insertion Unit Overview on page
582.
Original PWM (TIM0_CCx_pre)
Dead time
insertion
Fault
handling
Primary output (TIM0_CCx)
Complementary output (TIM0_CDTIx)
Fault sources
Figure 18.39 TIMER Dead-Time Insertion Unit Overview
When used for motor control, the PWM outputs TIM0_CC0, TIM0_CC1 and TIM0_CC2 are often connected to the high-side transistors
of a triple half-bridge setup (UH, VH and WH), and the complementary outputs connected to the respective low-side transistors (UL, VL,
WL shown in Figure 18.40 TIMER Triple Half-Bridge on page 582). Transistors used in such a bridge often do not open/close instantaneously, and using the exact complementary inputs for the high and low side of a half-bridge may result in situations where both gates
are open. This can give unnecessary current-draw and short circuit the power supply. The DTI unit provides dead-time insertion to deal
with this problem.
UH
VH
WH
W
V
U
UL
VL
WL
Figure 18.40 TIMER Triple Half-Bridge
For each of the 3 compare-match outputs of TIMER0, an additional complementary output is provided by the DTI unit. These outputs,
named TIM0_CDTI0, TIM0_CDTI1 and TIM0_CDTI2 are provided to make control of e.g. 3-channel BLDC or permanent magnet AC
(PMAC) motors possible using only a single timer, see Figure 18.41 TIMER Overview of Dead-Time Insertion Block for a Single PWM
channel on page 583.
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TIMER - Timer/Counter
DTFALLT
DTRISET
Select
Original PWM (TIM0_CCx_pre)
HFPERCLKTIMERn
Clock control
Counter
=0
Primary output (TIM0_CCx)
Complementary Output (TIM0_CDTIx)
Figure 18.41 TIMER Overview of Dead-Time Insertion Block for a Single PWM channel
The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the complementary outputs, the DTI unit then
also overrides the compare match outputs from the timer.
The DTI unit gives the rising edges of the PWM outputs and the rising edges of the complementary PWM outputs a configurable time
delay. By doing this, the DTI unit introduces a dead-time where both the primary and complementary outputs in a pair are inactive as
seen in Figure 18.42 TIMER Polarity of Both Signals are Set as Active-High on page 583.
Original PWM
TIM0_CC0
TIM0_CDTI0
dt1
dt2
Figure 18.42 TIMER Polarity of Both Signals are Set as Active-High
Dead-time is specified individually for the rising and falling edge of the original PWM. These values are shared across all the three
PWM channels of the DTI unit. A single prescaler value is provided for the DTI unit, meaning that both the rising and falling edge deadtimes share prescaler value. The prescaler divides the HFPERCLKTIMERn by a configurable factor between 1 and 1024, which is set in
the DTPRESC field in TIMER0_DTTIME. The rising and falling edge dead-times are configured in DTRISET and DTFALLT in TIMER0_DTTIME to any number between 1-64 HFPERCLKTIMER0 cycles.
The DTAR and DTFATS bits in TIMER0_DTCTRL control the DTI output behavior when the timer stops. By default the DTI block stops
when the timer is stopped. Setting the DTAR bit will cause the DTI to output on channel 0 to continue when the timer is stopped. DTAR
effects only channel 0. See 18.3.3.2 PRS Channel as a Source for an example of when this can be used. While in this mode the undivided HFPERCLK_TIMER0 (DTPRESC=0) is always used regardless of programmed DTPRESC value in TIMER0_DTTIME. This means
that rise and fall dead times are calculated assuming DTPRESC = 0.
When the timer stops DTI outputs are frozen by default, preserving their last state. To allow the outputs to go to a safe state as programmed in the DTFA field of TIMER0_DTFC register and set the DTFATS bitfield in the TIMER0_DTCTRL reg. Note that when DTAR
is also set, DTAR has priority over DTFATS for DTI channel 0 output.
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TIMER - Timer/Counter
Table 18.3. DTI output when timer halted
DTAR
DTFATS
State
0
0
frozen
0
1
safe
1
0
running
1
1
running
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TIMER - Timer/Counter
18.3.3.1 Output Polarity
The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of
the outputs can be changed however, if this is required by the application. The active values of the primary and complementary outputs
are set by the DTIPOL and DTCINV bits in the TIMER0_DTCTRL register. The DTIPOL bit of this register specifies the base polarity. If
DTIPOL =0, then the outputs are active-high, and if DTIPOL = 1 they are active-low. The relative phase of the primary and complementary outputs is not changed by DTIPOL, as the polarity of both outputs is changed, see Figure 18.45 TIMER Output Polarities on page
585
In some applications, it may be required that the primary outputs are active-high, while the complementary outputs are active-low. This
can be accomplished by manipulating the DTCINV bit of the TIMER0_DTCTRL register, which inverts the polarity of the complementary
outputs relative to the primary outputs.
DTIPOL = 0 and DTCINV = 0 results in outputs with opposite phase and active-high states.
Figure 18.43 TIMER DTI Example 1
DTIPOL = 1 and DTCINV = 1 results in outputs with equal phase. The primary output will be active-high, while the complementary will
be active-low
Figure 18.44 TIMER DTI Example 2
Original PWM
DTIPOL = 0
DTCINV = 0
DTIPOL = 1
DTCINV = 0
DTIPOL = 0
DTCINV = 1
DTIPOL = 1
DTCINV = 1
TIM0_CC0
TIM0_CDTI0
TIM0_CC0
TIM0_CDTI0
TIM0_CC0
TIM0_CDTI0
TIM0_CC0
TIM0_CDTI0
Figure 18.45 TIMER Output Polarities
Output generation on the individual DTI outputs can be disabled by configuring TIMER0_DTOGEN. When output generation on an output is disabled that output will go to and stay in its inactive state.
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TIMER - Timer/Counter
18.3.3.2 PRS Channel as a Source
A PRS channel can be used as input to the DTI module instead of the PWM output from the timer for DTI channel 0. Setting DTPRSEN
in TIMER0_DTCTRL will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS
channel. The rest of the DTI channels will continue to be driven by the PWM output from the timer. The input PRS channel is chosen by
configuring DTPRSSEL in TIMER0_DTCTRL. Note that the timer must be running even when PRS is used as DTI source. However, if it
is required to keep the DTI channel 0 running even when the timer is stopped, set DTAR in TIMER0_DTCTRL. When this bit is set, it
uses DTPRESC=0 regardless of the value programmed in DTPRESC in TIMER0_DTTIME.
The DTI prescaler, set by DTPRESC in TIMER0_DTTIME determines the accuracy with which the DTI can insert dead-time into a PRS
signal. The maximum dead-time error equals 2DTPRESC clock cycles. With zero prescaling, the inserted dead-times are therefore accurate, but they may be inaccurate for larger prescaler settings.
18.3.3.3 Fault Handling
The fault handling system of the DTI unit allows the outputs of the DTI unit to be put in a well-defined state in case of a fault. This
hardware fault handling system enables a fast reaction to faults, reducing the possibility of damage to the system.
The fault sources which trigger a fault in the DTI module are determined by the bitfields of TIMER0_DTFC register. Any combination of
the available error sources can be selected:
• PRS source 0, determined by DTPRS0FSEL in TIMER0_DTFC
• PRS source 1, determined by DTPRS1FSEL in TIMER0_DTFC
• Debugger
• Core Lockup
One or two PRS channels can be used as an error source. When PRS source 0 is selected as an error source, DTPRS0FSEL determines which PRS channel is used for this source. DTPRS1FSEL determines which PRS channel is selected as PRS source 1. Please
note that for Core Lockup, the LOCKUPRDIS in RMU_CTRL must be set. Otherwise this will generate a full reset of the chip.
18.3.3.4 Action on Fault
When a fault occurs, the bit representing the fault source is set in TIMER0_DTFAULT register, and the outputs from the DTI unit are set
to a well-defined state. The following options are available, and can be enabled by configuring DTFACT in TIMER0_DTFC:
• Set outputs to inactive level
• Clear outputs
• Tristate outputs
With the first option enabled, the output state in case of a fault depends on the polarity settings for the individual outputs. An output set
to be active high will be set low if a fault is detected, while an output set to be active low will be driven high.
When a fault occurs, the fault source(s) can be read out from TIMER0_DTFAULT register.
Additionally a fault action can also be triggered when the timer stops if DTFATS in TIMER0_DTCTRL is set. This allows the DTI output
to go to safe state programmed in DTFACT in TIMER0_DTFC when timer stops. When DTAR and DTFATS in TIMER0_DTCTRL are
both set, DTI channel 0 keeps running even when the timer stops. This is useful when DTI channel 0 has an input coming from PRS.
18.3.3.5 Exiting Fault State
When a fault is triggered by the PRS system, software intervention is required to re-enable the outputs of the DTI unit. This is done by
manually clearing bits in TIMER0_DTFAULT register. If the fault source as determined by checking TIMER0_DEFAULT is the debugger
alone, the outputs can be automatically restarted when the debugger exits. To eable automatic restart set DTDAS in TIMER0_DCTRL.
When an automatic restart occurs the DTDBGF bit in TIMER0_DTFAULT will be automatically cleared by hardware. If any other bits in
the TIMER0_DTFAULT register are set when the hardware clears DTDBGF the DTI module will not exit the fault state.
18.3.3.6 DTI Configuration Lock
To prevent software errors from making changes to the DTI configuration, a configuration lock is available. Writing any value but
0xCE80 to LOCKKEY in TIMER0_DTLOCK results in TIMER0_DTFC, TIMER0_DTCTRL, TIMER0_DTTIME and TIMER0_ROUTE being locked from writing. To unlock the registers, write 0xCE80 to LOCKKEY in TIMER0_DTLOCK. The value of TIMER0_DTLOCK is 1
when the lock is active, and 0 when the registers are unlocked.
18.3.4 Debug Mode
When the CPU is halted in debug mode, the timer can be configured to either continue to run or to be frozen. This is configured in
DEBUGRUN in TIMERn_CTRL.
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TIMER - Timer/Counter
18.3.5 Interrupts, DMA and PRS Output
The timer has 3 different types of output events:
• Counter Underflow
• Counter Overflow
• Compare match or input capture (one per Compare/Capture channel)
Each of the events has its own interrupt flag. Also, there is one interrupt flag for each Compare/Capture channel which is set on buffer
overflow in capture mode. Buffer overflow happens when a new capture pushes an old unread capture out of the TIMERn_CCx_CCV/
TIMERn_CCx_CCVB register pair.
If the interrupt flags are set and the corresponding interrupt enable bits in TIMERn_IEN are set high, the timer will send out an interrupt
request. Each of the events will also lead to a one HFPERCLKTIMERn cycle high pulse on individual PRS outputs. Setting PRSOCNF to
LEVEL in TIMERn_CCx_CTRL will make the compare match PRS output follow the compare match output, instead of outputting one
HFPERCLKTIMERn cycle high pulse. Interrupts are cleared by setting the corresponding bit in the TIMERn_IFC register.
Each of the events will also set a DMA request when they occur. The different DMA requests are cleared when certain acknowledge
conditions are met, see Table 18.4 TIMER DMA Events on page 587. Events which clear the DMA requests do not clear interrupt
flags. Software must still manaually clear the interrupt flag if interrupts are in use.
If DMACLRACT is set in TIMERn_CTRL, the DMA request is cleared when the triggered DMA channel is active, without having to access any timer registers. This is usfull in cases where a timer event is used to trigger a DMA tansfer that does not target the CCV or
CCVB register.
Table 18.4. TIMER DMA Events
Event
Acknowledge/Clear
Underflow/Overflow
Read or write to TIMERn_CNT or TIMERn_TOPB
CC 0
Read or write to TIMERn_CC0_CCV or TIMERn_CC0_CCVB
CC 1
Read or write to TIMERn_CC1_CCV or TIMERn_CC1_CCVB
CC 2
Read or write to TIMERn_CC2_CCV or TIMERn_CC2_CCVB
18.3.6 GPIO Input/Output
The TIMn_CCx inputs/outputs and TIM0_CDTIx outputs are accessible as alternate functions through GPIO. Each pin connection can
be enabled/disabled separately by setting the corresponding CCxPEN or CDTIxPEN bits in TIMERn_ROUTE. The LOCATION bits in
the same register can be used to move all enabled pins to alternate pins. See the device datasheet for the mapping between block
locations (LOC0, LOC1, etc.) and actual device pins (PA0, PA1, etc.).
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TIMER - Timer/Counter
18.4 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
TIMERn_CTRL
RW
Control Register
0x004
TIMERn_CMD
W1
Command Register
0x008
TIMERn_STATUS
R
Status Register
0x00C
TIMERn_IF
R
Interrupt Flag Register
0x010
TIMERn_IFS
W1
Interrupt Flag Set Register
0x014
TIMERn_IFC
(R)W1
Interrupt Flag Clear Register
0x018
TIMERn_IEN
RW
Interrupt Enable Register
0x01C
TIMERn_TOP
RWH
Counter Top Value Register
0x020
TIMERn_TOPB
RW
Counter Top Value Buffer Register
0x024
TIMERn_CNT
RWH
Counter Value Register
0x02C
TIMERn_LOCK
RWH
TIMER Configuration Lock Register
0x030
TIMERn_ROUTEPEN
RW
I/O Routing Pin Enable Register
0x034
TIMERn_ROUTELOC0
RW
I/O Routing Location Register
0x03C
TIMERn_ROUTELOC2
RW
I/O Routing Location Register
0x060
TIMERn_CC0_CTRL
RW
CC Channel Control Register
0x064
TIMERn_CC0_CCV
RWH(a)
CC Channel Value Register
0x068
TIMERn_CC0_CCVP
R
CC Channel Value Peek Register
0x06C
TIMERn_CC0_CCVB
RWH
CC Channel Buffer Register
...
TIMERn_CCx_CTRL
RW
CC Channel Control Register
...
TIMERn_CCx_CCV
RWH(a)
CC Channel Value Register
...
TIMERn_CCx_CCVP
R
CC Channel Value Peek Register
...
TIMERn_CCx_CCVB
RWH
CC Channel Buffer Register
0x0A0
TIMERn_DTCTRL
RW
DTI Control Register
0x0A4
TIMERn_DTTIME
RW
DTI Time Control Register
0x0A8
TIMERn_DTFC
RW
DTI Fault Configuration Register
0x0AC
TIMERn_DTOGEN
RW
DTI Output Generation Enable Register
0x0B0
TIMERn_DTFAULT
R
DTI Fault Register
0x0B4
TIMERn_DTFAULTC
W1
DTI Fault Clear Register
0x0B8
TIMERn_DTLOCK
RWH
DTI Configuration Lock Register
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TIMER - Timer/Counter
18.5 Register Description
18.5.1 TIMERn_CTRL - Control Register
0
1
RW 0x0
MODE
2
3
0
RW
SYNC
4
0
RW
OSMEN
5
0
RW
QDM
6
0
RW
DEBUGRUN
7
0
DMACLRACT RW
8
9
RW 0x0
RISEA
10
11
RW 0x0
12
13
FALLA
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0
RW
X2CNT
14
15
16
17
RW 0x0
CLKSEL
18
19
20
21
22
23
24
25
26
RW 0x0
PRESC
27
28
0
30
29
0
RW
Name
ATI
Access
RW
Reset
RSSCOIST
0x000
Bit Position
31
Offset
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TIMER - Timer/Counter
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29
RSSCOIST
0
RW
Description
Reload-Start Sets Compare Ouptut initial State
When set, compare output is set to COIST value at Reload-Start event
28
ATI
0
RW
Always Track Inputs
when set, makes CCPOL always track the polarity of the inputs
27:24
PRESC
0x0
RW
Prescaler Setting
These bits select the prescaling factor.
Value
Mode
Description
0
DIV1
The HFPERCLK is undivided
1
DIV2
The HFPERCLK is divided by 2
2
DIV4
The HFPERCLK is divided by 4
3
DIV8
The HFPERCLK is divided by 8
4
DIV16
The HFPERCLK is divided by 16
5
DIV32
The HFPERCLK is divided by 32
6
DIV64
The HFPERCLK is divided by 64
7
DIV128
The HFPERCLK is divided by 128
8
DIV256
The HFPERCLK is divided by 256
9
DIV512
The HFPERCLK is divided by 512
10
DIV1024
The HFPERCLK is divided by 1024
23:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
17:16
CLKSEL
0x0
RW
Clock Source Select
These bits select the clock source for the timer.
Value
Mode
Description
0
PRESCHFPERCLK
Prescaled HFPERCLK
1
CC1
Compare/Capture Channel 1 Input
2
TIMEROUF
Timer is clocked by underflow(down-count) or overflow(up-count) in the
lower numbered neighbor Timer
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13
X2CNT
0
RW
2x Count Mode
Enable 2x count mode
12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11:10
FALLA
0x0
RW
Timer Falling Input Edge Action
These bits select the action taken in the counter when a falling edge occurs on the input.
Value
Mode
Description
0
NONE
No action
1
START
Start counter without reload
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TIMER - Timer/Counter
Bit
9:8
Name
Reset
Access
2
STOP
Stop counter without reload
3
RELOADSTART
Reload and start counter
RISEA
0x0
Timer Rising Input Edge Action
RW
Description
These bits select the action taken in the counter when a rising edge occurs on the input.
7
Value
Mode
Description
0
NONE
No action
1
START
Start counter without reload
2
STOP
Stop counter without reload
3
RELOADSTART
Reload and start counter
DMACLRACT
0
DMA Request Clear on Active
RW
When this bit is set, the DMA requests are cleared when the corresponding DMA channel is active. This enables the timer
DMA requests to be cleared without accessing the timer.
6
DEBUGRUN
0
RW
Debug Mode Run Enable
Set this bit to enable timer to run in debug mode.
5
Value
Description
0
Timer is frozen in debug mode
1
Timer is running in debug mode
QDM
0
RW
Quadrature Decoder Mode Selection
This bit sets the mode for the quadrature decoder.
4
Value
Mode
Description
0
X2
X2 mode selected
1
X4
X4 mode selected
OSMEN
0
RW
One-shot Mode Enable
RW
Timer Start/Stop/Reload Synchronization
Enable/disable one shot mode.
3
SYNC
0
When this bit is set, the Timer is started/stopped/reloaded by start/stop/reload commands in the other timers
Value
Description
0
Timer is not started/stopped/reloaded by other timers
1
Timer is started/stopped/reloaded by other timers
2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1:0
MODE
0x0
RW
Timer Mode
These bit set the counting mode for the Timer. Note, when Quadrature Decoder Mode is selected (MODE = 'b11), the
CLKSEL is don't care. The Timer is clocked by the Decoder Mode clock output.
Value
Mode
Description
0
UP
Up-count mode
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TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
1
DOWN
Down-count mode
2
UPDOWN
Up/down-count mode
3
QDEC
Quadrature decoder mode
18.5.2 TIMERn_CMD - Command Register
1
0
START W1 0
2
STOP
Access
W1 0
Reset
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x004
Bit Position
31
Offset
Name
Bit
Name
Reset
Access
Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
1
STOP
0
W1
Stop Timer
W1
Start Timer
Set this bit to stop timer
0
START
0
Set this bit to start timer
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TIMER - Timer/Counter
18.5.3 TIMERn_STATUS - Status Register
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0
0
RUNNING R
1
0
R
DIR
2
3
0
R
TOPBV
4
5
6
7
8
R
CCVBV0
0
9
R
CCVBV1
0
10
0
R
CCVBV2
12
11
0
R
CCVBV3
13
14
15
16
R
ICV0
0
17
R
ICV1
0
18
R
ICV2
0
19
0
R
ICV3
20
21
22
23
24
R
CCPOL0
0
25
R
CCPOL1
0
26
R
Name
CCPOL2
0
27
0
R
28
29
Access
CCPOL3
Reset
30
0x008
Bit Position
31
Offset
Preliminary Rev. 0.2 | 593
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
31:28
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
27
CCPOL3
0
R
Description
CC3 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC3_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 3. These bits are cleared when
CCMODE is written to 0b00 (Off).
26
Value
Mode
Description
0
LOWRISE
CC3 polarity low level/rising edge
1
HIGHFALL
CC3 polarity high level/falling edge
CCPOL2
0
R
CC2 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC2_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 2. These bits are cleared when
CCMODE is written to 0b00 (Off).
25
Value
Mode
Description
0
LOWRISE
CC2 polarity low level/rising edge
1
HIGHFALL
CC2 polarity high level/falling edge
CCPOL1
0
R
CC1 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC1_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 1. These bits are cleared when
CCMODE is written to 0b00 (Off).
24
Value
Mode
Description
0
LOWRISE
CC1 polarity low level/rising edge
1
HIGHFALL
CC1 polarity high level/falling edge
CCPOL0
0
R
CC0 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC0_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 0. These bits are cleared when
CCMODE is written to 0b00 (Off).
Value
Mode
Description
0
LOWRISE
CC0 polarity low level/rising edge
1
HIGHFALL
CC0 polarity high level/falling edge
23:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19
ICV3
0
R
CC3 Input Capture Valid
This bit indicates that TIMERn_CC3_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
18
Value
Description
0
TIMERn_CC3_CCV does not contain a valid capture value(FIFO empty)
1
TIMERn_CC3_CCV contains a valid capture value(FIFO not empty)
ICV2
0
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R
CC2 Input Capture Valid
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
This bit indicates that TIMERn_CC2_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
17
Value
Description
0
TIMERn_CC2_CCV does not contain a valid capture value(FIFO empty)
1
TIMERn_CC2_CCV contains a valid capture value(FIFO not empty)
ICV1
0
R
CC1 Input Capture Valid
This bit indicates that TIMERn_CC1_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
16
Value
Description
0
TIMERn_CC1_CCV does not contain a valid capture value(FIFO empty)
1
TIMERn_CC1_CCV contains a valid capture value(FIFO not empty)
ICV0
0
R
CC0 Input Capture Valid
This bit indicates that TIMERn_CC0_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
Value
Description
0
TIMERn_CC0_CCV does not contain a valid capture value(FIFO empty)
1
TIMERn_CC0_CCV contains a valid capture value(FIFO not empty)
15:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
CCVBV3
0
R
CC3 CCVB Valid
This field indicates that the TIMERn_CC3_CCVB registers contain data which have not been written to
TIMERn_CC3_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to
0b00 (Off).
10
Value
Description
0
TIMERn_CC3_CCVB does not contain valid data
1
TIMERn_CC3_CCVB contains valid data which will be written to
TIMERn_CC3_CCV on the next update event
CCVBV2
0
R
CC2 CCVB Valid
This field indicates that the TIMERn_CC2_CCVB registers contain data which have not been written to
TIMERn_CC2_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to
0b00 (Off).
9
Value
Description
0
TIMERn_CC2_CCVB does not contain valid data
1
TIMERn_CC2_CCVB contains valid data which will be written to
TIMERn_CC2_CCV on the next update event
CCVBV1
0
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R
CC1 CCVB Valid
Preliminary Rev. 0.2 | 595
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TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
This field indicates that the TIMERn_CC1_CCVB registers contain data which have not been written to
TIMERn_CC1_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to
0b00 (Off).
8
Value
Description
0
TIMERn_CC1_CCVB does not contain valid data
1
TIMERn_CC1_CCVB contains valid data which will be written to
TIMERn_CC1_CCV on the next update event
CCVBV0
0
R
CC0 CCVB Valid
This field indicates that the TIMERn_CC0_CCVB registers contain data which have not been written to
TIMERn_CC0_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to
0b00 (Off).
Value
Description
0
TIMERn_CC0_CCVB does not contain valid data
1
TIMERn_CC0_CCVB contains valid data which will be written to
TIMERn_CC0_CCV on the next update event
7:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
TOPBV
0
R
TOPB Valid
This indicates that TIMERn_TOPB contains valid data that has not been written to TIMERn_TOP. This bit is also cleared
when TIMERn_TOP is written.
1
Value
Description
0
TIMERn_TOPB does not contain valid data
1
TIMERn_TOPB contains valid data which will be written to
TIMERn_TOP on the next update event
DIR
0
R
Direction
Indicates count direction.
0
Value
Mode
Description
0
UP
Counting up
1
DOWN
Counting down
RUNNING
0
R
Running
Indicates if timer is running or not.
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TIMER - Timer/Counter
18.5.4 TIMERn_IF - Interrupt Flag Register
Access
Name
Reset
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
ICBOF3
0
0
0
R
OF
1
0
R
2
UF
Bit
R
3
0
DIRCHG R
4
0
R
CC0
5
0
R
CC1
6
R
CC2
0
7
R
CC3
0
8
R
ICBOF0
0
9
R
ICBOF1
0
10
0
R
ICBOF2
Name
R
Access
ICBOF3
0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x00C
Bit Position
31
Offset
Description
CC Channel 3 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of TIMERn_CC3_CCVB.
10
ICBOF2
0
R
CC Channel 2 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of TIMERn_CC2_CCVB.
9
ICBOF1
0
R
CC Channel 1 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of TIMERn_CC1_CCVB.
8
ICBOF0
0
R
CC Channel 0 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of TIMERn_CC0_CCVB.
7
CC3
0
R
CC Channel 3 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 3.
6
CC2
0
R
CC Channel 2 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 2.
5
CC1
0
R
CC Channel 1 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 1.
4
CC0
0
R
CC Channel 0 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 0.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
DIRCHG
0
R
Direction Change Detect Interrupt Flag
This bit is set when count direction changes. Set only in Quadrature Decoder mode
1
UF
0
R
Underflow Interrupt Flag
This bit indicates that there has been an underflow.
0
OF
0
R
Overflow Interrupt Flag
This bit indicates that there has been an overflow.
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TIMER - Timer/Counter
18.5.5 TIMERn_IFS - Interrupt Flag Set Register
Access
Bit
Name
Reset
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
ICBOF3
0
1
W1 0
W1 0
UF
OF
0
2
3
DIRCHG W1 0
4
W1 0
CC0
5
W1 0
CC1
6
W1 0
CC2
7
W1 0
CC3
8
W1 0
ICBOF0
9
W1 0
ICBOF1
10
W1 0
ICBOF2
Name
11
12
Access
W1 0
Reset
ICBOF3
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x010
Bit Position
31
Offset
Description
W1
Set ICBOF3 Interrupt Flag
W1
Set ICBOF2 Interrupt Flag
W1
Set ICBOF1 Interrupt Flag
W1
Set ICBOF0 Interrupt Flag
W1
Set CC3 Interrupt Flag
W1
Set CC2 Interrupt Flag
W1
Set CC1 Interrupt Flag
W1
Set CC0 Interrupt Flag
Write 1 to set the ICBOF3 interrupt flag
10
ICBOF2
0
Write 1 to set the ICBOF2 interrupt flag
9
ICBOF1
0
Write 1 to set the ICBOF1 interrupt flag
8
ICBOF0
0
Write 1 to set the ICBOF0 interrupt flag
7
CC3
0
Write 1 to set the CC3 interrupt flag
6
CC2
0
Write 1 to set the CC2 interrupt flag
5
CC1
0
Write 1 to set the CC1 interrupt flag
4
CC0
0
Write 1 to set the CC0 interrupt flag
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
DIRCHG
0
W1
Set DIRCHG Interrupt Flag
Write 1 to set the DIRCHG interrupt flag
1
UF
0
W1
Set UF Interrupt Flag
W1
Set OF Interrupt Flag
Write 1 to set the UF interrupt flag
0
OF
0
Write 1 to set the OF interrupt flag
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TIMER - Timer/Counter
18.5.6 TIMERn_IFC - Interrupt Flag Clear Register
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1
(R)W1 0
(R)W1 0
UF
OF
0
2
3
DIRCHG (R)W1 0
4
(R)W1 0
CC0
5
(R)W1 0
CC1
6
(R)W1 0
CC2
7
(R)W1 0
CC3
8
(R)W1 0
ICBOF0
9
(R)W1 0
ICBOF1
10
(R)W1 0
12
13
14
15
16
17
18
19
20
21
11
ICBOF2
Name
(R)W1 0
Access
ICBOF3
Reset
22
23
24
25
26
27
28
29
30
0x014
Bit Position
31
Offset
Preliminary Rev. 0.2 | 599
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
ICBOF3
0
(R)W1
Description
Clear ICBOF3 Interrupt Flag
Write 1 to clear the ICBOF3 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
10
ICBOF2
0
(R)W1
Clear ICBOF2 Interrupt Flag
Write 1 to clear the ICBOF2 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
9
ICBOF1
0
(R)W1
Clear ICBOF1 Interrupt Flag
Write 1 to clear the ICBOF1 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
8
ICBOF0
0
(R)W1
Clear ICBOF0 Interrupt Flag
Write 1 to clear the ICBOF0 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
7
CC3
0
(R)W1
Clear CC3 Interrupt Flag
Write 1 to clear the CC3 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
6
CC2
0
(R)W1
Clear CC2 Interrupt Flag
Write 1 to clear the CC2 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
5
CC1
0
(R)W1
Clear CC1 Interrupt Flag
Write 1 to clear the CC1 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
4
CC0
0
(R)W1
Clear CC0 Interrupt Flag
Write 1 to clear the CC0 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
DIRCHG
0
(R)W1
Clear DIRCHG Interrupt Flag
Write 1 to clear the DIRCHG interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
1
UF
0
(R)W1
Clear UF Interrupt Flag
Write 1 to clear the UF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
0
OF
0
(R)W1
Clear OF Interrupt Flag
Write 1 to clear the OF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This
feature must be enabled globally in MSC.).
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TIMER - Timer/Counter
18.5.7 TIMERn_IEN - Interrupt Enable Register
Access
Bit
Name
Reset
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
11
ICBOF3
0
1
RW 0
RW 0
UF
OF
0
2
3
DIRCHG RW 0
4
RW 0
CC0
5
RW 0
CC1
6
RW 0
CC2
7
RW 0
CC3
8
RW 0
ICBOF0
9
RW 0
ICBOF1
10
RW 0
ICBOF2
Name
11
12
Access
RW 0
Reset
ICBOF3
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x018
Bit Position
31
Offset
Description
RW
ICBOF3 Interrupt Enable
RW
ICBOF2 Interrupt Enable
RW
ICBOF1 Interrupt Enable
RW
ICBOF0 Interrupt Enable
RW
CC3 Interrupt Enable
RW
CC2 Interrupt Enable
RW
CC1 Interrupt Enable
RW
CC0 Interrupt Enable
Enable/disable the ICBOF3 interrupt
10
ICBOF2
0
Enable/disable the ICBOF2 interrupt
9
ICBOF1
0
Enable/disable the ICBOF1 interrupt
8
ICBOF0
0
Enable/disable the ICBOF0 interrupt
7
CC3
0
Enable/disable the CC3 interrupt
6
CC2
0
Enable/disable the CC2 interrupt
5
CC1
0
Enable/disable the CC1 interrupt
4
CC0
0
Enable/disable the CC0 interrupt
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
DIRCHG
0
RW
DIRCHG Interrupt Enable
RW
UF Interrupt Enable
RW
OF Interrupt Enable
Enable/disable the DIRCHG interrupt
1
UF
0
Enable/disable the UF interrupt
0
OF
0
Enable/disable the OF interrupt
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TIMER - Timer/Counter
18.5.8 TIMERn_TOP - Counter Top Value Register
3
2
1
0
3
2
1
0
4
5
6
7
8
TOP RWH 0xFFFF
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x01C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
TOP
0xFFFF
RWH
Description
Counter Top Value
These bits hold the TOP value for the counter.
18.5.9 TIMERn_TOPB - Counter Top Value Buffer Register
4
5
6
7
8
TOPB RW 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x020
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
TOPB
0x0000
RW
Description
Counter Top Value Buffer
These bits hold the TOP buffer value.
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TIMER - Timer/Counter
18.5.10 TIMERn_CNT - Counter Value Register
3
2
1
0
3
2
1
0
4
5
6
7
8
CNT RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x024
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
CNT
0x0000
RWH
Description
Counter Value
These bits hold the counter value.
18.5.11 TIMERn_LOCK - TIMER Configuration Lock Register
4
5
6
7
8
TIMERLOCKKEY RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x02C
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
TIMERLOCKKEY
0x0000
RWH
Description
Timer Lock Key
Write any other value than the unlock code to lock TIMERn_CTRL, TIMERn_CMD, TIMERn_TOP, TIMERn_CNT,
TIMERn_CCx_CTRL and TIMERn_CCx_CCV from editing. Write the unlock code to unlock. When reading the register, bit
0 is set when the lock is enabled.
Mode
Value
Description
UNLOCKED
0
TIMER registers are unlocked
LOCKED
1
TIMER registers are locked
LOCK
0
Lock TIMER registers
UNLOCK
0xCE80
Unlock TIMER registers
Read Operation
Write Operation
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
18.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register
Access
Bit
Name
Reset
31:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
10
CDTI2PEN
0
RW
0
RW 0
CC0PEN
1
RW 0
CC1PEN
2
RW 0
CC2PEN
3
RW 0
CC3PEN
4
5
6
8
CDTI0PEN RW 0
7
9
CDTI1PEN RW 0
Name
10
Access
CDTI2PEN RW 0
Reset
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x030
Bit Position
31
Offset
Description
CC Channel 2 Complementary Dead-Time Insertion Pin Enable
Enable/disable CC channel 2 complementary dead-time insertion output connection to pin.
9
CDTI1PEN
0
RW
CC Channel 1 Complementary Dead-Time Insertion Pin Enable
Enable/disable CC channel 1 complementary dead-time insertion output connection to pin.
8
CDTI0PEN
0
RW
CC Channel 0 Complementary Dead-Time Insertion Pin Enable
Enable/disable CC channel 0 complementary dead-time insertion output connection to pin.
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
3
CC3PEN
0
RW
CC Channel 3 Pin Enable
Enable/disable CC channel 3 output/input connection to pin.
2
CC2PEN
0
RW
CC Channel 2 Pin Enable
Enable/disable CC channel 2 output/input connection to pin.
1
CC1PEN
0
RW
CC Channel 1 Pin Enable
Enable/disable CC channel 1 output/input connection to pin.
0
CC0PEN
0
RW
CC Channel 0 Pin Enable
Enable/disable CC Channel 0 output/input connection to pin.
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
18.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register
0
1
2
3
CC0LOC RW 0x00
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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CC1LOC RW 0x00
Name
CC2LOC RW 0x00
Access
CC3LOC RW 0x00
Reset
30
0x034
Bit Position
31
Offset
Preliminary Rev. 0.2 | 605
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
31:30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:24
CC3LOC
0x00
RW
Description
I/O Location
Decides the location of the CC3 pin.
23:22
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
21:16
CC2LOC
0x00
RW
I/O Location
Decides the location of the CC2 pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
CC1LOC
0x00
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RW
I/O Location
Preliminary Rev. 0.2 | 607
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
Decides the location of the CC1 pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
CC0LOC
0x00
RW
I/O Location
Decides the location of the CC0 pin.
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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Access
Description
Preliminary Rev. 0.2 | 609
EFM32JG1 Reference Manual
TIMER - Timer/Counter
18.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register
silabs.com | Smart. Connected. Energy-friendly.
0
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5
CDTI0LOC RW 0x00
Name
CDTI1LOC RW 0x00
Access
CDTI2LOC RW 0x00
Reset
22
23
24
25
26
27
28
29
30
0x03C
Bit Position
31
Offset
Preliminary Rev. 0.2 | 610
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
31:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
21:16
CDTI2LOC
0x00
RW
Description
I/O Location
Decides the location of the CDTI2 pin.
15:14
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
13:8
CDTI1LOC
0x00
RW
I/O Location
Decides the location of the CDTI1 pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
5:0
CDTI0LOC
0x00
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RW
I/O Location
Preliminary Rev. 0.2 | 612
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
Description
Decides the location of the CDTI0 pin.
Value
Mode
Description
0
LOC0
Location 0
1
LOC1
Location 1
2
LOC2
Location 2
3
LOC3
Location 3
4
LOC4
Location 4
5
LOC5
Location 5
6
LOC6
Location 6
7
LOC7
Location 7
8
LOC8
Location 8
9
LOC9
Location 9
10
LOC10
Location 10
11
LOC11
Location 11
12
LOC12
Location 12
13
LOC13
Location 13
14
LOC14
Location 14
15
LOC15
Location 15
16
LOC16
Location 16
17
LOC17
Location 17
18
LOC18
Location 18
19
LOC19
Location 19
20
LOC20
Location 20
21
LOC21
Location 21
22
LOC22
Location 22
23
LOC23
Location 23
24
LOC24
Location 24
25
LOC25
Location 25
26
LOC26
Location 26
27
LOC27
Location 27
28
LOC28
Location 28
29
LOC29
Location 29
30
LOC30
Location 30
31
LOC31
Location 31
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EFM32JG1 Reference Manual
TIMER - Timer/Counter
18.5.15 TIMERn_CCx_CTRL - CC Channel Control Register
silabs.com | Smart. Connected. Energy-friendly.
0
1
RW 0x0
MODE
3
2
0
RW
OUTINV
4
0
RW
COIST
5
6
7
8
9
RW 0x0
CMOA
10
11
RW 0x0
COFOA
12
13
RW 0x0
CUFOA
14
15
16
17
18
RW 0x0
PRSSEL
19
20
21
22
23
24
25
RW 0x0
ICEDGE
26
27
ICEVCTRL RW 0x0
28
0
PRSCONF RW
29
30
0
0
RW
Name
RW
Access
INSEL
Reset
FILT
0x060
Bit Position
31
Offset
Preliminary Rev. 0.2 | 614
EFM32JG1 Reference Manual
TIMER - Timer/Counter
Bit
Name
Reset
Access
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
30
FILT
0
RW
Description
Digital Filter
Enable digital filter.
29
Value
Mode
Description
0
DISABLE
Digital filter disabled
1
ENABLE
Digital filter enabled
INSEL
0
RW
Input Selection
Select Compare/Capture channel input.
28
Value
Mode
Description
0
PIN
TIMERnCCx pin is selected
1
PRS
PRS input (selected by PRSSEL) is selected
PRSCONF
0
RW
PRS Configuration
Select PRS pulse or level.
27:26
Value
Mode
Description
0
PULSE
Each CC event will generate a one HFPERCLK cycle high pulse
1
LEVEL
The PRS channel will follow CC out
ICEVCTRL
0x0
RW
Input Capture Event Control
These bits control when a Compare/Capture PRS output pulse and interrupt flag is set. DMA request however is set on
every capture.
25:24
Value
Mode
Description
0
EVERYEDGE
PRS output pulse and interrupt flag set on every capture
1
EVERYSECONDEDGE
PRS output pulse and interrupt flag set on every second capture
2
RISING
PRS output pulse and interrupt flag set on rising edge only (if ICEDGE
= BOTH)
3
FALLING
PRS output pulse and interrupt flag set on falling edge only (if ICEDGE
= BOTH)
ICEDGE
0x0
RW
Input Capture Edge Select
These bits control which edges the edge detector triggers on. The output is used for input capture and external clock input.
Value
Mode
Description
0
RISING
Rising edges detected
1
FALLING
Falling edges detected
2
BOTH
Both edges detected
3
NONE
No edge detection, signal is left as it is
23:20
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
19:16
PRSSEL
0x0
RW
Compare/Capture Channel PRS Input Channel Selection
Select PRS input channel for Compare/Capture channel.
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TIMER - Timer/Counter
Bit
Name
Reset
Access
Value
Mode
Description
0
PRSCH0
PRS Channel 0 selected as input
1
PRSCH1
PRS Channel 1 selected as input
2
PRSCH2
PRS Channel 2 selected as input
3
PRSCH3
PRS Channel 3 selected as input
4
PRSCH4
PRS Channel 4 selected as input
5
PRSCH5
PRS Channel 5 selected as input
6
PRSCH6
PRS Channel 6 selected as input
7
PRSCH7
PRS Channel 7 selected as input
8
PRSCH8
PRS Channel 8 selected as input
9
PRSCH9
PRS Channel 9 selected as input
10
PRSCH10
PRS Channel 10 selected as input
11
PRSCH11
PRS Channel 11 selected as input
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:12
CUFOA
0x0
RW
Description
Counter Underflow Output Action
Select output action on counter underflow.
11:10
Value
Mode
Description
0
NONE
No action on counter underflow
1
TOGGLE
Toggle output on counter underflow
2
CLEAR
Clear output on counter underflow
3
SET
Set output on counter underflow
COFOA
0x0
RW
Counter Overflow Output Action
Select output action on counter overflow.
9:8
Value
Mode
Description
0
NONE
No action on counter overflow
1
TOGGLE
Toggle output on counter overflow
2
CLEAR
Clear output on counter overflow
3
SET
Set output on counter overflow
CMOA
0x0
RW
Compare Match Output Action
Select output action on compare match.
Value
Mode
Description
0
NONE
No action on compare match
1
TOGGLE
Toggle output on compare match
2
CLEAR
Clear output on compare match
3
SET
Set output on compare match
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TIMER - Timer/Counter
Bit
Name
Reset
Access
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
4
COIST
0
RW
Description
Compare Output Initial State
This bit is only used in Output Compare and PWM mode. When this bit is set in Compare or PWM mode,the output is set
high when the counter is disabled. When counting resumes, this value will represent the initial value for the output. If the bit
is cleared, the output will be cleared when the counter is disabled.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
2
OUTINV
0
RW
Output Invert
Setting this bit inverts the output from the CC channel (Output compare,PWM).
1:0
MODE
0x0
RW
CC Channel Mode
These bits select the mode for Compare/Capture channel.
Value
Mode
Description
0
OFF
Compare/Capture channel turned off
1
INPUTCAPTURE
Input capture
2
OUTPUTCOMPARE
Output compare
3
PWM
Pulse-Width Modulation
18.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads)
0
1
2
3
4
5
6
7
8
CCV RWH 0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0x064
Bit Position
31
Offset
Reset
Access
Name
Bit
Name
Reset
Access
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
15:0
CCV
0x0000
RWH
Description
CC Channel Value
In input capture mode, this field holds the first unread capture value. When reading this register in input capture mode, the
contents of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle. In compare mode, this
fields holds the compare value.
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TIMER - Timer/Counter
18.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register
3
2
1
0
3
2
1
0
4
5
6
7
8
0x0000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
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