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ISO8200B
Galvanic isolated octal high-side smart power solid state relay
Datasheet - production data
• IEC 61000-4-2, IEC 61000-4-4, IEC 61000-4-5
and IEC 61000-4-8 compliant
Applications
• Programmable logic control
• Industrial PC peripheral input/output
PowerSO-36
• Numerical control machines
• Drivers for all types of loads (resistive,
capacitive, inductive)
Features
Type
Vdemag(1)
ISO8200B Vcc- 45 V
RDS(on)(1) IOUT(1)
0.11 Ω
0.7 A
Vcc
The ISO8200B is a galvanic isolated 8-channel
driver featuring a very low supply current. It
contains 2 independent galvanic isolated voltage
domains (Vcc for the Power stage and Vdd for the
Digital stage). Additional embedded functions are:
loss of GND protection, undervoltage shutdown
with hysteresis, and reset function for immediate
power output shutdown.
1. Per channel
• Parallel input interface
• Direct and synchronous control mode
• High common mode transient immunity
• Output current: 0.7 A per channel
• Short-circuit protection
• Channel overtemperature protection
• Thermal independence of separate channels
• Common output disable pin
• Case overtemperature protection
• Loss of GNDcc and Vcc protection
• Undervoltage shutdown with auto restart and
hysteresis
• Overvoltage protection (Vcc clamping)
• Very low supply current
• Common fault open drain output
• 5 V and 3.3 V TTL/CMOS compatible I/Os
• Fast demagnetization of inductive loads
• Reset function for IC outputs disable
• ESD protection
April 2014
This is information on a product in full production.
Description
45 V
The IC is intended to drive any kind of load with
one side connected to ground. Active channel
current limitation combined with thermal
shutdown, (independent for each channel), and
automatic restart, protect the device against
overload and short-circuit. In overload conditions,
if junction temperature overtakes threshold, the
channel involved is turned off and on again
automatically after the IC temperature decreases
below a reset threshold. If this condition causes
case temperature to reach limit threshold TCR,
the overloaded channel is turned off and it only
restarts when case and junction temperature
decrease down to the reset thresholds. Nonoverloaded channels continue operating normally.
An internal circuit provides an OR-wired not
latched common FAULT indicator signaling the
channel OVT. The FAULT pin is an open drain
active low fault indication pin.
DocID023802 Rev 9
1/35
www.st.com
35
Contents
ISO8200B
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.1
Input signals (IN1 to IN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.2
Load input data (LOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.3
Output synchronization (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.4
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.5
Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Direct control mode (DCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
Synchronous control mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
Fault indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1
7
Junction overtemperature and case overtemperature . . . . . . . . . . . . . . 22
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
Reverse polarity on Vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.1
11
2/35
Supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . 29
Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DocID023802 Rev 9
ISO8200B
Contents
11.1
Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID023802 Rev 9
3/35
List of tables
ISO8200B
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
4/35
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Diagnostic pin and output protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power switching characteristics (VCC = 24 V; -40 °C < TJ < 125 °C) . . . . . . . . . . . . . . . . 12
Logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Parallel interface timings (Vdd = 5 V; Vcc= 24 V; -40 °C < TJ < 125 °C) . . . . . . . . . . . . . . . 14
IEC 60747-5-2 insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interface signal operation (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interface signal operation in direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interface signal operation in synchronous control mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PowerSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Footprint data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID023802 Rev 9
ISO8200B
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RDS(on) measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
dV/dT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
td(ON)-td(OFF) synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
td(ON)-td(OFF) direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output channel enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Direct control mode IC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Direct control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Synchronous control mode IC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronous control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiple device synchronous control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal status update (DCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal status update (SCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Current limitation with different load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal protection flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reverse polarity protection on Vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Simplified thermal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSO-36 mechanical drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Footprint recommended data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID023802 Rev 9
5/35
Block diagram
1
ISO8200B
Block diagram
Figure 1. Block diagram
Vdd
Power
management
Undervoltage
detection
Vcc
Vcc clamp
SYNC
LOAD
OUT_EN
IN1
Output clamp
Logic
Logic
OUTi
Current limit
Junction temperature
detection
FAULT
GNDdd
Rpd
IN8
Case temperature
detection
GNDcc
AM14889v1
6/35
DocID023802 Rev 9
ISO8200B
2
Pin connection
Pin connection
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin
Name
Description
1
NC
Not connected
2
Vdd
Positive logic supply
3
OUT_EN
4
SYNC
Chip select
5
LOAD
Load input data
6
IN1
Channel 1 input
7
IN2
Channel 2 input
8
IN3
Channel 3 input
9
IN4
Channel 4 input
10
IN5
Channel 5 input
11
IN6
Channel 6 input
12
IN7
Channel 7 input
13
IN8
Channel 8 input
14
FAULT
Common fault indication - active low
15
GNDdd
Input logic ground, negative logic supply
16
NC
Output enable
Not connected
DocID023802 Rev 9
7/35
Pin connection
ISO8200B
Table 1. Pin description (continued)
8/35
Pin
Name
Description
17
NC
Not connected
18
NC
Not connected
19
GNDcc
20
NC
21
OUT8
Channel 8 power output
22
OUT8
Channel 8 power output
23
OUT7
Channel 7 power output
24
OUT7
Channel 7 power output
25
OUT6
Channel 6 power output
26
OUT6
Channel 6 power output
27
OUT5
Channel 5 power output
28
OUT5
Channel 5 power output
29
OUT4
Channel 4 power output
30
OUT4
Channel 4 power output
31
OUT3
Channel 3 power output
32
OUT3
Channel 3 power output
33
OUT2
Channel 2 power output
34
OUT2
Channel 2 power output
35
OUT1
Channel 1 power output
36
OUT1
Channel 1 power output
TAB
TAB
Output power ground
Not connected
Exposed tab internally connected to Vcc, positive power
supply voltage
DocID023802 Rev 9
ISO8200B
3
Absolute maximum ratings
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
VCC
Power supply voltage
-0.3
45
V
Vdd
Digital supply voltage
-0.3
6.5
V
VIN
DC input pins, Id and output enable voltage
-0.3
+6.5
V
VFAULT
Fault voltage
-0.3
+6.5
V
IGNDdd
DC digital ground reverse current
-25
mA
Internally
limited
A
-250
mA
-5
A
IOUT
IGNDcc
Channel output current (continuous)
DC power ground reverse current
IR
Reverse output current (per channel)
IIN
DC input pins, ld and output enable current
-10
+ 10
mA
IFAULT
Fault current
-10
+ 10
mA
VESD
Electrostatic discharge with human body model
(R = 1.5 KΩ; C = 100 pF)
2000
V
Single pulse avalanche energy per channel not
simultaneously @Tamb= 125 °C, IOUT = 0.5 A
0.9
Single pulse avalanche energy per channel, all
channels driven simultaneously @Tamb= 125 °C,
IOUT = 0.5 A
0.2
EAS
J
PTOT
Power dissipation at Tc = 25 °C
Internally
limited(1)
W
TJ
Junction operating temperature
Internally
limited(1)
°C
Storage temperature
-55 to 150
°C
TSTG
1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for
continuous operation. Continuous or repetitive operations of protection functions may reduce the IC
lifetime.
DocID023802 Rev 9
9/35
Thermal data
4
ISO8200B
Thermal data
Table 3. Thermal data
Symbol
Rthj-case
Rthj-amb
Parameter
Max. value
Unit
1.3
°C/W
15
°C/W
Thermal resistance, junction-case(1)
(2)
Thermal resistance, junction-ambient
1. For each channel.
2.
5
PSSO36 mounted on the product evaluation board STEVAL-IFP015V2 (FR4, 4 layers, 8 cm2 for each
layer, copper thickness 35 μm.
Electrical characteristics
(10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C, unless otherwise specified).
Table 4. Power section
Symbol
Parameter
Vcc(under)THON
Vcc undervoltage turn-ON
threshold
Vcc(under)THOFF
Vcc undervoltage turnOFF threshold
Test conditions
Vcc(hys)
Vcc undervoltage
hysteresis
Vccclamp
Clamp on Vcc pin
Iclamp = 20 mA
RDS(on)
On-state resistance (1)
IOUT = 0.5 A, TJ = 25 °C
IOUT = 0.5 A TJ = 125 °C
Typ.
Max. Unit
9.5
10.5
V
9
V
0.35
0.5
V
45
50
52
V
0.24
Ω
Ω
0.12
210
kΩ
5
9
mA
mA
Rpd
Output pull-down resistor
Icc
Power supply current
All channels in OFF state
All channels in ON state
ILGND
Ground disconnection
output current
Vcc= VGND =0 V VOUT= 24 V
500
µA
VOUT(OFF)
Off-state output voltage
Channel OFF and IOUT = 0
A
1
V
IOUT(OFF)
Off-state output current
Channel OFF and VOUT =
0V
5
µA
1. See Figure 3.
10/35
Min.
DocID023802 Rev 9
ISO8200B
Electrical characteristics
Table 5. Digital supply voltage
Symbol
Parameter
Vdd(under)
Vdd undervoltage protection
turn-OFF threshold
Vdd(hys)
Vdd undervoltage hysteresis
Idd
Idd supply current
Test conditions
Min.
Typ.
Max.
Unit
2.8
2.9
3
V
0.1
V
Vdd = 5 V and input
channel with a steady
logic level
4.5
6
mA
Vdd = 3.3 V and input
channel with a steady
logic level
4.4
5.9
mA
Table 6. Diagnostic pin and output protection function
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VFAULT
FAULT pin open drain
voltage output low
IFAULT = 10 mA
0.4
V
ILFAULT
FAULT output leakage
current
VFAULT = 5 V
1
µA
IPEAK
Maximum DC output
current before limitation
1.4
ILIM
Short-circuit current
limitation
RLOAD = 0 Ω
Hyst
ILIM tracking limits
RLOAD = 0 Ω
TJSD
Junction shutdown
temperature
TJR
0.7
1.1
A
1.7
A
0.3
A
170
°C
Junction reset temperature
150
°C
THIST
Junction thermal
hysteresis
20
°C
TCSD
Case shutdown
temperature
TCR
Case reset temperature
110
°C
TCHYST Case thermal hysteresis
20
°C
Vdemag
150
115
Output voltage at turn-OFF IOUT = 0.5 A; ILOAD > = 1 mH Vcc-45
DocID023802 Rev 9
130
Vcc-50
145
Vcc-52
°C
V
11/35
Electrical characteristics
ISO8200B
Table 7. Power switching characteristics (VCC = 24 V; -40 °C < TJ < 125 °C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
dV/dt(ON)
Turn-ON voltage slope
IOUT = 0.5 A, resistive
load 48 Ω
-
5.6
-
V/µs
dV/dt(OFF)
= 0.5 A, resistive
I
Turn-OFF voltage slope OUT
load 48 Ω
-
2.81
-
V/µs
td(ON)
Turn-ON delay time(1)
IOUT = 0.5 A, resistive
load 48 Ω
-
17
22
µs
td(OFF)
Turn-OFF delay time (1)
IOUT = 0.5 A, resistive
load 48 Ω
-
22
40
µs
tf
Fall time (1)
IOUT = 0.5 A, resistive
load 48 Ω
-
5
-
µs
tr
Rise time (1)
IOUT = 0.5 A, resistive
load 48 Ω
-
5
-
µs
1. See Figure 4, Figure 5, and Figure 6.
Figure 3. RDS(on) measurement
TAB Vcc
VRDS(on)
Load
AM14891v1
12/35
DocID023802 Rev 9
ISO8200B
Electrical characteristics
Figure 4. dV/dT
Figure 5. td(ON)-td(OFF) synchronous mode
Sync
SCM
50%
90%
t
80%
td(OFF)
dV (ON)
Vout
dV (OFF)
Vout
90%
10%
tr
t
tf
10%
AM14892v1
t
td(ON)
AM14893v1
Figure 6. td(ON)-td(OFF) direct control mode
In(i)
DCM
50%
t
Vout
90%
10%
td(ON)
t
td(OFF)
AM14894v1
Table 8. Logic input and output
Symbol
Parameter
VIL
Logic input, LOAD and
OUT_EN low level voltage
VIH
Logic input, LOAD and
OUT_EN high level
voltage
VI(HYST)
Logic input, LOAD and
OUT_EN hysteresis
voltage
Vdd = 5 V
IIN
Logic input, LOAD and
OUT_EN current
VIN = 5 V
tWM
Test conditions
Power side watchdog time
DocID023802 Rev 9
Min.
Typ.
Max.
Unit
-0.3
0.3 x Vdd
V
0.7 x Vdd
Vdd+0.3
V
100
mV
10
272
µA
320
400
µs
13/35
Electrical characteristics
ISO8200B
Table 9. Parallel interface timings (Vdd = 5 V; Vcc= 24 V; -40 °C < TJ < 125 °C)
Symbol
Parameter
tdis(SYNC)
SYNC disable
time
Sync. control mode
10
µs
tdis(DCM)
SYNC LOAD
disable time
Direct control mode
80
ns
tw(SYNC)
SYNC negative
pulse width
Sync. control mode
20
tsu(LOAD)
LOAD setup time
Sync. control mode
80
ns
th(LOAD)
LOAD hold time
Sync. control mode
400
ns
tw(LOAD)
LOAD pulse width Sync. control mode
240
ns
tsu(IN)
Input setup time
80
ns
th(IN)
Input hold time
10
ns
Sync. control mode
160
ns
tw(IN)
Input pulse width
Direct control mode
20
µs
tINLD
IN to LOAD time
Direct control mode
From IN variation to LOAD falling
edge
80
ns
tLDIN
LOAD to IN time
Direct control mode
From LOAD falling edge to IN
variation
400
ns
tw(OUT_EN)
OUT_EN pulse
width
150
ns
tp(OUT_EN)
OUT_EN
propagation
delay
tjitter(SCM)
tjitter(DCM)
frefresh
14/35
Jitter on single
channel
Test conditions
Min.
Typ.
Max. Unit
195
22
40
Sync. mode
6
Direct mode
20
µs
µs
µs
Refresh delay
15
DocID023802 Rev 9
kHz
ISO8200B
Electrical characteristics
Table 10. IEC 60747-5-2 insulation characteristics
Symbol
CTI
VISO
VPR
Parameter
Test conditions
Value
Unit
V
Comparative tracking index
(tracking resistance)
DIN IEC 112/VDE 0303 part 1
≥ 400
Isolation group
Material group (DIN VDE 0110,
1/89, table 1
II
Isolation voltage per UL 1577
100% production
VTEST = 1.2 x VISO=1644 V,
t=1s
1370
VPEAK
100% production test
method b, tm = 1 s
partial discharge < 5 pC
1644
VPEAK
Characterization test
method a, tm = 10 s
partial discharge < 5 pC
1315
VPEAK
3500
VPEAK
Input-to-output test voltage as
per IEC 60747-5-2
VIOTM
Transient overvoltage as per
IEC 60747-5-2
Characterization test
VTEST = 1.2 x VIOTM,
t = 60 s
CLR
Clearance (minimum external
air gap)
Measured from input terminals
to output terminals, the
shortest distance through air
2.6
mm
CPG
Creepage (minimum external
tracking)
Measured from input terminals
to output terminals, the
shortest distance path analog
body
2.6
mm
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Functional description
ISO8200B
6
Functional description
6.1
Parallel interface
Smart parallel interface built-in ISO8200B offers three interfacing signals easily managed by
a microcontroller.
The LOAD signal enables the input buffer storing the value of the channel inputs.
The SYNC signal copies the input buffer value into the transmission buffer and manages the
synchronization between low voltage side and the channel outputs on the isolated side.
The OUT_EN signal enables the channel outputs.
An internal refresh signal updates the configuration of the channel outputs with a frefresh
frequency. This signal can be disabled forcing low the SYNC input when LOAD is high.
SYNC and LOAD pins can be in direct control mode (DCM) or synchronous control mode
(SCM).
The operation of these two signals is described as follows:
Table 11. Interface signal operation (general)
LOAD
SYNC
OUT_EN
Device behavior
Don’t care
Don’t care
Low(1)
High
High
High
The outputs are left unchanged
Low
High
High
The input buffer is enabled
The outputs are left unchanged
High
Low
High
The internal refresh signal is disabled
The transmission buffer is updated
The outputs are left unchanged
Low
Low
High
The device operates in direct control mode as
described in the respective paragraph
The outputs are disabled (turned off)
1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.
6.1.1
Input signals (IN1 to IN8)
Inputs from IN1 to IN8 are the driving signals of the corresponding OUT1 to OUT8 outputs.
Data are direct loaded on related outputs if SYNC and LOAD inputs are low (DCM
operation) or stored into input buffer when LOAD is low and SYNC is high.
6.1.2
Load input data (LOAD)
The input is active low; it stores the data from IN1 to IN8 into the input buffer.
6.1.3
Output synchronization (SYNC)
The input is active low; it enables the ISO8200B transmission buffer loading input buffer
data and manages the transmission between the two isolated sides of the device.
16/35
DocID023802 Rev 9
ISO8200B
6.1.4
Functional description
Watchdog
The isolated side of the device provides a watchdog function in order to guarantee a safe
condition when Vdd supply voltage is missing.
If the logic side does not update the output status within tWD, all outputs are disabled until a
new update request is received.
The refresh signal is also considered a valid update signal, so the isolated side watchdog
does not protect the system from a failure of the host controller (MCU freezing).
Figure 7. Watchdog behavior
Vdd
______
SYNCH
Don’t Care
_____
LOAD
Don’t Care
D0…D7
A
B
Don’t Care
C
C
REFRESH
SKIPPED
If the isolated side does not
receive an update request
within the watchdog timeout
all outputs are turned OFF
OUT0…OUT7
A
B
!
Outputs are kept
OFF until an update
request is received
C
C
Timeout
Counter
Any update request
Resets the watchdog counter
IPG1912131338LM
6.1.5
Output enable (OUT_EN)
This pin provides a fast way to disable all outputs simultaneously. When the OUT_EN pin is
driven low the outputs are disabled. To enable the output stage, the OUT_EN pin has to be
raised. This timing execution is compatible with an external reset push, safety requirement,
and allows, in a PLC system, the microcontroller polling to obtain all internal information
during a reset procedure.
Figure 8. Output channel enable timing
OUT_EN
tw(OUT_EN)
t
OUTx
t
tp(OUT_EN)
DocID023802 Rev 9
AM14896v1
17/35
Functional description
6.2
ISO8200B
Direct control mode (DCM)
When SYNC and LOAD inputs are driven by the same signal, the device operates in direct
control mode (DCM).
In DCM the SYNC / LOAD signal operates as an active low input enable:
•
when the signal is high, the current output configuration is kept regardless the input
values
•
when the signal is low, each channel input directly drives the respective output
This operation mode can also be set shorting both signals to the digital ground; in this case
the channel outputs are always directly driven by the inputs except when OUT_EN is low
(outputs disabled).
Table 12. Interface signal operation in direct control mode
SYNC / LOAD
OUT_EN
Device behavior
Don’t care
Low(1)
High
High
The outputs are left unchanged
Low
High
The channel inputs drive the outputs
The outputs are disabled (turned off)
1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.
Figure 9. Direct control mode IC configuration
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
OUT_EN
OUT_EN
SYNC
SYNC
LOAD
LOAD
IN1
MCU
IN2
IN3
IN1
ISO8200
IN4
IN5
IN6
GPIO
MCU
IN2
IN3
IN4
IN5
IN6
GPIO
IN7
IN8
IN7
IN8
Vdd
Vdd
FAULT
GND
ISO8200
GNDdd
Inputs are enabled by MCU through
the SYNC/LOAD signals
FAULT
GND
GNDdd
Inputs are always enabled
(outputs can be disabled through OUT_EN)
AM14897v1
18/35
DocID023802 Rev 9
ISO8200B
Functional description
Figure 10. Direct control mode time diagram
SYNC
LOAD
tds(DMC)
INx
t INLD
t LDIN
t SU(IN)
t h(IN)
Internal
refresh
1/ f refresh
OUTx
td(OFF)
6.3
tf
td(ON)
tr
AM14898v1
Synchronous control mode (SCM)
When SYNC and LOAD inputs are independently driven, the device can operate in
synchronous control mode (SCM). The SCM is used to reduce the jittering of the outputs
and to drive all outputs of different devices at the same time.
In SCM the LOAD signal is forced low to update the input buffer while the SYNC signal is
high. The LOAD signal is raised and the SYNC one is forced low for at least tSYNC(SCM).
During this period, the internal refresh is disabled and any pending transmission between
the low voltage and the isolated side is completed. When the SYNC signal is raised the
channel output configuration is changed according to the one stored in the input.
If the tSYNC(SCM) limit is met, the maximum jitter of the channel outputs is tjitter(SCM).
If more devices share the same SYNC signal, all device outputs change simultaneously with
a maximum jitter related to maximum delay and maximum jitter for single device.
DocID023802 Rev 9
19/35
Functional description
ISO8200B
Table 13. Interface signal operation in synchronous control mode
LOAD
SYNC
OUT_EN
Device behavior
Don’t care
Don’t care
Low (1)
High
High
High
The outputs are left unchanged
Low
High
High
The input buffer is enabled
The outputs are left unchanged
High
Low
High
The internal refresh signal is disabled
The transmission buffer is updated
The outputs are left unchanged
High
Rising edge
High
The outputs are updated according to the current
transmission buffer value
Low
Low
High
Should be avoided (DCM operation only)
The outputs are disabled (turned off)
1. The outputs are turned off on OUT_EN falling edge and they are kept disabled as long as it is low.
Figure 11. Synchronous control mode IC configuration
Vdd
Vdd
Vdd
OUT_EN
SYNC
LOAD
IN1
MCU
IN2
IN3
ISO8200
IN4
GPIO
IN5
IN6
IN7
IN8
Vdd
FAULT
GND
GNDdd
AM14899v1
20/35
DocID023802 Rev 9
ISO8200B
Functional description
Figure 12. Synchronous control mode time diagram
tdis (SYNC)
tw(SYNC)
tsu(LOAD)
tw(LOAD)
th(LOAD)
tsu(IN) th(IN)
tw(IN)
td(OFF)
tf
GIPGLM3101141151
Figure 13. Multiple device synchronous control mode
DEV1
MCU
SYNC
LOAD
SYNC
LD1
LD2
DATA1..DATA8
8
SYNC
IN1..IN8
OUT0..OUT7
8
LD1
LD2
DEV2
DATA1..DATA8
SYNC
LOAD
IN1..IN8
OUT0..OUT7
8
OUT1..OUT8
DEV1
OUT1..OUT8
DEV2
A
B
X
A
X
B
AM14901v1
DocID023802 Rev 9
21/35
Functional description
6.4
ISO8200B
Fault indication
The FAULT pin is an active low open drain output indicating fault conditions. This pin is
active when at least one of the following conditions occurs:
6.4.1
•
Junction overtemperature of one or more channels (TJ >TTJSD)
•
Communication error
Junction overtemperature and case overtemperature
The thermal status of the device is updated during each transmission sequence between
the two isolated sides.
In SCM operation, when the LOAD signal is high and the SYNC one is low, the
communication is disabled. In this case the thermal status of the device cannot be updated
and the FAULT indication can be different from the current status.
In any case, the thermal protection of the channel outputs is always operative.
Figure 14. Thermal status update (DCM)
22/35
DocID023802 Rev 9
ISO8200B
Functional description
Figure 15. Thermal status update (SCM)
SYNC
FAULT
SKIPPED
Internal
refresh
Tx/Rx
Tx/Rx
Tx/Rx
THERMAL
FAULT
AM14992v1
DocID023802 Rev 9
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Power section
ISO8200B
7
Power section
7.1
Current limitation
The current limitation process is active when the current sense connected on the output
stage measures a current value, which is higher than a fixed threshold.
When this condition is verified the gate voltage is modulated to avoid the increase of the
output current over the limitation value.
Figure 16 shows typical output current waveforms with different load conditions.
Figure 16. Current limitation with different load conditions
24/35
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ISO8200B
7.2
Power section
Thermal protection
The device is protected against overheating in case of overload conditions. During the
driving period, if the output is overloaded, the device suffers two different thermal stresses,
the former related to the junction, and the latter related to the case.
The two faults have different trigger thresholds: the junction protection threshold is higher
than the case protection one; generally the first protection, that is active in thermal stress
conditions, is the junction thermal shutdown. The output is turned off when the temperature
is higher than the related threshold and turned back on when it goes below the reset
threshold. This behavior continues until the fault on the output is present.
If the thermal protection is active and the temperature of the package increases over the
fixed case protection threshold, the case protection is activated and the output is switched
off and back on when the junction temperature of each channel in fault and case
temperature is below the respective reset thresholds.
Figure 17 shows the thermal protection behavior, while Figure 18 reports typical
temperature trends and output vs. input state.
Figure 17. Thermal protection flowchart
Input IN(i) HIGH
Output (i) ON
Fault(i) Off
N
TJ(i) >TJSD
Y
N
Output (i) OFF
Fault(i) ON
TC >TCSD
N
Y
TJR >TJ(i)
Y
Y
TC >TCR
N
AM14995v1
DocID023802 Rev 9
25/35
Power section
ISO8200B
Figure 18. Thermal protection
26/35
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ISO8200B
8
Reverse polarity protection
Reverse polarity protection
Reverse polarity protection can be implemented on board using two different solutions:
1.
Placing a resistor (RGND) between IC GND pin and load GND
2.
Placing a diode between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to the
following equation:
Equation 1
RGND ≥ VCC/IGNDcc
where IGNDcc is the DC reverse ground pin current and can be found in Section 3: Absolute
maximum ratings of this datasheet.
Power dissipated by RGND during reverse polarity situations is:
Equation 2
PD = (VCC)2/RGND
If option 2 is selected, the diode has to be chosen by taking into account VRRM >|Vcc| and
its power dissipation capability:
Equation 3
PD ≥ IS*VF
In normal conditions (no reverse polarity) due to the diode, there is a voltage drop between
GND of the device and GND of the system.
Figure 19. Reverse polarity protection
+Vdd
Intputi
GNDdd
+Vcc
Isolation
Note:
Outputi
GNDCC
Load
RGND
Diode
GIPD2611131255LM
This schematic can be used with any type of load.
DocID023802 Rev 9
27/35
Reverse polarity on Vdd
9
ISO8200B
Reverse polarity on Vdd
The reverse polarity on Vdd can be implemented on board by placing a diode between
GNDdd pin and GND digital ground.
The diode has to be chosen by taking into account VRRM >|Vdd| and its power dissipation
capability:
Equation 4
PD ≥ Idd*VF
Note:
In normal conditions (no reverse polarity), due to the diode, there is a voltage drop between
GNDdd of the device and digital ground of the system.
Figure 20. Reverse polarity protection on Vdd
+Vcc
Isolation
+Vdd
Intputi
Outputi
GNDCC
GNDdd
Load
Diode
RGND
Diode
GIPD2611131302LM
28/35
DocID023802 Rev 9
ISO8200B
Conventions
10
Conventions
10.1
Supply voltage and power output conventions
Figure 21 shows the convention used in this paper for voltage and current usage.
Figure 21. Supply voltage and power output conventions
Idd
Icc
Vdd
IFAULT
IIN
Vdd
Vcc
FAULT
IN
I OUT_EN
OUT_EN
Vcc
Iout
OUT
ISYNC
ILOAD
SYNC
LOAD
GNDdd
GNDcc
Vout
AM14997v1
11
Thermal information
11.1
Thermal impedance
Figure 22. Simplified thermal model
Rth1a
Tj1
Rthc_a
Rth2
Rth1b
Cth
Tj2
Rth1h
Tj8
AM14998v1
DocID023802 Rev 9
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Package mechanical data
12
ISO8200B
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 23. PowerSO-36 mechanical drawings
30/35
DocID023802 Rev 9
ISO8200B
Package mechanical data
Table 14. PowerSO-36 mechanical data
mm
Dim.
Min.
Typ.
A
a1
Max.
3.60
0.10
0.30
a2
3.30
a3
0
0.10
b
0.22
0.38
c
0.23
0.32
D
15.80
16.00
D1
9.40
9.80
E
13.90
14.50
E1
10.90
11.10
E2
E3
2.90
5.8
6.2
e
0.65
e3
11.05
G
0
0.10
H
15.50
15.90
h
L
1.10
0.80
N
S
1.10
10°
0°
DocID023802 Rev 9
8°
31/35
Package mechanical data
ISO8200B
Figure 24. Footprint recommended data
Table 15. Footprint data
32/35
Dim.
mm
A
9.5
B
14.7-15.0
C
12.5-12.7
D
6.3
E
0.46
G
0.65
DocID023802 Rev 9
ISO8200B
13
Ordering information
Ordering information
Table 16. Ordering information
Order code
Package
Packaging
ISO8200B
PowerSO-36
Tube
ISO8200BTR
PowerSO-36
Tape and reel
DocID023802 Rev 9
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Revision history
14
ISO8200B
Revision history
Table 17. Document revision history
Date
Revision
19-Oct-2012
1
Initial release.
01-Jul-2013
2
Updated Figure 24: Footprint recommended data and Table 15:
Footprint data.
28-Oct-2013
3
Document status promoted from preliminary to production data.
Added IEC bullet to features.
Updated Table 4, Table 6, Table 7, and Table 9.
Deleted table titled: “Insulation and safety-related specifications” and
table titled: “Device immunity specifications”.
Changed Table 10: IEC 60747-5-2 insulation characteristics
Changed Figure 10.
12-Nov-2013
4
Added to Table 10 CLR and CPG parameters.
5
Removed VIORM parameter from Table 10.
Updated Section 8: Reverse polarity protection.
Added Section 9: Reverse polarity on Vdd .
Changed Figure 19.
Added Figure 20.
24-Jan-2014
6
Changed Figure 7.
Added note to Table 3.
Added test conditions: TJ = 125 °C to Table 4.
Added typ. and max. values of Idd to Table 5.
Added max. values of td(ON) and td(OFF) to Table 7.
Added typ. and max. values of tp(OUT_EN) to Table 9.
Added tjitter(DCM) value to Table 9.
03-Feb-2014
7
Updated Figure 12.
06-Feb-2014
8
Updated Figure 12 and Table 9.
22-Apr-2014
9
Updated EAS parameter in Table 2.
Updated IPEAK parameter in Table 6.
Updated mechanical data.
29-Nov-2013
34/35
Changes
DocID023802 Rev 9
ISO8200B
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