TH7122 DataSheet DownloadLink 4798

TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Features
ˆ Single chip solution with only a few external
components
ˆ Stand-alone fixed-frequency user mode
ˆ Programmable multi-channel user mode
ˆ Low current consumption in active mode and
very low standby current
ˆ PLL-stabilized RF VCO (LO) with internal
varactor diode
ˆ Lock detect output in programmable
user mode
ˆ On-chip AFC for extended input frequency
acceptance range
ˆ 3wire bus serial control interface
ˆ FSK/ASK mode selection
ˆ FSK for digital data or FM for analog signal
reception
ˆ RSSI output for signal strength indication and
ASK reception
ˆ Peak detector for ASK detection
ˆ Switchable LNA gain for improved dynamic
range
ˆ Automatic PA turn-on after PLL lock
ˆ ASK modulation achieved by PA on/off keying
ˆ 32-pin Low profile Quad Flat Package (LQFP)
Ordering Information
Package Code
Delivery Form
E (-40 °C to 85 °C)
NE (LQFP32)
250 pc/tray
2000 pc/T&R
E (-40 °C to 85 °C)
NE (LQFP32)
Application Examples
250 pc/tray
2000 pc/T&R
Pin Description
ˆ General bi-directional half duplex digital data
RF signaling or analog signal communication
ˆ Tire Pressure Monitoring Systems (TPMS)
ˆ Remote Keyless Entry (RKE)
ˆ Low-power telemetry systems
ˆ Alarm and security systems
ˆ Wireless access control
ˆ Garage door openers
ˆ Networking solutions
ˆ Active RFID tags
ˆ Remote controls
ˆ Home and building automation
LF
VEE_PLL
TNK_LO
VCC_PLL
FS1/LD
VEE_DIG
FS0/SDEN
TH7122.1
(only for existing designs,
not for new design-ins)
TH7122.2
(for new design-ins)
Temperature Code
17
24
OUT_PA
IN_LNA
VEE_LNA
OUT_LNA
GAIN_LNA
IN_MIX
VEE_IF
OUT_MIX
16
25
TH7122
32
9
1
RE/SCLK
VCC_DIG
ASK/FSK
IN_DTA
FSK_SW
RO
VEE_RO
8
IN_IFA
VCC_IF
IN_DEM
INT2/PDO
INT1
OUT_DEM
RSSI
OUT_DTA
Part Number
General Description
The TH7122 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multichannel programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used
for applications in automotive, industrial-scientific-medical (ISM), short range devices (SRD) or similar applications operating in the frequency range of 300 MHz to 930 MHz. In programmable user mode, the transceiver can operate down to 27 MHz by employing an external VCO varactor diode.
39010 07122
Rev. 010
Page 1 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Document Content
1
Theory of Operation ...................................................................................................4
1.1
General ............................................................................................................................. 4
1.2
Technical Data Overview.................................................................................................. 4
1.3
Note on ASK Modulation .................................................................................................. 4
1.4
Block Diagram .................................................................................................................. 5
1.5
User Mode Features ......................................................................................................... 5
2
Pin Definitions and Descriptions ..............................................................................6
3
Functional Description ............................................................................................10
3.1
PLL Frequency Synthesizer ........................................................................................... 10
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.2
Reference Oscillator (XOSC)..................................................................................................... 11
Reference Divider ...................................................................................................................... 11
Feedback Divider ....................................................................................................................... 11
Frequency Resolution and Operating Frequency ...................................................................... 11
Phase-Frequency Detector ........................................................................................................ 12
Lock Detector............................................................................................................................. 12
Voltage Controlled Oscillator with external Loop Filter.............................................................. 13
Loop Filter .................................................................................................................................. 13
Receiver Part .................................................................................................................. 13
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
LNA ............................................................................................................................................ 14
Mixer .......................................................................................................................................... 14
IF Amplifier ................................................................................................................................. 14
ASK Demodulator ...................................................................................................................... 14
FSK Demodulator ...................................................................................................................... 15
Transmitter Part .............................................................................................................. 15
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
4
Power Amplifier.......................................................................................................................... 15
Output Power Adjustment .......................................................................................................... 16
Modulation Schemes ................................................................................................................. 16
ASK Modulation ......................................................................................................................... 16
FSK Modulation ......................................................................................................................... 17
Crystal Tuning............................................................................................................................ 17
Description of User Modes......................................................................................18
4.1
Stand-alone User Mode Operation ................................................................................. 18
4.1.1
4.1.2
4.1.3
4.1.4
4.2
Frequency Selection .................................................................................................................. 18
Operation Mode ......................................................................................................................... 18
Modulation Type ........................................................................................................................ 19
LNA Gain Mode ......................................................................................................................... 19
Programmable User Mode Operation............................................................................. 19
4.2.1
5
Serial Control Interface Description ........................................................................................... 19
Register Description ................................................................................................20
39010 07122
Rev. 010
Page 2 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
5.1
Register Overview .......................................................................................................... 21
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
6
Default Register Settings for FS0, FS1...................................................................................... 21
A – word ..................................................................................................................................... 22
B – word ..................................................................................................................................... 23
C – word..................................................................................................................................... 24
D – word..................................................................................................................................... 25
Technical Data..........................................................................................................26
6.1
Absolute Maximum Ratings ............................................................................................ 26
6.2
Normal Operating Conditions ......................................................................................... 26
6.3
DC Characteristics.......................................................................................................... 27
6.4
PLL Synthesizer Timings ................................................................................................ 29
6.5
AC Characteristics of the Receiver Part ......................................................................... 29
6.6
AC Characteristics of the Transmitter Part ..................................................................... 30
6.7
Serial Control Interface ................................................................................................... 30
6.8
Crystal Parameters ......................................................................................................... 30
7
Application Circuit Examples..................................................................................31
7.1
FSK Application Circuit Programmable User Mode (internal AFC option)...................... 31
7.2
FSK Application Circuit Stand-alone User Mode ............................................................ 32
7.3
FSK Test Circuit Component List (Fig. 14 and Fig. 15) .................................................. 33
7.4
ASK Application Circuit Programmable User Mode (normal data slicer option) ............. 34
7.5
ASK Test Circuit Component List (Fig. 16)..................................................................... 35
7.6
ASK Application Circuit Programmable User Mode (peak detector option).................... 36
7.7
ASK Test Circuit Component List (Fig. 17)..................................................................... 37
8
Extended Frequency Range ....................................................................................38
8.1
9
Board Component List (Fig. 18) ..................................................................................... 38
TX/RX Combining Network......................................................................................39
9.1
Board Component List (Fig. 19) ..................................................................................... 39
9.2
Typical LNA S-Parameters in Receive Mode ................................................................. 39
9.3
LNA Input Impedances in Transmit Mode ...................................................................... 40
10
Package Description ................................................................................................41
10.1
Soldering Information ..................................................................................................... 41
11
Reliability Information..............................................................................................42
12
ESD Precautions ......................................................................................................42
13
Disclaimer .................................................................................................................44
39010 07122
Rev. 010
Page 3 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
1
Theory of Operation
1.1
General
The main building block of the transceiver is a programmable PLL frequency synthesizer that is based on an
integer-N topology. The PLL is used for generating the carrier frequency during transmission and for
generating the LO signal during reception. The carrier frequency can be FSK-modulated either by pulling the
crystal or by modulating the VCO directly. ASK modulation is done by on/off keying of the power amplifier.
The receiver is based on the principle of a single conversion superhet. Therefore the VCO frequency has to
be changed between transmit and receive mode. In receive mode, the default LO injection type is low-side
injection.
The TH7122 transceiver IC consists of the following building blocks:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
1.2
Low-noise amplifier (LNA) for high-sensitivity
RF signal reception with switchable gain
Mixer (MIX) for RF-to-IF down-conversion
IF amplifier (IFA) to amplify and limit the IF
signal and for RSSI generation
Phase-coincidence FSK demodulator with
external ceramic discriminator or LC tank
Operational amplifier (OA1), connected to
demodulator output
Operational amplifier (OA2), for general use
Peak detector (PKDET) for ASK detection
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Control logic with 3wire bus serial control
interface (SCI)
Reference oscillator (RO) with external crystal
Reference divider (R counter)
Programmable divider (N/A counter)
Phase-frequency detector (PFD)
Charge pump (CP)
Voltage controlled oscillator (VCO) with internal
varactor
Power amplifier (PA) with adjustable output
power
Technical Data Overview
ˆ Frequency range: 300 MHz to 930 MHz in
programmable user mode
ˆ Extended frequency range with external VCO
varactor diode: 27 MHz to 930 MHz
ˆ 315 MHz, 433 MHz, 868 MHz or 915 MHz fixedfrequency settings in stand-alone mode
ˆ Power supply range: 2.2 V to 5.5 V
ˆ Temperature range: -40 °C to +85 °C
ˆ Standby current: 50 nA
ˆ Operating current in receive: 6.5 mA (low gain)
ˆ Operating current in transmit: 12 mA (at -2 dBm)
ˆ Adjustable RF power range: -20 dBm to +10dBm
ˆ Sensitivity: -105 dBm at FSK with 180 kHz
IF filter BW
1.3
ƒ
ˆ Sensitivity: -107 dBm at ASK with 180 kHz
IF filter BW
ˆ Max. data rate with crystal pulling: 20 kbps NRZ
ˆ Max. data rate with direct VCO modulation:
115 kbps NRZ
ˆ Max. input level: -10 dBm at FSK
and -20 dBm at ASK
ˆ Input frequency acceptance: ± 10 to ± 150 kHz
(depending on FSK deviation)
ˆ FM/FSK deviation range: ±2.5 to ±80 kHz
ˆ Analog modulation frequency: max. 10 kHz
ˆ Crystal reference frequency: 3 MHz to 12 MHz
ˆ External reference frequency: 1 MHz to 16 MHz
Note on ASK Operation
Optimum ASK performance can be achieved by using an 8-MHz crystal for operation at 315 MHz, 434 MHz
and 915 MHz. For details please refer to the software settings shown in sections 7.4 and 7.6. FSK operation
is the preferred choice for applications in the European 868MHz band.
39010 07122
Rev. 010
Page 4 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
2
7
3 IN_DEM
RSSI
1
VCC_IF
31
IN_IFA
32
VEE_IF
6 OUT_DEM
PKDET
SW1
1.5pF
26
FSK Demodulator
MIX
LNA
5
INT1
IFA
SW2
OA1
Control Logic
15
16
TE/SDTA
13
RE/SCLK
12
ASK/FSK
9
IN_DTA
19
VEE_RO
11
FS1/LD
22 VEE_PLL 10 RO
17
FS0/SDEN
FSK
FSK_SW
23 LF
SCLK
21 TNK_LO 20 VCC_PLL
Fig. 1:
1.5
RO
SDTA
RO
PA
24 PS_PA
SCI
R
counter
SDEN
N
counter
VCO
25
8
OUT_DTA
200k
LO
OUT_PA
4
INT2/PDO
MIX
IF
ASK
OA2
18
14
VCC_DIG
IN_LNA
bias
VEE_DIG
30
OUT_MIX
28
IN_MIX
29
OUT_LNA
27
GAIN_LNA
Block Diagram
VEE_LNA
1.4
TH7122 block diagram
User Mode Features
The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled
programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Standalone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC in
order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz,
433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up
in order to remain in fixed-frequency mode.
After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode
(PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins
FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the
3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer.
A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two
idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL
settings for the PLL idle mode are taken over from the last operating mode which can be either receive or
transmit mode.
The different operating modes can be set in SUM and PUM as well. In SUM the user can program the transceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the
modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI.
39010 07122
Rev. 010
Page 5 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
2
Pin Definitions and Descriptions
Pin No.
Name
I/O Type
1
IN_IFA
input
Functional Schematic
VCC
Description
VCC
IF amplifier input, approx.
2 kΩ single-ended
2.2k
IN_IFA
50
1
140µA
VEE
2
VCC_IF
supply
3
IN_DEM
analog I/O
VEE
positive supply of LNA, MIX,
IFA, FSK Demodulator, PA,
OA1 and OA2
VCC
VCC
IF amplifier output and demodulator input, connection
to external ceramic discriminator or LC tank
90k
IN_DEM
60k
3
1.5p
10µA
100µA
VEE
4
INT2/PDO
VEE
VCC
output
OA2 output or peak detector
output, high impedance in
transmit and idle mode
INT2/PDO
4
VEE
5
INT1
input
VCC
inverting inputs of OA1 and
OA2
VCC
200k
INT1
120
120
+
OA1
5
VCC
VEE
6
bias
120
OUT_DEM analog I/O
550k
6
OUT_DEM
1k
7
RSSI
550k
OA2
output
10p
VEE
demodulator output and
non-inverting OA1 input,
high impedance in transmit
and idle mode
10p
RSSI output, approx. 31 kΩ
VCC
RSSI
120
31k
7
VEE
39010 07122
Rev. 010
Page 6 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Pin No.
Name
I/O Type
8
OUT_DTA
output
Functional Schematic
VCC
Description
OA1 output, high impedance
in transmit and idle mode
OUT_DTA
8
VEE
9
VEE_RO
ground
10
RO
analog I/O
ground of RO
VCC
RO input, base of bipolar
transistor
2.6µA
36p
RO
36p
10
39k
VEE
11
FSK_SW
VCC
analog I/O
FSK_SW
11
FSK pulling pin, switch to
ground or OPEN
The switch is open in receive and idle mode
VEE
12
IN_DTA
VCC
input
IN_DTA
120
12
ASK/FSK modulation data
input, pull down resistor
120kΩ
120k
VEE
13
ASK/FSK
VCC
input
ASK/FSK
ASK/FSK mode select input
120
13
VEE
14
VCC_DIG
supply
15
RE/SCLK
input
positive supply of serial port
and control logic
VCC
RE/SCLK
120
receiver enable input / clock
input for the shift register,
pull down resistor 120kΩ
15
120k
VEE
16
TE/SDTA
input
VCC
TE/SDTA
16
120
transmitter enable input /
serial data input, pull down
resistor 120kΩ
120k
VEE
39010 07122
Rev. 010
Page 7 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Pin No.
Name
I/O Type
17
FS0/SDEN
input
Functional Schematic
Description
VCC
frequency select input / serial data enable input
FS0/SDEN
120
17
VEE
18
VEE_DIG
ground
19
FS1/LD
input /
output
ground of serial port and
control logic
VCC
frequency select input / lock
detector output
FS1/LD
19
120
VEE
20
VCC_PLL analog I/O
VCC_PLL
TNK_LO
21
VD
6.3pF
20
VCO open-collector output,
connection to VCC or external LC tank
VCC
21
TNK_LO
analog I/O
VEE
LF
6.5k
23
23
LF
VEE
VCC
VCOCUR
analog I/O
120
VEE
VCO open-collector output,
connection to external LC
tank
charge pump output, connection to external loop filter
VEE
22
VEE_PLL
ground
24
PS_PA
analog I/O
ground of PLL frequency
synthesizer
VCC
VCC
power-setting input
10µA
PS_PA
120
24
VEE
25
OUT_PA
output
VEE
VCC
OUT_PA
power amplifier opencollector output
1k
25
20p
VEE
39010 07122
Rev. 010
Page 8 of 44
VEE
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Pin No.
Name
I/O Type
27
VEE_LNA
ground
28
OUT_LNA
Functional Schematic
ground of LNA and PA
OUT_LNA
output
bias
28
37
3.8k
26
IN_LNA
input
LNA input, single-ended
0.8p
VEE
GAIN_LNA
LNA open-collector output,
connection to external LC
tank at RF
VEE
IN_LNA
26
29
Description
VEE
VCC
input
GAIN_LNA
LNA gain control input
120
29
VEE
30
IN_MIX
VCC
input
mixer input, approx. 200Ω
single-ended
210
IN_MIX
30
LO
bias
VEE
31
VEE_IF
ground
32
OUT_MIX
output
VEE
ground of IFA, Demodulator,
OA1 and OA2
VCC
OUT_MIX
mixer output, approx. 330Ω
single-ended
100
32
VEE
39010 07122
Rev. 010
Page 9 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
3
Functional Description
3.1
PLL Frequency Synthesizer
The TH7122 contains an integer-N PLL frequency synthesizer. A PLL circuit performs the frequency synthesis via a feedback mechanism. The output frequency fVCO is generated as an integer multiple of the phase
detector comparison frequency fR .This reference frequency fR is generated by dividing the output frequency
fRO of a crystal oscillator. The phase detector utilizes this signal as a reference to tune the VCO and in the
locked state it must be equal to the desired output frequency, divided by the feedback divider ratio N.
VCC
Reference
Oscillator
Reference
Divider
f RO
Phase-frequency
Detector
LF
fR
Feedback
Divider
fN
Fig. 2:
External
Loop Filter
Charge
Pump
f VCO
Voltage Controlled
Oscillator
Integer-N PLL Frequency Synthesizer Topology
The output frequency of the synthesizer fVCO can be selected by programming the feedback divider and the
reference divider. The only constraint for the frequency output of the system is that the minimum frequency
resolution, or the channel spacing, must be equal to the PFD frequency fR, which is given by the reference
frequency fRO and the reference divider factor R:
fR =
f RO
.
R
(1)
When the PLL is unlocked (e.g. during power up or during reprogramming of a new feedback divider ratio N),
the phase-frequency detector PFD and the charge pump create an error signal proportional to the phase
difference of the two input signals. This error signal is low-pass filtered through the external loop filter and
input to the VCO to control its frequency. A very low frequency resolution increases the settling time of the
PLL and reduces the ability to cancel out VCO perturbations, because the loop filter is updated every 1/fR.
After the PLL has locked, the VCO frequency is given by the following equation:
f VCO = N ⋅
f RO
= N ⋅ fR .
R
(2)
There are four registers available to set the VCO frequencies in receive (registers RR and NR) and in transmit mode (registers RT and NT). These registers can be programmed using the Serial Control Interface in
Programmable User Mode (PUM). In case of Stand-alone User Mode (SUM), the registers are set fixed values (refer to para. 4.1.1).
The VCO frequency is equal to the carrier frequency in transmit mode. While in receive mode the VCO
frequency is offset by the intermediate frequency IF. This is because of the super-heterodyne nature of the
receive part.
39010 07122
Rev. 010
Page 10 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
3.1.1
Reference Oscillator (XOSC)
The reference oscillator is based on a Colpitts topology with two integrated functional capacitors as shown in
figure 3. The circuitry is optimized for a load capacitance range of 10 pF to 15 pF. The equivalent input
capacitance CRO offered by the oscillator input pin RO is about 18pF.
To ensure a fast and reliable start-up and a very stable frequency
VCC
over the specified supply voltage and temperature range, the
IRO
oscillator bias circuitry provides an amplitude regulation. The amplitude on pin RO is monitored in order to regulate the current of
36pF
36pF
the oscillator core IRO. There are two limits ROMAX and ROMIN
RO
between the regulation is maintained. These values can be
changed via serial control interface in Programmable User Mode
XTAL
(PUM). In Stand-alone User Mode (SUM), ROMAX and ROMIN
are set to default values (refer to para. 5.1.3). ROMAX defines the
CX2
VEE
start-up current of the oscillator. The ROMIN value sets the desired steady-state current. If ROMIN is sufficient to achieve an
FSKSW
amplitude of about 400 mV on pin RO, the current IRO will be set
CX1
to ROMIN. Otherwise the current will be permanently regulated
between ROMIN and ROMAX. If ROMIN and ROMAX are equal,
no regulation takes place. For most of the applications ROMIN
and ROMAX should not be changed from default.
Fig. 3: Reference oscillator circuit
3.1.2
Reference Divider
The reference divider provides the input signal of the phase detector by dividing the signal of the reference
oscillator. The range of the reference divider is
4 ≤ R ≤ 1023 .
3.1.3
(3)
Feedback Divider
The feedback divider of the PLL is based on a pulse-swallow topology. It contains a 4-bit swallow A-counter,
a 13-bit program B-counter and a prescaler. The divider ratio of the prescaler is controlled by the program
counter and the swallow counter. During one cycle, the prescaler divides by 17 until the swallow A-counter
reaches its terminal count. Afterwards the prescaler divides by 16 until the program counter reaches its
terminal count. Therefore the overall feedback divider ratio can be expressed as:
N = 17 ⋅ A + 16 ⋅ (B - A) .
(4)
The A-counter configuration represents the lower bits in the feedback divider register (N0-3 = A0-3) and the
upper bits the B-counter configuration (N4-16 = B0-12) respectively. According to that, the following counter
ranges are implemented:
0 ≤ A ≤ 15 ; 4 ≤ B ≤ 8191 whereas B > A
(5)
and therefore the range of the overall feedback divider ratio results in:
64 ≤ N ≤ 131071 .
(6)
The user does not need to care about the A- and B-counter settings. It is only necessary to know the overall
feedback divider ratio N to program the register settings.
3.1.4
Frequency Resolution and Operating Frequency
It is obvious from (2) that, at a given frequency resolution fR, the maximum operating frequency of the VCO is
limited by the maximum N-counter setting. The table below provides some illustrative numbers. Please also
refer to section 4.4.1 for the pre-configured settings in Stand-alone User Mode (SUM).
39010 07122
Rev. 010
Page 11 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Crystal
frequency fRO
Frequency
resolution fR
R
counter
N
counter
Operating
frequency fVCO
3.0000MHz
2.93kHz
1023
13107
38.437MHz
3.0000MHz
2.93kHz
1023
131071
384.372MHz
8.0000MHz
12.5kHz
640
35812
447.65MHz
8.0000MHz
25kHz
320
34746
868.65MHz
8.0000MHz
250kHz
32
3660
915.0MHz
3.1.5
Phase-Frequency Detector
The phase-frequency detector creates an error voltage proportional to the phase difference between the
reference signal fR and fN. The implementation of the phase detector is a phase-frequency type. That circuitry
is very useful because it decreases the acquisition time significantly. The gain of the phase detector can be
expressed as:
K PD =
I CP
,
2π
(7)
where ICP is the charge pump current which is set via register CPCUR. In the TH7122 design the VCO
frequency control characteristic is with negative polarity. This means the VCO frequency increases if the loop
filter output voltage decreases and vice versa. When an external varactor diode is added to the VCO tank,
the tuning characteristic can be changed between positive and negative depending on the particular varactor
diode circuitry. Therefore the PDFPOL register can be used to define the phase detector polarity.
3.1.6
Lock Detector
In Programmable User Mode a lock-detect signal LD is available at pin FS1/LD (pin 19). The lock detection
circuitry uses Up and Down signals from the phase detector to check them for phase coherency. Figure 4
shows an overview of the lock signal generation. The locked state and the unlock condition will be decided
on the register settings of LDTM and ERTM respectively. In the start-up phase of the PLL, Up and Down
signals are quite unbalanced and counter CNT_LD receives no clock signal. When the loop approaches
steady state, the signals Up and Down begin to overlap and CNT_LD counts down. Herein register LDTM
sets the number of counts which are necessary to set the lock detection signal LD. If an unlock condition
occurs, the counter CNT_LD will be reloaded and therefore its CARRY falls back.
LDTM [1 : 0]
2
D
CARRY
Control
Logic
LOCKMODE
RESET LD
Up
Down
&
&
CR
LOAD
PFD
CNT_LD
=
ERTM [1 : 0]
FRO
RO
2
D
&
R
Q
LD
S
MUX
CARRY
CR
LOAD
Fig. 4:
Lock Detection Circuit
CNT_ER
39010 07122
Rev. 010
Page 12 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
The CNT_ER supervises the unlock condition. If Up and Down are consecutive, the counter CNT_ER will be
reloaded permanently and its CARRY will not be set, otherwise the counter level of CNT_ER will be reduced
by the reference oscillator clock (1/fRO). The register ERTM decides on the maximum number of clocks
during Up and Down signals can be non-consecutive without loosing the locked state.
The transceiver offers two ways of analyzing the locked state. If the register LOCKMODE is set to ‘0’, only
one occurrence of the locked state condition is needed to remain LD = 1 during the whole active mode, otherwise the state of the PLL will be observed permanently.
3.1.7
Voltage Controlled Oscillator with external Loop Filter
Fig. 5:
3.1.8
External
Loop Filter
TNK_LO
LF
VCC_PLL
VD
6.3pF
VCOCUR
Charge Pump
VEE
VCO schematic
Loop Filter
Since the loop filter has a strong impact on the function of the PLL, it
must be chosen carefully. For FSK operation the bandwidth of the loop
filter must be selected wide enough for a fast relock of the PLL during
crystal pulling. The bandwidth must of course also be larger than the data
rate. In case of ASK or OOK the bandwidth should be extended even
further to allow the PLL to cancel out VCO perturbations that might be
caused by the PA on/off keying. The suggested filter topology is shown in
Fig. 6. The dimensions of the loop filter elements can be derived using
well known formulas in application notes and other reference literature.
Fig. 6:
3.2
VCC
+
The transceiver provides a LC-based voltage-controlled oscillator with an
external inductance element connected between VCC and pin TNK_LO.
An internal varactor diode in series with a fixed capacitor forms the variable part of the oscillator tank. The oscillation frequency is adjusted by
the DC-voltage at pin LF. The tuning sensitivity of the VCO is approximately 20MHz/V for 433MHz operations and 40MHz/V at 868MHz. Since
the internal varactor is connected to VCC, a lower voltage on pin LF
causes the capacitance to decrease and the VCO frequency to increase.
For this reason the phase detector polarity should be negative (PFDPOL
= 0). If the operation frequency is below 300MHz, an external varactor
diode between pin TNK_LO and VCC_PLL is necessary. The corresponding application schematic is shown in section 8. The VCO current
VCOCUR can be adjusted via serial control interface in order to ensure
stable oscillations over the whole frequency range. For lowest LO emission in receive mode, VCOCUR should be set to the lowest value.
VCC
RF
CF1
CF2
LF
VCO
+
2nd order Loop filter
Receiver Part
The RF front-end of the receiver part is a super-heterodyne configuration that converts the input radiofrequency (RF) signal into an intermediate frequency (IF) signal. The most commonly used IF is 10.7 MHz,
but IFs in the range of 0.4 to 22 MHz can also be used. According to the block diagram, the front-end consists of a LNA, a Mixer and an IF limiting amplifier with received signal strength indicator (RSSI). The local
oscillator (LO) signal for the mixer is generated by the PLL frequency synthesizer.
As the receiver constitutes a superhet architecture, there is no inherent suppression of the image frequency.
It depends on the particular application and the system’s environmental conditions whether an RF front-end
filter should be added or not. If image rejection and/or good blocking immunity are relevant system parameters, a band-pass filter must be placed either in front or after the LNA. This filter can be a SAW (surface
acoustic wave) or LC-based filter (e.g. helix type).
39010 07122
Rev. 010
Page 13 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
3.2.1
LNA
The LNA is based on a cascode topology for low-noise, high gain and good reverse isolation. The open collector output has to be connected to an external resonance circuit which is tuned to the receive frequency.
The gain of the LNA can be changed in order to achieve a high dynamic range. There are two possibilities for
the gain setting which can be selected by the register bit LNACTRL. External control can be done via the pin
GAIN_LNA, internal control is given by the register bit LNAGAIN. In case of external gain control, a hysteresis of about 340 mV can be chosen via the register bit LNAHYST. This configuration is useful if an automatic
gain control loop via the RSSI signal is established. In transmit mode the LNA-input is shorted to protect the
amplifier from saturation and damaging.
3.2.2
Mixer
The mixer is a double-balanced mixer which down converts the receive frequency to the IF. The default LO
injection type is low side (fVCO = fRX – fIF). But also high side injection is possible (fVCO = fRX + fIF). In this case,
the data signal´s polarity is inverted due to the mixing process. To avoid this, the transmitted data stream can
be inverted too by setting DTAPOL to ‘1’.
The output impedance of the mixer is about 330Ω in order to match to an external IF filter.
3.2.3
IF Amplifier
After passing the channel select filter which sets the IF bandwidth the signal is limited by means of an high
gain limiting amplifier. The small signal gain is about 80 dB. The RSSI signal is generated within the IF amplifier. The output of the RSSI signal is available at pin RSSI. The voltage at this pin is proportional to the input
power of the receiver in dBm. Using this RSSI output signal the signal strength of different transmitters can
be distinguished.
3.2.4
ASK Demodulator
The receive part of the TH7122 allows for two ASK demodulation configurations:
•
•
standard ASK demodulation or
ASK demodulation with peak detector.
The default setting is standard ASK demodulation. In this mode SW1 and SW2 are closed and the RSSI
output signal directly feeds the data slicer setup by means of OA1. The data slicer time constant equals to
T = 200kΩ ⋅ C3 ,
(8)
with C3 external to pin INT1. This time constant should be larger than the longest possible bit duration of the
data stream. This is required to properly extract the ASK data’s DC level. The purpose of the DC (or mean)
level at the negative input of OA1 is to set an adaptive comparator threshold to perform the ASK detection.
Alternatively a peak detector can be used to define the ASK detection threshold. In this configuration the
peak detector PKDET is enabled, SW1 is closed and SW2 is open, and the peak detector output is multiplexed to pin INT2/PDO. This way the peak detector can feed the data slicer, again constituted by OA1 and a
few external R and C components. The peak detection mode is selectable in programmable user mode.
39010 07122
Rev. 010
Page 14 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
3.2.5
FSK Demodulator
The implemented FSK demodulator is based on the phase-coincidence principle. A discriminator tank, which
can either consist of a ceramic discriminator or an LC tank, is connected to pin IN_DEM. If FSK mode is
selected SW1 is open, SW2 is closed and the output of OA2 is multiplexed to pin INT2/PDO.
The demodulator output signal directly feeds the data slicer setup by means of OA1. The data slicer time
constant can be calculated using (8). This time constant should be larger than the longest possible bit duration of the data stream as described in the previous paragraph.
An on-chip AFC circuit tolerates input frequency variations. The input frequency acceptance range is proportional to the FSK or FM deviation. It can be adjusted by the discriminator tank. The AFC feature is disabled
by default and can be activated in programmable mode.
3.3
Transmitter Part
The output of the PLL frequency synthesizer feeds a power amplifier (PA) in order to setup a complete RF
transmitter. The VCO frequency is identical to the carrier frequency.
3.3.1
Power Amplifier
The power amplifier (PA) has been designed to deliver about 10 dBm in the specified frequency bands. Its
pin OUT_PA is an open collector output. The larger the output voltage swing can be made the better the
power efficiency will be. The PA must be matched to deliver the best efficiency in terms of output power and
current consumption.
The collector must be biased to the positive supply. This is
done by means of an inductor parallel tuned with a capacitor. Or it is made large enough in order not to affect the outVCC
VCC
put matching network. S-parameters of pin OUT_PA are not
useful because the output is very high resistive with a small
3pF
L
RL
portion of parallel capacitance. Since the open-collector
output transistor can be considered as a current source, the
only parameters needed to design the output matching netOUT_PA
work are the output capacitance, the supply voltage VCC, the
transistor’s saturation voltage and the power delivered to the
VEE
load PO.
In order to avoid saturation of the output stage, a saturation
voltage VCESAT of about 0.7 V should be considered. The
Fig. 7: OUT_PA schematic
real part of the load impedance can then be calculated using
RL =
(VCC − VCE SAT ) 2
.
2 ⋅ PO
(9)
The output capacitance is typically 3 pF.
39010 07122
Rev. 010
Page 15 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Output Power Adjustment
The maximum output power is adjustable via
the external resistor RPS as shown in Figure
8. There are four predefined power settings
in programmable user mode which can be
set in the register TXPOWER. The maximum power setting P4 is the default setting.
P4
20.00
10.00
P0 / dBm
3.3.2
0.00
315MHz
433MHz
868MHz
915MHz
-10.00
-20.00
-30.00
Fig. 8:
Output power vs. RPS
-40.00
1
3.3.3
10
RPS / kOhm
100
Modulation Schemes
The RF carrier generated by the PLL frequency synthesizer can be ASK or FSK modulated. Depending on
the selected user mode, the modulation type can be selected either by the ASK/FSK pin or via the serial
control interface. Data is applied to pin IN_DTA. The data signal can be inverted by the bit DTAPOL. The
following tables for ASK and FSK modulation are valid for non-inverted data (DTAPOL = 0)
3.3.4
ASK Modulation
IN_DTA
Description
0
Power amplifier is turned off
1
Power amplifier is turned on
(according to the selected output power)
39010 07122
Rev. 010
Page 16 of 44
The transceiver is ASK-modulated by
turning on and off the power amplifier.
Please also refer to para. 1.3 for ASK
modulation limits.
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
3.3.5
FSK Modulation
•
FSK modulation via crystal pulling
VCC
FSK modulation can be achieved by pulling the crystal oscillator
frequency. A CMOS-compatible data stream applied at pin
IN_DTA digitally modulates the XOSC via an integrated NMOS
switch. Two external pulling capacitors CX1 and CX2 allow the
FSK deviation Δf and center frequency fc to be adjusted independently. At IN_DTA = LOW CX2 is connected in parallel to CX1
leading to the low-frequency component of the FSK spectrum
(fmin); while at IN_DTA = HIGH CX2 is deactivated and the XOSC
is set to its high frequency, leading to fmax.
IRO
36pF
36pF
RO
XTAL
CX2
VEE
FSKSW
CX1
IN_DTA
Description
0
fmin = fc - Δf (FSK switch is closed)
1
fmax = fc + Δf (FSK switch is open)
Fig. 9:
Crystal Pulling Circuit
An external reference signal can be directly AC-coupled to the reference oscillator input pin RO. Then the
transceiver is used without a XTAL. Now the reference signal sets the carrier frequency and has to contain
the FSK (or FM) modulation
•
FSK modulation via direct VCO modulation
IN_DTA
Alternatively FSK or FM can be achieved by injecting the modulating signal into the loop filter to directly control the VCO frequency. Fig. 10 shows a circuit proposal for direct VCO modulation. This circuit is recommended for data rates in excess of about
20 kbps NRZ. An external VCO tuning varactor should be added
for narrow-band applications, for example at channel spacings of
25 kHz. For details please refer to the application notes “TH7122
and TH71221 High Speed Data Communication” and “TH7122
and TH71221 Used In Narrow Band FSK Applications” as well as
to the “TH7122 and TH71221 Cookbook”
CB6
VCC
17 FS0/SDEN
18 VEE_DIG
L0
RM1
CM1
RF
19 FS1/LD
20 VCC_PLL
21 TNK_LO
CF1
22 VEE_PLL
23 LF
CF2
24
Fig. 10: Circuit schematic for direct VCO modulation
3.3.6
Crystal Tuning
A crystal is tuned by the manufacturer to the requested oscillation frequency f0 for a certain load
capacitance CL within the specified calibration
tolerance. The only way to tune this oscillation
frequency is to vary the effective load capacitance
CLeff seen by the crystal.
Figure 8 shows the oscillation frequency of a crystal in dependency on the effective load capacitance. This capacitance changes in accordance
with the logic level of IN_DTA around the specified
load capacitance. The figure illustrates the relationship between the external pulling capacitors
and the frequency deviation.
f
XTAL
C1
fo
C0
CL eff
R1
f min
Fig. 11: Crystal Tuning Characteristic
39010 07122
Rev. 010
L1
f max
Page 17 of 44
CX1 CRO
CX1+CRO
CL
(CX1+CX2) CRO
CX1+CX2+CRO
CL eff
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
4
Description of User Modes
4.1
Stand-alone User Mode Operation
After power up the transceiver is set to stand-alone user mode. In this mode, pins FS0/SDEN and FS1/LD
must be connected to VEE or VCC to set the desired frequency of operation. The logic level at pin FS0/SDEN
must not be changed after power up in order to remain in stand-alone user mode. The default settings of the
control word bits in stand-alone user mode are described in the frequency selection table. Detailed information about the default settings can be found in the tables of section 5.
4.1.1
Frequency Selection
Channel frequency
433.92 MHz
868.3 MHz
315 MHz
915 MHz
FS0/SDEN
1
0
1
0
FS1/LD
0
0
1
1
Reference oscillator frequency
R counter ratio in RX mode (RR)
7.1505 MHz
32
16
18
32
223.45 kHz
446.91 kHz
397.25 kHz
223.45 kHz
1894
1919
766
4047
VCO frequency in RX mode
423.22 MHz
857.60 MHz
304.30 MHz
904.30 MHz
RX frequency
433.92 MHz
868.30 MHz
315.00 MHz
915.00 MHz
32
16
18
32
223.45 kHz
446.91 kHz
397.25 kHz
223.45 kHz
1942
1943
793
4095
VCO frequency in TX mode
433.92 MHz
868.30 MHz
315.00 MHz
915.00 MHz
TX frequency
433.92 MHz
868.30 MHz
315.00 MHz
915.00 MHz
IF in RX mode
10.7 MHz
10.7 MHz
10.7 MHz
10.7 MHz
PFD frequency in RX mode
N counter ratio in RX mode (NR)
R counter ratio in TX mode (RT)
PFD frequency in TX mode
N counter ratio in TX mode (NT)
In stand-alone user mode, the transceiver can be set to Standby, Receive, Transmit or Idle mode (only PLL
synthesizer active) via control pins RE/SCLK and TE/SDTA. The modulation scheme and the LNA gain are
set by pins ASK/FSK and GAIN_LNA, respectively.
4.1.2
Operation Mode
Operation mode
Standby
Receive
Transmit
Idle
RE/SCLK
0
1
0
1
TE/SDTA
0
0
1
1
Note: Pins with internal pull-down
39010 07122
Rev. 010
Page 18 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
4.1.3
4.1.4
4.2
Modulation Type
Modulation type
ASK
FSK
ASK / FSK
0
1
LNA gain
high
low
GAIN_LNA
0
1
LNA Gain Mode
Programmable User Mode Operation
The transceiver can also be used in programmable user mode. After power-up the first logic change at pin
FS0/SDEN enters into this mode. Now full programmability can be achieved via the Serial Control Interface
(SCI).
4.2.1
Serial Control Interface Description
A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in programmable user mode. At each rising edge of the SCLK signal, the logic value on the SDTA pin is written into a
24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches on
the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first two
bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant 24
bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To
program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word
and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the
appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in
Fig. 12 and 13.
SDTA
SCLK
24-BIT
SHIFT REGISTER
22
22
22
2
22
‘00’
A - LATCH
22
A-word
B - LATCH
22
B-word
C - LATCH
22
C-word
D - LATCH
22
D-word
‘01’
SDEN
ADDR DECODER
‘10’
‘11’
22
Fig. 12: SCI Block Diagram
39010 07122
Rev. 010
Page 19 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as
well as in standby mode.
If the transceiver is set from standby mode to any of the active modes (idle, receive, transmit), the SCI settings remain the same as previously set in one of the active modes, unless new settings are done on the SCI
while entering into an active mode.
Invalid
data
SDTA
MSB
bit 23
LSB
bit 22
bit 1
t CH
t CWL tCWH
Invalid
data
bit 0
SCLK
SDEN
t CS
tES
tEW
tEH
Fig. 13: Serial Data Input Timing
5
Register Description
As shown in the previous section there are four control words which stipulate the operation of the whole chip.
In Stand-alone User Mode SUM the intrinsic default values with respect to the applied levels at pins FS0 and
FS1 lay down the configuration of the transceiver. In Programmable User Mode (PUM) the register settings
can be changed via 3-wire interface SCI. The default settings which vary with the desired operating frequency depend on the voltage levels at the frequency selection pins FS0 and FS1 before entering the PUM.
Table 5.1.1 shows the default register settings of different frequency selections. It should be noted that the
channel frequency listed below will be achieved with a crystal frequency of 7.1505 MHz. The following table
depicts an overview of the register configuration of the TH7122.
39010 07122
Rev. 010
Page 20 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
5.1
Register Overview
DATA
WORD
MSB
LSB
PACTRL
1
1
1
0
0
1
0
0
LNAHYST
AFC
OA2
1
1
1
0
1
0
5.1.1
Bit No.
Depends on FS0/FS1 voltage level after power up
default
9
4
3
2
1
0
Bit No.
Depends on FS0/FS1 voltage level after power up
default
9
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
1
0
0
NR
[ 16 : 0 ]
9
8
7
6
5
4
3
2
0
1
0
Bit No.
default
NT
[ 16 : 0 ]
1
Bit No.
default
Depends on FS0/FS1 voltage level after power up
ERTM
[ 1 :0 ]
0
LDTM
[ 1 :0 ]
D
0
MODCTRL
1
5
Depends on FS0/FS1 voltage level after power up
23 22 21 20 19 18 17 16 15 14 13 12 11 10
1
0
BAND
0
VCOCUR
[ 1 :0 ]
C
0
PFDPOL
0
LNACTRL
23 22 21 20 19 18 17 16 15 14 13 12 11 10
1
6
ROMIN
[2:0]
1
ROMAX
[2:0]
1
DELPLL
B
0
Set to 1
1
PKDET
23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
7
RR
[9:0]
LOCKMODE
1
8
RT
[9:0]
1
9
OPMODE
[1:0]
0
LNAGAIN
0
Set to 1
0
TXPOWER
[ 1 :0 ]
0
CPCUR
A
0
MODSEL
0
DATAPOL
0
IDLE
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Default Register Settings for FS0, FS1
FS1
FS0
Channel
frequency
BAND
VCOCUR
[1:0]
RR
[9:0]
NR
[ 16 :0 ]
RT
[ 9 :0 ]
NT
[ 16 : 0 ]
0
0
868.30 MHz
1
11
16d
1919d
16d
1943d
0
1
433.92 MHz
0
01
32d
1894d
32d
1942d
1
0
915.00 MHz
1
11
32d
4047d
32d
4095d
1
1
315.00 MHz
0
00
18d
766d
18d
793d
Note:
d – decimal code
A detailed description of the registers function and their configuration can be found in the following sections.
39010 07122
Rev. 010
Page 21 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
5.1.2
A – word
Name
Bits
RR
[9:0]
Description
Reference divider ratio in RX operation mode
4d .. 1023d
Operation mode
OPMODE
[11:10]
00
01
10
11
#default
Standby mode
Receive mode
Transmit mode
Idle mode
LNA gain
LNAGAIN
[12]
0
1
low LNA gain
high LNA gain
#default
This selection is valid if bit LNACTR (bit 21 in C-word) is set to internal LNA gain control.
not used
[13]
set to ‘1’ for correct function
Output power steps
TXPOWER
[15:14]
00
01
10
11
P1
P2
P3
P4
#default
Set the PA-on condition
PACTRL
[16]
0
1
0
LOCKMODE
PA is switched on if the PLL locks
PA is always on in TX mode
Set the PLL locked state observation mode
before lock only
#default
#default
Locked state condition will be ascertained only one time afterwards the LD signal remains in
high state.
[17]
1
before and after lock
locked state will be observed permanently
Charge Pump output current
CPCUR
[18]
0
1
260 µA
1300 µA
0
1
ASK
FSK
#default
Modulation mode
MODSEL
[19]
#default
This selection is valid if bit MODCTRL (bit 21 in D-word) is set to internal modulation
control.
Input data polarity
0
DTAPOL
[20]
#default
normal
‘0’ for space at ASK or fmin at FSK, ‘1’ for mark at ASK or fmax at FSK
1
inverse
‘1’ for space at ASK or fmin at FSK, ‘0’ for mark at ASK or fmax at FSK
Active blocks in IDLE mode
IDLESEL
39010 07122
Rev. 010
[21]
0
1
only RO active
whole PLL active
Page 22 of 44
#default
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
5.1.3
B – word
Name
Bits
RT
[9:0]
Description
Reference divider ratio in TX operation mode
4d .. 1023d
Set the desired steady state current of the reference oscillator
ROMIN
[12:10]
000
001
010
011
100
101
110
111
0 μA
75 μA
150 μA #default
225 μA
300 μA
375 μA
450 μA
525 μA
The control circuitry regulates the current of the oscillator core
between the values ROMAX and ROMIN. As the regulation input
signal the amplitude on pin RO is used. If the ROMIN value is
sufficient to achieve an amplitude of about 400mV on pin RO the
current of the reference oscillator core will be set to ROMIN.
Otherwise the current will be permanently regulated between
ROMAX and ROMIN. If ROMIN and ROMAX are equal no
regulation of the oscillator current occurs. Please also note the
block description of the reference oscillator in para. 3.1.1
Set the start-up current of the reference oscillator
ROMAX
[15:13]
000
001
010
011
100
101
110
111
0 μA
75 μA
150 μA
225 μA
300 μA
375 μA
450 μA
525 μA #default
Set the start-up current of the reference oscillator core. Please
also note the description of the ROMIN register and the block
description of the reference oscillator which can be seen above.
OA2 operation
OA2
[16]
0
1
#default
disabled
enabled
OA2 can be enabled in FSK receive mode. OA2 is disabled in ASK mode receive.
Internal AFC feature
AFC
[17]
LNAHYST
[18]
0
1
#default
disabled
enabled
Hysteresis on pin GAIN_LNA
0
1
disabled
enabled
0
undelayed start
1
starts after 8 valid RO-cycles
#default
Delayed start of the PLL
DELPLL
[19]
PLL starts at the reference oscillator start-up
#default
PLL starts after 8 valid RO-cycles before entering an active mode to ensure reliable oscillation
of the reference oscillator.
not used
[20]
set to ‘1’ for correct function
RSSI Peak Detector
0
PKDET
[21]
#default
disabled
The RSSI output signal directly feeds the data slicer setup by means of OA1.
1
enabled
In ASK receive mode the RSSI Peak Detector output is multiplexed to pin INT2/PDO.
39010 07122
Rev. 010
Page 23 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
5.1.4
C – word
Name
Bits
NR
[16:0]
BAND
[17]
Description
Feedback divider ratio in RX operation mode
64d .. 131071d
0
1
Set the desired frequency range
recommended at fRF < 500 MHz
recommended at fRF > 500MHz
Some tail current sources are linked to this bit in order to save current for low frequency
operations.
VCO active current
VCOCUR
[19:18]
00
01
10
11
low current (300 µA)
standard current (500 µA)
high1 current (700 µA)
high2 current (900 µA)
Phase Detector polarity
0
PFDPOL
LNACTRL
[20]
negative
#default
VCO
OUTPUT
FREQUENCY
pos
neg
1
positive
0
LNA gain control mode
external LNA gain control
VCO INPUT VOLTAGE
#default
LNA gain will be set via pin GAIN_LNA.
[21]
1
internal LNA gain control
LNA gain will be set via bit LNAGAIN (bit 12 in A-word). Nevertheless pin GAIN_LNA must
be connected to either VCC or VEE.
39010 07122
Rev. 010
Page 24 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
5.1.5
D – word
Name
Bits
NT
[16:0]
ERTM
LDTM
MODCTRL
[18:17]
[20:19]
Description
Feedback divider ratio in TX operation mode
64d .. 131071d
00
01
10
11
Set the unlock condition of the PLL
2 clocks #default
Set the maximum allowed number of reference
4 clocks
(1/fRO) during the phase detector output signals
8 clocks
DOWN) can be in-consecutive.
16 clocks
clocks
(UP &
00
01
10
11
Set the lock condition of the PLL
4 clocks
Set the minimum number of consecutive edges of
16 clocks #default
detector output cycles, without appearance of any
64 clocks
condition.
256 clocks
phase
unlock
0
Set mode of modulation control:
external modulation control
#default
Modulation will be set via pin ASK/FSK.
[21]
1
internal modulation control
Modulation will be set via bit MODSEL (bit 19 in A-word). Nevertheless pin ASK/FSK must be
connected to either VCC or VEE.
39010 07122
Rev. 010
Page 25 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
6
Technical Data
6.1
Absolute Maximum Ratings
Operation beyond absolute maximum ratings may cause permanent damage of the device.
Parameter
Supply voltage
Input voltage
Input RF level
Storage temperature
Junction temperature
Power dissipation
Thermal Resistance
Electrostatic discharge
Electrostatic discharge
Symbol
VCC
VIN
PiRF
TSTG
TJ
Pdiss
RthJA
VESD1
VESD2
Condition / Note
Min
Max
Unit
-0.3
-0.3
-1.0
-0.75
6.0
Vcc+0.3
10
+125
+150
0.25
60
+1.0
+0.75
V
V
dBm
°C
°C
W
K/W
kV
kV
Min
Max
Unit
2.2
-40
5.5
+85
V
ºC
0.3*VCC
V
@ LNA input
-40
human body model, 1)
human body model, 2)
1) all pins, except LF, TNK_LO, VCC_PLL and FS1/LD
2) pins LF, TNK_LO, VCC_PLL and FS1/LD
6.2
Normal Operating Conditions
Parameter
Symbol
Supply voltage
Operating temperature
Input low voltage (CMOS)
pins IN_DTA, ASK/FSK,
RE/SCLK, TE/SDTA, FS0/SDEN,
FS1/LD
Input high voltage (CMOS)
pins IN_DTA, ASK/FSK,
RE/SCLK, TE/SDTA, FS0/SDEN,
FS1/LD
Transmit frequency range
Receive frequency range
VCO frequency
IF range
FSK demodulator operating range
RO frequency
fTX
fRX
fVCO
fIF
fIF_FSK
fRO
PFD comparison frequency
fR
Frequency deviation
Δf
FSK data rate
RFSK
ASK data rate
FM bandwidth
RASK
fm
VCO gain
39010 07122
Rev. 010
fRF= 433.92MHz
fRF= 868.3MHz
Condition
VCC
TA
VIL
VIH
VIL_FS1/LD only
in Stand-alone user
mode
VIH_FS1/LD only
in Stand-alone user
mode
Set by tank configuration
| fRX - fVCO |
Set by crystal
Set by crystal and
R-counter
at FM or FSK
w/ crystal pulling, NRZ
w/ direct VCO mod., NRZ
NRZ
0.7*VCC
300
300
300
0.4
2
3
930
930
930
22
22
12
MHz
MHz
MHz
MHz
MHz
MHz
0.003
1
MHz
±2.5
±80
20
115
40
10
23
55
kHz
kbps
kbps
kbps
kHz
14
28
KVCO
Page 26 of 44
V
MHz/V
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
6.3
DC Characteristics
all parameters under normal operating conditions, unless otherwise stated;
typical values at TA = 23 °C and VCC = 3 V
Parameter
Symbol
Condition
Min
Typ
Max
Unit
50
200
nA
0.3
0.7
mA
3.5
4.8
6.3
7.8
6.1
8.9
7.4
10.2
6.7
9.5
8.0
10.8
8.0
12.8
9.9
14.7
9.0
13.6
10.9
15.5
13.2
16.2
Operating currents
Standby current
ISBY
Standby mode
Reg. BAND
Idle current
1 (> 500 MHz)
IIDLE
1 (> 500 MHz)
Receive supply
current - ASK
Receive supply
current - FSK
Transmit
supply current
@ P1
Transmit
supply current
@ P2
Transmit
supply current
@ P3
Transmit
supply current
@ P4
0 (< 500 MHz)
1 (> 500 MHz)
0 (< 500 MHz)
1 (> 500 MHz)
0 (< 500 MHz)
1 (> 500 MHz)
0 (< 500 MHz)
1 (> 500 MHz)
IRXL_ASK
IRXH_ASK
IRXL_FSK
IRXH_FSK
0 (< 500 MHz)
IP1
1 (> 500 MHz)
0 (< 500 MHz)
IP2
1 (> 500 MHz)
0 (< 500 MHz)
IP3
1 (> 500 MHz)
0 (< 500 MHz)
IP4
1 (> 500 MHz)
Idle mode (RO only),
Reg. IDLESEL = 0
Idle mode,
(whole PLL),
Reg. IDLESEL = 1
ASK Receive mode,
LNA @ low gain
ASK Receive mode,
LNA @ high gain
FSK Receive mode,
LNA @ low gain
FSK Receive mode,
LNA @ high gain
Transmit mode,
Reg. TXPOWER =00,
VPS_PA = 0.3V,
continuous wave
(CW) mode
Transmit mode,
Reg. TXPOWER =01,
VPS_PA = 0.3V,
CW mode
Transmit mode,
Reg. TXPOWER =10,
VPS_PA = 0.3V,
CW mode
Transmit mode,
Reg. TXPOWER =11,
VPS_PA = 0.3V,
CW mode
mA
mA
mA
mA
mA
mA
17.1
20.6
15.2
19.2
19.1
23.9
18.6
23.4
22.5
28.6
23.0
30.6
mA
mA
mA
26.9
36.7
Digital pin characteristics
Input low voltage (CMOS)
pins IN_DTA, ASK/FSK,
VIL
RE/SCLK, TE/SDTA, FS0/SDEN,
FS1/LD
Input high voltage (CMOS)
pins IN_DTA, ASK/FSK,
VIH
RE/SCLK, TE/SDTA, FS0/SDEN,
FS1/LD
39010 07122
Rev. 010
VIL_FS1/LD only
in Stand-alone user
mode
VIH_FS1/LD only
in Stand-alone user
mode
Page 27 of 44
-0.3
0.3*VCC
V
0.7*VCC
Vcc+0.3
V
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Parameter
Symbol
Condition
Min
Typ
Max
Unit
70
120
220
kΩ
Digital pin characteristics
Pull-down Resistor
RPD
pins IN_DTA , RE/SCLK,
TE/SDTA
Low level input leakage current
pins IN_DTA, ASK/FSK,
IIL
RE/SCLK, TE/SDTA, FS0/SDEN,
FS1/LD
High level input leakage current
IIH
pins ASK/FSK, FS0/SDEN,
FS1/LD
IINL_FS1/LD only
in Stand-alone user
mode
μA
-2
IINH_FS1/LD only
in Stand-alone user
mode
2
μA
30
Ω
Analog pin characteristics
MOS switch On resistance
FSK_SW pin
RON
Transmit mode,
if Reg. DTAPOL = 0:
IN_DTA = 0
if Reg. DTAPOL = 1:
IN_DTA = 1
ROFF
Transmit mode,
if Reg. DTAPOL = 0:
IN_DTA = 1
if Reg. DTAPOL = 1:
IN_DTA = 0
1
MΩ
IPU_PDO
ASK Receive mode,
Reg. PKDET = 1
VOUT_DEM > VINT2/PDO
-1.1
mA
Peak detector leakage current
INT2/PDO pin
IL_PDO
ASK Receive mode,
Reg. PKDET = 1
VOUT_DEM =< VINT2/PDO
-2
2
μA
OA input offset voltage
VOS
Receive mode
-25
25
mV
VGAIN_HL
Receive mode,
Reg. LNACTRL = 0,
Reg. LNAHYST = 1
1.0
1.3
1.6
V
VGAIN_LH
Receive mode,
Reg. LNACTRL = 0,
Reg. LNAHYST = 1
1.3
1.6
1.9
V
MOS switch Off resistance
FSK_SW pin
Peak detector pull-up current
INT2/PDO pin
Voltage threshold for high to low
LNA gain transition
GAIN_LNA pin
Voltage threshold for low to high
LNA gain transition
GAIN_LNA pin
10
RSSI characteristics
RSSI voltage at low IFA
input level
VL_RSSI
RSSI voltage at high IFA
input level
VH_RSSI
39010 07122
Rev. 010
Receive mode,
VIN_IFA = 100μV
(CW, 10.7MHz)
Receive mode,
VIN_IFA = 100mV
(CW, 10.7MHz)
Page 28 of 44
0.72
V
1.64
V
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
6.4
PLL Synthesizer Timings
Parameter
Channel
switching time
wide band
tSW_WB
narrow band
tSW_NB
TX – RX switching time
6.5
Symbol
tTX_RX
Condition
Min
BPLL = 20kHz,
ICP = 260µA
BPLL = 2kHz,
ICP = 260µA
IF = 10.7MHz
Typ
Max
Unit
200
µs
500
µs
1
ms
AC Characteristics of the Receiver Part
all parameters under normal operating conditions, unless otherwise stated;
typical values at Ta = 23 °C and VCC = 3 V;
all parameters based on test circuits for FSK (Fig. 14 to 15) and ASK (Fig. 16 to 17), respectively;
Parameter
fRF= 433.92MHz
Input sensitivity
ASK
fRF= 868.3MHz
fRF= 433.92MHz
fRF= 868.3MHz
Symbol
PminL_ASK
PminH_ASK
fRF= 433.92MHz
PminL_FSK
Input sensitivity
FSK
fRF= 868.3MHz
fRF= 433.92MHz
PminH_FSK
fRF= 868.3MHz
fRF= 433.92MHz
Maximum input
signal
ASK
fRF= 868.3MHz
fRF= 433.92MHz
fRF= 868.3MHz
fRF= 433.92MHz
Maximum input
signal
FSK
fRF= 868.3MHz
fRF= 433.92MHz
fRF= 868.3MHz
PmaxL_ASK
BIF = 180kHz, fm = 2kHz
BER ≤ 3⋅10-3
LNA @ low gain
BIF = 180kHz, fm = 2kHz
BER ≤ 3⋅10-3
LNA @ high gain
BIF = 180kHz, fm = 2kHz
Δf = ± 50 kHz
BER ≤ 3⋅10-3
LNA @ low gain
BIF = 180kHz, fm = 2kHz
Δf = ± 50 kHz
BER ≤ 3⋅10-3
LNA @ high gain
LNA @ low gain
PmaxH_ASK LNA @ high gain
PmaxL_FSK
LNA @ low gain
PmaxH_FSK LNA @ high gain
Start-up time - ASK
ton_ASK
Start-up time - FSK
ton_FSK
Spurious emission
Pspur_RX
39010 07122
Rev. 010
Condition
from standby to receive
mode
from standby to receive
mode
referred to receiver
input
Page 29 of 44
Min
Typ
Max
-96
Unit
dBm
-96
-107
dBm
-107
-87
dBm
-87
-105
dBm
-105
-10
dBm
-10
-20
dBm
-20
-10
dBm
-10
-20
dBm
-20
1
1.5
ms
1
1.5
ms
-54
dBm
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
6.6
AC Characteristics of the Transmitter Part
all parameters under normal operating conditions, unless otherwise stated;
typical values at Ta = 23 °C and VCC = 3 V;
all parameters based on test circuits for FSK (Fig. 14 to 15) and ASK (Fig. 16 to 17), respectively;
Parameter
Output power
fRF= 433.92MHz
fRF= 868.3MHz
Output power
fRF= 433.92MHz
fRF= 868.3MHz
Output power
fRF= 433.92MHz
fRF= 868.3MHz
Output power
fRF= 433.92MHz
fRF= 868.3MHz
Symbol
P1
P2
P3
P4
FSK deviation
ΔfFSK
FM deviation
ΔfFM
Modulation frequency FM
PLL reference spurious emission
Harmonic emission
fmod
Pspur_PLL
Pharm
Start-up time
ton_TX
6.7
mode = transmit,
RPS = see para. 7.3
TXPOWER = 00
mode = transmit,
RPS = see para. 7.3
TXPOWER = 01
mode = transmit,
RPS = see para. 7.3
TXPOWER = 10
mode = transmit,
RPS = see para. 7.3
TXPOWER = 11
depends on Cx1, Cx2
and crystal parameters
please refer to the FM
circuit in the cookbook
Min
Typ
Max
-7
dBm
-10
1
dBm
-2
6
dBm
3
10
dBm
9
±2.5
±25
±80
±6
From standby to
transmit mode
Unit
kHz
kHz
1
10
-40
-36
kHz
dBm
dBm
1.5
ms
Serial Control Interface
Parameter
SDTA to SCLK set up time
SCLK to SDTA hold time
SCLK pulse width low
SCLK pulse width high
SCLK to SDEN set up time
SDEN pulse width
SDEN to SCLK hold time
6.8
Condition
Symbol
Condition
tCS
tCH
tCWL
tCWH
tES
tEW
tEH
Min
Max
150
50
100
100
100
100
100
Unit
ns
ns
ns
ns
ns
ns
ns
Crystal Parameters
Parameter
Crystal frequency
Load capacitance
Static capacitance
Equivalent series resistance
Spurious response
39010 07122
Rev. 010
Symbol
fcrystal
Cload
C0
R1
aspur
Condition
fundamental mode, AT
only required for FSK
Page 30 of 44
Min
Max
Unit
3
10
12
15
5
180
MHz
pF
pF
-10
Ω
dB
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
7
Application Circuit Examples
7.1
FSK Application Circuit Programmable User Mode (internal AFC option)
CF2
RX_IN
TX_OUT
RF
CB2
LTX0
CF1
CB6
C0
CTX4
Lock
detect
L0
SDEN
CTX0
C2
C1
3wire bus
SCLK
26
CRX0
L1
SDTA
25
Combining
network
CB7
27
28
FSK
input
29
30
31
32
CB1
CB5
C3
FSK
output
RSSI
C4
CB4
39010 07122
Rev. 010
CERDIS
C5
RP
Page 31 of 44
CB0
VCC
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
FSK Application Circuit Stand-alone User Mode
CF1
CF2
VEE_DIG 18
FS1/LD 19
VCC_PLL 20
VEE_PLL 22
INT2/PDO
INT1
OUT_DEM
RSSI
OUT_DTA
RO 10
IN_DEM
31 VEE_IF
VCC_IF
FSK_SW 11
IN_IFA
CERFIL
RB1
IN_DTA 12
30 IN_MIX
1
2
3
4
5
6
7
8
OUT_MIX
CB5
RX
enable
C3
CB7
ASK/FSK 13
TH7122
29 GAIN_LNA
32
CB1
VCC_DIG 14
27 VEE_LNA
28 OUT_LNA
C1
TX
enable
16
RE/SCLK 15
26 IN_LNA
C2
FS0/SDEN
17
CPS
25 OUT_PA
CRX0
L1
see para. 4.1.1
L0
CTX4
CTX0
Combining
network
CB6
C0
24
LTX0
RF
LF 23
CB2
RPS
RX_IN
TX_OUT
TNK_LO 21
7.2
FSK
input
LX
CX2
CX1
XTAL
9
VEE_RO
FSK
output
RSSI
C4
CB4
CERDIS
C5
RP
CB0
VCC
Fig. 15: Test circuit for FSK operation in Stand-alone User Mode
39010 07122
Rev. 010
Page 32 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
7.3
FSK Test Circuit Component List (Fig. 14 and Fig. 15)
Value @
Value @
Value @
315 MHz 433.92 MHz 868.3 MHz
Value @
915 MHz
Tol.
1.8 pF
0.82 pF
±5%
VCO tank capacitor
2.2 pF
1.8 pF
±5%
LNA output tank capacitor
1.5 pF
1.5 pF
±5%
MIX input matching capacitor
10 nF
10 nF
10 nF
330 pF
330 pF
330 pF
330 pF
±10% data slicer capacitor
±5% demodulator output low-pass
capacitor, depending on data rate
0603
1.5 nF
1.5 nF
1.5 nF
1.5 nF
CB0
1210
10 μF
10 μF
10 μF
10 μF
±20% de-coupling capacitor
CB1
0603
10 nF
10 nF
10 nF
10 nF
±10% de-coupling capacitor
CB2
0603
330 pF
330 pF
330 pF
330 pF
±10% de-coupling capacitor
CB4
0603
10 nF
10 nF
10 nF
10 nF
±10% de-coupling capacitor
CB5
0603
100 nF
100 nF
100 nF
100 nF
±10% de-coupling capacitor
CB6
0603
100 pF
100 pF
100 pF
100 pF
±10% de-coupling capacitor
CB7
0603
100 nF
100 nF
100 nF
100 nF
±10% de-coupling capacitor
CF1
0603
1 nF
1 nF
1 nF
1 nF
CF2
0603
68 pF
120 pF
150 pF
82 pF
±5%
CPS
0603
10 nF
10 nF
10 nF
10 nF
±10% power-select capacitor
CX1
0603
8.2 pF
10 pF
12 pF
12 pF
±5%
RO capacitor for FSK (Δf = ±20 kHz)
CX2
0603
150 pF
56 pF
18 pF
15 pF
±5%
RO capacitor for FSK (Δf = ±20 kHz)
CRX0
0603
100 pF
100 pF
100 pF
100 pF
±5%
RX coupling capacitor
CTX0
0603
10 pF
10 pF
10 pF
10 pF
±5%
TX coupling capacitor
Part
Size
C0
0603
1.2 pF
1.5 pF
C1
0603
3.9 pF
5.6 pF
C2
0603
1.5 pF
1.5 pF
C3
0603
10 nF
C4
0603
C5
Description
±10% RSSI output low pass capacitor
±10% loop filter capacitor
loop filter capacitor
CTX4
0603
12 pF
4.7 pF
2.2 pF
1.8 pF
±5%
TX impedance matching capacitor
RB1
0603
100 Ω
100 Ω
100 Ω
100 Ω
±5%
protection resistor
loop filter resistor
RF
0603
47 kΩ
47 kΩ
33 kΩ
33 kΩ
±5%
RP
0603
3.3 kΩ
3.3 kΩ
3.3 kΩ
3.3 kΩ
±5%
CERDIS loading resistor
RPS
0603
22 kΩ
33 kΩ
47 kΩ
47 kΩ
±5%
power-select resistor
L0
0603
47 nH
22 nH
3.9 nH
3.9 nH
±5%
VCO tank inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
L1
0603
33 nH
15 nH
4.7 nH
4.7 nH
±5%
LTX0
0603
15 nH
15 nH
3.9 nH
3.9 nH
±5%
LX
0603
0Ω
0Ω
10 nH
10 nH
±5%
XTAL
HC49
SMD
7x5
7.1505 MHz
±20ppm cal., ±20ppm temp.
CERFIL
SMD
3.45x3.1
SFECF10M7HA00
B3dB = 180 kHz
CERDIS
SMD
4.5x2
CDSCB10M7GA136
Note:
LNA output tank inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
impedance matching inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
RO inductor
fundamental-mode crystal,
Cload = 10 pF to 15pF, C0, max = 7 pF,
Rm, max = 70 Ω
ceramic filter from Murata,
or equivalent part
ceramic Discriminator from Murata,
or equivalent part
- Antenna matching network according to paragraph 9
39010 07122
Rev. 010
Page 33 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
ASK Application Circuit Programmable User Mode (normal data slicer option)
CF1
CPS
VEE_DIG 18
VCC_DIG 14
INT1
OUT_DEM
RSSI
OUT_DTA
RO 10
INT2/PDO
31 VEE_IF
IN_DEM
FSK_SW 11
1
2
3
4
5
6
7
8
CB7
ASK
input
XTAL CX1
9
VEE_RO
ASK
output
RSSI
C3
CB5
3wire bus
SCLK
IN_DTA 12
30 IN_MIX
OUT_MIX
SDTA
ASK/FSK 13
TH7122
VCC_IF
CERFIL
RB1
FS1/LD 19
27 VEE_LNA
32
CB1
VCC_PLL 20
RE/SCLK 15
29 GAIN_LNA
C1
16
IN_IFA
L1
SDEN
26 IN_LNA
28 OUT_LNA
C2
VEE_PLL 22
25 OUT_PA
CRX0
Lock
detect
L0
CTX4
CTX0
Combining
network
CB6
C0
24
LTX0
RF
LF 23
CB2
RPS
RX_IN
TX_OUT
FS0/SDEN
17
CF2
TNK_LO 21
7.4
C5
CB0
VCC
Fig. 16: Test circuit for ASK operation in Programmable User Mode (normal data slicer option)
Software Settings for ASK
fRO = 8.0000MHz
CPCUR
VCOCUR
Channel
frequency
RR
NR
RT
NT
RX
TX
RX
TX
315.00 MHz
80
3043
8
315
260µA
1300µA
300 µA
900µA
434.00 MHz
80
4233
8
434
260µA
1300µA
300 µA
900µA
915.00 MHz
80
9043
8
915
260µA
1300µA
300 µA
900µA
39010 07122
Rev. 010
Page 34 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
7.5
ASK Test Circuit Component List (Fig. 16)
Part
Size
Value @
315 MHz
Value @
434 MHz
Value @
915 MHz
Tol.
C0
0603
1.5 pF
C1
0603
3.9 pF
1.8 pF
1 pF
±5%
VCO tank capacitor
5.6 pF
1.8 pF
±5%
C2
0603
LNA output tank capacitor
1.5 pF
1.0 pF
1.5 pF
±5%
C3
MIX input matching capacitor
0603
10 nF
10 nF
10 nF
±10%
C5
data slicer capacitor
0603
1.5 nF
1.5 nF
1.5 nF
±10%
RSSI output low pass capacitor
CB0
1210
10 μF
10 μF
10 μF
±20%
de-coupling capacitor
CB1
0603
10 nF
10 nF
10 nF
±10%
de-coupling capacitor
CB2
0603
330 pF
330 pF
330 pF
±10%
de-coupling capacitor
CB5
0603
100 nF
100 nF
100 nF
±10%
de-coupling capacitor
CB6
0603
100 pF
100 pF
100 pF
±10%
de-coupling capacitor
CB7
0603
100 nF
100 nF
100 nF
±10%
de-coupling capacitor
CF1
0603
100 pF
100 pF
100 pF
±10%
loop filter capacitor
CF2
0603
39 pF
39 pF
39 pF
±5%
loop filter capacitor
CPS
0603
1 nF
1 nF
1 nF
±10%
power-select capacitor,
depending on data rate
Description
CX1
0805
18 pF
18 pF
18 pF
±5%
RO capacitor
CRX0
0603
100 pF
100 pF
10 pF
±5%
RX coupling capacitor
CTX0
0603
10 pF
10 pF
10 pF
±5%
TX coupling capacitor
CTX4
0603
12 pF
4.7 pF
1.8 pF
±5%
TX impedance matching capacitor
RB1
0603
100 Ω
100 Ω
100 Ω
±5%
protection resistor
RF
0603
33 kΩ
33 kΩ
33 kΩ
±5%
loop filter resistor
RPS
0603
18 kΩ
33 kΩ
43 kΩ
±5%
L0
0603
47 nH
22 nH
3.9 nH
±5%
L1
0603
33 nH
15 nH
4.7 nH
±5%
LTX0
0603
15 nH
15 nH
3.9 nH
±5%
XTAL
HC49
SMD
7x5
8.0000 MHz
±20ppm cal., ±20ppm temp.
CERFIL
SMD
3.45x3.1
SFECF10M7HA00
B3dB = 180 kHz
Note:
power-select resistor
VCO tank inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
LNA output tank inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
impedance matching inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
fundamental-mode crystal,
Cload = 10 pF to 15pF, C0, max = 7 pF,
Rm, max = 70 Ω
ceramic filter from Murata,
or equivalent part
- Antenna matching network according to paragraph 9
39010 07122
Rev. 010
Page 35 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
ASK Application Circuit Programmable User Mode (peak detector option)
CF1
CPS
VEE_DIG 18
INT2/PDO
INT1
OUT_DEM
RSSI
OUT_DTA
RO 10
IN_DEM
FSK_SW 11
31 VEE_IF
1
2
3
4
5
6
7
8
R1
CB5
3wire bus
SCLK
CB7
ASK
input
IN_DTA 12
30 IN_MIX
OUT_MIX
SDTA
ASK/FSK 13
TH7122
VCC_IF
CERFIL
RB1
FS1/LD 19
VCC_DIG 14
32
CB1
VCC_PLL 20
26 IN_LNA
27 VEE_LNA
29 GAIN_LNA
C1
16
IN_IFA
L1
SDEN
RE/SCLK 15
28 OUT_LNA
C2
VEE_PLL 22
25 OUT_PA
CRX0
Lock
detect
L0
CTX4
CTX0
Combining
network
CB6
C0
24
LTX0
RF
LF 23
CB2
RPS
RX_IN
TX_OUT
FS0/SDEN
17
CF2
TNK_LO 21
7.6
XTAL CX1
9
VEE_RO
R2
ASK
output
RSSI
C5
C6
CB0
VCC
Fig. 17: Test circuit for ASK operation in Programmable User Mode (internal Peak Detector option)
Software Settings for ASK
fRO = 8.0000MHz
CPCUR
VCOCUR
Channel
frequency
RR
NR
RT
NT
RX
TX
RX
TX
315.00 MHz
80
3043
8
315
260µA
1300µA
300 µA
900µA
434.00 MHz
80
4233
8
434
260µA
1300µA
300 µA
900µA
915.00 MHz
80
9043
8
915
260µA
1300µA
300 µA
900µA
39010 07122
Rev. 010
Page 36 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
7.7
ASK Test Circuit Component List (Fig. 17)
Part
Size
Value @
315 MHz
Value @
434 MHz
Value @
915 MHz
C0
0603
1.5 pF
1.8
1 pF
±5%
VCO tank capacitor
C1
0603
3.9 pF
5.6 pF
1.8F
±5%
LNA output tank capacitor
C2
0603
1.5 pF
1.0 pF
1.5 pF
±5%
MIX input matching capacitor
C5
0603
1.5 nF
1.5 nF
1.5 nF
±10%
RSSI output low pass capacitor
C6
0603
100 nF
100 nF
100 nF
±10%
PKDET capacitor
CB0
1210
10 μF
10 μF
10 μF
±20%
de-coupling capacitor
CB1
0603
10 nF
10 nF
10 nF
±10%
de-coupling capacitor
CB2
0603
330 pF
330 pF
330 pF
±10%
de-coupling capacitor
CB5
0603
100 nF
100 nF
100 nF
±10%
de-coupling capacitor
CB6
0603
100 pF
100 pF
100 pF
±10%
de-coupling capacitor
CB7
0603
100 nF
100 nF
100 nF
±10%
de-coupling capacitor
CF1
0603
100 pF
100 pF
100 pF
±10%
loop filter capacitor
CF2
0603
39 pF
39 pF
39 pF
±5%
loop filter capacitor
CPS
0603
1 nF
1 nF
1 nF
±10%
power-select capacitor,
depending on data rate
Tol.
Description
CX1
0805
18 pF
18 pF
18 pF
±5%
RO capacitor
CRX0
0603
100 pF
100 pF
10 pF
±5%
RX coupling capacitor
CTX0
0603
10 pF
10 pF
10 pF
±5%
TX coupling capacitor
CTX4
0603
12 pF
4.7 pF
1.8 pF
±5%
TX impedance matching capacitor
R1
0603
100 kΩ
100 kΩ
100 kΩ
±5%
PKDET resistor
R2
0603
680 kΩ
680 kΩ
680 kΩ
±5%
PKDET resistor
RB1
0603
100 Ω
100 Ω
100 Ω
±5%
protection resistor
RF
0603
33 kΩ
33 kΩ
33 kΩ
±5%
loop filter resistor
RPS
0603
18 kΩ
33 kΩ
43 kΩ
±5%
power-select resistor
VCO tank inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
L0
0603
47 nH
22nH
3.9 nH
±5%
L1
0603
33 nH
15 nH
4.7 nH
±5%
LTX0
0603
15 nH
15 nH
3.9 nH
±5%
XTAL
HC49
SMD
7x5
8.0000 MHz
±20ppm cal., ±20ppm temp.
CERFIL
SMD
3.45x3.1
SFECF10M7HA00
B3dB = 180 kHz
Note:
LNA output tank inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
impedance matching inductor
from Würth-Elektronik (WE-KI series)
or equivalent part
fundamental-mode crystal,
Cload = 10 pF to 15pF, C0, max = 7 pF,
Rm, max = 70 Ω
ceramic filter from Murata,
or equivalent part
- Antenna matching network according to paragraph 9
39010 07122
Rev. 010
Page 37 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
8
Extended Frequency Range
The operating frequency range of 300 MHz to 930 MHz can be covered without the use of an additional VCO
varactor diode. A frequency range extension down to 27 MHz can be realized by adding an external varactor
diode to the VCO tank.
VCC
CRX0
Fig. 18: VCO tank circuit for
extended frequency range
8.1
Part
CB6
Lock
detect
L0
FS1/LD 19
VCC_PLL 20
OUT_PA
TNK_LO 21
25
VEE_PLL 22
CTX0
Combining
network
VD1
C0
CTX4
24
LTX0
RB0
VEE_DIG 18
FS0/SDEN
17
RPS
LF 23
CB2
CF2
CF1
RPS
RX_IN
TX_OUT
R01 C01
RF1
RF
CF2
SDEN
16
26 IN_LNA
RE/SCLK 15
27 VEE_LNA
VCC_DIG 14
28 OUT_LNA
TH7122
SDTA
3wire bus
SCLK
CB7
ASK/FSK 13
VCC
29 GAIN_LNA
Board Component List (Fig. 18)
Size
Value @
27 MHz
Value @
40 MHz
Value @
80 MHz
Value @
144 MHz
Value @
170 MHz
Description
C0
0805
NIP
NIP
NIP
NIP
NIP
VCO tank capacitor
C01
0805
1 nF
1 nF
68 pF
100pF
100 pF
VCO tank capacitor
CB2
VD1
CF1
CF2
CTX4
0603
SOD-323
0605
0605
0605
330 pF
BBY65
1 µF
220 nF
NIP
330 pF
BBY65
1 µF
100 nF
33 pF
330 pF
BB639
1µF
100nF
18pF
330 pF
BB833
1µF
100 nF
10 pF
330 pF
BB535
1µF
100 nF
8.2 pF
de-coupling capacitor
varactor diode
loop filter capacitor
loop filter capacitor
TX impedance matching capacitor
RB0
0605
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
protection resistor
R01
0805
22 Ω
22 Ω
0Ω
0Ω
0Ω
VCO tank resistor
RF
0805
1.8 kΩ
1.8 kΩ
1.8 kΩ
2.7 kΩ
390 Ω
loop filter resistor
RF1
0805
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
loop filter resistor
power-select resistor
RPS
0805
CTX0
CRX0
L0
0805
0805
0805
15 kΩ
10 nF
10 nF
1.2 µH
15 kΩ
10 nF
10 nF
1.0 µH
15 kΩ
10 nF
10 nF
220 nH
22 kΩ
1 nF
1 nF
100 nH
33 kΩ
220 pF
220 pF
47 nH
TX coupling capacitor
RX coupling capacitor
VCO tank inductor
LTX0
CB6
CB7
0805
0805
0805
2.2 µH
10 nF
100 nF
330 nH
10 nF
100 nF
220 nH
10 nF
100 nF
100 nH
1 nF
100 nF
100 nH
1 nF
100 nF
TX impedance matching inductor
de-coupling capacitor
de-coupling capacitor
fR
NT
NR
LO injection
25 kHz
1080
1508
high
25 kHz
1600
2028
high
25 kHz
3200
2772
low
25 kHz
5760
5332
low
100 kHz
1700
1807
high
frequency resolution
NT counter
NR counter
Note: The component values are optimized for the above listed settings of fR, NR and NT. Direct VCO modulation as explained in section 3.3.5 must be applied.
39010 07122
Rev. 010
Page 38 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
9
TX/RX Combining Network
9.1
Board Component List (Fig. 19)
Value @ Value @ Value @ Value @
315
433.92
868.3
915
MHz
MHz
MHz
MHz
Part
Size
CRX0
0603
100 pF
100 pF
100 pF
100 pF
CTX0
0603
10 pF
10 pF
10 pF
10 pF
CTX1
CTX2
CTX4
LRX2
LTX0
LTX1
CB2
0603
0603
0603
0603
0603
0603
0603
10 pF
10 pF
12 pF
82 nH
15 nH
33 nH
330 pF
6.8 pF
6.8 pF
4.7 pF
56 nH
15 nH
33 nH
330 pF
5.6 pF
3.9 pF
2.2 pF
15 nH
3.9 pF
10 nH
330 pF
4.7 pF
3.9 pF
1.8 pF
15 nH
3.9 nH
10 nH
330 pF
ƒ
ƒ
No TX/RX switch required
Direct connection to λ/4 antenna possible
CB2
RF input
RF output
VCC
CTX4
LTX0
LTX1
CTX0
50Ω
CTX2
CTX1
25
OUT_PA
26
IN_LNA
LRX2
CRX0
Fig. 19: Combining network schematic
9.2
Typical LNA S-Parameters in Receive Mode
Low Gain Mode
Frequency
Re[S11]
Im[S11]
Re[S12]
Im[S12]
Re[S21]
Im[S21]
Re[S22]
Im[S22]
27 MHZ
40 MHz
80 MHz
170 MHz
315 MHz
433 MHz
868 MHz
915 MHz
0.9137
0.9137
0.9116
0.9005
0.8702
0.8278
0.6035
0.5729
-0.0194
-0,0302
-0.0625
-0.1310
-0.2510
-03347
-0,5771
-05964
6.38E-005
6.28E-005
8.45E-005
2.26E-004
4.86E-004
8.33E-004
1.79E-003
4.43E-003
2.27E-004
3.41E-004
6.94E-004
1.47E-003
2.54-E003
3.32E-003
4.50E-003
4.43E-003
-0.4167
-0.4085
-0.3970
-0.3703
-0.3500
-0.2958
-0.0639
-0.0388
0.0365
0.0445
0.0672
0.1281
0.1921
0.2550
0.3517
0.3515
0.9986
0.9983
0.9974
0.9945
0.9851
0.9734
0.8085
0.8872
-0.0140
-0.0204
-0.0400
-0.0846
-0.1560
-0.2146
-0.4242
-0.4463
Note:
input and output of the LNA are connected to 50 Ω ports without matching elements
High Gain Mode
Frequency
Re[S11]
Im[S11]
Re[S12]
Im[S12]
Re[S21]
Im[S21]
Re[S22]
Im[S22]
27 MHZ
40 MHz
80 MHz
170 MHz
315 MHz
433 MHz
868 MHz
915 MHz
0.8418
0.8422
0.8387
0.8196
0.7657
0.6994
0.3924
0.3620
-0.0194
-0.0340
-0.0747
-0.1563
-0.2997
-0.3853
-0.5397
-0.5409
1.40E-004
1.51E-004
1.87E-004
3.61E-004
5.85E-004
9.07E-004
7.90E-004
4.18E-004
2.64E-004
3.70E-004
7.07E-004
1.47E-003
2.43E-003
3.11E-003
4.15E-003
4.20E-003
-4.0770
-4.0750
-4.0400
-3.8190
-3.5870
-3.0640
-0.7692
-0.5246
0.1658
0.2628
0.5498
1.2100
1.8370
2.4650
3.3460
3.3190
0.9994
0.9992
0.9984
0.9952
0.9806
0.9664
0.8844
0.8738
-0.0141
-0.0208
-0.0415
-0.0882
-0.1607
-0.2192
-0.4150
-0.4344
Note:
input and output of the LNA are connected to 50 Ω ports without matching elements
39010 07122
Rev. 010
Page 39 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
9.3
LNA Input Impedances in Transmit Mode
Mode
LNA off, Pin LNA is shorted
IN_LNA
Frequency
RS
LS
Frequency
RS
LS
27 MHz
40 MHz
80 MHz
170 MHz
33.6 Ω
33.6 Ω
33.6 Ω
34.3 Ω
1.9 nH
2.1 nH
2.4 nH
2.2 nH
315 MHz
433 MHz
868 MHz
915 MHz
32.7 Ω
33.6 Ω
35.7 Ω
36.6 Ω
2.2 nH
2.3 nH
2.7 nH
2.8 nH
39010 07122
Rev. 010
Page 40 of 44
26
RS
LS
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
10
Package Description
The device TH7122 is RoHS compliant.
D
D1
A
24
17
16
25
E
b
e
E1
32
9
1
8
A2
A1
12° +1°
0.25
(0.0098)
c
L
12° +1°
Fig. 4:
.10 (.004)
LQFP32 (Low profile Quad Flat Package)
All Dimension in mm, coplanaríty < 0.1mm
min
max
E1, D1
E, D
A
A1
A2
e
b
c
L
α
7.00
9.00
1.40
1.60
0.05
0.15
1.35
1.45
0.8
0.30
0.45
0.09
0.20
0.45
0.75
0°
7°
0.053
0.057
0.031
0.012
0.018
0.0035
0.0079
0.018
0.030
0°
7°
All Dimension in inch, coplanaríty < 0.004”
min
max
0.276
0.354
0.055
0.063
0.002
0.006
10.1 Soldering Information
•
39010 07122
Rev. 010
The device TH7122 is qualified for MSL3 with soldering peak temperature 260 deg C
according to JEDEC J-STD-20
Page 41 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
11
Reliability Information
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture
sensitivity level, as defined in this specification, according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
•
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)”
Wave Soldering SMD’s (Surface Mount Devices)
•
EN60749-20
“Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat”
Solderability SMD’s (Surface Mount Devices)
•
EIA/JEDEC JESD22-B102
“Solderability”
For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be
agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
12 ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
39010 07122
Rev. 010
Page 42 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
Your Notes
39010 07122
Rev. 010
Page 43 of 44
Data Sheet
Feb/09
TH7122
27 to 930MHz
FSK/FM/ASK Transceiver
13
Disclaimer
1) The information included in this documentation is subject to Melexis intellectual and other property rights.
Reproduction of information is permissible only if the information will not be altered and is accompanied
by all associated conditions, limitations and notices.
2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in
clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered
documentation.
3) The information furnished by Melexis in this documentation is provided ’as is’. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation.
4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any
responsibility in connection herewith.
5) Melexis reserves the right to change the documentation, the specifications and prices at any time and
without notice. Therefore, prior to designing this product into a system, it is necessary to check with
Melexis for current information.
6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation.
7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application.
8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on
www.melexis.com.
© Melexis NV. All rights reserved.
For the latest version of this document, go to our website at:
www.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa:
Americas:
Asia:
Phone: +32 1367 0495
E-mail: [email protected]
Phone: +1 603 223 2362
E-mail: [email protected]
Phone: +32 1367 0495
E-mail: [email protected]
ISO/TS 16949 and ISO14001 Certified
39010 07122
Rev. 010
Page 44 of 44
Data Sheet
Feb/09