Application Note Transceiver TH7122x High Speed TH7122 and TH71221 High Speed Data Communication 1 Introduction to Direct Modulation The data sheet for the TH7122x transceiver shows FSK generation by switching the load capacitance of the crystal. Since the data signal modulates the reference frequency of the PLL we can call it Indirect Modulation. This method works well for data rates up to about 20kbps NRZ (non-return to zero) code or 10kbps RZ (return to zero) code and it has the advantage that the FSK response is down to DC. The drawback is that the PLL bandwidth must be about 5 times the modulation frequency fm so the reference frequency fR must be high to suppress the reference spurs sufficiently. As a rule of thumb the reference frequency of the PLL should be at least 10 times the loop bandwidth. Since the reference frequency is equal to the channel spacing in an integer-N PLL as used in the TH7122x, the transmitter can only set a limited number of different channels. For a data rate of 10kbps RZ, the channels should thus be spaced ≥500kHz. If high speed data transmission (i.e. high FSK data rates) or small channel spacing is desired, another technique should be used. This method is called Direct Modulation of the VCO because the VCO control voltage is combined with the modulation signal in order to modulate outside the loop bandwidth. In this case, the PLL does not track on the modulation signal. Therefore, is necessary to use a small PLL bandwidth and to modulate the VCO outside the loop bandwidth. As a rule of thumb the lowest data signal frequency should be 10 times higher than the loop bandwidth. The only drawback is that the FSK response does not extend to DC (unless it is combined with modulation of the reference). In this case, the data format should not contain a DC component. A bi-phase or Manchester code can be used. If a data burst using NRZ code is used, the ratio of 1’s to 0’s must be kept small. The channel switching time also increases because of the smaller PLL bandwidth. 2 PLL setup In order to design the PLL filter, it is first necessary to know the phase detector constant and VCO tuning sensitivity around the desired frequency. There are two ways to determine KVCO : 1. Tune the VCO with a variable voltage from a potentiometer (e.g. 10kΩ) or power supply and measure the output frequency with a counter or spectrum analyzer. This can be done by simply connecting the variable voltage via a 100kΩ resistor to pin 23 of the TH7122x. Using the software for programming the TH7122x with a personal computer, set it to transmit mode, VCOCUR to “11 - high2 current” and PACTRL to ‘1’ so the PA is always on. Adjust the tuning voltage and measure the output frequency. 2. Set-up the TH7122x to operate at the desired frequency in transmit mode using the loop filter on the evaluation board. Connect a high-impedance digital voltmeter to pin 23, the charge pump output. Using the TH7122x software, set the transmitter to frequencies around the operating frequency, and measure the tuning voltage at each frequency. Note capacitive and resistive loading at pin 23 should be as low as possible since this node influences the over-all stability of the PLL directly. A tuning curve taken on a 433.92MHz evaluation board looks is shown in Fig. 1. In this example it can be seen that the slope of the tuning voltage around 434MHz is typically about 22MHz/Volt. Expressed in an angular relation the KVCO yields in K VCO = 2π ⋅ 22 MHz rad 1 = 138.23 ⋅ 10 6 . V s V It should be noted that the VCO gain also highly depends on the layout of the PCB. Every additional parasitic capacitive loading of the VCO tank will lower the tuning range of the internal varactor diode and therefore the gain of the VCO. 39011 07122 02 Rev. 002 Page 1 of 8 AN7122x-HS July/04 Application Note Transceiver TH7122x High Speed A second design parameter is the gain of the phase detector KPD. This parameter is proportional to the charge pump current ICP which is 260µA by default. The charge pump current can be changed by setting the CPCUR bit in the ‘A’ word register. The phase detector constant is expressed as I CP µA . = 41.38 2π rad K PD = Loop filter Voltage / V (pin 23) As we will see below the 2π term cancels out since KPD and KVCO are always multiplied together. 3.0 2.0 1.0 0.0 390 400 410 420 430 440 450 460 VCO frequency / MHz Fig. 1: TH7122 VCO tuning curve for 430MHz center frequency The recommended loop filter topology is a 2nd order as depicted in Fig. 2. From the filter transfer function F(s) we can obtain a zero and a non-DC pole frequency1: ωz = 1 R F ⋅ C F1 ωP = C F1 + C F2 C F1 ⋅ C F2 ⋅ R F The 3dB bandwidth of the PLL in a closed loop configuration is approximately the transit frequency ωT of the loop filter. Since CF2 is much smaller than CF1 in most of the cases, ωT can be approximated as described in [4]: ωT ≈ K PD ⋅ K VCO ⋅ R F C F1 ⋅ N C F1 + C F 2 ≈ K PD ⋅ K VCO ⋅ R F N 1 Investigation of the details of the PLL behaviour would require more space than this application note allows. A more detailed analysis of the PLL behaviour can be found in references [1-3]. 39011 07122 02 Rev. 002 Page 2 of 8 AN7122x-HS July/04 Application Note Transceiver TH7122x High Speed Where N represents the value of the feedback divider. For a stable loop the available phase margin is of importance. It should be between 45 and 70 degrees. To ensure enough phase margin at the transit frequency ωT, the zero frequency should be located M times below and the pole frequency M times above ωT. As mentioned in [4] a factor M of four gives a phase margin of approximately 60 degrees. With M = 2.5 the phase margin will be approximately 45 degrees. Fig. 2: 2nd order Loop filter K PD K VCO s + LF F(s) CF1 CF2 RF By using these equations the loop-filter elements can be easily obtained: RF = N ⋅ ωT K PD ⋅ K VCO C F1 = M R F ⋅ ωT C F2 = 1 M ⋅ R F ⋅ ωT This approximation is quite accurate for calculating the loop filter elements. Normally the step size between the available component values is larger than the error using this calculation method, so that there is no need to use the more complex exact formulas. Nevertheless the exact calculation can be found in [1-3]. Example: If a channel step size of 100kHz is used, a feedback divider of N = 4340 is necessary to achieve a desired operating frequency of 434MHz. Assume a narrow loop frequency, ωT of about 2π ⋅ 250 Hz because of the external VCO modulation. In case of direct modulation of the VCO as a rule of thumb the lowest data signal frequency should be 10 times higher than the loop frequency. To insure loop stability we want a phase margin of about 45 degrees, so the factor M is 2.5. With the equations above and the calculated gains KPD and KVCO the loop filter elements result in: C F1 = 1.2 µF 39011 07122 02 Rev. 002 C F2 = 220 nF Page 3 of 8 R F = 1.2 kΩ AN7122x-HS July/04 Application Note Transceiver TH7122x High Speed As shown in Fig. 3 the modulation is applied through the parallel combination of CM1 and RM1. CM1 is required to compensate for the parallel RC time constant CF2 ⋅ RF. So the following relationship should be fulfilled: R M1 ⋅ C M1 = R F ⋅ C F 2 Knowing the slope of the VCO control voltage, RM can be calculated: ⎞ ⎛ V ⋅K R M1 = R F ⎜⎜ DTAH VCO − 1 ⎟⎟ 4π ∆f ⎠ ⎝ Where VDTAH is the high level of the data input signal and ∆f the FSK peak deviation. 3 Receiver Set-Up The standard receiver circuit used in the data sheet works fine up to about 40kbps NRZ, but needs to be modified for higher data rates. Since the OUT_DEM (pin 6) has a 275kΩ output resistance, any stray capacitance on the output will limit the frequency response, so it needs to be loaded to reduce its equivalent resistance. Since the nominal output voltage from the demodulator is ½ VCC, equal resistors to ground and VCC should be used. These are shown as RL1 and RL2 in Fig. 3. The bandwidth of CERRES, the FM discriminator resonator, is quite small when the load resistor, RP is 10k. For low data rates, this is satisfactory, but for a modulating frequency of 50kHz and above it results in a loss of signal and low detector output. For modulating frequencies of 115kHz, RP was made 2.2kΩ to get a higher detector frequency response. The overall result with the receivers shown in Fig. 3 is a sensitivity of –95dBm (4µV) for a BER of about 450 ⋅10-6 at 115kHz modulating frequency. One note when setting up the receiver: In the standard evaluation boards which are set-up for FSK modulation by crystal pulling via CX1 and CX2, the reference oscillator is either above or below the center frequency depending on the state of the FSK_SW on pin 11. In receive mode, the on-chip FSK modulation switch on pin FSK_SW is off, so the crystal oscillator is above the center frequency. If the VCO is below the incoming frequency, the intermediate frequency (IF) is low by the FSK offset frequency. For this reason, the discriminator resonator must be tuned low to operate properly in receive. CP0 across the resonator tunes the discriminator. When using direct VCO modulation the crystal load capacitor CX1 is set such that the crystal oscillator and hence the VCO operates at the center of the channel. Therefore, the IF will also be at its center frequency (10.7MHz). Because of this, CP0 must be reduced to tune the discriminator. In this case, it has been changed to 10pF. 39011 07122 02 Rev. 002 Page 4 of 8 AN7122x-HS July/04 Application Note VCC GND GND SDTA SDEN SCLK IN_DTA GND OUT_DTA GND RSSI GND OUT_DEM GND Transceiver TH7122x High Speed 2 1 4 3 2 1 4 3 2 1 4 3 2 1 12 3 CX1 RO 10 IN_DTA 12 FSK_SW 11 ASK/FSK 13 RL2 OUT_DTA 8 RSSI 7 OUT_DEM 6 18 VEE_DIG 19 FS1/LD 20 VCC_PLL 21 TNK_LO VCC_IF 2 24 RPS CTX4 CB2 LTX0 CRX0 LRX2 C2 CTX2 50 C5 C3 RL1 R RP CB5 1 IN_IFA CERDIS RL0 CB4 CERFIL C1 VCC CTX1 CTX0 32 OUT_MIX 23 LF 31 VEE_IF 3 30 IN_MIX IN_DEM 29 GAIN_LNA 22 VEE_PLL 26 IN_LNA CF2 4 OUT_PA CF1 INT2/PDO 25 RF INT1 5 TH7122 28 OUT_LNA CM1 27 VEE_LNA L0 RM1 C4 LTX1 L1 CB1 VCC VCC_DIG 14 FS0/SDEN 17 RE/SCLK 15 16 CB6 9 XTAL CB7 VEE_RO 12 3 RE/SCLK 12 3 TE/SDTA ASK/FSK RS2 RS3 RS1 12 3 FS0/SDEN 12 3 FS1/LD CB0 TX_OUT RX_IN Fig. 3: TH7122x circuit schematic for direct VCO modulation 39011 07122 02 Rev. 002 Page 5 of 8 AN7122x-HS July/04 Application Note Transceiver TH7122x High Speed 3.1 Component Values for Fig. 3 Part Size Value @ 315 MHz Value @ Value @ 433.92 MHz 868.3 MHz Value @ Tol. Description 915 MHz C1 0603 5.6 pF 4.7 pF 1.5 pF 1.0 pF ±5% LNA output tank capacitor C2 0603 1.5 pF 1.5 pF 1.5 pF 1.5 pF ±5% MIX input matching capacitor C3 0805 10 nF 10 nF 10 nF 10 nF ±5% data slicer capacitor C4 0805 0 – 39 pF 0 – 39 pF 0 – 39 pF 0 – 39 pF demodulator output low-pass ±10% capacitor, optionally C5 0805 1.5 nF 1.5 nF 1.5 nF 1.5 nF ±10% RSSI output low pass capacitor CB0 1210 10 µF 10 µF 10 µF 10 µF ±20% de-coupling capacitor CB1 0603 330 pF 330 pF 330 pF 330 pF ±10% de-coupling capacitor CB2 0805 330 pF 330 pF 330 pF 330 pF ±10% de-coupling capacitor CB4 0603 10 nF 10 nF 10 nF 10 nF ±10% de-coupling capacitor CB5 0603 100 nF 100 nF 100 nF 100 nF ±10% de-coupling capacitor CB6 0603 100 pF 100 pF 100 pF 100 pF ±5% CB7 0603 100 nF 100 nF 100 nF 100 nF ±10% de-coupling capacitor CF1 0805 TBD 1.2 µF 1.2 µF TBD ±5% loop filter capacitor CF2 0603 TBD 220 nF 220 nF TBD ±5% loop filter capacitor CM1 0603 TBD 390 pF 390 pF TBD ±5% modulation capacitor RO capacitor for FSK de-coupling capacitor CX1 0805 TBD 33 pF 33 pF TBD ±5% CP0 0805 10 - 12 pF 10 - 12 pF 10 - 12 pF 10 - 12 pF ±5% CERRES tuning capacitor CRX0 0603 100 pF 100 pF 100 pF 100 pF ±5% RX coupling capacitor CTX0 0603 100 pF 100 pF 100 pF 100 pF ±5% TX coupling capacitor CTX1 0805 12 pF 5.6 pF 3.9 pF 3.3 pF ±5% TX impedance matching capacitor CTX2 0805 12 pF 4.7 pF 4.7 pF 4.7 pF ±5% TX impedance matching capacitor CTX4 0603 12 pF 4.7 pF 3.3 pF 3.3 pF ±5% TX impedance matching capacitor loop filter resistor RF 0603 TBD 1.2 kΩ 1.2 kΩ TBD ±5% RL0 0603 390 Ω 390 Ω 390 Ω 390 Ω ±5% CERFIL loading, optionally RL1 0603 100 kΩ 100 kΩ 100 kΩ 100 kΩ ±5% demodulator output loading demodulator output loading RL2 0603 100 kΩ 100 kΩ 100 kΩ 100 kΩ ±5% RM1 0603 TBD 680 kΩ 680 kΩ TBD ±5% modulation resistor, adjust for ∆f RP 0603 2.2 KΩ 2.2 KΩ 2.2 KΩ 2.2 KΩ ±5% CERRES loading resistor RPS 0603 27 kΩ 33 kΩ 47 kΩ 62 kΩ ±5% power-select resistor RS1...RS3 0603 10 kΩ 10 kΩ 10 kΩ 10 kΩ ±5% protection resistor L0 0603 56 nH 33 nH 3.9 nH 3.9 nH ±5% VCO tank inductor L1 0603 27 nH 15 nH 3.9 nH 3.9 nH ±5% LNA output tank inductor LRX2 0603 100 nH 56 nH 10 nH 10 nH ±5% RX impedance matching inductor LTX0 0603 15 nH 15 nH 3.9 nH 3.9 nH ±5% TX impedance matching inductor LTX1 0603 33 nH 27 nH 8.2 nH 8.2 nH ±5% TX impedance matching inductor XTAL HC49 SMD 7.1505 MHz (or 8.000MHz) ±20ppm calibration, ±20ppm temperature CERFIL SMD type SFECV10M7JA00 @ BIF2 = 150 kHz, ±40kHz CERDIS SMD type CDSCB10M7GA136 39011 07122 02 Rev. 002 Page 6 of 8 fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70 Ω ceramic filter from Murata, or equivalent part ceramic discriminator, from Murata, or equivalent part AN7122x-HS July/04 Application Note Transceiver TH7122x High Speed Your Notes 39011 07122 02 Rev. 002 Page 7 of 8 AN7122x-HS July/04 Application Note Transceiver TH7122x High Speed References [1] [2] [3] [4] Ulrich L. Rohde: “Microwave and Wireless Synthesizers”, John Wiley & Sons, New York, 1997 Floyd. M. Gardner: “Phaselock Techniques”, John Wiley & Sons, New York, 1979 Behzad Razavi: “Monolithic Phase-Locked Loops and Clock Recovery Circuits - Theory and Design”, IEEE Press, 1996 J. Craninckx and M. Steyaert: “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998 For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: All other locations: Phone: +32 1367 0495 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] ISO/TS16949 and ISO14001 Certified 39011 07122 02 Rev. 002 Page 8 of 8 AN7122x-HS July/04