MachXO2-1200HC Control Development Kit User Guide March 2015 EB60_1.6 MachXO2-1200HC Control Development Kit User Guide Introduction Thank you for choosing the Lattice Semiconductor MachXO2™-1200HC Control Development Kit! This guide describes how to start using the MachXO2-1200HC Control Development Kit, an easy-to-use platform for rapidly prototyping system control designs using MachXO2 PLDs. Along with the evaluation board and accessories, this kit includes a pre-loaded control system-on-chip (Control SoC) design that demonstrates board diagnostic functions including I/O control, voltage monitoring, time-stamps and data logging to non-volatile memory. The Power Manager II ispPAC®-POWR1014A and 8-bit LatticeMico8™ microcontroller are featured in the board and demonstration design. The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and bill of materials for the MachXO2-1200HC Control Evaluation Board. Note: Static electricity can severely shorten the lifespan of electronic components. See the MachXO2-1200HC Control Development Kit QuickSTART Guide for handling and storage tips. Features The MachXO2-1200HC Control Development Kit includes: • MachXO2-1200HC Control Evaluation Board – The MachXO2-1200HC Control Evaluation Board features the following on-board components and circuits: – MachXO2 LCMXO2-1200HC-csBGA132 PLD. The board is designed for density migration, allowing a higher-density MachXO2 device (up to 4000 LUTs) to be assembled on the board. - Part number LCMXO2-1200HC-C-EVN is populated with the R1 silicon. For more information on the R1 to Standard migration refer to the AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices. – Power Manager II POWR1014A mixed-signal PLD – 4 Mbit SPI Flash memory – microSD (micro Secure Digital) memory socket – 60-ball VFBGA footprint for LPDDR memory. When populated, 128-Mbit LPDDR memory will be added to the board. – Current and voltage sensor circuits – Voltage ramp circuits – Electret microphone – Audio amplifier and Delta-Sigma ADC – PWM analog output circuit – Audio output channel – Up to two DVI sources and one DVI output – Up to two 7:1 LVDS sources and one 7:1:VDS output – Expansion header for JTAG, SPI, I2C and PLD I/Os – LEDs and switches – Standard USB cable for device programming – RS-232/USB and JTAG/USB interface – RoHS-compliant packaging and process – AC adapter (international plugs) • Pre-loaded Reference Designs and Demo – The kit includes the pre-loaded Control SoC demo design that integrates several Lattice reference designs including: the LatticeMico8 microcontroller, master WISHBONE bus controller, soft Delta-Sigma ADC, SPI master controller, UART peripheral, Embedded Block RAM and additional control functions. • USB connector Cable – A mini B USB port provides a communication and debug port via a USB-to-RS-232 physical channel and programming interface to the MachXO2 JTAG port. 2 MachXO2-1200HC Control Development Kit User Guide • AC Adapter (international plugs) with 5 V DC output, center positive. • QuickSTART Guide – Provides information on connecting the MachXO2-1200HC Control Evaluation Board, installing Windows hardware drivers, and running the Control SoC demo. Figure 1 shows the top side of the MachXO2-1200HC Control Evaluation Board with comments on the specific features that are designed in the board. Figure 1. MachXO2-1200HC Control Evaluation Board, Top Side DVI Video Output 7:1 LVDS Video Output GSR Push-button 5V Power Indicator MachXO2 DIP Switches Electret Microphone 2x20 GPIO Header Speaker/Headphone Jack MachXO2-1200/4000 AC-DC Adapter Jack microSD Socket ADC Input (J9: Pin 2) POWR1014A JTAG Device Select (J6), MachXO2 Position Shown 7:1 LVDS Video Source (Channel Link) MachXO2 LED Field DVI Video Source USB 2.0 Interface Socket Note: The bill of materials of this board has the following limitations: • Video Source 1 is available in both DVI and 7:1 LVDS interfaces. Video Source 2 is not populated. • LPDDR memory component is not populated. This feature will be populated with greater MachXO2 device density on the board. • The initial MachXO2 device that is assembled on the board is LCMXO2-1200HC. The footprint is compatible with greater device densities and an LCMXO2-4000HC device is planned to be populated in future versions of the board. Lattice Semiconductor Devices MachXO2 This board features a 3.3 V MachXO2 PLD packaged in a 132-ball csBGA package. This package allows density migration to devices as large as 4340 LUTs. A complete description of this device can be found in DS1035, MachXO2 Family Data Sheet. Power Manager II This board also features a Power Manager II mixed-signal PLD. The POWR1014A device serves as a general-purpose power supply monitor, reset generator, sequence controller, and high-voltage FET drivers. More information about Power Manager II devices can be found on the Lattice web site at www.latticesemi.com/products/powermanager. 3 MachXO2-1200HC Control Development Kit User Guide Software Requirements You should install the following software before you begin developing designs for the evaluation board: • Lattice Diamond™ 1.2 or higher • ispVM™ System 17.9.1 or higher Control SoC Demonstration Design The Control System-on-Chip (SoC) demonstration illustrates the use of the LatticeMico8 microcontroller, peripherals, and firmware integrated to provide system control features such as power supply sequencing, voltage monitoring, data logging to nonvolatile memory, I/O control, embedded block RAM utilization, UART communication and PLL status monitoring. • The Power Manager II device sequences the power-up of voltage rails on the board and performs reset distribution. • LatticeMico8 executable program initializes the peripherals that are embedded in the SoC design. During initialization, LatticeMico8 uploads the user menu on the HyperTerminal of a PC. • Users interact with LatticeMico8 and the board through the HyperTerminal of a PC. Figure 2. Control SoC Demo Block Diagram MachXO2 Control Evaluation Board MachXO2-1200 PC USB/ RS232 UART Timer/ Counter LatticeMico8 Microcontroller LEDs/ DIP Switches WISHBONE Bus Soft ADC Master SPI Analog Signal SPI Flash Embedded Block RAM Power management is handled in two phases by the MachXO2-1200HC Control Evaluation Board system: 1. Power On – After power is supplied to the board and the 3.3 V rail is stable, the POWR1014A sequences four supply rails. Two circuits demonstrate the voltage ramp of 2N7002E power MOSFETs using the high-voltage (HVOUT) outputs and two demonstrate power rail enable of VCC_CORE and VCCP of the MachXO2 using digital outputs. Next, the POWR1014A asserts the MachXO2 reset. Finally, the POWR1014A enters a supply monitoring state. Note: SW2 should be set to the off position or the cycle will be repeated. 2. Post Power On – During the second phase of power management, the board’s “condition” is monitored. Power supply rail voltage, and current is monitored by the POWR1014A. If any supply rail fails, the POWR1014A asserts a reset for the MachXO2. MachXO2 Function – After the reset is de-asserted, LatticeMico8 initializes the peripherals embedded in the MachXO2 device and uploads the user menu onto the HyperTerminal window of a PC. 4 MachXO2-1200HC Control Development Kit User Guide Figure 3. HyperTerminal User Menu Users interact with LatticeMico8 microcontroller and the board by selecting the available options in the HyperTerminal menu. The available options are: • ‘m’ – This option will re-display the main menu anytime during the demonstration. • ‘a’ – This option will sample the voltage in the pin #2 of header J9. By default, the node is biased at 1.65 V, which is half of the VCCIO = 3.30 V. The voltage will be displayed in the HyperTerminal window. The ADC input voltage should be limited to the range 0 to 3.0 V to avoid device damage. • ‘s’ – This option will read the device ID of the SPI Flash on the board and display it in the HyperTerminal. The resulting ID is hexadecimal 0x44, which corresponds to AT25DF041A device. • ‘t’ – This option samples and displays the elapsed time since the reset was de-asserted. • ‘r’ - This option samples the DIP switches (reference designator SW1) on the board and displays the data in the HyperTerminal. Users can change the DIP switches on the board and press ‘r’ to display the new value. • “0-9” – These are BCD numerical values that can be typed on the keyboard. The value will be received by LatticeMico8, which will update the LEDs (D0-D3) on the board. • ‘l’ – This is a lower case ‘L’ character. Pressing ‘l’ will sample the voltage in pin #2 of header J9 and log the data in the SPI Flash device on the board. The WRITE page pointer will increment when ‘l’ is pressed. The initial value of the page pointer after power-up or after a reset is 0. • ‘d’ – This option will read the data from SPI Flash device and display it on the HyperTerminal window. The READ page pointer will increment when ‘d’ is pressed. The initial value of the page pointer after power-up or after a reset is 0. • ‘c’ – This option will clear (reset) the WRITE and READ page pointers. • ‘e’ – This selection will perform a bulk-erase of the Flash memory in the SPI Flash device. Setting up the Board Drivers and Firmware Before you begin, you will need to obtain the necessary hardware drivers for Windows from the Lattice web site. 1. Browse to the www.latticesemi.com/MachXO2-control-kit and locate the hardware device drivers for the USB interface. 5 MachXO2-1200HC Control Development Kit User Guide 2. Download the ZIP file to your system and unzip it to a location on your PC. Linux Support: The USB interface drivers for the evaluation board are included in Linux kernel 2.4.20 or greater including distributions compatible with Lattice Diamond design software (Red Hat Enterprise v.3, v.4 or Novell SUSE Enterprise v.10). The Control SoC Demo is preprogrammed into the MachXO2-1200HC Control Evaluation Board, however over time it is likely that your board will be modified. To download the demo source files and reprogram the MachXO2-1200HC Control Evaluation Board: 1. Download demo application source code from www.latticesemi.com/mxo2-control-kit. 2. Use .\Demo_MachXO2_Control_SoC\project\control_soc_demo.jed to restore the MachXO2280 Control SoC demo design. 3. Use .\Demo_PM_Control_BM\project\bm_demo.jed to restore the POWR1014A Board Management demo design. Connecting to the MachXO2-1200HC Control Evaluation Board 1. Plug the AC-DC adopter to an outlet. 2. Power the board by inserting the AC-DC adopter into the power jack with reference designator J11. Once the connection is made, a red LED with reference designator D12 will illuminate. 3. Connect the evaluation board to your PC using the USB cable provided. The USB connector in the board has reference designator J5. 4. If you are prompted, “Windows may connect to Windows Update”, select No, not this time from available options and click Next to proceed with the installation. 5. Choose the Install from specific location (Advanced) option and click Next. 6. Select Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created earlier. Select the CDM 2.04.06 WHQL Certified folder and click OK. 7. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message indicating that the installation was successful. Programming the PLDs The three-pin header with reference designator J6 is used to select between the JTAG port of the MachXO2 or POWR1014A device. Installing a jumper in pins 1 and 2 of J6 will select the JTAG port of the POWR1014A device. Installing a jumper in pins 2 and 3 of J6 will select the JTAG port of the MachXO2 device. Pin 1 of header J6 is marked on the silkscreen of the board with a white triangle as shown in Figure 4. This example shows the jumper installed in pins 2 and 3 of the J6 header and the JTAG port of the MachXO2 device has been selected. 6 MachXO2-1200HC Control Development Kit User Guide Figure 4. J6 Header Used for Selecting the JTAG Port of the PLDs Using ispVM System software, users can scan and perform JTAG operations, including programming, with the MachXO2 and POWR1014A devices. Setting Up Windows HyperTerminal You will use a terminal program to communicate with the evaluation board. The following instructions describe the Windows HyperTerminal program which is found on most Windows PCs. You may use another terminal program if desired although setup will be different. Windows 7 does not include HyperTerminal. Tera Term has been verified to work with Windows 7. For Linux, Minicom is a good alternative. Note: This step uses the procedure for Windows XP users. Steps may vary slightly if using another Windows version. 1. From the Start menu, select Control Panel > System. The “System Properties” dialog appears. 2. Select the Hardware tab and click Device Manager. The “Device Manager” dialog appears. Figure 5. Device Manager – COM Port 3. Expand the Ports (COM & LPT) entry and note the COM port number for the USB Serial Port. 4. From the Start menu, select Programs > Accessories > Communications > HyperTerminal. The HyperTerminal application and a “Connection Description” dialog appear. 7 MachXO2-1200HC Control Development Kit User Guide Figure 6. New Connection – COM Port 5. Specify a Name and Icon for the new connection. Click OK. The “Connect To” dialog appears. 6. Select the COM port identified in Step 3 from the Connect using: list. Click OK. Figure 7. Selecting the COM Port 7. The “COMn Properties” dialog appears where n is the COM port selected from the list. 8. Select the following Port Settings and click OK. Bits per second: 115200 Data bits: 8 Parity: None Stop bits: 1 Flow control: None Figure 8. COM Port Properties 8 MachXO2-1200HC Control Development Kit User Guide 9. The HyperTerminal window appears. 10. From the MachXO2-1200HC Control Evaluation Board, press the reset push-button with reference designator S1. The Control SoC demo main menu appears. Setting Up Linux Minicom Minicom is a terminal program found with most Linux distributions. It can be used to communicate with the MachXO2-1200HC Control Evaluation Board. To setup Minicom: 1. Check active serial ports: #dmesg | grep tty Note the tty label assigned to the USB port 2. From a command prompt, start Minicom: #minicom –s The configuration menu appears. 3. Highlight Serial port setup and press Enter. Serial port settings appear. 4. Press A (Serial Device). Specify the active serial device noted in Step 1 and press Enter. 5. Press E (Bps/Par/Bits). Specify 115200, None, 8 and press Enter. 6. Press F (Hardware Flow Control). Specify None and press Enter. 7. Press Esc. The configuration menu appears. 8. Select Save setup as dfl. Minicom saves the port setup as the new default. 9. Select Exit. The Minicom interface appears. 10. From the evaluation board, press the S1 push-button (GSR).The Control SoC demo main menu appears. Ordering Information Description MachXO2-1200HC Control Development Kit Ordering Part Number LCMXO2-1200HC-C-EVN 9 China RoHS Environment-Friendly Use Period (EFUP) MachXO2-1200HC Control Development Kit User Guide Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version March 2015 1.6 Change Summary Updated Features section. Added “center positive” to AC Adapter description. Updated Technical Support Assistance information. March 2013 01.5 Document title changed from MachXO2 Control Development Kit User’s Guide to MachXO2-1200HC Control Development Kit User’s Guide. Updated power management handling information in the Control SoC Demonstration Design section. Added reference to Appendix A on how to use the Crystal OSC (X2). June 2012 01.4 Added Appendix C, Limitations. February 2012 01.3 Updated document with new corporate logo. December 2011 01.2 Updated Bill of Materials list. July 2011 01.1 Updated Features list with information on migration from MachXO21200-R1 to Standard (non-R1) devices. April 2011 01.0 Initial release. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 11 A B C SPI 4Mbit 5 Page 7 2x20 Header D JTAG Chain UART & USB PORT Page 3,5 Board Power Managment Voltage Monitor High Voltage Drivers Page 8 MachXO2 Control Board Architecture 5 Page 4 Page 6 Page 4 4 Page 7 DVI Conn Page 11 3 DVI to 7:1LVDS Conversion DVI Conn MachXO2 3 7:1LVDS RX 7:1LVDS TX 7:1LVDS to DVI Conversion GPIO Page 9 RESET 7:1LVDS Conn UART SW & LEDs ispPAC POWR1014A Power Manager II I2C Bus GPIO SPI Bus 4 DVI Conn 2 Page 7 Page 7 Page 8 Page 8 Page 12 Page 12 7:1LVDS Conn Page 10 DVI to 7:1LVDS Conversion Page 13,14 ADC-DAC DAC: Page 12 ADC: Page 14 7:1LVDS Conn 2 Date: Size B Title Tuesday, February 15, 2011 Document Number MachXO2 Control Board Architecture Crystal SW & LEDs LPDDR 128Mb SD Flash Audio OUT Audio IN Sheet 1 1 2 of 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Appendix A. Schematic Figure 9. Architecture 12 A B C D J11 DI PWR_JACK 1 2 3 VCC5 IO20 IO19 0_01uF DI C108 5 VCC33 C33 10uF DI 1 2 3 4 BYPASS NC GND INPUT OUTPUT SENSE NC_1 ~SD 9 U17 LP3879MR_1_2 DI 5 6 7 8 9 Linear VREG Step Down 3.3V to 1.2V Rail 5V Input AC-DC Jack - 5V DI 4 R200 10K VCC33 VCC12 4 C106 10uF DI Q6 BSS138LT1 VCC_CORE DI R81 10K VCC33 PM_OUT8 3 3 [4,5] 2 DI R122 470 C54 10uF DI 3 IN U11 2 4 1 DI NCP1117ST33 GND OUT TAB DI C53 22uF VCC33 2 Date: Size B Title IN 2 4 1 DI NCP1117ST18 GND OUT TAB Tuesday, February 15, 2011 Document Number MachXO2 Control Board Power VCC33, VCC18, VCC12 C66 10uF DI 3 U12 DI Sheet C65 22uF Linear VREG Step Down 3.3V to 1.8V Rail DI VCC5 Linear VREG Step Down 5V to 3.3V Rail D12 LED 5 3 VCC18 VCC33 1 of 1 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 10. VCC33, VCC18, VCC12 A B C D VCC_CORE 5 VCCIO33 PM_IN1 PM_IN2 PM_IN3 PM_IN4 SCL SDA 44 46 47 48 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 39 38 19 17 18 16 22 21 25 26 27 28 32 33 34 35 36 37 VMON1 HVOUT2 HVOUT1 C83 1uF DI 1KDI C35 1uF DI R196 1KDI R195 1 1 R198 200 DI Q2 2N7002E DI VCC33 R179 200 DI Q5 2N7002E DI VCC33 VMON8 VMON7 4 ispPAC-POWR1014A DI SCL SDA TDISEL ATDI TDI TMS TCK TDO IN1 IN2 IN3 IN4 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 U7 Voltage Ramp Circuit SCL SDA PM_TDI PM_TMS PM_TCK PM_TDO [7,14] [7,14] [6] [6] [6] [6] [14] PM_IN1 [14] PM_IN2 [7] VMON9 [7] VMON10 [5] ICCIO33_Sense [5] ICCIO18_Sense [5] ICC_Sense 4 IO18 HVOUT1 HVOUT2 30 31 7 42 43 40 PM_PLDCLK PM_MCLK PM_SMBA_OUT3 PM_LED0 PM_LED1 PM_LED2 PM_LED3 PM_OUT8 PM_OUT9 PM_OUT10 PM_OUT11 PM_OUT12 PM_OUT13 PM_OUT14 HVOUT1 HVOUT2 C99 0_1uF DI VCC33 PM_LED0 PM_LED1 PM_LED2 PM_LED3 LED LED LED LED D10 D9 D8 D7 DI DI DI DI RN4 RN2_4_470 DI PM LEDs GNDA GNDD GNDD PLDCLK MCLK RESETB 13 12 11 10 9 8 6 5 4 3 2 1 15 14 C89 0_1uF DI SMBA_OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 VCC33 23 41 29 45 24 20 VCCD VCCD VCCA VCCINP VCCPROG VCCJ POWER MANAGER II 3 2 3 2 8 7 6 5 1 2 3 4 13 [7] [7] [3,5] [5] [7,14] [14] [14] [14] 3 VCC33 PM_IN3 PM_IN4 SW DIP_2 DI SW2 PM DIP Switch PM DIP SWITCH PM_PLDCLK [7,14] PM_MCLK [7,14] PM_OUT8 PM_OUT9 XO2_RESETn PM_OUT11 PM_OUT12 PM_OUT13 PM_OUT14 PM_SMBA_OUT3 [14] HVOUT1 HVOUT2 C107 0_1uF DI 3 DI 10K R164 DI 10K R163 5 2 2 Date: Size B Title Power ispPAC-POWR1014A Tuesday, February 15, 2011 Document Number MachXO2 Control Board Sheet 1 1 4 of 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 11. ispPAC-POWR1014A A B C PM_OUT8 C142 10uF DI [4] PM_OUT9 ICC_P 4 IO9 5 DI ZDT758 Q7A R59 1 DI R58 0 DNI VCC12 C143 10uF DI IO8 ICCIO33_P 2 R67 1K DI ZDT758 Q7B 7DI R235 2 DI 5 IO14 ICCIO18_P VCC18 R148 2 DI IO15 ICCIO18_N VCCIO18 IO11 IO7 ICC_N VCC_CORE ICCIO33_N VCCIO33 MachXO2 - ICCIO18 Current R60 220 DI VCC33 MachXO2 - ICCIO33 Current C142, C143 to limit Vcc, Vccio ramp rates to data sheet spec. [3,4] DI R219 220 R232 1K DI VCC33 3 6 D MachXO2 Power Rails MachXO2 - Core Current 1 8 4 4 R197 2K DI R192 3_92K DI 3 9 - ICCIO33_N DI 100 R185 10 + ICCIO33_P R191 100 DI 6 - ICC_N DI 100 R206 5 + ICC_P R201 100 DI 3 VCC33 4 VCC33 11 4 11 8 C38 0_01uF DI R190 3_92K DI U16C AD8604ARZ 0_1uF DI C46 C41 0_01uF DI R204 2K DI AD8604ARZ 7 U16B 0_1uF DI C44 ICCIO33_Sense ICC_Sense [4] [4] 2 Date: Size B Title ICCIO18_N ICCIO18_P R193 3_92K DI 13 12 2 3 - + - + Tuesday, February 22, 2011 Document Number MachXO2 Control Board Power Current Sense DI 100 R184 R194 100 DI Current Sense 2 VCC33 4 VCC33 11 4 14 11 5 U16A Sheet 14 5 C91 0_01uF DI R189 3_92K DI AD8604ARZ U16D 0_1uF DI C105 AD8604ARZ 1 of 1 1 14 Rev A ICCIO18_Sense [4] A B C D MachXO2-1200HC Control Development Kit User Guide Figure 12. Power Current Sense A B C119 0.1uF J5 C126 0.1uF MH1 MH2 CASE CASE CASE CASE NC GND DD+ VCC C27 0.1uF 10 11 6 7 8 9 4 5 2 3 1 USB_MINI_B DI 1 2 C 1 2 5 VCC33 R79 100K DI SHLD_Debug 0_01uF VBUS 8 7 6 5 U21 CS CLK DI DO 93LC56-SO8 VCC NU ORG VSS C32 DI DI R63 1 2 3 4 0 R68 DI 2 2k2 R203 10k 0 Dm Dp R240 1 R202 10k The USB interface draws no power from the USB bus. It is self-powered. 1 2 1 2 1 2 FT_EECS FT_EECLK FT_EEDATA R241 10k 4 C29 18pF VCC18FT 2 1 2 1 12MHZ 3 G1 G2 1 X3 3 4 C31 0.1uF cc0402 50 14 7 8 49 VCC33 13 3 2 63 62 61 C23 18pF C104 0.1uF 3 C48 0.1uF cc0402 FT2232H 3 VCC33 PWREN# BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 C82 0.1uF cc0402 C85 0.1uF cc0402 SUSPEND# FTDI High-Speed USB TEST OSCO OSCI EECS EECLK EEDATA REF RESET# DM DP VREGOUT VREGIN U20 FT2232HL FT_EECS FT_EECLK FT_EEDATA 2 C145 0.1uF C144 4u7 6 R56 1 12k 1% 2 R199 1 2k2 1 C28 10u L3 2 1 600ohm 500mA VCC33 VCC33 1 2 1 2 2 1 2 D 1 2 AGND 10 2 1 12 37 64 VCORE VCORE VCORE USB Port: CPLD Configuration & USB<->UART Communication 4 1 2 4 9 VPHY VPLL 1 2 1 2 20 31 42 56 VCCIO VCCIO VCCIO VCCIO GND GND GND GND GND GND GND GND 1 5 11 15 25 35 47 51 1 2 36 60 48 52 53 54 55 57 58 59 38 39 40 41 43 44 45 46 26 27 28 29 30 32 33 34 16 17 18 19 21 22 23 24 1 2 15 C30 0.1uF cc0402 1 2 5 1 2 3 R249 10k R205 4_7K DI VBUS Jumper_2way DI J6 VCC33 0 DI 0 DI R36 R37 R38 R39 R78 R75 2 0 DI 0 DI 0 DI 0 DI 2 VCC33 11 3 10 16 5 8 13 2 C109 0_1uF DI U5 2S1 2S2 1S1 1S2 12 14 7 9 4 6 15 1 R82 STG3693QTR 3S1 123SEL 3S2 4SEL 4S1 4S2 GND D1 D2 D3 D4 VCC 0 DI R83 0 DI 0 DI Date: Size C Title 0 DI R87 R76 PM_TCK XO2_TCK Tuesday, February 15, 2011 Document Number MachXO2 Control Board 1 XO2_TMS PM_TMS R55 4_7K DI Sheet [7,13,14] [4] [13] [4] [13,14] [4] [7,13,14] [4] R54 4_7K DI XO2_TDO PM_TDO XO2_TDI PM_TDI Configuration USB Port USB_UART_TX [14] USB_UART_RX [14] XO2_TMS PM_TMS PM_TDO XO2_TDI XO2_TDO 0 DI 0 DI 0 DI R62 R61 R71 PM_TDI R65 4_7K DI R88 4_7K DI R89 4_7K DI 68 XO2_TCK 68 PM_TCK 0 DI DI DI R85 4_7K DI R70 R80 R86 PM_TMS XO2_TMS PM_TDI XO2_TDI PM_TDO XO2_TDO PM_TCK XO2_TCK R84 4_7K DI VCC33 1 6 R66 4_7K DI of 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 13. Configuration USB Port 16 A B C D XO2_LED0 XO2_LED1 XO2_LED2 XO2_LED3 VCC12 [4] VMON10 [4] VMON9 [14] XO2_GPIO_0 [14] XO2_GPIO_1 [14] XO2_GPIO_2 [14] XO2_GPIO_3 [14] XO2_GPIO_4 [14] XO2_GPIO_5 [14] XO2_GPIO_6 [14] XO2_GPIO_7 [13] TDO_HDR [13] TDI_HDR [6,13,14] TMS_HDR [6,13,14] TCK_HDR LED D1 5 VCC33 VMON10 VMON9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 CON40A DNI 2x20x100mil J4 RN1 RN2_4_470 DI DI DI DI DI XO2_GPIO_0 XO2_GPIO_1 XO2_GPIO_2 XO2_GPIO_3 XO2_GPIO_4 XO2_GPIO_5 XO2_GPIO_6 XO2_GPIO_7 VCC33 XO2_LED0 XO2_LED1 XO2_LED2 XO2_LED3 LED D2 2x20 Header [14] [14] [14] [14] LED LED D4 D3 XO2 LEDs 8 7 6 5 1 2 3 4 5 SCL SDA XO2_GPIO_10 XO2_GPIO_9 XO2_GPIO_8 XO2_SPI_CLK XO2_SPI_IN XO2_SPI_OUT HVOUT2 PM_OUT14 PM_PLDCLK PM_MCLK HVOUT1 XO2_GPIO_11 XO2_ADC_IN VCC18 4 2 1 DI [4] SCL SDA XO2_GPIO_10 XO2_GPIO_9 XO2_GPIO_8 XO2_SPI_CLK XO2_SPI_IN XO2_SPI_OUT [4,14] [4,14] [14] [14] [14] [8,14] [8,14] [8,14] HVOUT2 [4] PM_OUT14 PM_PLDCLK [4,14] PM_MCLK [4,14] HVOUT1 XO2_GPIO_11 [14] XO2_ADC_IN [14] [4,14] XO2_RESETn 3 4 XO2 Global Reset S1 Reset Push-Button Switch 4 DI DI X2 2 1 VCC C11 12pF DI 1K R4 OUTPUT X1 10K DI 2 3 4 DI [14] [14] [14] [14] R2 1M DI X_2 SW0 SW1 SW2 SW 3 C8 0_1uF DI VCC33 R3 0 DNI IO2 X_1 IO3 SW0 SW1 SW2 SW3 X_2 X_1 4-DIP Switch [14] [14] R127 10K DI 2 R126 10K DI VCC33 2 R125 10K DI Date: Size B Title 1 2 3 4 R124 10K DI CT1934MS-ND 8 7 6 5 Tuesday, February 15, 2011 Document Number MachXO2 Control Board SW, LED, Crystal, Header DI SWDIP_4 SW1 Note: For more information on how to use the Crystal OSC (X2), refer to. AN8080, Using a Discrete Crystal as a PLD Clock Source. 3 CTS-CB3LV-3C-25MHz GND EOH R1 25 MHz OSC DI C4 12pF 1 HCM49 24.000MABJ-UT 24 MHz Crystal C63 0_1uF DI R128 10K VCC33 3 Sheet 1 1 7 of 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 14. Software, LED, Crystal, Header A B C D 8 7 3 4 8 7 3 4 5 [14] uSD_DAT2 [14] uSD_DAT3 [14] uSD_CMD [14] uSD_CLK [14] uSD_DAT0 [14] uSD_DAT1 S C D Q 1 6 5 2 S C D Q 1 6 5 2 uSD_DAT2 uSD_DAT3 uSD_CMD uSD_CLK uSD_DAT0 uSD_DAT1 1 2 3 5 7 8 microSD Socket DAT2 CD/DAT3 CMD CLK DAT0 DAT1 U1 4 VSS VDD XO2_SPI_CS0 XO2_SPI_CLK XO2_SPI_IN XO2_SPI_OUT XO2_SPI_CS0 XO2_SPI_CLK XO2_SPI_IN XO2_SPI_OUT Package: UDFN AT25DF041A-MH-B Vcc Reset W Vss U15 AT25DF041A-SH-B Vcc Reset W Vss U14 Package: SOIC8 (WIDE) Micro SD Card Socket C74 0_1uF DI VCC33 VCC33 (Refer to Appendix C. Limitations) 4MBit SPI 4 6 4 C81 0_1uF DI VCC33 XO2_SPI_CS0 XO2_SPI_CLK XO2_SPI_IN XO2_SPI_OUT [14] [7,14] [7,14] [7,14] 3 3 LPDDR_A0 LPDDR_A1 LPDDR_A2 LPDDR_A3 LPDDR_A4 LPDDR_A5 LPDDR_A6 LPDDR_A7 LPDDR_A8 LPDDR_A9 LPDDR_A10 LPDDR_A11 LPDDR_A12 H8 H9 G7 LPDDR_BA0 LPDDR_BA1 LPDDR_WEn LPDDR_DQ0 LPDDR_DQ1 LPDDR_DQ2 LPDDR_DQ3 LPDDR_DQ4 LPDDR_DQ5 LPDDR_DQ6 LPDDR_DQ7 RN2 R186 0 DI G9 G8 LPDDR_RASn LPDDR_CASn NC NC NC WE# BA0 BA1 RAS# CAS# CS# CK CK# CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 9 8 10 7 11 6 12 5 13 4 14 3 2 15 16 1 RN1_8_10K DNI F7 F3 D9 H7 G2 G3 G1 LPDDR_CSn LPDDR_CK LPDDR_CKn LPDDR_CKE J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3 C79 0_1uF DI VCC18 LDM LDQS UDM UDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LPDDR_LDM LPDDR_LDQS F8 E8 LPDDR_LDM [14] LPDDR_LDQS [14] 10K DI 10K DI VCC18 [14] [14] [14] [14] [14] [14] [14] [14] VCC18 MT46H16M16LFBF U6 Lower Byte Mask & Strobe R159 R158 LPDDR_DQ0 LPDDR_DQ0 LPDDR_DQ1 LPDDR_DQ1 LPDDR_DQ2 LPDDR_DQ2 LPDDR_DQ3 LPDDR_DQ3 LPDDR_DQ4 LPDDR_DQ4 LPDDR_DQ5 LPDDR_DQ5 LPDDR_DQ6 LPDDR_DQ6 LPDDR_DQ7 LPDDR_DQ7 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 RN3 RN1_8_10K DI F2 E2 A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2 1 2 Date: Size B Title Tuesday, February 15, 2011 Document Number MachXO2 Control Board Memory LPDDR, SD, SPI Sheet 1 8 of Empty External Pull-UP resistors. The internal XO2 resistors are used for bias. [14] LPDDR_WEn [14] LPDDR_BA0 [14] LPDDR_BA1 C75 0_1uF DI LPDDR_A0 LPDDR_A1 LPDDR_A2 LPDDR_A3 LPDDR_A4 LPDDR_A5 LPDDR_A6 LPDDR_A7 LPDDR_A8 LPDDR_A9 LPDDR_A10 LPDDR_A11 LPDDR_A12 C72 0_01uF DI [14] LPDDR_RASn [14] LPDDR_CASn [14] LPDDR_CSn [14] LPDDR_CK [14] LPDDR_CKn [14] LPDDR_CKE [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] C71 0_001uF DI LPDDR - 128Mb (4 Meg x 4 banks x 8 data) 2 A9 F9 K9 A7 B1 C9 D1 E9 VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSSQ VSSQ VSSQ VSSQ 17 A1 F1 K1 A3 B9 C1 E1 5 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 15. Memory LPDDR, SD, SPI 18 A B C D J2 Mounting_R Mounting_L DDC_Gnd_26 RxIn0RxIn0Gnd RxIn0+ Sense USB/DDC_Gnd RxIn1RxIn1Gnd RxIn1+ DDC/SDA RxIn2RxIn2Gnd RxIn2+ USB+ USB_Shield USBDDC/SCL RxClkInRxClkInGnd RxClkIn+ USB_+5VDC DDC_+5VDC RxIn3RxIn3Gnd RxIn3+ DDC_Gnd_1 10226-1A10PE-ND J1 27 28 26 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 5 Analog_Ground_1 Analog_Ground_2 MDR Connector DVI_I Analog_Horizontal_Sync Analog_Red Analog_Green Analog_Blue TMDS_Clock+ TMDS_Clock- TMDS_Clock_Shield TMDS_Data5TMDS_Data5+ TMDS_Data0/5_Shield TMDS_Data0TMDS_Data0+ Hot_Plug_Detect +5V_Power GND(for +5V) TMDS_Data3TMDS_Data3+ TMDS_Data1/3_Shield TMDS_Data1TMDS_Data1+ Analog_Vertical_Sync DDC_Clock DDC_Data TMDS_Data4TMDS_Data4+ TMDS_Data2/4_Shield TMDS_Data2TMDS_Data2+ DVI-Integrated DVI Connector DDC_CLK DDC_DATA [10,11] [10,11] C5 C6 C4 C1 C2 C3 23 24 22 20 21 19 17 18 16 14 15 DI Hot_Plug_Video 0 98 97 19 28 45 58 76 18 29 43 57 78 5 39 68 6 38 67 2 9 100 1 4 7 3 TFP401A PGND PVDD OGND OGND OGND OGND OGND OVDD OVDD OVDD OVDD OVDD DGND DGND DGND DVDD DVDD DVDD PDN PDON OCK_INV DFO PIXS STAGN ST 0 R5 R233 Channel Link - RX MDR_TX_OUT3_P_1 MDR_TX_OUT3_N_1 MDR_TX_CLKOUT_P_1 10K 10K R22 10K DNI DI DI DI DI DI DI DI DI DI DNI DI DNI SCDT VSYNC HSYNC DNI NS_STB_1 OCK_INV_1 ST_1 STAGN_1 PIXS_1 DFO_1 NS_STB_1 PWRDWN_1 PDON_1 PDN_1 DE CTL3 CTL2 CTL1 OCK_INV_1 CTL3_1 CTL2_1 CTL1_1 QO7 QO6 QO5 QO4 QO3 QO2 QO1 QO0 ODCK QE7 QE6 QE5 QE4 QE3 QE2 QE1 QE0 QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 QE15 QE14 QE13 QE12 QE11 QE10 QE9 QE8 QO23 QO22 QO21 QO20 QO19 QO18 QO17 QO16 QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 8 47 48 46 42 41 40 44 56 55 54 53 52 51 50 49 17 16 15 14 13 12 11 10 66 65 64 63 62 61 60 59 27 26 25 24 23 22 21 20 77 75 74 73 72 71 70 69 37 36 35 34 33 32 31 30 4 R27 IO5 IO4 DI 470 SCDT_1 2 Q1 BSS138LT1 3 (1) Gate SOT-23 3 (2) Source (3) Drain VCC33 32 31 TXCLKIN_1 PWRDWN_1 50 30 28 27 25 24 23 22 20 19 18 16 15 14 12 11 10 8 7 6 4 3 2 56 55 54 52 51 TXIN27_1 TXIN26_1 TXIN25_1 TXIN24_1 TXIN23_1 TXIN22_1 TXIN21_1 TXIN20_1 TXIN19_1 TXIN18_1 TXIN17_1 TXIN16_1 TXIN15_1 TXIN14_1 TXIN13_1 TXIN12_1 TXIN11_1 TXIN10_1 TXIN9_1 TXIN8_1 TXIN7_1 TXIN6_1 TXIN5_1 TXIN4_1 TXIN3_1 TXIN2_1 TXIN1_1 TXIN0_1 LVDS Translator D5 LED_Green 3 TOP Package View 1 LED will be ON when link is active. (SCDT high) DVDD_1 SCDT_1 TXIN15_1 TXIN14_1 TXIN18_1 CTL3_1 CTL2_1 CTL1_1 TXCLKIN_1 TXIN6_1 TXIN4_1 TXIN13_1 TXIN12_1 TXIN9_1 TXIN8_1 TXIN26_1 TXIN25_1 B G TXIN3_1 TXIN2_1 TXIN24_1 TXIN22_1 TXIN21_1 TXIN20_1 TXIN19_1 TXIN23_1 R TXIN1_1 TXIN0_1 TXIN17_1 TXIN16_1 TXIN11_1 TXIN10_1 TXIN5_1 TXIN27_1 ODCK opposite edge from Video Source 2 R237 10K R242 10K 10K R239 R19 R244 10K 10K R18 R236 10K R20 MDR_TX_OUT2_P_1 MDR_TX_CLKOUT_N_1 10K DVDD_1 R21 10K 0 0 R6 U2 RSVD (Tie high) TXIN7_1 R8 Supporting Circuits TI_PVDD_1 TI_OVDD_1 DVDD_1 PDN_1 PDON_1 OCK_INV_1 DFO_1 PIXS_1 STAGN_1 ST_1 99 Clk-in B-in G-in R-in EXT_RES AVDD RxCP RxCN AGND Rx0P Rx0N AGND AVDD AGND Rx1P Rx1N AVDD AGND AVDD Rx2P Rx2N AGND MDR_TX_OUT2_N_1 MDR_TX_OUT1_P_1 MDR_TX_OUT1_N_1 MDR_TX_OUT0_P_1 MDR_TX_OUT0_N_1 TMDS_1_CLK_P TMDS_1_CLK_N TMDS_1_DATA0_N TMDS_1_DATA0_P R248 DVDD_1 93 94 92 90 91 96 TMDS_1_CLK_P TMDS_1_CLK_N TMDS_1_DATA0_P TMDS_1_DATA0_N 85 86 TMDS_1_DATA1_P TMDS_1_DATA1_N 87 88 89 82 83 84 12 13 [14] Hot_Plug_Video 79 80 81 TI_AVDD_1 TMDS_1_DATA2_P TMDS_1_DATA2_N 95 TMDS_1_DATA1_N TMDS_1_DATA1_P DDC_CLK DDC_DATA TMDS_1_DATA2_N TMDS_1_DATA2_P 11 9 10 8 6 7 4 5 3 1 2 DVI - TMDS Decoder Video Input Source 1 : DVI or MDR for direct 7:1LVDS 4 R-even R-odd G-even G-odd B-even B-odd 5 DS90CR287 PWRDWN TxCLKIN TxIN27 TxIN26 TxIN25 TxIN24 TxIN23 TxIN22 TxIN21 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 U19 10uF DI C21 10uF DI C121 10uF DI C122 GND GND GND GND GND VCC VCC VCC VCC PLLGND PLLGND PLLVCC LVDSGND LVDSGND LVDSGND LVDSVCC TxCLKOUTN TxCLKOUTP TxOUT3N TxOUT3P TxOUT2N TxOUT2P TxOUT1N TxOUT1P TxOUT0N TxOUT0P 0_1uF DI C16 0_1uF DI C115 0_1uF DI C123 5 13 21 29 53 1 9 17 26 33 35 34 36 43 49 44 40 39 0_001uF DI C137 0_001uF DI C125 C113 0_001uF DI C5 0_01uF DI TI_OVDD_1 0_01uF DI C6 DVDD_1 0_01uF DI C124 TI_AVDD_1 NS_STB_1 DVDD_1 NS_PVCC_1 NS_LVCC_1 TX_CLKOUT_N_1 TX_CLKOUT_P_1 2 VCC33 TX_OUT3_N_1 TX_OUT3_P_1 TX_OUT3_N_1 TX_OUT3_P_1 38 37 10uF DI C22 10uF DI C20 10uF DI C140 MDR_TX_CLKOUT_N_1 R212 MDR_TX_CLKOUT_P_1 R211 MDR_TX_OUT3_N_1 R210 MDR_TX_OUT3_P_1 R209 MDR_TX_OUT2_N_1 R214 MDR_TX_OUT2_P_1 R213 MDR_TX_OUT1_N_1 R216 MDR_TX_OUT1_P_1 R215 MDR_TX_OUT0_N_1 R218 MDR_TX_OUT0_P_1 R217 TX_CLKOUT_N_1 R225 TX_CLKOUT_P_1 R224 R223 R222 R227 R226 TX_OUT2_N_1 TX_OUT2_P_1 TX_OUT2_N_1 TX_OUT2_P_1 42 41 R231 R230 R229 R228 TX_OUT0_N_1 TX_OUT0_P_1 TX_OUT1_N_1 TX_OUT1_P_1 TX_OUT1_N_1 TX_OUT1_P_1 TX_OUT0_N_1 TX_OUT0_P_1 Resistor MUX 46 45 48 47 2 0 0 0_1uF DI C112 0_1uF DI C19 0_1uF DI C141 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0_001uF DI C135 0_001uF DI C17 Date: Size C Title 0_01uF DI C15 Video Input 1 1 Tuesday, February 15, 2011 Document Number MachXO2 Control Board 0_001uF DI C14 NS_PVCC_1 0_01uF DI C18 NS_LVCC_1 0_01uF DI C136 TI_PVDD_1 DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DI DI DI DI DI DI DI DI DI DI 1 [14] [14] [14] [14] [14] [14] [14] [14] Sheet 9 XO2_CLKIN_1_N [14] XO2_CLKIN_1_P [14] XO2_IN3_1_N XO2_IN3_1_P XO2_IN2_1_N XO2_IN2_1_P XO2_IN1_1_N XO2_IN1_1_P XO2_IN0_1_N XO2_IN0_1_P of 14 A Rev A B C D MachXO2-1200HC Control Development Kit User Guide Figure 16. Video Input 1 19 A B C D 5 J10 10226-1A10PE-ND Mounting_R Mounting_L DDC_Gnd_26 RxIn0RxIn0Gnd RxIn0+ Sense USB/DDC_Gnd RxIn1RxIn1Gnd RxIn1+ DDC/SDA RxIn2RxIn2Gnd RxIn2+ USB+ USB_Shield USBDDC/SCL RxClkInRxClkInGnd RxClkIn+ USB_+5VDC DDC_+5VDC RxIn3RxIn3Gnd RxIn3+ DDC_Gnd_1 J13 27 28 26 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 5 Analog_Ground_1 Analog_Ground_2 MDR Connector DVI_I Analog_Horizontal_Sync Analog_Red Analog_Green Analog_Blue TMDS_Clock+ TMDS_Clock- TMDS_Clock_Shield TMDS_Data5TMDS_Data5+ TMDS_Data0/5_Shield TMDS_Data0TMDS_Data0+ Hot_Plug_Detect +5V_Power GND(for +5V) TMDS_Data3TMDS_Data3+ TMDS_Data1/3_Shield TMDS_Data1TMDS_Data1+ Analog_Vertical_Sync DDC_Clock DDC_Data TMDS_Data4TMDS_Data4+ TMDS_Data2/4_Shield TMDS_Data2TMDS_Data2+ DVI-Integrated DVI Connector DDC_CLK DDC_DATA [9,11] [9,11] 98 97 19 28 45 58 76 18 29 43 57 78 TFP401A PGND PVDD OGND OGND OGND OGND OGND OVDD OVDD OVDD OVDD OVDD DGND DGND DGND DVDD DVDD DVDD PDN PDON OCK_INV DFO PIXS STAGN ST MDR_TX_OUT3_P_2 MDR_TX_OUT3_N_2 MDR_TX_CLKOUT_P_2 MDR_TX_CLKOUT_N_2 MDR_TX_OUT2_P_2 MDR_TX_OUT2_N_2 MDR_TX_OUT1_P_2 MDR_TX_OUT1_N_2 0 4 10K 10K R243 R101 10K R118 10K 10K R117 R116 10K 10K R97 R120 10K R94 10K R119 R115 10K 0 DVDD_2 R121 R103 R100 MDR_TX_OUT0_P_2 0 DNI DI DI DI DI DI DI DI DI DI DNI DI 10K U9 RSVD (Tie high) DNI Clk-in B-in G-in EXT_RES AVDD RxCP RxCN AGND Rx0P Rx0N AGND AVDD AGND Rx1P Rx1N AVDD AGND AVDD R-in TXIN7_2 R105 Supporting Circuits TI_PVDD_2 TI_OVDD_2 6 38 67 5 39 68 2 9 DVDD_2 100 1 4 7 3 PDN_2 PDON_2 OCK_INV_2 DFO_2 PIXS_2 STAGN_2 ST_2 99 AGND Rx2P Rx2N MDR_TX_OUT0_N_2 Channel Link - RX C5 C6 C4 C1 C2 C3 23 24 22 20 21 TMDS_2_CLK_P TMDS_2_CLK_N TMDS_2_DATA0_N TMDS_2_DATA0_P 19 DI 17 18 0 R247 Hot_Plug_Video 16 14 15 DVDD_2 93 94 92 90 91 96 TMDS_2_CLK_P TMDS_2_CLK_N TMDS_2_DATA0_P TMDS_2_DATA0_N 85 86 TMDS_2_DATA1_P TMDS_2_DATA1_N 87 88 89 82 83 84 12 13 [14] Hot_Plug_Video 79 80 81 TI_AVDD_2 TMDS_2_DATA2_P TMDS_2_DATA2_N 95 TMDS_2_DATA1_N TMDS_2_DATA1_P DDC_CLK DDC_DATA TMDS_2_DATA2_N TMDS_2_DATA2_P 11 9 10 8 6 7 4 5 3 1 2 DVI - TMDS Decoder 4 R-even R-odd G-even DNI NS_STB_2 OCK_INV_2 ST_2 STAGN_2 PIXS_2 DFO_2 NS_STB_2 PWRDWN_2 PDON_2 PDN_2 OCK_INV_2 CTL3_2 CTL2_2 CTL1_2 SCDT VSYNC HSYNC DE CTL3 CTL2 CTL1 ODCK QO7 QO6 QO5 QO4 QO3 QO2 QO1 QO0 QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 QE15 QE14 QE13 QE12 QE11 QE10 QE9 QE8 QO23 QO22 QO21 QO20 QO19 QO18 QO17 QO16 QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 QE7 QE6 QE5 QE4 QE3 QE2 QE1 QE0 G-odd B-even B-odd Video Input Source 2 : DVI or MDR for direct 7:1LVDS 8 47 48 46 42 41 40 44 56 55 54 53 52 51 50 49 17 16 15 14 13 12 11 10 66 65 64 63 62 61 60 59 27 26 25 24 23 22 21 20 77 75 74 73 72 71 70 69 37 36 35 34 33 32 31 30 R114 IO17 IO16 DI 470 1 2 Q8 BSS138LT1 3 D11 LED_Green (1) Gate SOT-23 3 (2) Source (3) Drain VCC33 32 31 TXCLKIN_2 PWRDWN_2 50 30 28 27 25 24 23 22 20 19 18 16 15 14 12 11 10 8 7 6 4 3 2 56 55 54 52 51 TXIN27_2 TXIN26_2 TXIN25_2 TXIN24_2 TXIN23_2 TXIN22_2 TXIN21_2 TXIN20_2 TXIN19_2 TXIN18_2 TXIN17_2 TXIN16_2 TXIN15_2 TXIN14_2 TXIN13_2 TXIN12_2 TXIN11_2 TXIN10_2 TXIN9_2 TXIN8_2 TXIN7_2 TXIN6_2 TXIN5_2 TXIN4_2 TXIN3_2 TXIN2_2 TXIN1_2 TXIN0_2 LVDS Translator TOP Package View SCDT_2 LED will be ON when link is active. (SCDT high) DVDD_2 SCDT_2 TXIN15_2 TXIN14_2 TXIN18_2 CTL3_2 CTL2_2 CTL1_2 TXCLKIN_2 B TXIN6_2 TXIN4_2 TXIN13_2 TXIN12_2 TXIN9_2 TXIN8_2 TXIN26_2 TXIN25_2 G TXIN3_2 TXIN2_2 TXIN24_2 TXIN22_2 TXIN21_2 TXIN20_2 TXIN19_2 TXIN23_2 TXIN1_2 TXIN0_2 TXIN17_2 TXIN16_2 TXIN11_2 TXIN10_2 TXIN5_2 TXIN27_2 R 3 DS90CR287 PWRDWN TxCLKIN TxIN27 TxIN26 TxIN25 TxIN24 TxIN23 TxIN22 TxIN21 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 U18 10uF DI C118 10uF DI C120 10uF DI C127 GND GND GND GND GND VCC VCC VCC VCC PLLGND PLLGND PLLVCC LVDSGND LVDSGND LVDSGND LVDSVCC TxCLKOUTN TxCLKOUTP TxOUT3N TxOUT3P TxOUT2N TxOUT2P TxOUT1N TxOUT1P TxOUT0N TxOUT0P 0_1uF DI C45 0_1uF DI C116 0_1uF DI C128 5 13 21 29 53 1 9 17 26 33 35 34 36 43 49 44 0_001uF DI C139 0_001uF DI C132 0_01uF DI C117 0_001uF DI C114 TI_OVDD_2 0_01uF DI C34 DVDD_2 0_01uF DI C130 TI_AVDD_2 NS_STB_2 DVDD_2 NS_PVCC_2 NS_LVCC_2 2 VCC33 10uF DI C111 10uF DI C43 10uF DI C129 MDR_TX_CLKOUT_N_2 R96 MDR_TX_CLKOUT_P_2 R92 0 0 0 0 0 0 0 0 0 0 0_001uF DI C131 0_001uF DI C39 0_001uF DI C37 Tuesday, February 15, 2011 Document Number MachXO2 Control Board Video Input 2 0_01uF DI C36 NS_PVCC_2 0_01uF DI C40 NS_LVCC_2 0_01uF DI C138 TI_PVDD_2 DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DI DI DI DI DI DI DI DI DI DI Date: Size C Title 0_1uF DI C110 0_1uF DI C42 0_1uF DI C133 MDR_TX_OUT3_N_2 R104 MDR_TX_OUT3_P_2 R98 MDR_TX_OUT2_N_2 R109 MDR_TX_OUT2_P_2 R106 MDR_TX_OUT1_N_2 R208 MDR_TX_OUT1_P_2 R207 MDR_TX_OUT0_N_2 R113 MDR_TX_OUT0_P_2 R110 0 0 0 0 0 0 R108 R107 R102 R99 0 0 0 0 R221 R220 R112 R111 TX_CLKOUT_N_2 R95 TX_CLKOUT_P_2 R93 TX_OUT3_N_2 TX_OUT3_P_2 TX_OUT3_N_2 TX_OUT3_P_2 38 37 TX_CLKOUT_N_2 TX_CLKOUT_P_2 TX_OUT2_N_2 TX_OUT2_P_2 TX_OUT2_N_2 TX_OUT2_P_2 42 41 40 39 TX_OUT1_N_2 TX_OUT1_P_2 TX_OUT0_N_2 TX_OUT0_P_2 TX_OUT1_N_2 TX_OUT1_P_2 TX_OUT0_N_2 TX_OUT0_P_2 Resistor MUX 46 45 48 47 2 1 1 XO2_IN0_2_N XO2_IN0_2_P [14] [14] [14] [14] [14] [14] [14] [14] Sheet 10 of XO2_CLKIN_2_N [14] XO2_CLKIN_2_P [14] XO2_IN3_2_N XO2_IN3_2_P XO2_IN2_2_N XO2_IN2_2_P XO2_IN1_2_N XO2_IN1_2_P 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 17. Video Input 2 20 A B C D 5 Channel Link - TX MDR_RX_IN3_P MDR_RX_IN3_N MDR_RX_CLKOUT_P MDR_RX_CLKOUT_N MDR_RX_IN2_P MDR_RX_IN2_N MDR_RX_IN1_P MDR_RX_IN1_N MDR_RX_IN0_P MDR_RX_IN0_N MDR Connector [14] XO2_CLKOUT_P [14] XO2_CLKOUT_N [14] XO2_OUT3_P [14] XO2_OUT3_N [14] XO2_OUT2_P [14] XO2_OUT2_N [14] XO2_OUT1_P [14] XO2_OUT1_N [14] XO2_OUT0_P [14] XO2_OUT0_N Resistor De-MUX 5 J8 27 28 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 26 10226-1A10PE-ND Mounting_R Mounting_L DDC_Gnd_1 TxOut0TxOut0Gnd TxOut0+ Sense USB/DDC_Gnd TxOut1TxOut1Gnd TxOut1+ DDC/SDA TxOut2TxOut2Gnd TxOut2+ USB+ USB_Shield USBDDC/SCL TxClkOutTxClkOutGnd TxClkOut+ USB_+5VDC DDC_+5VDC TxOut3TxOut3Gnd TxOut3+ DDC_Gnd_26 0 R23 DI DNI DNI 0 R29 0 R25 0 R16 0 R15 0 R34 DI 0 R172 0 R173 0 R13 DI DNI DNI 0 R17 DI DNI DNI 0 R174 DI 0 R169 0 R168 0 R171 DI 0 R11 0 R10 0 R9 DI DNI DNI 0 R12 DNI DNI 0 R167 DI 0 R170 DI DI Video Output : DVI or MDR for direct 7:1LVDS RX_IN0_N DVDD 0 10K R48 4 0 R51 0 10K R49 10K R44 10K R47 R45 10K R7 10K 10K R32 R132 10K 10K R43 R46 RXOUT7 R50 Supporting Circuits MDR_RX_CLKOUT_N MDR_RX_CLKOUT_P MDR_RX_IN3_N MDR_RX_IN3_P MDR_RX_IN2_N MDR_RX_IN2_P MDR_RX_IN1_N MDR_RX_IN1_P MDR_RX_IN0_N MDR_RX_IN0_P RX_CLKIN_P R129 100 SM_R_0603 RX_CLKIN_N RX_IN3_P R133 100 SM_R_0603 DI CTL2 DI DNI DI DI DI DI DI DI DI DI DI EDGE CTL3 CTL1 DSEL ISEL EDGE DKEN VREF PWRDWN PDN BSEL NS_DVDD MSEN DS90CR288A GND GND GND GND GND VCC VCC VCC VCC PLLGND PLLGND PLLVCC LVDSGND LVDSGND LVDSGND LVDSVCC PWRDWN RxCLKINN RxCLKINP RxIN3N RxIN3P RxIN2N RxIN2P RxIN1N RxIN1P RxIN0N RxIN0P DVDD 4 28 36 44 52 31 40 48 56 22 24 23 NS_PVCC RX_IN3_N 13 NS_LVCC 8 14 21 25 PWRDWN 17 18 19 20 RX_IN3_N RX_IN3_P RX_CLKIN_N RX_CLKIN_P 15 16 11 12 9 10 RX_IN2_N RX_IN2_P RX_IN1_N RX_IN1_P RX_IN0_N RX_IN0_P LVDS Translator RX_IN2_P R134 100 SM_R_0603 RX_IN2_N RX_IN1_P R130 100 SM_R_0603 RX_IN1_N RX_IN0_P R135 100 SM_R_0603 4 R123 10K DI R64 DI U10 26 7 6 5 3 2 1 55 54 53 51 50 49 47 46 45 43 42 41 39 38 37 35 34 33 32 30 29 27 2 Q3 BSS138LT1 3 D6 LED_Green (1) Gate SOT-23 3 (2) Source (3) Drain IO13 IO10 DI RXCLKOUT DI VCC33 PDN 10 15 14 6 7 8 CTL3 CTL2 CTL1 BSEL DSEL 13 9 DKEN ISEL 3 35 EDGE 5 4 2 57 56 50 51 52 53 54 55 58 59 60 61 62 63 36 37 38 39 40 41 42 43 44 45 46 47 VREF RXOUT15 RXOUT14 RXOUT18 0 R14 0 R131 RXOUT21 RXOUT20 RXOUT19 RXOUT23 RXOUT6 RXOUT4 RXOUT13 RXOUT12 RXOUT9 RXOUT8 RXOUT26 RXOUT25 RXOUT1 RXOUT0 RXOUT17 RXOUT16 RXOUT11 RXOUT10 RXOUT5 RXOUT27 RXOUT3 RXOUT2 RXOUT24 RXOUT22 TMDS - DVI Decoder LED will be OFF when a powered receiver is attached to DVI. (MSEN low) RXCLKOUT RXOUT27 RXOUT26 RXOUT25 RXOUT24 RXOUT23 RXOUT22 RXOUT21 RXOUT20 RXOUT19 RXOUT18 RXOUT17 RXOUT16 RXOUT15 RXOUT14 RXOUT13 RXOUT12 RXOUT11 RXOUT10 RXOUT9 RXOUT8 RXOUT7 RXOUT6 RXOUT5 RXOUT4 RXOUT3 RXOUT2 RXOUT1 RXOUT0 TOP Package View 1 470 RxCLKOUT RxOUT27 RxOUT26 RxOUT25 RxOUT24 RxOUT23 RxOUT22 RxOUT21 RxOUT20 RxOUT19 RxOUT18 RxOUT17 RxOUT16 RxOUT15 RxOUT14 RxOUT13 RxOUT12 RxOUT11 RxOUT10 RxOUT9 RxOUT8 RxOUT7 RxOUT6 RxOUT5 RxOUT4 RxOUT3 RxOUT2 RxOUT1 RxOUT0 3 TFP410 PDN 10uF DI C49 10uF DI C62 10uF DI C60 BSEL/SCL DSEL/SDA CTL3/A3/DK3 CTL2/A2/DK2 CTL1/A1/DK1 ISEL/RSTN DKEN EDGE/HTPLG VREF VSYNC HSYNC DE IDCKP IDCKN DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 DATA15 DATA14 DATA13 DATA12 U3 DGND DGND DGND DVDD DVDD DVDD PGND PVDD TFADJ TGND TXCP TXCN TVDD TX0P TX0N TGND TX1P TX1N TVDD TX2P TX2N TGND 0_1uF DI C57 0_1uF DI C58 0_1uF DI C59 2 0_01uF DI C51 11 49 34 16 48 64 1 12 33 17 18 19 20 22 21 23 25 24 26 28 27 29 31 30 32 0_001uF DI C12 0_001uF DI C26 0_001uF DI C50 NS_DVDD 0_01uF DI C24 DVDD 0_01uF DI C25 TI_TVDD MSEN/PO1 N/C RESERVED (Tie to GND) Clk Out B/CTL3:2 G/CTL1 R/HVSync 2 TI_TVDD Date: Size C Title DVDD TI_PVDD 510, 1% SM_R_0603 MSEN VCC33 R31 TMDS_CLK_P TMDS_CLK_N TMDS_DATA0_P TMDS_DATA0_N TMDS_DATA1_P TMDS_DATA1_N TI_TVDD TMDS_DATA2_P TMDS_DATA2_N R245 R246 DNI TMDS_DATA1_N TMDS_DATA1_P DDC_CLK DDC_DATA 10K DNI TMDS_DATA2_N TMDS_DATA2_P 10K 0_1uF DI C64 0_1uF DI C10 0_1uF DI C61 TI_PVDD 0_001uF DI C7 0_01uF DI C2 1 Sheet 0_001uF DI C1 NS_PVCC 0_01uF DI C52 C5 C6 C4 C1 C2 C3 23 24 22 20 21 19 17 18 16 14 15 12 13 11 9 10 8 6 7 4 5 3 1 2 0_001uF DI C55 NS_LVCC 0_01uF DI C56 Tuesday, February 15, 2011 Document Number MachXO2 Control Board Video Output 10uF DI C3 10uF DI C9 10uF DI C13 TMDS_CLK_P TMDS_CLK_N TMDS_DATA0_N TMDS_DATA0_P [14] 0_1uF Hot_Plug_Video DI C134 DDC_CLK DDC_DATA [9,10] [9,10] VCC5 DVI_I 11 of Analog_Ground_1 Analog_Ground_2 14 Analog_Horizontal_Sync Analog_Red Analog_Green Analog_Blue TMDS_Clock+ TMDS_Clock- TMDS_Clock_Shield TMDS_Data5TMDS_Data5+ TMDS_Data0/5_Shield TMDS_Data0TMDS_Data0+ Hot_Plug_Detect +5V_Power GND(for +5V) TMDS_Data3TMDS_Data3+ TMDS_Data1/3_Shield TMDS_Data1TMDS_Data1+ Analog_Vertical_Sync DDC_Clock DDC_Data TMDS_Data4TMDS_Data4+ TMDS_Data2/4_Shield TMDS_Data2TMDS_Data2+ Rev A DVI-Integrated J3 TMDS - DVI Connector 1 A B C D MachXO2-1200HC Control Development Kit User Guide Figure 18. Video Output A B C TERM2 TERM1 DI R149 1000K DI R162 1000K VCC33 5 C73 Audio Amplifier CMA-4544PF-W U8 Microphone DI R150 DI R147 2_2K DI AUDIO_SIG 10uF 2 1 C69 0_1uF DI VCC33 10K DI 10uF DI C70 3 4 R160 DI 0_1uF C47 VCC33 DI 680K R154 0 2 5 U13 4 MCP6L71R 1 AUDIO_SIG AUDIO_IN [14] R161 0 DNI Optional Bypass AUDIO_SIG 4 AUDIO_IN 3 3 [14] AUDIO_OUT AUDIO_OUT PWM Analog Signal Output DI 2 DI R146 100 DI R145 330 3 1 2 Q4 2N2369A DI R136 100 DI VCC5 2 Date: Size B Title C68 0_1uF DNI C67 10uF DI D2A_OUT Tuesday, February 15, 2011 Document Number MachXO2 Control Board AUDIO IN / AUDIO OUT PHONEJACK STEREO J12 10K R151 2 3 1 D + 21 - 5 Sheet 12 1 1 of 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 19. Audio In/Audio Out A B C D C92 C90 0_1uF 0_1uF DI DI C84 VCCIO18 0_1uF 0_1uF DI DI C96 VCCIO33 C88 DNI 5 C95 0_1uF DNI C87 0_1uF 0_1uF 0_1uF DNI DNI C86 MachXO2 Power C80 DNI C94 0_1uF DNI C93 0_1uF DNI C101 0_1uF DNI C102 0_1uF VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO0 VCCIO0 VCCIO0 NC C103 C100 0_1uF 0_1uF DI DI VCCIO33 1 1 1 MH2 1 MH1 4 M_HOLE1 M_HOLE1 M_HOLE1 M_HOLE1 DI DI DI DI IW_MNT0 IW_MNT0 IW_MNT0 IW_MNT0 MH16 MH13 Socket (080SQ 132U6618A) Mounting Holes 0_1uF 0_1uF DI DI C77 VCCIO33 L1 D3 G1 N11 M6 P1 L12 H14 D14 C5 A8 B10 C7 LCMXO2-1200-CSBGA132 4 GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC U4E L2 G2 D2 L13 P10 P5 A5 B11 D13 H13 N1 P14 A1 A14 0_1uF DI 0_1uF DI 3 C76 C97 0_1uF DI C98 VCC_CORE 3 TCK GND TMS TRST NC TDI TDO POWER 8 7 6 5 4 3 2 1 VCC33 XO2_TCK XO2_TMS XO2_TDI XO2_TDO 2 TDI TDO JTAG Header J12 TDI R203 2 To Prototype Header 1 Date: Size B Title TDO DNI XO2_TDO_PIN XO2_TDO XO2_TDI XO2_TMS XO2_TCK Tuesday, February 15, 2011 Document Number MachXO2 Control Board [6] Sheet 1 13 of XO2_TDO_PIN [14] XO2_TDO [6,14] [6,7,14] [6,7,14] [6,7,14] [6,7,14] TDO_HDR TDI_HDR R156 0 DNI XO2_TDI XO2_TMS XO2_TCK TMS_HDR TCK_HDR R157 0 DI XO2_TDO XO2_TMS XO2_TCK XO2 Supplies, JTAG MachXO2 XO2_TDO_PIN R155 0 Expand JTAG Chain to Prototype Header: Expand JTAG Chain to Prototype Header: NOT Populated XO2 JTAG HD J7 MachXO2 JTAG Port R202 22 R201 5 14 Rev A [7] [7] A B C D MachXO2-1200HC Control Development Kit User Guide Figure 20. MachXO2 Supplies, JTAG A B C D XO2_GPIO_2 XO2_GPIO_3 XO2_GPIO_4 XO2_GPIO_5 XO2_GPIO_6 XO2_GPIO_7 XO2_GPIO_8 XO2_GPIO_9 [7] [7] [7] [7] [7] [7] [7] [7] [7] 0 R57 DNI XO2_IO_6 0 R52 DNI XO2_IO_7 0 R26 DNI XO2_IO_8 0 R24 DNI XO2_IO_9 XO2_IO_0 XO2_IO_1 XO2_IO_5 XO2_IO_6 0 R144DI 0 R143DI 0 R142DI 0 R141DI 0 R140DI 0 R139DI 0 R138DI 0 R137DI 0 R152DI 0 R153DI XO2_IN1_2_N XO2_IN0_2_P XO2_IN0_2_N XO2_GPIO_0 XO2_GPIO_1 XO2_GPIO_2 XO2_GPIO_3 XO2_GPIO_4 XO2_GPIO_5 XO2_GPIO_6 XO2_GPIO_7 XO2_GPIO_8 XO2_GPIO_9 DI DI VCCIO33 XO2_ADC_IN R41 10K 5 LVDS_COMP_P_VREF R53 10K AUDIO_IN 0 ADC_IN R165 IO12 0 AUDIO_IN R166 DI DI DI DI Jumper_2way J9 R180 10K LVDS_COMP_N R181 10K 1 2 3 DI PWM_FB_Delta_Sigma XO2_IO_9 XO2_IO_8 XO2_IO_7 XO2_IO_4 XO2_IO_3 XO2_IO_2 0 R42 DNI XO2_IO_5 XO2_IN2_2_P XO2_IN1_2_P 0 R28 DNI XO2_IO_3 XO2_CLKIN_2_N XO2_IN2_2_N 0 R33 DNI XO2_IO_2 0 R40 DNI XO2_IO_4 XO2_CLKIN_2_P 0 R35 DNI XO2_IO_1 XO2_IN3_2_N ADC Delta-Sigma Interface XO2_GPIO_0 XO2_GPIO_1 [7] [10] XO2_IN0_2_N [10] XO2_IN0_2_P [10] XO2_IN1_2_N [10] XO2_IN1_2_P [10] XO2_IN2_2_N [10] XO2_IN2_2_P [10] XO2_CLKIN_2_N [10] XO2_CLKIN_2_P [10] XO2_IN3_2_N 3300pF DI C78 SCL SDA XO2_IN3_1_P XO2_IN3_1_N XO2_IN1_1_P XO2_IN1_1_N PM_IN1 PM_IN2 4 [9] XO2_CLKIN_1_P [9] XO2_CLKIN_1_N [4] [4] [7,8] XO2_SPI_CLK [7,8] XO2_SPI_OUT [9] [9] [8] XO2_SPI_CS0 [4] PM_SMBA_OUT3 [9] [9] N3 P4 XO2_IN1_1_P XO2_IN1_1_N U4A LCMXO2-1200-CSBGA132 PB11C PB11D PB9A/PCLKT2_0 PB9B/PCLKC2_0 PB9C PB9D PB20A PB20B PB18C PB18D PB18A PB18B PB15C PB15D PB15A PB15B PB11A/PCLKT2_1 PB11B/PCLKC2_1 PT17C/INITN PT17D/DONE PT17A PT17B PT16C PT16D PT16A PT16B PB20C/SN PB20D/SI/SISPI/IO0 Bank2 PB6C/MCLK/CCLK PB6D/SO/SPISO/IO1 PB6A PB6B PB4C/CSSPIN PB4D PB4A PB4B U4C LCMXO2-1200-CSBGA132 TCK TMS TDO TDI PT15A PT15B PT15C PT15D/PROGRAMN Bank0 PT12C/SCL/IO2/PCLKT0_0 PT12D/SDA/IO3/PCLKC0_0 PT12A/PCLKT0_1 PT12B/PCLKC0_1 PT11A PT11B PT10A PT10B PT9A PT9B N12 P13 M11 P12 M10 P11 M9 N10 P9 N9 P8 M8 M7 N8 B13 A13 C12 A12 A11 B12 A10 C11 B9 C10 C9 A9 VCC18 LVCMOS33 Open Drain LPDDR_WEn LPDDR_CSn LPDDR_CASn LPDDR_RASn [8] LPDDR_CKE_3p3 SW0 XO2_OUT0_P XO2_OUT0_N 3 [8] LPDDR_BA0 LPDDR_CKE LPDDR_CKE_1p8 LPDDR_CKE_3p3 LPDDR_BA0_1p8 LPDDR_BA0_3p3 LPDDR_BA1 [8] LPDDR_BA1_1p8 LPDDR_BA1_3p3 [9] [9] [9] [9] [7] [7] [8] [8] [8] [8] [7] XO2_GPIO_11 [7] XO2_SPI_IN [7,8] XO2_IN2_1_P XO2_IN2_1_N XO2_IN0_1_P XO2_IN0_1_N SW1 SW2 LPDDR_WEn LPDDR_CASn LPDDR_CSn LPDDR_RASn SW0 XO2_OUT0_P [11] XO2_OUT0_N [11] LVCMOS33 Voltage Devider XO2_GPIO_11 MOSI XO2_IN2_1_P XO2_IN2_1_N XO2_IO_8 XO2_IO_9 XO2_IO_6 XO2_IO_7 XO2_IO_4 XO2_IO_5 XO2_IN0_1_P XO2_IN0_1_N XO2_IO_2 XO2_IO_3 SW1 SW2 LPDDR_BA1_3p3 LPDDR_WEn LPDDR_CASn LPDDR_CSn LPDDR_RASn LPDDR_BA0_3p3 Interface between LVCMOS33 and LPDDR1.8V P7 N7 N6 P6 XO2_IO_0 XO2_IO_1 N5 M5 PM_IN1 PM_IN2 XO2_CLKIN_1_P XO2_CLKIN_1_N M4 N4 P3 M3 XO2_SPI_CS0 PM_SMBA_OUT3 XO2_SPI_CLK MISO P2 N2 B6 A6 A4 B4 C8 B8 A7 B7 B5 C6 A3 C4 A2 B3 XO2_IN3_1_P XO2_IN3_1_N XO2_TCK XO2_TMS XO2_TDO_PIN XO2_TDI SCL SDA XO2_OUT1_P XO2_OUT1_N XO2_OUT2_P XO2_OUT2_N XO2_CLKOUT_P XO2_CLKOUT_N XO2_OUT3_P XO2_OUT3_N MachXO2 Bank 2 [6,7,13] XO2_TCK [6,7,13] XO2_TMS [13] XO2_TDO_PIN [6,13] XO2_TDI [4,7] [4,7] [11] XO2_OUT1_P [11] XO2_OUT1_N [11] XO2_OUT2_P [11] XO2_OUT2_N [11] XO2_CLKOUT_P [11] XO2_CLKOUT_N [11] XO2_OUT3_P [11] XO2_OUT3_N MachXO2 Bank 0 1K R175 DI 0 R30 DNI XO2_IO_0 1K R178 DI XO2_IN3_2_P 1K R176 DI [10] XO2_IN3_2_P [8] [8] LPDDR_A3 LPDDR_A2 LPDDR_A5 LPDDR_A4 LPDDR_A7 LPDDR_A6 LPDDR_A9 LPDDR_A8 LPDDR_A12 LPDDR_A11 [8] [8] [8] [8] LPDDR_A10 LPDDR_LDM LPDDR_CK LPDDR_CKn LPDDR_A3 LPDDR_A2 LPDDR_A5 LPDDR_A4 LPDDR_A7 LPDDR_A6 LPDDR_A9 LPDDR_A8 [4] [4] [4] PM_OUT12 PM_OUT13 PM_OUT11 [4,7] PM_MCLK uSD_DAT1 uSD_DAT0 [4,7] XO2_RESETn uSD_CMD uSD_CLK [6] USB_UART_TX [6] USB_UART_RX G13 H12 G12 G14 F13 F14 E13 F12 E12 E14 C14 D12 B14 C13 Bank1 M1 M2 L3 K1 K3 J3 K2 J1 J2 H1 H3 2 SDA SCL VCC33 PR8A PR8B PR10C PR10D PR10A PR10B PR9C PR9D PR9A PR9B PR8C PR8D N13 N14 M12 M14 L14 M13 K13 K14 J13 K12 J12 J14 Date: Size C Title 10K R73 DI 1 PM_PLDCLK XO2_LED3 G3 H2 AUDIO_OUT XO2_LED1 XO2_LED0 XO2_LED2 Tuesday, February 15, 2011 Document Number MachXO2 Control Board [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] 1 [7] [7] uSD_DAT3 [7] [8] [7] [7] Sheet 14 PM_PLDCLK [4,7] XO2_LED3 [7] XO2_LED0 XO2_LED2 AUDIO_OUT XO2_LED1 [7] X_2 X_1 SW3 uSD_DAT2 LVDS_COMP_P_VREF LVDS_COMP_N XIN XOUT PWM_FB_Delta_Sigma uSD_DAT3 SW3 uSD_DAT2 LPDDR_A0 LPDDR_A1 LPDDR_DQ2 LPDDR_DQ0 LPDDR_DQ3 LPDDR_DQ1 LPDDR_DQ5 LPDDR_DQ4 LPDDR_DQ7 LPDDR_DQ6 LPDDR_LDQS [8] XO2_GPIO_10 [7] VCC18 F1 F3 E3 F2 E1 E2 C2 D1 C1 C3 B1 B2 LPDDR_A0 LPDDR_A1 LPDDR_DQ2 LPDDR_DQ0 LPDDR_DQ3 LPDDR_DQ1 LPDDR_DQ5 LPDDR_DQ4 LPDDR_DQ7 LPDDR_DQ6 LPDDR_LDQS XO2_GPIO_10 XO2 TOP, BOTTOM PL5A/PCLKT3_1 PL5B/PCLKC3_1 PL4C PL4D PL4A PL4B PL3C PL3D PL3A/PCLKT3_2 PL3B/PCLKC3_2 PL2C/L_GPLLT_IN PL2D/L_GPLLC_IN PL2A/L_GPLLT_FB PL2B/L_GPLLC_FB Bank3 LCMXO2-1200-CSBGA132 PL10C PL10D PL10B PL9A/PCLKT3_0 PL9B/PCLKC3_0 PL8C PL8D PL8A PL8B PL5C PL5D U4D LCMXO2-1200-CSBGA132 PR5C/PCLKT1_0 PR5D/PCLKC1_0 PR5A PR5B PR4C PR4D PR4A PR4B PR3A PR3B PR2C PR2D PR2A PR2B U4B I2C Bus Pull-up Resistors PM_OUT12 PM_OUT13 PM_OUT11 PM_MCLK uSD_DAT1 uSD_DAT0 XO2_RESETn uSD_CMD uSD_CLK USB_UART_TX USB_UART_RX MachXO2 Bank 3 [8] LPDDR_A10 [8] LPDDR_LDM [8] LPDDR_CK [8] LPDDR_CKn [8] [8] [8] [8] [8] [8] [8] [8] LPDDR_A12 LPDDR_A11 MachXO2 Bank 1 4_7K Resistor Mux between Prototype Header and Video Channel 2 (7:1LVDS) 1K R177 DI 2 R91 3 4_7K 4 820 1K R188 DI R182 DI 820 1K R187 DI R183 DI 820 1K R69 DI R74 DI R90 DI 23 DI 5 of [8] [12] 14 Rev A A B C D MachXO2-1200HC Control Development Kit User Guide Figure 21. MachXO2 Top, Bottom MachXO2-1200HC Control Development Kit User Guide Appendix B. Bill of Materials Table 1. Bill of Materials Item Quantity Reference Value PCB Footprint 1 19 C1, C7, C12, C14, C17, C26, C37, C39, C50, C55, C71, C113, C114, C125, C131, C132, C135, C137, C139 0_001uF SM_C_0201 Mfr Part Number Manufacturer 2 23 C2, C5, C6, C15, C18, C24, C25, C32, C34, C36, C38, C40, C41, C51, C52, C56, C72, C91, C117, C124, C130, C136, C138 0_01uF SM_C_0201 3 18 C3, C9, C13, C20, C21, C22, C43, C49, C60, C62, C111, C118, C120, C121, C122, C127, C129, C140 10uF SM_C_0603 C1608Y5V0J106Z TDK 4 2 C4, C11 12pF SM_C_0603 5 32 C8, C10, C16, C19, C42, C44, C45, C46, C47, C57, C58, C59, C61, C63, C64, C69, C74, C81, C89, C99, C105, C107, C109, C110, C112, C115, C116, C123, C128, C133, C134, C141 0_1uF SM_C_0603 6 2 C23, C29 18pF 7 3 C27, C30, C31 0.1uF cc0402 C0402C180K3GACTU Kemet cc0402 C0402C104K4RACTU 8 1 C28 Kemet 10u cc0603 ECJ-1VB0J106M Panasonic JMK212BJ106KD-T TAIYO YUDEN 9 4 C33, C106, C142, C143 10uF SM_C_0805 10 2 C35, C83 1uF SM_C_0805 11 7 C48, C82, C85, C104, C119, C126, C145 0.1uF cc0402 C0402C104K4RACTU Kemet 12 2 C53, C65 22uF SM_C_0805 LMK212BJ226MG-T TAIYO YUDEN 13 4 C54, C66, C70, C73 10uF SM_C_0805 14 1 C67 10uF SM_C_0603 15 1 C68 0_1uF SM_C_0603 16 13 C75, C76, C77, C79, C80, C84, C90, C92, C96, C97, C98, C100, C103 0_1uF SM_C_0201 17 1 C78 3300pF SM_C_0603 18 8 C86, C87, C88, C93, C94, C95, C101, C102 0_1uF SM_C_0201 19 1 C108 0_01uF SM_C_0201 EMK107BJ103K TAIYO YUDEN 20 1 C144 4u7 cc0603 ECJ-1VB0J475K 21 8 D1, D2, D3, D4, D7, D8, D9, D10 LED SM_D_0603 LTST-C190CKT LITE ON 22 2 D5, D6 LED_Green SM_D_0603 LTST-C190KGKT LITE ON 22a 1 D11 LED_Green SM_D_0603 LTST-C190KGKT LITE ON 23 1 D12 LED SM_D_0603 LTST-C190CKT LITE ON 24 15 IO2, IO3, IO4, IO5, IO9, IO10, IO11, IO12, IO13, IO14, IO16, IO17, IO18, IO19, IO20 T POINT R TP 25 3 IO7, IO8, IO15 T POINT R TP 26 2 J1, J8 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M 26a 1 J13 (not installed) 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M 27 2 J2, J3 DVI_I DVI_I 74320-1004 Molex 27a 1 J10 (not installed) 28 1 J4 29 1 J5 USB_MINI_B TYPE_B UX60-MB-5ST Hirose 30 1 J6 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc. 30 1 J9 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc. 31 1 J7 XO2 JTAG HD XO2_JTAG_HD 32 1 J11 PWR_JACK PWR_CON RAPC712 Switchcraft 33 1 J12 PHONEJACK STEREO SM MJ1-3510-SMT CUI 34 1 L3 600ohm 500mA FB0603 BLM18AG601SN1D Murata 35 4 MH1, MH2, MH13, MH16 M_HOLE1 IW_MNT0 SJ-5003 (BLACK) 36 4 Q1, Q3, Q6, Q8 37 2 Q2, Q5 DVI_I DVI_I 74320-1004 Molex CON40A 2x20x100mil TSW-120-07-G-D Samtec BSS138LT1 SOT_23 BSS138LT3G ON Semi 2N7002E SM_SOT23 2N7002ET1G ON_Semi 24 MachXO2-1200HC Control Development Kit User Guide Table 1. Bill of Materials (Continued) Item Quantity Value PCB Footprint Mfr Part Number 38 1 Q4 Reference 2N2369A 2N2369A_SOT23 MMBT2369A Fairchild 39 1 Q7 ZDT758 SM_8_DUAL_PNP ZDT758 Diodes/Zetex 40 2 RN1, RN4 RN2_4_470 RN2_4_470_0603 TC164-JR-07470RL Yageo 41 1 RN2 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi 42 1 RN3 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi 43 45 R1, R7, R18, R19, R20, R21, R32, R41, R43, R44, R45, R46, R47, R53, R73, R81, R94, R97, R115, R116, R117, R118, R119, R120, R121, R123, R124, R125, R126, R127, R128, R132, R151, R158, R159, R163, R164, R180, R181, R200, R233, R236, R239, R242, R244 10K SM_R_0402 44 1 R2 1M SM_R_0603 45 48 R3, R5, R8, R10, R11, R15, R16, R24, R25, R26, R28, R29, R30, R33, R35, R40, R42, R52, R57, R92, R96, R98, R100, R104, R105, R106, R109, R110, R113, R155, R156, R161, R168, R169, R172, R173, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218 0 SM_R_0402 46 5 R4, R67, R195, R196, R232 1K SM_R_0603 47 68 R6, R9, R12, R13, R14, R17, R23, R34, R36, R37, R38, R39, R49, R50, R51, R61, R62, R70, R71, R75, R76, R78, R82, R83, R87, R93, R95, R99, R102, R103, R107, R108, R111, R112, R131, R137, R138, R139, R140, R141, R142, R143, R144, R152, R153, R154, R157, R165, R166, R167, R170, R171, R174, R186, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R247, R248 0 SM_R_0402 48 7 R22, R48, R101, R237, R243, R245, R246 10K SM_R_0402 49 4 R27, R64, R114, R122 470 SM_R_0603 ERJ-3EKF4700V Panasonic ECG 50 1 R31 510, 1% SM_R_0603 51 9 R54, R55, R65, R66, R84, R85, R88, R89, R205 4_7K SM_R_0603 52 1 R56 TNPW04022K20BEED Vishay/Dale 53 1 R58 (not installed) 54 1 R59 55 2 R60, R219 56 2 R63, R68 0 SM_R_0603 57 3 R69, R187, R188 820 SM_R_0402 58 8 R74, R175, R176, R177, R178, R182, R183, R240 1K SM_R_0402 59 1 R79 100K SM_R_0603 60 2 R80, R86 68 SM_R_0402 61 2 R90, R91 4_7K SM_R_0402 62 5 R129, R130, R133, R134, R135 100 SM_R_0603 63 8 R136, R146, R184, R185, R191, R194, R201, R206 100 SM_R_0603 64 1 R145 330 SM_R_0603 65 1 R147 2_2K SM_R_0603 66 2 R148, R235 2 SM_R_0805 67 2 R149, R162 1000K SM_R_0603 68 1 R150 10K SM_R_0603 69 1 R160 680K SM_R_0603 70 2 R179, R198 200 SM_R_0603 71 4 R189, R190, R192, R193 3_92K SM_R_0603 72 2 R197, R204 2K SM_R_0603 2k2 cr0402 0 SM_R_0805 1 SM_R_0805 220 SM_R_0603 25 Manufacturer MachXO2-1200HC Control Development Kit User Guide Table 1. Bill of Materials (Continued) Item Quantity Value PCB Footprint Mfr Part Number Manufacturer 73 1 R199 Reference 12k cr0402 RC0402FR-0712KL Yageo 74 4 R202, R203, R241, R249 10k cr0402 RC0402FR-0710KL Yageo 75 0 R240 2k2 cr0402 RC0402FR-072K2L Yageo 76 1 SW1 SWDIP_4 SMD_8check 3-5435640-5 Tyco 77 1 SW2 SW DIP_2 SP_75 195-2MST CTS 78 1 S1 XO2 Global Reset SMT_SW EVQ-Q2K03W Panasonic 79 1 U1 microSD Socket SM_SD 460DE08C3 MULTICOMP 80 1 U2 TFP401A HTQFP_100 TFP401APZPG4 TI 80 1 U9 (not installed) TFP401A HTQFP_100 TFP401APZPG4 TI 81 1 U3 TFP410 HTQFP_64 TFP410PAP TI 82 1 U4 LCMXO2-1200HCCSBGA132 CSBGA132 LCMXO2-1200HCCSBGA132 Lattice Semi 83 1 U5 STG3693QTR QFN STG3693QTR STMicroelectronics 84 1 U6 MT46H16M16LFBF SM/60VFBGA MT46H16M16LFBF Micron 85 1 U7 ispPAC-POWR1014A TQFP_48 ispPAC-POWR1014A01TN48I Lattice 86 1 U8 CMA-4544PF-W 2 Solder Pins (TH) CMA-4544PF-W CUI Inc 87 1 U10 DS90CR288A TSSOP_56 DS90CR288AMTD/NOP B National Semi 88 1 U11 NCP1117ST33 SOT_223 NCP1117ST33T3G ONSemi 89 1 U12 NCP1117ST18 SOT_223 NCP1117ST18T3G ONSemi 90 1 U13 MCP6L71R SOT_23_5_MC MCP6L71RT-E/OT Microchip 91 1 U14 AT25DF041A-SH-B SOIC8 AT25DF041A-SH-B Atmel 92 1 U15 AT25DF041A-MH-B UDFN AT25DF041A-MH-B Atmel 93 1 U16 AD8604ARZ 14_SOIC AD8604ARZ Analog Devices 95 1 U17 (not installed) Value MRA08A_M LP3879MR-1.2 National 96 1 U18 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI 96 1 U19 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI 97 1 U20 FT2232HL tqfp64_0p5_12p2x12 p2_h1p6 FT2232HL FTDI 98 1 U21 99 1 X1 (not installed) 100 1 X2 101 1 X3 102 1 XO2_Control_board_RevE_PCB 93LC56-SO8 so8_50_244 93LC56T-I/SN Microchip CTS-CB3LV-3C-25MHz SMD 7.00mm x 5.00mm CB3LV-3C-25M0000 CTS HCM49 24.000MABJ-UT SMD HCM49 24.000MABJ-UT Citizen Finetech 12 MHZ crystal_4p_3p2x2p5 7M-12.000MAAJ-T TXC CORP 305-PD-11-XXX 26 MachXO2-1200HC Control Development Kit User Guide Appendix C. Limitations • It is recommended to have a 1 kOhm pull up on MachXO2 pin MCLK (signal XO2_SPI_CLK) 27