VBUS54GD-FBL Datasheet

VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
4-Line BUS-Port ESD Protection - Flow Through Design
FEATURES
• Compact LLP2510-10M package
nc.
10
nc. GND nc.
9
8
7
nc.
6
• Low package height < 0.6 mm
• 4-line ESD-protection
• Low leakage current IR < 0.1 μA
• Low capacitance between I/O lines: 0.3 pF
1
2
3
4
5
D1+ D1- GND D2+ D2-
• Ideal for high speed data line like
- HDMI, DisplayPort, eSATA
- USB, 1394/firewire
- Thunderbolt
22791
22552
• ESD-protection acc. IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
MARKING (example only)
• Soldering can be checked by standard vision inspection.
No X-ray necessary
YYXX
20720
• e3 - Sn
Dot = pin 1 marking
YY = type code (see table below)
XX = date code
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
ORDERING INFORMATION
DEVICE NAME
ORDERING CODE
TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL)
MINIMUM ORDER QUANTITY
VBUS54GD-FBL
VBUS54GD-FBL-G3-08
3000
30 000
PACKAGE DATA
DEVICE NAME
PACKAGE
NAME
TYPE
CODE
WEIGHT
MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VBUS54GD-FBL
LLP2510-10M
4G
3.9 mg
UL 94 V-0
MSL level 1
(according J-STD-020)
260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS VBUS54GD-FBL
PARAMETER
Peak pulse current
Peak pulse power
ESD immunity
Operating temperature
Storage temperature
Rev. 1.1, 27-Nov-15
TEST CONDITIONS
SYMBOL
VALUE
UNIT
Acc. IEC 61000-4-5; tP = 8/20 μs; single shot
IPPM
3
A
Acc. IEC 61000-4-5; tP = 8/20 μs; single shot
PPP
45
W
Contact discharge acc. IEC 61000-4-2; 10 pulses
Air discharge acc. IEC 61000-4-2; 10 pulses
Junction temperature
VESD
± 15
± 15
kV
TJ
-40 to +125
°C
TSTG
-55 to +150
°C
Document Number: 85916
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
ELECTRICAL CHARACTERISTICS VBUS54GD-FBL (pin 1, 2, 4 or 5 to pin 3)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER
Protection paths
Reverse stand-off voltage
Reverse voltage
Reverse current
Reverse breakdown voltage
Reverse clamping voltage
Forward clamping voltage
Clamping voltage
Dynamic resistance
Capacitance
Capacitance between I/O lines
TEST CONDITIONS/REMARKS
Number of lines which can be protected
Max. reverse working voltage
at IR = 0.1 μA
at VRWM = 5.5 V
at IR = 1 mA
at IPP = 1 A
at IPP = IPPM = 3 A
at IPP = 1 A
at IPP = 3 A
Transmission line pulse (TLP), tp = 100 ns
ITLP = 8 A
Transmission line pulse (TLP), tp = 100 ns
ITLP = 16 A
Transmission line pulse (TLP), tp = 100 ns
at VR = 0 V; f = 1 MHz
at VR = 3.3 V; f = 1 MHz
at VR = 3.3 V; f = 1 MHz
SYMBOL
Nchannel
VRWM
VR
IR
VBR
VC
VC
VF
VF
MIN.
5.5
6.9
-
TYP.
0.02
7.5
9.1
12
2.1
3.5
MAX.
4
5.5
0.1
8.7
11
15
2.4
4.5
UNIT
lines
V
V
μA
V
V
V
V
V
VC-TLP
-
15
-
V
VC-TLP
-
21
-
V
RDYN
-
0.76
0.6
0.65
0.3
0.75
0.75
0.4

pF
pF
pF
CD
CDD
APPLICATION NOTE
The VBUS54GD-FBL is a four-line ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a
very low capacitance which makes it usable for high frequency applications like USB2.0, USB3.0 or HDMI.
With the VBUS54GD-FBL four high speed data lines can be protected against transient voltage signals like ESD (Electro Static
Discharge). Connected to the data line (pin 1, 2 and pin 4, 5) and to ground (pin 3 and 8) negative transients will be clamped
close below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping
behaviour of the VBUS54GD-FBL is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications
running up to 5.5 V.
Pin configuration:
• Pin 3 and 8 are internally shorted and have to be connected to ground
• Pin 1, 2 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2• Pin 6, 7 and 9, 10 are not connected internally
-----USB / HDMI Interface
nc. GND nc.
9
8
7
D2+
nc.
6
1
2
3
4
5
D1+ D1- GND D2+ D2-
D2-
matched pair
nc.
10
D1-
matched pair
D1+
10
9
8
7
6
1
2
3
4
5
22552
D1+
D1- GND D2+
D2-
I/O Port Connector
22553
FLOW THROUGH DESIGN
Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI).
At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding
their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated
depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected
to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and
distances.
With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the
VBUS54GD-FBL is placed on top without any via or loops.
Rev. 1.1, 27-Nov-15
Document Number: 85916
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
CONNECTION DIAGRAM EXAMPLE FOR THUNDERBOLT DATA PORT
3 x VBUS54GD-FBL
10
9
8
7
6
10
9
8
7
6
10
9
8
7
6
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
Pin 4
CFG1
Cio0_RX-
Pin 6
CFG2
Cio0_RX+
Pin 10
DP3+
Pin 12
DP3-
Pin 16
AUX+
Cio1_RX-
Pin 18
Pin 3
AUXDP0+
Cio1_RX+
Cio0_TX-
Pin 5
DP0-
Cio0_TX+
Pin 9
DP1+
Lsx_tx-ctrl
Pin 11
DP1-
Lsx_rx-ctrl
Pin 15
DP2+
Cio1_TX-
Pin 17
DP2-
Cio1_TX+
-
Display Port
mode
Connector
Thunderbolt
mode
22788
CONNECTION DIAGRAM EXAMPLE FOR USB 3.0 DATA PORT
VBUS54GD-FBL VBUS052CD-FAH
10
9
8
7
6
6
5
4
7
1
2
3
4
5
1
2
3
VBUS
VBUS
D-
D-
D+
D+
Pwr Gnd
Pwr Gnd
SSRX-
SSRX-
SSRX+
SSRX+
GND
GND
SSTX-
SSTX-
SSTX+
SSTX+
USB 3.0
Connector
USB 3.0
Transmitter
22789
CONNECTION DIAGRAM EXAMPLE FOR HDMI DATA PORT
2 x VBUS54GD-FBL
10
9
8
7
6
10
9
8
7
6
1
2
3
4
5
1
2
3
4
5
TMDS D2+
TMDS D2+
TMDS D2-
TMDS D2-
TMDS D1+
TMDS D1+
TMDS D1-
TMDS D1-
TMDS D0+
TMDS D0+
TMDS D0TMDS Clock+
TMDS D0TMDS Clock+
TMDS Clock-
TMDS Clock-
HDMI
Connector
HDMI
Transmitter
22790
Rev. 1.1, 27-Nov-15
Document Number: 85916
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Axis Title
2.5
10000
120
Rise time = 0.7 ns to 1 ns
100
2
1000
60
53
1.5
2nd line
VF (V)
1st line
2nd line
2nd line
IESD (%)
80
1
100
40
27
0.5
20
0
10
0
-10 0
0
10 20 30 40 50 60 70 80 90 100
t (ns)
2nd line
20557
0.2
0.4
0.6
0.8
1
IF (A)
2nd line
22799
Fig. 4 - Typical Forward Voltage vs. Forward Current
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Axis Title
10000
100
9
8 µs to 100 %
8
7
80
20 µs to 50 %
40
2nd line
VR (V)
60
6
1st line
2nd line
2nd line
IPPM (%)
1000
100
5
4
3
2
20
1
0
10
0
10
20
30
t (µs)
2nd line
20548
0
0.01
40
0.1
1
10
100
1000
10 000
IR (µA)
2nd line
22800
Fig. 5 - Typical Reverse Voltage vs. Reverse Current
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
1
14
f = 1 MHz
0.9
12
0.8
10
0.7
2nd line
VC (V)
2nd line
CD (pF)
0.6
0.5
0.4
0.3
8
6
4
0.2
2
0.1
0
Measured according IEC 61000-4-5
(8/20 µs - wave form)
0
0
1
2
3
4
5
VR (V)
2nd line
22798
Fig. 3 - Typical Capacitance vs. Reverse Voltage
Rev. 1.1, 27-Nov-15
0
22801
1
2
3
4
IPP (A)
2nd line
Fig. 6 - Typical Peak Clamping Voltage vs. Peak Pulse Current
Document Number: 85916
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
35
4.5
4
Transmission line pulse (TLP):
tp = 100 ns
30
3.5
25
2nd line
VC-TLP (V)
2nd line
VF (V)
3
2.5
2
20
15
1.5
10
1
5
Measured according IEC 61000-4-5
(8/20 µs - wave form)
0.5
0
0
0
22802
1
2
3
IF (A)
2nd line
Fig. 7 - Typical Peak Forward Voltage vs. Forward Current
Rev. 1.1, 27-Nov-15
0
4
22803
10
20
30
ITLP (A)
2nd line
Fig. 8 - Typical Clamping Voltage vs. Peak Pulse Current
Document Number: 85916
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
PACKAGE DIMENSIONS in millimeters: LLP2510-10M
Package = Chip Dimensions in mm
A
L1
e
D
b2
b1
Pin 1 marking
L2
A1
E
Millimeters
A
Min.
Nom.
Max.
0.455
-
0.555
A1
0.00
-
0.05
b1
0.19
-
0.25
b2
0.39
-
0.45
D
2.45
-
2.55
E
0.95
-
1.05
e
-
0.50
-
L1
0.35
-
0.41
L2
0.48
-
0.54
foot print recommendation:
2.25
0.625
0.25
0.7
1.4
0.575
4 x 0.5 = 2
0.5
0.45
Document no.: S8-V-3906.04-040 (4)
Created - Date: 27. July 2015
22804
Rev. 1.1, 27-Nov-15
Document Number: 85916
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS54GD-FBL
www.vishay.com
Vishay Semiconductors
CARRIER TAPE in millimeters LLP2510
A-A section
B
5° ma
B
x.
0.8 ± 0.05
0.25
2.7 ± 0.05
4 ± 0.1
3.5 ± 0.05
2 ± 0.05
1.75 ± 0.1
A
8 +- 0.3
0.1
1.5 ± 0.1
A
0.7 ± 0.05
B-B section
5° max
.
1.23 ± 0.05
Cummulative tolerances of 10 sprocket holes is ± 0.2 mm
Document no. S8-V-3906.04-0028 (4)
Created - Date: 08. Jul. 2011
ORIENTATION IN CARRIER TAPE LLP2510
Pin 1 - Location
LLP2510
Top view
pad layout - view from top
seen at bottom side
Document no. S8-V-3906.04-0029 (4)
Created - Date: 07. Jul. 2011
Rev. 1.1, 27-Nov-15
Document Number: 85916
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000