Quality and a Reliab R bility R Report Fou urth Quarte Q er 201 12 Iso olator Prod ducts s Document ID: ISOProdQ Q412.doc Note: Alll rights reserrved. No parrt of this pub blication may be reproducced or transm mitted withoutt prior approval by b Silicon Lab boratories, Inc. This docum ment is the prroperty of Siliicon Laborato ories, Inc. and d shall be returne ed upon reque est. S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Tab ble of Conteents Quality y and Relia ability Report ................................................................................. 3 Overvie ew ...................................................................................................................... 3 Quality y Assurance ..................................................................................................... 4 Overvie ew ...................................................................................................................... 4 Electric cal and Visual / Mech hanical Outgoing Quality Graph hs ................................... 5 Failure Rate Estiimation ............................................................................................ 6 culation Me ethod ................................................................................ 6 Failure Rate Calc oltage Isola ation Relia ability 2.5K KV rms Rate ed Productts .................................... 9 High Vo High Vo oltage Isola ation Relia ability 5KV rms Rated Products ..................................... 10 Reliability Monitor Progra am .................................................................................. 11 ew .................................................................................................................... 11 Overvie Stress Descriptions................................................................................................. 11 P es and Con nditions Ta able ............................................... 11 Reliability Tests, Procedure ethod and Conditions ................................................ 12 Silicon Reliabilitty Test Me n Stresses s .................................................... 13 Reliability Monitor Reportt – Silicon ge Reliability Test Method M an nd Conditiions ............................................. 14 Packag Reflow w Profile an nd Moistu ure Sensitivity Leve el ................................................... 15 Reliability Monitor Reportt – Packag ge Stresse es ................................................. 16 Revisio on History y ...................................................................................................... 17 A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 2/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Qualitty and Reliabilit R ty Reporrt Overvie ew Silicon La aboratories is pleased to o share this ISO Qualityy and Reliabiility Report w with our custtomers and othe er interested parties. It provides p the latest qualityy performan nce data alon ng with failure rate estimates s and reliabiility monitor data. These e data are co ollected on a continual b basis as qualificattion, producttion and relia ability monito ors are com pleted. The e report is pu ublished and d updated quarterly to provide customers visib bility to the m most recent information. The Qualityy Trend ch harts on page e 5 are show wn on a rollin ng five year basis. All other reports include data a from the previous four qua arters on a rolling, one year y basis. The repo ort provides data d coverin ng: Estimates E off shipped pro oduct quality y Long-term L operating life estimates Mean M time to o failure Data D retentio on life estima ates Reliability R monitor resultts aboratories is registered d to the curre ent versionss of ISO 9001, ISO14001 1, and ISO/T TS Silicon La 16949 (a automotive products p only y) and is com mmitted to q uality excelle ence. That commitment is dergoes extensive demonstrated by extensive product and proc cess qualificcation. Each h product und qualificattion testing prior p to produ uction releas se. Silicon L Laboratoriess qualifies integrated circcuit products using JEDE EC JESD47, Stress-Testt-Driven Qua alification off Integrated C Circuits or A AECQ100, Sttress Test Qualification Q for f Integrate ed Circuits, a as appropriatte. Once a product p is qu ualified, on-g going produc ct quality and d reliability iss verified thrrough monito oring programs s. Monitors are schedulled to period dically samplle wafer fab technologie es and packa age technolog gies. The re esults are pu ublished in th his report. A Any failures are used to drive correcctive action an nd process and a product improvemen nt. We hope e you find this report use eful. Please let us know if you have any specificc questions o or suggestio ons. A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 3/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Qualitty Assurrance Overvie ew Two elem ments of product quality are reported d – electrica al quality and d mechanica al/visual quality. We meas sure electric cal quality by y taking a sample (monittor) of produ uction parts a and retesting g the sample to o the datash heet limits (s see Figure 1). The samp ple electrical test may be e performed at an alternate e test temperrature to verify part perfo ormance acrross the data asheet temp perature rang ge. This sam mple method identifies de efects introduced at the test processs step or tha at have esca aped the test process. p Any failures drrive correctiv ve actions an nd product/p process imprrovements. Visual/Mechanical qu uality is estim mated by sample inspecction of the ccompleted product prior to final spection item ms cover a broad b range of characte ristics and in nclude markk, count, labe el, pack. Ins cover tap pe workmans ship, moistu ure barrier ba ag integrity, lead location n, part place ement, and m many other gen neral workmanship items required fo or customer satisfaction and producct protection during shipmentt. Any failurres drive corrective actio ons and proccess improve ements. Figure 1 – Quality Monitor Flow Orderr Fulfillme ent Ass sembly Tes st Electrrical DPP PM Sca an FGI Ship Me echanicall DPPM A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 4/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Electric cal and Visual / Mechanical Outgoing O Quality G Graphs 12Q4 Sample S size = 8,132,084 dppm m=6 12Q4 Sa ample size = 16,547,757 dppm m = 0.1 A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 5/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Failure Rate Esttimation Failure in Time (FIT T) A long-te erm, steady-s state failure rate is often n required byy circuit and system eng gineers for allocation ns of the failure rates at the compon nent level du uring system design. FIT T, which stan nds for failure-in-time, is a widely w used term to describe failure rrates of elecctronic components, and as used herre, representts the numbe er of failures s in a billion hours of ope eration. FIT T rates are re eported in the following sectio on as curves s and in tables for speciffic temperattures and asssumptions. me to Failure (MTTF) Mean Tim Another way w to expre ess failure ra ates is by me ean time to ffailure (MTT TF). MTTF iss the inverse e of the FIT rate and a is usefu ul for repair and a maintenance plannin ng. This relationship ca an be seen b by examinin ng the units of o each mea asure: MTTF F is given in time/failure;; FIT is given n in failure/tiime. MTTF is reported in the t tables fo ollowing the FIT rate curv rves for each h specific fab b technologyy. Failure Rate Callculation Method M Long-term m failure rate es are estim mated by app plying the Arrrhenius equ uation to data a collected ffrom long term m operating life tests. A confidence factor is app plied based u upon the sample size an nd number of o failures to o estimate the maximum failure rate at a specificc confidence e level. The calculatio on details arre provided in the table below b each o of the follow wing FIT rate curves. A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 6/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 FIT Rate Curves s and Data Proces ss - 0.25 m icron Failu ure Rate as a Function off Junction Te emperature Esttimated uppe er bound at ttwo confiden nce levels 180 0.0 160 0.0 140 0.0 120 0.0 FIT Rate 100 0.0 FIT (90%) 80 0.0 FIT (60%) 60 0.0 40 0.0 20 0.0 0.0 0 3 40 25 30 35 45 50 55 60 65 70 7 75 80 85 5 90 95 100 105 110 115 12 20 Junction Temperature T [C]] A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 7/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 8/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 High Vo oltage Iso olation Reliability 2.5KV rms R Rated Prod ducts Note: TDDB = Time Dependent D Dielectric Brea akdown (stan ndard dielecttric characterrization methodollogy) A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 9/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 High Vo oltage Iso olation Reliability 5K KV rms Ratted Produ ucts 1000 266 yyears @ 800V Vrms 100 Years (10ppm) 10 1 0.1 0.01 y = 6522.9e‐0.004x 0.001 0 0.0 0001 0 500 1000 1 150 00 2000 2500 3000 3500 4 4000 Voltagee Note: TDDB = Time Dependent D Dielectric Brea akdown (stan ndard dielecttric characterrization methodollogy) A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 10/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Reliab bility Mo onitor Prrogram Overvie ew Once a product p is qu ualified, we verify v continu ued product reliability wiith a reliability monitor program.. The monito or program is i scheduled d to periodica ally sample wafer fab an nd package technolog gies. The re esults are pu ublished in th his report. A Any failures are used to drive correcctive action an nd product and process improvemen nt. Stress s Descriiptions Silicon La aboratories follows JEDEC as the preferred p ind ustry standa ard. The mo ost common reliability y tests and co onditions are e listed in the following ttable. The sspecific JEDEC docume ents are available e on the Interrnet at www.jedec.org. Reliability Tests, Procedures and Conditions C s Table Symb bol DR R Stress Name N Data Retention Ba ake Stress P Procedure AEC C_Q100 Sta andard Conditions 150°C (pkg form); 250C (wafer) ELFR Early y Life Failure Rate JEDEC J ESD22-A108 125°C; Max operating vo oltage HAST Highly-Accelerate ed Temp perature and Humidity Stresss Test JEDEC J ESD22-A110 130°C; 85%rrh; 22.2 psia; biased HTB B High Temperature e Bake JEDEC J ESD22-A103 150°C JEDEC J ESD22-A108 -10°C; Max operating voltage JEDEC J ESD22-A108 125°C; Max operating vo oltage LTOL HTO OL Low Temperature e Operating Life e Operating High Temperature Life PC Preco onditioning JEDEC J ESD22-A113 According to o MSL level p prior to package stre esses (listed below) TC Temp perature Cycle JEDEC J ESD22-A104 Condition C: -65 to 150°C Unbiased HAST JEDEC J ESD22-A118 130°C; 85%rrh Temp perature Hum midity Bias JEDEC J ESD22-A101 85°C; 85%RH H; Max opera ating voltage U-HA AST THB B Qualification Guidelline en Qualification of Integraated Circuits;; EIA / JEDEC C EIA/JESD47 / AEC-Q100 Stress Test Drive A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 11/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Silicon Reliab bility Tes st Metho od and C Conditio ons Early Liffe Failure Rate (ELFR) The purp pose of this test t is to sim mulate the us ser operation n over the firrst portion off the productt lifetime, also a called early e life. Sillicon Labora atories typica ally uses dyn namic condittions, meaniing the device is s powered up p, and the in nputs are tog ggled to exerrcise a maximum numbe er of transisttors and circu uit area. Relliability acce eleration is accomplished d primarily b by temperatu ure and secondarily by voltag ge. High Tem mperature Operating O Life L (HTOL) The purp pose of this test t is to sim mulate the us ser part operration over th he expected d life of the product. We typically y use dynam mic condition ns, meaning the device iis powered u up, and the iinputs are toggled to exercise a maximu um number of transistorrs and circuitt area. Relia ability accele eration is accom mplished prim marily by tem mperature an nd secondariily by voltage e. High Tem mperature Storage S Life e (HTSL) / High H Tempe erature Bake e (HTB) The purp pose of this test t is to determine the effect e of storrage at eleva ated tempera ature. This is performe ed to assess the stability y of semiconductor devicce materials and interfacces. Low Tem mperature Operating O Life (LTOL) The purp pose of this test t is to sim mulate the us ser operation n at low temp perature. Th his is a speccialized test to ad ddress speciific fab failurre mechanisms, such ass hot-carrier injection. W Wafer level reliability y tests are more effective e for this cha aracterizatio n and are th he primary qualification method. Silicon Laboratories typ pically uses dynamic con nditions, me eaning the de evice is pow wered up, and the t inputs arre toggled to o exercise a maximum n umber of tra ansistors and d circuit area a. Nonvola atile Memory y Data Rete ention (DR) The purp pose of this test t is to measure the ab bility of a non nvolatile me emory cell to retain its ch harge state at elevated e tem mperature in the absence e of applied external bia as. This test can be done either in wafer form or o on packag ged units. A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 12/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Reliab bility Mo onitor Re eport – Silicon S S Stresses s QLotNum m Stress FabPrrocess ReadDate SampleSiz ze ReadPtt Fails ºC 31872 32544 32540 32402 32403 32404 32698 32699 33171 33118 33119 BAKE BAKE BAKE BAKE BAKE BAKE BAKE BAKE BAKE BAKE BAKE 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 0.25 5 um 11-Jan-12 27-Mar-12 11-May-12 2 27-Jun-12 27-Jun-12 27-Jun-12 22-Aug-12 22-Aug-12 11-Oct-12 23-Nov-12 27-Nov-12 80 80 80 28 28 28 80 80 45 80 80 1000 1000 1000 1000 1000 1000 500 500 1000 500 500 0 0 0 0 0 0 0 0 0 0 0 150 150 150 150 150 150 175 175 125 135 135 A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 13/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Packa age Relia ability Test T Method and d Condittions Precond ditioning (PC C) This test method is performed p to o simulate the various sh hipping cond ditions, the e end use environm ment and cus stomer board d mounting process p for a given packkaging syste em. Precondiitioning is an n industry sta andard flow for non-herm metic (plastic) integrated d circuit packages that is representative e of a typicall industry solder reflow o operation. Th he test partss are subjectt to bake, mo oisture soak and three re eflow cycles prior to bein ng submitted d to package e reliability te esting. Tempera ature Cyclin ng (TC) This test evaluates potential p relia ability degrad dation due to o thermal cyycling effectss. Devices are placed in n a chamber using forced d air to cycle e devices be etween the sspecified tem mperature extremes s. This test is s conducted d to determin ne the abilityy of compone ents and solder intercon nnects to withsta and mechan nical stresses s induced by y alternating g high and lo ow temperatu ure extremes. Permane ent changes in electrical and/or phys sical charactteristics can result from these mechanical stresses.. Tempera ature Humid dity and Bia as (THB) This test evaluates th he reliability of non-herm metic packag ged integrate ed circuits in n humid environm ments. It employs severe e conditions of temperatture, humiditty and bias tto accelerate e the penetration of moistu ure through the t external protective m material (enccapsulant) or along the interface between the e external protective ma aterial and th he metallic cconductors p passing throu ugh it. This test is less acce elerated than n autoclave and a unbiase ed HAST and d takes long ger to comple ete. It provides more realisttic results in line with ac ctual field pe rformance. The domina ant failure mechanis sm is alumin num corrosio on accelerated by moistu ure, bias and d contamina ation. Highly-A Accelerated Temperatu ure and Hum midity Stres ss Test (HAS ST) This test evaluates th he reliability of non-herm metic packag ged integrate ed circuits in n humid environm ments. It emp ploys severe e conditions of temperatu ure, humidityy, and bias w which accele erate the pene etration of mo oisture throu ugh the external protectivve material (encapsulan nt or seal) orr along the interfface between the external protective e material an nd the metallic conducto ors which pass through it. The stress s usually acttivates the same failure mechanismss as the “85/85” Temperrature y and Bias (T THB) test. Humidity Unbiased Highly-Ac ccelerated Stress S Testt (U-HAST) This test is performed to evaluate the reliability of non-he ermetic packkaged integrrated circuitss in nvironments. It is an alte ernate to Auttoclave and tests for the e same failurre mechanisms. It humid en employs severe cond ditions of tem mperature, humidity, h and d pressure to accelerate e the penetra ation of moisture through the e external pro otective matterial (encap psulant) or along the inte erface betwe een the external protective material m and the t metallic conductors passing thro ough it. UHA AST is prefe erred over the autoclave sttress method d due to the reduction in n artifacts ind duced by the e 100%rh environm ment of autoc clave, such as a lead corro osion or con ntamination ttransfer by liiquid water. The dominant failure mec chanism is corrosion c of internal mate erials. A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 14/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Reflow w Profile e and Moisture Sensitiv vity Leve el Overvie ew Non-herm metic (plastic c) integrated d circuit pack kages are cl assified by m moisture sen nsitivity leve el according g to IPC/JED DEC J-Std-0 020. It is crittical for final product qua ality that the board asse embly process account a for package mo oisture sensitivity, especcially the pea ak reflow tem mperature an nd the maximum m manufactu uring expose e time (MET)). Reflow w Profile Non-herm metic integra ated circuit SMD S (surface mount devvices) are qu ualified in co ompliance to o the applicablle reflow pro ofiles provide ed in IPC/JEDEC J-Std-0 020. The bo oard assemb bler should n not exceed the limits deffined in the reflow r profile e tables of IP PC/JEDEC JJ-Std-020. Moisturre Sensitivity Levell The Mois sture Sensitivity Level (M MSL) and pe eak reflow te emperature a are indicated d on each prroduct packing label. l A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 15/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Reliab bility Mo onitor Re eport – Package P e Stress ses QLotNum m Stresss PkgType Read Date Sa ample Size Read Pointt Fails 32700 32704 32701 32703 33121 33120 33116 33117 31793 31881 31883 32545 HAST HAST TEMPCY YCLE TEMPCY YCLE HAST TEMPCY YCLE HAST TEMPCY YCLE TEMPCY YCLE TEMPCY YCLE HAST UHAS ST 8-PD DIPGW-300-L LF 8-PD DIPGW-300-L LF 8-PD DIPGW-300-L LF 8-PD DIPGW-300-L LF 8-PD DIPGW-300-L LF 8-PD DIPGW-300-L LF 8-S SOIC-150-LF F 8-S SOIC-150-LF F 16--SOIC-150-LF F 16--SOIC-300-LF F 16--SOIC-300-LF F 16--SOIC-300-LF F 02-Au ug-12 07-Au ug-12 08-Au ug-12 08-Au ug-12 05-No ov-12 07-No ov-12 13-No ov-12 13-No ov-12 10-Ja an-12 28-Ja an-12 01-Fe eb-12 15-Ma ar-12 80 80 80 80 80 80 80 80 80 30 30 80 96 96 500 500 96 500 96 500 500 500 96 96 0 0 0 0 0 0 0 0 0 0 0 0 A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 16/17 S Silicon L Laborato ories TITLE Quartterly Quality & Reliability Report R Do oc ID ISO OProdQ412 Revision Histtory Rev No 01 Description Effective D Date Orriginal 17-Jan-20 013 A All rights reserv ved. No part off this publication n may be repro oduced withoutt prior approvall by Silicon Lab boratories, Inc. Pg 17/17