HM62A16100I Series Wide Temperature Range Version 16 M SRAM (1-Mword × 16-bit) REJ03C0053-0001Z Preliminary Rev. 0.01 Jun.02.2003 Description The Renesas HM62A16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62A16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75 mm bump pitch for high density surface mounting. Features • Single 1.8 V supply: 1.65 V to 2.2 V • Fast access time: 70 ns (max) • Power dissipation: Active: 3.6 mW/MHz (typ) Standby: 0.9 µW (typ) • Completely static memory. No clock or timing strobe required • Equal access and cycle times • Common data input and output. Three state output • Battery backup operation. 2 chip selection for battery backup • Temperature range: −40 to +85°C Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Renesas Technology’s Sales Dept. regarding specification. Rev.0.01, Jun.02.2003, page 1 of 17 HM62A16100I Series Ordering Information Type No. Access time Package HM62A16100LBPI-7 70 ns 48-bump CSP with 0.75 mm bump pitch (TBP-48F) HM62A16100LBPI-7SL 70 ns Rev.0.01, Jun.02.2003, page 2 of 17 HM62A16100I Series Pin Arrangement 48-bumps CSP 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 VSS A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NU (Top view) Pin Description Pin name Function A0 to A19 Address input I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable LB Lower byte select UB Upper byte select VCC Power supply VSS Ground 1 NU* Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Rev.0.01, Jun.02.2003, page 3 of 17 HM62A16100I Series Block Diagram LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 MSB A6 V CC V SS • • • • • Row decoder I/O0 Memory matrix 8,192 x 128 x 16 Column I/O • • Input data control Column decoder I/O15 MSB A17 A7 A5 A4 A2 A1 A0 LSB • • CS2 CS1 LB UB WE OE Rev.0.01, Jun.02.2003, page 4 of 17 Control logic • • HM62A16100I Series Operation Table CS1 CS2 WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS VCC −0.3 to + 2.6 V Terminal voltage on any pin relative to VSS VT −0.3* to VCC + 0.3* V Power dissipation PT 1.0 W Storage temperature range Tstg −55 to +125 °C Storage temperature range under bias Tbias −40 to +85 °C 1 2 Notes: 1. VT min: −2.0 V for pulse half-width ≤ 10 ns. 2. Maximum voltage is +2.6 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 1.65 1.8 2.2 V VSS 0 0 0 V VIH 0.75 × VCC VCC + 0.3 V Input high voltage Input low voltage VIL −0.3 0.25 × VCC V Ambient temperature range Ta −40 85 Note: 1. VIL min: −2.0 V for pulse half-width ≤ 10 ns. Rev.0.01, Jun.02.2003, page 5 of 17 °C Note 1 HM62A16100I Series DC Characteristics Parameter 1 Symbol Min Typ* Max Unit Test conditions Input leakage current |ILI| 1 µA Vin = VSS to VCC Output leakage current |ILO| 1 µA CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL or LB = UB = VIH, VI/O = VSS to VCC Operating current ICC 8 mA CS1 = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA Average operating current ICC1 20 30 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL ICC2 2 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V 0.1 0.5 mA CS2 = VIL 2 0.5 25 µA 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Average value ISB1* 3 0.5 8 µA Output high voltage VOH VCC − 0.2 V IOH = −100 µA Output low voltage VOL 0.2 V IOL = 100 µA Standby current ISB Standby current ISB1* Notes: 1. Typical values are at VCC = 1.8 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L-version. 3. This characteristic is guaranteed only for L-SL version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.0.01, Jun.02.2003, page 6 of 17 HM62A16100I Series AC Characteristics (Ta = −40 to +85°C, VCC = 1.65 V to 2.2 V, unless otherwise noted.) Test Conditions • Input pulse levels: VIL = 0.2 V, VIH = VCC − 0.2 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 0.5 × VCC • Output load: See figures (Including scope and jig) VCC 3K Dout 30pF Rev.0.01, Jun.02.2003, page 7 of 17 3K HM62A16100I Series Read Cycle HM62A16100I -7 Parameter Symbol Min Max Unit Notes Read cycle time tRC 70 ns Address access time tAA 70 ns Chip select access time tACS1 70 ns tACS2 70 ns Output enable to output valid tOE 35 ns Output hold from address change tOH 10 ns LB, UB access time tBA 70 ns Chip select to output in low-Z tCLZ1 10 ns 2, 3 tCLZ2 10 ns 2, 3 LB, UB enable to low-Z tBLZ 5 ns 2, 3 Output enable to output in low-Z tOLZ 5 ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 25 ns 1, 2, 3 tCHZ2 0 25 ns 1, 2, 3 LB, UB disable to high-Z tBHZ 0 25 ns 1, 2, 3 Output disable to output in high-Z tOHZ 0 25 ns 1, 2, 3 Notes Write Cycle HM62A16100I -7 Parameter Symbol Min Max Unit Write cycle time tWC 70 ns Address valid to end of write tAW 60 ns Chip selection to end of write tCW 60 ns 5 Write pulse width tWP 50 ns 4 LB, UB valid to end of write tBW 60 ns Address setup time tAS 0 ns 6 Write recovery time tWR 0 ns 7 Data to write time overlap tDW 30 ns Data hold from write time tDH 0 ns Output active from end of write tOW 5 ns 2 Output disable to output in high-Z tOHZ 0 25 ns 1, 2 Write to output in high-Z tWHZ 0 25 ns 1, 2 Rev.0.01, Jun.02.2003, page 8 of 17 HM62A16100I Series Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. Rev.0.01, Jun.02.2003, page 9 of 17 HM62A16100I Series Timing Waveform Read Cycle t RC Valid address Address tAA tACS1 CS1 tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 tCHZ2 tBHZ tBA LB, UB tBLZ tOHZ tOE OE tOLZ Dout High impedance Rev.0.01, Jun.02.2003, page 10 of 17 tOH Valid data HM62A16100I Series Write Cycle (1) (WE Clock) tWC Valid address Address tWR tCW CS1 tCW CS2 tBW LB, UB tAW tWP WE tAS tDW tDH Valid data Din tWHZ tOW High impedance Dout Rev.0.01, Jun.02.2003, page 11 of 17 HM62A16100I Series Write Cycle (2) (CS1, CS2 Clock, OE = VIH) tWC Valid address Address tAW tAS tCW tAS tCW tWR CS1 CS2 tBW LB, UB tWP WE tDW Din Dout Rev.0.01, Jun.02.2003, page 12 of 17 Valid data High impedance tDH HM62A16100I Series Write Cycle (3) (LB, UB Clock, OE = VIH) tWC Valid address Address tAW tCW tWR CS1 tCW CS2 tAS tBW UB (LB) tBW LB (UB) tWP WE tDW Din-UB (Din-LB) Din-LB (Din-UB) Dout Rev.0.01, Jun.02.2003, page 13 of 17 tDH Valid data tDW Valid data High impedance tDH HM62A16100I Series Low VCC Data Retention Characteristics (Ta = −40 to +85°C) 4 3 Parameter Symbol Min Typ* Max Unit Test conditions* VCC for data retention VDR 1.0 2.2 V Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Data retention current ICCDR* 1 0.5 25 µA VCC = 1.5 V, Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Average value ICCDR* 2 0.5 8 µA Chip deselect to data retention time tCDR 0 ns Operation recovery time tR 5 ms See retention waveforms Notes: 1. This characteristic is guaranteed only for L-version. 2. This characteristic is guaranteed only for L-SL version. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. 4. Typical values are at VCC = 1.5 V, Ta = +25°C and not guaranteed. Rev.0.01, Jun.02.2003, page 14 of 17 HM62A16100I Series Low VCC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR Data retention mode tR V CC 1.65 V 0.75 × V CC V DR CS1 CS1 ≥ VCC – 0.2 V 0V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR V CC 1.65 V CS2 V DR 0.25 × V CC 0 V < CS2 < 0.2 V 0V Low VCC Data Retention Timing Waveform (3) (LB, UB Controlled) t CDR Data retention mode V CC 1.65 V 0.75 × V CC V DR LB, UB 0V Rev.0.01, Jun.02.2003, page 15 of 17 LB, UB ≥ VCC – 0.2 V tR HM62A16100I Series Package Dimensions HM62A16100LBPI Series (TBP-48F) As of January, 2003 8.00 0.20 S A 2.125 0.20 S B Unit: mm A INDEX MARK A 6 5 4 3 2 1 Pin#1 INDEX A B 9.50 C D E F 0.75 G 4´ 0.75 0.15 0.2 S 2.125 48 ´ f0.35 ± 0.05 f0.08 M S A B 1.2 Max 0.25 ± 0.05 S 0.10 S H Details of the part A Package Code JEDEC JEITA Mass (reference value) Rev.0.01, Jun.02.2003, page 16 of 17 TBP-48F – – 0.15 g B HM62A16100I Series Sales Strategic Planning Div. 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