C8051F388x and C8051F389x and C80538Ax and C80538Bx Flash MCU Family

C8051F388/9/A/B
Flash MCU Family
Analog Peripherals
- 10-Bit ADC
• Up to 500 ksps
• Built-in analog multiplexer with single-ended and
•
•
•
differential mode
VREF from external pin, internal reference, or VDD
Built-in temperature sensor
External conversion start input option
- Two comparators
- Internal voltage reference
- Brown-out detector and POR Circuitry
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 2.7 to 5.25 V supported using On-Chip
Voltage Regulators
High Speed 8051 μC Core
- Pipelined instruction architecture; executes 70% of
-
instructions in 1 or 2 system clocks
Up to 48 MIPS operation
Expanded interrupt handler
Rev. 1.1 5/15
Memory
- 4352 or 2304 Bytes RAM
- 64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Digital Peripherals
- 40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, two I2C/SMBus™, and two
-
enhanced UART serial ports
Six general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five capture/compare modules
External Memory Interface (EMIF)
Clock Sources
- Internal Oscillator: ±1.5% accuracy. Supports all UART
-
modes
External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
Low Frequency (80 kHz) Internal Oscillator
Can switch between clock sources on-the-fly
Packages
- 48-pin TQFP (C8051F388/A)
- 32-pin LQFP (C8051F389/B)
- 5x5 mm 32-pin QFN (C8051F389/B)
Temperature Range: –40 to +85 °C
Copyright © 2015 by Silicon Laboratories
C8051F388/9/A/B
2
Rev. 1.1
C8051F388/9/A/B
Table of Contents
1. System Overview ..................................................................................................... 15
2. C8051F34x Compatibility ........................................................................................ 19
2.1. Hardware Incompatibilities ................................................................................ 20
3. Pinout and Package Definitions ............................................................................. 21
4. Typical Connection Diagrams ................................................................................ 33
4.1. Power ............................................................................................................ 33
5. Electrical Characteristics ........................................................................................ 34
5.1. Absolute Maximum Specifications..................................................................... 34
5.2. Electrical Characteristics ................................................................................... 35
6. 10-Bit ADC ................................................................................................................ 42
6.1. Output Code Formatting .................................................................................... 43
6.3. Modes of Operation ........................................................................................... 46
6.3.1. Starting a Conversion................................................................................ 46
6.3.2. Tracking Modes......................................................................................... 47
6.3.3. Settling Time Requirements...................................................................... 48
6.4. Programmable Window Detector....................................................................... 52
6.4.1. Window Detector Example........................................................................ 54
6.5. ADC0 Analog Multiplexer .................................................................................. 55
7. Voltage Reference Options ..................................................................................... 58
8. Comparator0 and Comparator1.............................................................................. 60
8.1. Comparator Multiplexers ................................................................................... 67
9. Voltage Regulators (REG0 and REG1)................................................................... 70
9.1. Voltage Regulator (REG0)................................................................................. 70
9.1.1. Regulator Mode Selection......................................................................... 70
9.1.2. External Interrupt 2 (INT2) ........................................................................ 70
9.2. Voltage Regulator (REG1)................................................................................. 70
10. Power Management Modes................................................................................... 72
10.1. Idle Mode......................................................................................................... 72
10.2. Stop Mode ....................................................................................................... 73
10.3. Suspend Mode ................................................................................................ 73
11. CIP-51 Microcontroller........................................................................................... 75
11.1. Instruction Set.................................................................................................. 76
11.1.1. Instruction and CPU Timing .................................................................... 76
11.2. CIP-51 Register Descriptions .......................................................................... 81
12. Prefetch Engine...................................................................................................... 84
13. Memory Organization ............................................................................................ 85
13.1. Program Memory............................................................................................. 86
13.2. Data Memory ................................................................................................... 86
13.3. General Purpose Registers ............................................................................. 87
13.4. Bit Addressable Locations ............................................................................... 87
13.5. Stack ............................................................................................................ 87
14. External Data Memory Interface and On-Chip XRAM ......................................... 88
14.1. Accessing XRAM............................................................................................. 88
Rev. 1.1
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C8051F388/9/A/B
14.1.1. 16-Bit MOVX Example ............................................................................ 88
14.1.2. 8-Bit MOVX Example .............................................................................. 88
14.2. Configuring the External Memory Interface ..................................................... 89
14.3. Port Configuration............................................................................................ 89
14.4. Multiplexed and Non-multiplexed Selection..................................................... 92
14.4.1. Multiplexed Configuration........................................................................ 92
14.4.2. Non-multiplexed Configuration................................................................ 93
14.5. Memory Mode Selection.................................................................................. 94
14.5.1. Internal XRAM Only ................................................................................ 94
14.5.2. Split Mode without Bank Select............................................................... 94
14.5.3. Split Mode with Bank Select.................................................................... 95
14.5.4. External Only........................................................................................... 95
14.6. Timing ............................................................................................................ 96
14.6.1. Non-multiplexed Mode ............................................................................ 98
14.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................... 98
14.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ......... 99
14.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 100
14.6.2. Multiplexed Mode .................................................................................. 101
14.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 101
14.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 102
14.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 103
15. Special Function Registers................................................................................. 105
15.1. SFR Paging ................................................................................................... 105
16. Interrupts .............................................................................................................. 112
16.1. MCU Interrupt Sources and Vectors.............................................................. 113
16.1.1. Interrupt Priorities.................................................................................. 113
16.1.2. Interrupt Latency ................................................................................... 113
16.2. Interrupt Register Descriptions ...................................................................... 113
16.3. INT0 and INT1 External Interrupt Sources .................................................... 121
17. Reset Sources ...................................................................................................... 123
17.1. Power-On Reset ............................................................................................ 124
17.2. Power-Fail Reset / VDD Monitor ................................................................... 125
17.3. External Reset ............................................................................................... 126
17.4. Missing Clock Detector Reset ....................................................................... 126
17.5. Comparator0 Reset ....................................................................................... 126
17.6. PCA Watchdog Timer Reset ......................................................................... 127
17.7. Flash Error Reset .......................................................................................... 127
17.8. Software Reset .............................................................................................. 127
18. Flash Memory....................................................................................................... 129
18.1. Programming The Flash Memory .................................................................. 129
18.1.1. Flash Lock and Key Functions .............................................................. 129
18.1.2. Flash Erase Procedure ......................................................................... 129
18.1.3. Flash Write Procedure .......................................................................... 130
18.2. Non-Volatile Data Storage............................................................................. 131
18.3. Security Options ............................................................................................ 131
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C8051F388/9/A/B
19. Oscillators and Clock Selection ......................................................................... 136
19.1. System Clock Selection................................................................................. 137
19.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 139
19.2.1. Internal Oscillator Suspend Mode ......................................................... 139
19.3. Clock Multiplier .............................................................................................. 141
19.4. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 142
19.4.1. Calibrating the Internal L-F Oscillator.................................................... 142
19.5. External Oscillator Drive Circuit..................................................................... 143
19.5.1. External Crystal Mode........................................................................... 143
19.5.2. External RC Example............................................................................ 145
19.5.3. External Capacitor Example.................................................................. 145
20. Port Input/Output ................................................................................................. 147
20.1. Priority Crossbar Decoder ............................................................................. 148
20.2. Port I/O Initialization ...................................................................................... 152
20.3. General Purpose Port I/O .............................................................................. 155
21. SMBus0 and SMBus1 (I2C Compatible)............................................................. 166
21.1. Supporting Documents .................................................................................. 167
21.2. SMBus Configuration..................................................................................... 167
21.3. SMBus Operation .......................................................................................... 167
21.3.1. Transmitter Vs. Receiver....................................................................... 168
21.3.2. Arbitration.............................................................................................. 168
21.3.3. Clock Low Extension............................................................................. 168
21.3.4. SCL Low Timeout.................................................................................. 168
21.3.5. SCL High (SMBus Free) Timeout ......................................................... 169
21.4. Using the SMBus........................................................................................... 169
21.4.1. SMBus Configuration Register.............................................................. 169
21.4.2. SMBus Timing Control Register............................................................ 171
21.4.3. SMBnCN Control Register .................................................................... 175
21.4.3.1. Software ACK Generation ............................................................ 175
21.4.3.2. Hardware ACK Generation ........................................................... 175
21.4.4. Hardware Slave Address Recognition .................................................. 178
21.4.5. Data Register ........................................................................................ 182
21.5. SMBus Transfer Modes................................................................................. 184
21.5.1. Write Sequence (Master) ...................................................................... 184
21.5.2. Read Sequence (Master) ...................................................................... 185
21.5.3. Write Sequence (Slave) ........................................................................ 186
21.5.4. Read Sequence (Slave) ........................................................................ 187
21.6. SMBus Status Decoding................................................................................ 187
22. UART0 ................................................................................................................... 193
22.1. Enhanced Baud Rate Generation.................................................................. 194
22.2. Operational Modes ........................................................................................ 195
22.2.1. 8-Bit UART ............................................................................................ 195
22.2.2. 9-Bit UART ............................................................................................ 196
22.3. Multiprocessor Communications ................................................................... 197
23. UART1 ................................................................................................................... 201
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5
C8051F388/9/A/B
23.1. Baud Rate Generator .................................................................................... 202
23.2. Data Format................................................................................................... 203
23.3. Configuration and Operation ......................................................................... 204
23.3.1. Data Transmission ................................................................................ 204
23.3.2. Data Reception ..................................................................................... 204
23.3.3. Multiprocessor Communications ........................................................... 205
24. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 211
24.1. Signal Descriptions........................................................................................ 212
24.1.1. Master Out, Slave In (MOSI)................................................................. 212
24.1.2. Master In, Slave Out (MISO)................................................................. 212
24.1.3. Serial Clock (SCK) ................................................................................ 212
24.1.4. Slave Select (NSS) ............................................................................... 212
24.2. SPI0 Master Mode Operation ........................................................................ 212
24.3. SPI0 Slave Mode Operation .......................................................................... 214
24.4. SPI0 Interrupt Sources .................................................................................. 215
24.5. Serial Clock Phase and Polarity .................................................................... 215
24.6. SPI Special Function Registers ..................................................................... 217
25. Timers ................................................................................................................... 224
25.1. Timer 0 and Timer 1 ...................................................................................... 227
25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 227
25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 228
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 228
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 229
25.2. Timer 2 .......................................................................................................... 235
25.2.1. 16-bit Timer with Auto-Reload............................................................... 235
25.2.2. 8-bit Timers with Auto-Reload............................................................... 236
25.2.3. Timer 2 Capture Modes: LFO Falling Edge .......................................... 236
25.3. Timer 3 .......................................................................................................... 242
25.3.1. 16-bit Timer with Auto-Reload............................................................... 242
25.3.2. 8-bit Timers with Auto-Reload............................................................... 243
25.3.3. Timer 3 Capture Modes: LFO Falling Edge .......................................... 243
25.4. Timer 4 .......................................................................................................... 249
25.4.1. 16-bit Timer with Auto-Reload............................................................... 249
25.4.2. 8-bit Timers with Auto-Reload............................................................... 250
25.5. Timer 5 .......................................................................................................... 254
25.5.1. 16-bit Timer with Auto-Reload............................................................... 254
25.5.2. 8-bit Timers with Auto-Reload............................................................... 255
26. Programmable Counter Array............................................................................. 259
26.1. PCA Counter/Timer ....................................................................................... 260
26.2. PCA0 Interrupt Sources................................................................................. 261
26.3. Capture/Compare Modules ........................................................................... 262
26.3.1. Edge-triggered Capture Mode............................................................... 263
26.3.2. Software Timer (Compare) Mode.......................................................... 264
26.3.3. High-Speed Output Mode ..................................................................... 265
26.3.4. Frequency Output Mode ....................................................................... 266
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C8051F388/9/A/B
26.3.5. 8-bit Pulse Width Modulator Mode ....................................................... 267
26.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 268
26.4. Watchdog Timer Mode .................................................................................. 269
26.4.1. Watchdog Timer Operation ................................................................... 269
26.4.2. Watchdog Timer Usage ........................................................................ 270
26.5. Register Descriptions for PCA0..................................................................... 272
27. C2 Interface .......................................................................................................... 277
27.1. C2 Interface Registers................................................................................... 277
27.2. C2 Pin Sharing .............................................................................................. 280
28. Revision Specific Behavior................................................................................. 281
28.1. Revision Identification.................................................................................... 281
28.2. INT2 Pin Not Connected................................................................................ 283
Document Change List.............................................................................................. 284
Contact Information................................................................................................... 285
Rev. 1.1
7
C8051F388/9/A/B
List of Figures
Figure 1.1. C8051F388/A Block Diagram ................................................................ 17
Figure 1.2. C8051F389/B Block Diagram ................................................................ 18
Figure 3.1. TQFP-48 (C8051F388/A) Pinout Diagram (Top View) .......................... 24
Figure 3.2. TQFP-48 Package Diagram .................................................................. 25
Figure 3.3. TQFP-48 Recommended PCB Land Pattern ........................................ 26
Figure 3.4. LQFP-32 (C8051F389/B) Pinout Diagram (Top View) .......................... 27
Figure 3.5. LQFP-32 Package Diagram .................................................................. 28
Figure 3.6. LQFP-32 Recommended PCB Land Pattern ........................................ 29
Figure 3.7. QFN-32 (C8051F389/B) Pinout Diagram (Top View) ............................ 30
Figure 3.8. QFN-32 Package Drawing .................................................................... 31
Figure 3.9. QFN-32 Recommended PCB Land Pattern .......................................... 32
Figure 4.1. Connection Diagram with Voltage Regulator Used ............................... 33
Figure 4.2. Connection Diagram with Voltage Regulator Not Used ........................ 33
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 42
Figure 6.2. Typical Temperature Sensor Transfer Function .................................... 44
Figure 6.3. Temperature Sensor Error with 1-Point Calibration .............................. 45
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing ............................. 47
Figure 6.5. ADC0 Equivalent Input Circuits ............................................................. 48
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 54
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 54
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 58
Figure 8.1. Comparator0 Functional Block Diagram ............................................... 60
Figure 8.2. Comparator1 Functional Block Diagram ............................................... 61
Figure 8.3. Comparator Hysteresis Plot .................................................................. 62
Figure 8.4. Comparator Input Multiplexer Block Diagram ........................................ 67
Figure 11.1. CIP-51 Block Diagram ......................................................................... 75
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F388/9) ................... 85
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F38A/B) .................. 86
Figure 14.1. Multiplexed Configuration Example ..................................................... 92
Figure 14.2. Non-multiplexed Configuration Example ............................................. 93
Figure 14.3. EMIF Operating Modes ....................................................................... 94
Figure 14.4. Non-Multiplexed 16-bit MOVX Timing ................................................. 98
Figure 14.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing .................. 99
Figure 14.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing ..................... 100
Figure 14.7. Multiplexed 16-bit MOVX Timing ....................................................... 101
Figure 14.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 102
Figure 14.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 103
Figure 17.1. Reset Sources ................................................................................... 123
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 124
Figure 18.1. Flash Program Memory Map and Security Byte ................................ 131
Figure 19.1. Oscillator Options .............................................................................. 136
Figure 19.2. External Crystal Example .................................................................. 144
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 147
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Rev. 1.1
C8051F388/9/A/B
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 148
Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 149
Figure 20.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped) ............................................................................................ 150
Figure 20.5. Crossbar Priority Decoder in Example Configuration
(3 Pins Skipped) ............................................................................................... 151
Figure 21.1. SMBus Block Diagram ...................................................................... 166
Figure 21.2. Typical SMBus Configuration ............................................................ 167
Figure 21.3. SMBus Transaction ........................................................................... 168
Figure 21.4. Typical SMBus SCL Generation ........................................................ 170
Figure 21.5. Typical Master Write Sequence ........................................................ 184
Figure 21.6. Typical Master Read Sequence ........................................................ 185
Figure 21.7. Typical Slave Write Sequence .......................................................... 186
Figure 21.8. Typical Slave Read Sequence .......................................................... 187
Figure 22.1. UART0 Block Diagram ...................................................................... 193
Figure 22.2. UART0 Baud Rate Logic ................................................................... 194
Figure 22.3. UART Interconnect Diagram ............................................................. 195
Figure 22.4. 8-Bit UART Timing Diagram .............................................................. 195
Figure 22.5. 9-Bit UART Timing Diagram .............................................................. 196
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram ......................... 197
Figure 23.1. UART1 Block Diagram ...................................................................... 201
Figure 23.2. UART1 Timing Without Parity or Extra Bit ......................................... 203
Figure 23.3. UART1 Timing With Parity ................................................................ 203
Figure 23.4. UART1 Timing With Extra Bit ............................................................ 203
Figure 23.5. Typical UART Interconnect Diagram ................................................. 204
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 205
Figure 24.1. SPI Block Diagram ............................................................................ 211
Figure 24.2. Multiple-Master Mode Connection Diagram ...................................... 213
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ........................................................................................ 213
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ........................................................................................ 214
Figure 24.5. Master Mode Data/Clock Timing ....................................................... 216
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 216
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 217
Figure 24.8. SPI Master Timing (CKPHA = 0) ....................................................... 221
Figure 24.9. SPI Master Timing (CKPHA = 1) ....................................................... 221
Figure 24.10. SPI Slave Timing (CKPHA = 0) ....................................................... 222
Figure 24.11. SPI Slave Timing (CKPHA = 1) ....................................................... 222
Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 228
Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 229
Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 230
Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 235
Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 236
Figure 25.6. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 237
Rev. 1.1
9
C8051F388/9/A/B
Figure 25.7. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 238
Figure 25.8. Timer 3 16-Bit Mode Block Diagram ................................................. 242
Figure 25.9. Timer 3 8-Bit Mode Block Diagram ................................................... 243
Figure 25.10. Timer 3 Capture Mode (T3SPLIT = 0) ............................................. 244
Figure 25.11. Timer 3 Capture Mode (T3SPLIT = 0) ............................................. 245
Figure 25.12. Timer 4 16-Bit Mode Block Diagram ............................................... 249
Figure 25.13. Timer 4 8-Bit Mode Block Diagram ................................................. 250
Figure 25.14. Timer 5 16-Bit Mode Block Diagram ............................................... 254
Figure 25.15. Timer 5 8-Bit Mode Block Diagram ................................................. 255
Figure 26.1. PCA Block Diagram ........................................................................... 259
Figure 26.2. PCA Counter/Timer Block Diagram ................................................... 260
Figure 26.3. PCA Interrupt Block Diagram ............................................................ 261
Figure 26.4. PCA Capture Mode Diagram ............................................................. 263
Figure 26.5. PCA Software Timer Mode Diagram ................................................. 264
Figure 26.6. PCA High-Speed Output Mode Diagram ........................................... 265
Figure 26.7. PCA Frequency Output Mode ........................................................... 266
Figure 26.8. PCA 8-Bit PWM Mode Diagram ........................................................ 267
Figure 26.9. PCA 16-Bit PWM Mode ..................................................................... 268
Figure 26.10. PCA Module 4 with Watchdog Timer Enabled ................................ 269
Figure 27.1. Typical C2 Pin Sharing ...................................................................... 280
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Rev. 1.1
C8051F388/9/A/B
List of Tables
Table 1.1. Product Selection Guide ......................................................................... 16
Table 2.1. C8051F388/9/A/B Replacement Part Numbers ...................................... 19
Table 3.1. Pin Definitions for the C8051F388/9/A/B ................................................ 21
Table 3.2. TQFP-48 Package Dimensions .............................................................. 25
Table 3.3. TQFP-48 PCB Land Pattern Dimensions ............................................... 26
Table 3.4. LQFP-32 Package Dimensions .............................................................. 28
Table 3.5. LQFP-32 PCB Land Pattern Dimensions ............................................... 29
Table 3.6. QFN-32 Package Dimensions ................................................................ 31
Table 3.7. QFN-32 PCB Land Pattern Dimensions ................................................. 32
Table 5.1. Absolute Maximum Ratings .................................................................... 34
Table 5.2. Global Electrical Characteristics ............................................................. 35
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 36
Table 5.4. Reset Electrical Characteristics .............................................................. 36
Table 5.5. Internal Voltage Regulator Electrical Characteristics ............................. 37
Table 5.6. Flash Electrical Characteristics .............................................................. 37
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 38
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics ................. 38
Table 5.9. External Oscillator Electrical Characteristics .......................................... 38
Table 5.10. ADC0 Electrical Characteristics ............................................................ 39
Table 5.11. Temperature Sensor Electrical Characteristics .................................... 40
Table 5.12. Voltage Reference Electrical Characteristics ....................................... 40
Table 5.13. Comparator Electrical Characteristics .................................................. 41
Table 11.1. CIP-51 Instruction Set Summary .......................................................... 77
Table 14.1. AC Parameters for External Memory Interface ................................... 104
Table 15.1. Special Function Register (SFR) Memory Map .................................. 106
Table 15.2. Special Function Registers ................................................................. 107
Table 16.1. Interrupt Summary .............................................................................. 114
Table 21.1. SMBus Clock Source Selection .......................................................... 170
Table 21.2. Minimum SDA Setup and Hold Times ................................................ 171
Table 21.3. Sources for Hardware Changes to SMBnCN ..................................... 178
Table 21.4. Hardware Address Recognition Examples (EHACK = 1) ................... 179
Table 21.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 188
Table 21.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 190
Table 22.1. Timer Settings for Standard Baud Rates Using Internal Oscillator ..... 199
Table 23.1. Baud Rate Generator Settings for Standard Baud Rates ................... 202
Table 24.1. SPI Slave Timing Parameters ............................................................ 223
Table 26.1. PCA Timebase Input Options ............................................................. 260
Table 26.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules ............. 262
Table 26.3. Watchdog Timer Timeout Intervals1 ................................................... 271
Rev. 1.1
11
C8051F388/9/A/B
List of Registers
SFR Definition 6.1. ADC0CF: ADC0 Configuration ...................................................... 49
SFR Definition 6.2. ADC0H: ADC0 Data Word MSB .................................................... 50
SFR Definition 6.3. ADC0L: ADC0 Data Word LSB ...................................................... 50
SFR Definition 6.4. ADC0CN: ADC0 Control ................................................................ 51
SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 52
SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 52
SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 53
SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 53
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select ..................................... 56
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select ................................. 57
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 59
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 63
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 64
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 65
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 66
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 68
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 69
SFR Definition 9.1. REG01CN: Voltage Regulator Control .......................................... 71
SFR Definition 10.1. PCON: Power Control .................................................................. 74
SFR Definition 11.1. DPL: Data Pointer Low Byte ........................................................ 81
SFR Definition 11.2. DPH: Data Pointer High Byte ....................................................... 81
SFR Definition 11.3. SP: Stack Pointer ......................................................................... 82
SFR Definition 11.4. ACC: Accumulator ....................................................................... 82
SFR Definition 11.5. B: B Register ................................................................................ 82
SFR Definition 11.6. PSW: Program Status Word ........................................................ 83
SFR Definition 12.1. PFE0CN: Prefetch Engine Control .............................................. 84
SFR Definition 14.1. EMI0CN: External Memory Interface Control .............................. 90
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration ..................... 91
SFR Definition 14.3. EMI0TC: External Memory Timing Control .................................. 97
SFR Definition 15.1. SFRPAGE: SFR Page ............................................................... 105
SFR Definition 16.1. IE: Interrupt Enable .................................................................... 115
SFR Definition 16.2. IP: Interrupt Priority .................................................................... 116
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 ............................................ 117
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1 ............................................ 118
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2 ............................................ 119
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2 ............................................ 120
SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO ........................................... 122
SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 126
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 128
SFR Definition 18.1. PSCTL: Program Store R/W Control ......................................... 133
SFR Definition 18.2. FLKEY: Flash Lock and Key ...................................................... 134
SFR Definition 18.3. FLSCL: Flash Scale ................................................................... 135
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 138
12
Rev. 1.1
C8051F388/9/A/B
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration .............................. 139
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control ................................... 140
SFR Definition 19.4. CLKMUL: Clock Multiplier Control ............................................. 141
SFR Definition 19.5. OSCLCN: Internal L-F Oscillator Control ................................... 142
SFR Definition 19.6. OSCXCN: External Oscillator Control ........................................ 146
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 153
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 154
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2 .......................................... 155
SFR Definition 20.4. P0: Port 0 ................................................................................... 156
SFR Definition 20.5. P0MDIN: Port 0 Input Mode ....................................................... 156
SFR Definition 20.6. P0MDOUT: Port 0 Output Mode ................................................ 157
SFR Definition 20.7. P0SKIP: Port 0 Skip ................................................................... 157
SFR Definition 20.8. P1: Port 1 ................................................................................... 158
SFR Definition 20.9. P1MDIN: Port 1 Input Mode ....................................................... 158
SFR Definition 20.10. P1MDOUT: Port 1 Output Mode .............................................. 159
SFR Definition 20.11. P1SKIP: Port 1 Skip ................................................................. 159
SFR Definition 20.12. P2: Port 2 ................................................................................. 160
SFR Definition 20.13. P2MDIN: Port 2 Input Mode ..................................................... 160
SFR Definition 20.14. P2MDOUT: Port 2 Output Mode .............................................. 161
SFR Definition 20.15. P2SKIP: Port 2 Skip ................................................................. 161
SFR Definition 20.16. P3: Port 3 ................................................................................. 162
SFR Definition 20.17. P3MDIN: Port 3 Input Mode ..................................................... 162
SFR Definition 20.18. P3MDOUT: Port 3 Output Mode .............................................. 163
SFR Definition 20.19. P3SKIP: Port 3 Skip ................................................................. 163
SFR Definition 20.20. P4: Port 4 ................................................................................. 164
SFR Definition 20.21. P4MDIN: Port 4 Input Mode ..................................................... 164
SFR Definition 20.22. P4MDOUT: Port 4 Output Mode .............................................. 165
SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration ...................................... 172
SFR Definition 21.2. SMB1CF: SMBus Clock/Configuration ...................................... 173
SFR Definition 21.3. SMBTC: SMBus Timing Control ................................................ 174
SFR Definition 21.4. SMB0CN: SMBus Control .......................................................... 176
SFR Definition 21.5. SMB1CN: SMBus Control .......................................................... 177
SFR Definition 21.6. SMB0ADR: SMBus0 Slave Address .......................................... 179
SFR Definition 21.7. SMB0ADM: SMBus0 Slave Address Mask ................................ 180
SFR Definition 21.8. SMB1ADR: SMBus1 Slave Address .......................................... 180
SFR Definition 21.9. SMB1ADM: SMBus1 Slave Address Mask ................................ 181
SFR Definition 21.10. SMB0DAT: SMBus Data .......................................................... 182
SFR Definition 21.11. SMB1DAT: SMBus Data .......................................................... 183
SFR Definition 22.1. SCON0: Serial Port 0 Control .................................................... 198
SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 199
SFR Definition 23.1. SCON1: UART1 Control ............................................................ 206
SFR Definition 23.2. SMOD1: UART1 Mode .............................................................. 207
SFR Definition 23.3. SBUF1: UART1 Data Buffer ...................................................... 208
SFR Definition 23.4. SBCON1: UART1 Baud Rate Generator Control ...................... 209
SFR Definition 23.5. SBRLH1: UART1 Baud Rate Generator High Byte ................... 209
Rev. 1.1
13
C8051F388/9/A/B
SFR Definition 23.6. SBRLL1: UART1 Baud Rate Generator Low Byte ..................... 210
SFR Definition 24.1. SPI0CFG: SPI0 Configuration ................................................... 218
SFR Definition 24.2. SPI0CN: SPI0 Control ............................................................... 219
SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate ....................................................... 220
SFR Definition 24.4. SPI0DAT: SPI0 Data ................................................................. 220
SFR Definition 25.1. CKCON: Clock Control .............................................................. 225
SFR Definition 25.2. CKCON1: Clock Control 1 ......................................................... 226
SFR Definition 25.3. TCON: Timer Control ................................................................. 231
SFR Definition 25.4. TMOD: Timer Mode ................................................................... 232
SFR Definition 25.5. TL0: Timer 0 Low Byte ............................................................... 233
SFR Definition 25.6. TL1: Timer 1 Low Byte ............................................................... 233
SFR Definition 25.7. TH0: Timer 0 High Byte ............................................................. 234
SFR Definition 25.8. TH1: Timer 1 High Byte ............................................................. 234
SFR Definition 25.9. TMR2CN: Timer 2 Control ......................................................... 239
SFR Definition 25.10. TMR2RLL: Timer 2 Reload Register Low Byte ........................ 240
SFR Definition 25.11. TMR2RLH: Timer 2 Reload Register High Byte ...................... 240
SFR Definition 25.12. TMR2L: Timer 2 Low Byte ....................................................... 240
SFR Definition 25.13. TMR2H Timer 2 High Byte ....................................................... 241
SFR Definition 25.14. TMR3CN: Timer 3 Control ....................................................... 246
SFR Definition 25.15. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 247
SFR Definition 25.16. TMR3RLH: Timer 3 Reload Register High Byte ...................... 247
SFR Definition 25.17. TMR3L: Timer 3 Low Byte ....................................................... 247
SFR Definition 25.18. TMR3H Timer 3 High Byte ....................................................... 248
SFR Definition 25.19. TMR4CN: Timer 4 Control ....................................................... 251
SFR Definition 25.20. TMR4RLL: Timer 4 Reload Register Low Byte ........................ 252
SFR Definition 25.21. TMR4RLH: Timer 4 Reload Register High Byte ...................... 252
SFR Definition 25.22. TMR4L: Timer 4 Low Byte ....................................................... 252
SFR Definition 25.23. TMR4H Timer 4 High Byte ....................................................... 253
SFR Definition 25.24. TMR5CN: Timer 5 Control ....................................................... 256
SFR Definition 25.25. TMR5RLL: Timer 5 Reload Register Low Byte ........................ 257
SFR Definition 25.26. TMR5RLH: Timer 5 Reload Register High Byte ...................... 257
SFR Definition 25.27. TMR5L: Timer 5 Low Byte ....................................................... 257
SFR Definition 25.28. TMR5H Timer 5 High Byte ....................................................... 258
SFR Definition 26.1. PCA0CN: PCA Control .............................................................. 272
SFR Definition 26.2. PCA0MD: PCA Mode ................................................................ 273
SFR Definition 26.3. PCA0CPMn: PCA Capture/Compare Mode .............................. 274
SFR Definition 26.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 275
SFR Definition 26.5. PCA0H: PCA Counter/Timer High Byte ..................................... 275
SFR Definition 26.6. PCA0CPLn: PCA Capture Module Low Byte ............................. 276
SFR Definition 26.7. PCA0CPHn: PCA Capture Module High Byte ........................... 276
C2 Register Definition 27.1. C2ADD: C2 Address ...................................................... 277
C2 Register Definition 27.2. DEVICEID: C2 Device ID ............................................... 278
C2 Register Definition 27.3. REVID: C2 Revision ID .................................................. 278
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control ........................ 279
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data ............................ 279
14
Rev. 1.1
C8051F388/9/A/B
1. System Overview
C8051F388/9/A/B devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features
are listed below. Refer to Table 1.1 for specific product feature selection.











High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Supply Voltage Regulator
True 10-bit 500 ksps differential / single-ended ADC with analog multiplexer
On-chip Voltage Reference and Temperature Sensor
On-chip Voltage Comparators (2)
Precision internal calibrated 48 MHz internal oscillator
Internal low-frequency oscillator for additional power savings
Up to 64 kB of on-chip Flash memory
Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
External Memory Interface (EMIF) available on 48-pin versions.

2 I2C/SMBus, 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector

Up to 40 Port I/O (5 V tolerant)



With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F388/9/A/B devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be
reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051
firmware. User software has complete control of all peripherals, and may individually shut down any or all
peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6 V, the on-chip Voltage Regulator must be used. The Port I/O and RST pins are tolerant of input signals up to 5 V. C8051F388/9/A/B devices are available in 48-pin TQFP, 32-pin LQFP, or
32-pin QFN packages. See Table 1.1, “Product Selection Guide,” on page 16 for feature and package
choices.
Rev. 1.1
15
C8051F388/9/A/B
64k
4352
   2
 2
6
 25
—    2
LQFP32
C8051F389-B-GM
48
64k
4352
   2
 2
6
 25
—    2
QFN32
C8051F38A-B-GQ
48
32k
2304
   2
 2
6
 40
    2
TQFP48
C8051F38B-B-GQ
48
32k
2304
   2
 2
6
 25
—    2
LQFP32
C8051F38B-B-GM
48
32k
2304
   2
 2
6
 25
—    2
QFN32
Package
48
Analog Comparators
C8051F389-B-GQ
Voltage Reference
TQFP48
Temperature Sensor
    2
10-bit 500ksps ADC
Programmable Counter Array
 40
Digital Port I/O
Timers (16-bit)
6
UARTs
 2
Enhanced SPI
   2
SMBus/I2C
4352
Supply Voltage Regulator
64k
Low Frequency Oscillator
RAM
48
Calibrated Internal Oscillator
Flash Memory (Bytes)
C8051F388-B-GQ
Ordering Part Number
MIPS (Peak)
External Memory Interface (EMIF)
Table 1.1. Product Selection Guide
Note: Starting with silicon revision B, the ordering part numbers have been updated to include the silicon revision and
use this format: "C8051F388-B-GQ".
16
Rev. 1.1
C8051F388/9/A/B
Figure 1.1. C8051F388/A Block Diagram
Rev. 1.1
17
C8051F388/9/A/B
Figure 1.2. C8051F389/B Block Diagram
18
Rev. 1.1
C8051F388/9/A/B
2. C8051F34x Compatibility
The C8051F388/9/A/B family is designed to be a pin and code compatible replacement for the C8051F34x
device family. The C8051F388/9/A/B device should function as a drop-in replacement for the C8051F34x
devices in most applications that do not use USB. Table 2.1 lists recommended replacement part numbers
for C8051F34x devices. See “2.1. Hardware Incompatibilities” to determine if any changes are necessary
when upgrading an existing C8051F34x design to the C8051F388/9/A/B.
Table 2.1. C8051F388/9/A/B Replacement Part Numbers
C8051F34x Part Number
C8051F38x Part Number
C8051F340-GQ
C8051F388-B-GQ
C8051F341-GQ
C8051F38A-B-GQ
C8051F342-GQ
C8051F389-B-GQ
C8051F342-GM
C8051F389-B-GM
C8051F343-GQ
C8051F38B-B-GQ
C8051F343-GM
C8051F38B-B-GM
C8051F344-GQ
C8051F388-B-GQ
C8051F345-GQ
C8051F38A-B-GQ
C8051F346-GQ
C8051F389-B-GQ
C8051F346-GM
C8051F389-B-GM
C8051F347-GQ
C8051F38B-B-GQ
C8051F347-GM
C8051F38B-B-GM
C8051F348-GQ
C8051F38A-B-GQ
C8051F349-GQ
C8051F38B-B-GQ
C8051F349-GM
C8051F38B-B-GM
C8051F34A-GQ
C8051F389-B-GQ
C8051F34A-GM
C8051F389-B-GM
C8051F34B-GQ
C8051F38B-B-GQ
C8051F34B-GM
C8051F38B-B-GM
C8051F34C-GQ
C8051F388-B-GQ
C8051F34D-GQ
C8051F389-B-GQ
Rev. 1.1
19
C8051F388/9/A/B
2.1. Hardware Incompatibilities
While the C8051F388/9/A/B family includes a number of new features not found on the C8051F34x family,
there are some differences that should be considered for any design port.




20
Clock Multiplier: The C8051F388/9/A/B does not include the 4x clock multiplier from the C8051F34x
device families. This change only impacts systems which use the clock multiplier in conjunction with an
external oscillator source.
USB: The C8051F388/9/A/B devices do not include the USB module.
External Oscillator C and RC Modes: The C and RC modes of the oscillator have a divide-by-2 stage
on the C8051F388/9/A/B to aid in noise immunity. This was not present on the C8051F34x device
family, and any clock generated with C or RC mode will change accordingly.
Fab Technology: The C8051F388/9/A/B is manufactured using a different technology process than the
C8051F34x. As a result, many of the electrical performance parameters will have subtle differences.
These differences should not affect most systems but it is nonetheless important to review the electrical
parameters for any blocks that are used in the design, and ensure they are compatible with the existing
hardware.
Rev. 1.1
C8051F388/9/A/B
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F388/9/A/B
Name
Pin Numbers
Type
Description
48-pin 32-pin
VDD
10
6
Power In 2.7–3.6 V Power Supply Voltage Input.
Power
Out
GND
7
3
RST/
13
9
C2CK
3.3 V Voltage Regulator Output.
Ground.
D I/O
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 μs.
D I/O
Clock signal for the C2 Debug Interface.
C2D
14
—
D I/O
Bi-directional data signal for the C2 Debug Interface.
P3.0 /
—
10
D I/O
Port 3.0. See Section 20 for a complete description of Port 3.
D I/O
Bi-directional data signal for the C2 Debug Interface.
C2D
REGIN
11
7
Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.
INT2
12
8
NC
8
4
This pin is a no-connect and can be left floating.
NC
9
5
This pin is a no-connect and can be left floating.
P0.0
6
2
D I/O or Port 0.0. See Section 20 for a complete description of Port 0.
A In
P0.1
5
1
D I/O or Port 0.1.
A In
P0.2
4
32
D I/O or Port 0.2.
A In
P0.3
3
31
D I/O or Port 0.3.
A In
P0.4
2
30
D I/O or Port 0.4.
A In
P0.5
1
29
D I/O or Port 0.5.
A In
P0.6
48
28
D I/O or Port 0.6.
A In
P0.7
47
27
D I/O or Port 0.7.
A In
D In
INT2 interrupt input.
Rev. 1.1
21
C8051F388/9/A/B
Table 3.1. Pin Definitions for the C8051F388/9/A/B (Continued)
Name
Pin Numbers
Type
Description
48-pin 32-pin
P1.0
46
26
D I/O or Port 1.0. See Section 20 for a complete description of Port 1.
A In
P1.1
45
25
D I/O or Port 1.1.
A In
P1.2
44
24
D I/O or Port 1.2.
A In
P1.3
43
23
D I/O or Port 1.3.
A In
P1.4
42
22
D I/O or Port 1.4.
A In
P1.5
41
21
D I/O or Port 1.5.
A In
P1.6
40
20
D I/O or Port 1.6.
A In
P1.7
39
19
D I/O or Port 1.7.
A In
P2.0
38
18
D I/O or Port 2.0. See Section 20 for a complete description of Port 2.
A In
P2.1
37
17
D I/O or Port 2.1.
A In
P2.2
36
16
D I/O or Port 2.2.
A In
P2.3
35
15
D I/O or Port 2.3.
A In
P2.4
34
14
D I/O or Port 2.4.
A In
P2.5
33
13
D I/O or Port 2.5.
A In
P2.6
32
12
D I/O or Port 2.6.
A In
P2.7
31
11
D I/O or Port 2.7.
A In
P3.0
30
—
D I/O or Port 3.0. See Section 20 for a complete description of Port 3.
A In
P3.1
29
—
D I/O or Port 3.1.
A In
22
Rev. 1.1
C8051F388/9/A/B
Table 3.1. Pin Definitions for the C8051F388/9/A/B (Continued)
Name
Pin Numbers
Type
Description
48-pin 32-pin
P3.2
28
—
D I/O or Port 3.2.
A In
P3.3
27
—
D I/O or Port 3.3.
A In
P3.4
26
—
D I/O or Port 3.4.
A In
P3.5
25
—
D I/O or Port 3.5.
A In
P3.6
24
—
D I/O or Port 3.6.
A In
P3.7
23
—
D I/O or Port 3.7.
A In
P4.0
22
—
D I/O or Port 4.0. See Section 20 for a complete description of Port 4.
A In
P4.1
21
—
D I/O or Port 4.1.
A In
P4.2
20
—
D I/O or Port 4.2.
A In
P4.3
19
—
D I/O or Port 4.3.
A In
P4.4
18
—
D I/O or Port 4.4.
A In
P4.5
17
—
D I/O or Port 4.5.
A In
P4.6
16
—
D I/O or Port 4.6.
A In
P4.7
15
—
D I/O or Port 4.7.
A In
Rev. 1.1
23
C8051F388/9/A/B
Figure 3.1. TQFP-48 (C8051F388/A) Pinout Diagram (Top View)
24
Rev. 1.1
C8051F388/9/A/B
Figure 3.2. TQFP-48 Package Diagram
Table 3.2. TQFP-48 Package Dimensions
Dimension
A
A1
A2
b
c
D
D1
e
Min
—
0.05
0.95
0.17
0.09
Nom
—
—
1.00
0.22
—
9.00 BSC
7.00 BSC
0.50 BSC
Max
1.20
0.15
1.05
0.27
0.20
Dimension
E
E1
L
aaa
bbb
ccc
ddd
q
Min
0.45
0°
Nom
9.00 BSC
7.00 BSC
0.60
0.20
0.20
0.08
0.08
3.5°
Max
0.75
7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation ABC.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
25
C8051F388/9/A/B
Figure 3.3. TQFP-48 Recommended PCB Land Pattern
Table 3.3. TQFP-48 PCB Land Pattern Dimensions
Dimension
C1
C2
E
X1
Y1
Min
8.30
8.30
Max
8.40
8.40
0.50 BSC
0.20
1.40
0.30
1.50
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 μm minimum, all the way around
the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
26
Rev. 1.1
C8051F388/9/A/B
Figure 3.4. LQFP-32 (C8051F389/B) Pinout Diagram (Top View)
Rev. 1.1
27
C8051F388/9/A/B
Figure 3.5. LQFP-32 Package Diagram
Table 3.4. LQFP-32 Package Dimensions
Dimension
A
A1
A2
b
c
D
D1
e
Min
—
0.05
1.35
0.30
0.09
Nom
—
—
1.40
0.37
—
9.00 BSC
7.00 BSC
0.80 BSC
Max
1.60
0.15
1.45
0.45
0.20
Dimension
E
E1
L
aaa
bbb
ccc
ddd
q
Min
0.45
0°
Nom
9.00 BSC
7.00 BSC
0.60
0.20
0.20
0.10
0.20
3.5°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
28
Rev. 1.1
Max
0.75
7°
C8051F388/9/A/B
Figure 3.6. LQFP-32 Recommended PCB Land Pattern
Table 3.5. LQFP-32 PCB Land Pattern Dimensions
Dimension
C1
C2
E
X1
Y1
Min
8.40
8.40
Max
8.50
8.50
0.80 BSC
0.40
1.25
0.50
1.35
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 μm minimum, all the way around
the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.1
29
C8051F388/9/A/B
Figure 3.7. QFN-32 (C8051F389/B) Pinout Diagram (Top View)
30
Rev. 1.1
C8051F388/9/A/B
Figure 3.8. QFN-32 Package Drawing
Table 3.6. QFN-32 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
A1
b
D
D2
e
E
0.80
0.00
0.18
0.85
0.02
0.25
5.00 BSC
3.30
0.50 BSC
5.00 BSC
0.90
0.05
0.30
E2
L
aaa
bbb
ddd
eee
3.20
0.35
—
—
—
—
3.30
0.40
—
—
—
—
3.40
0.45
0.10
0.10
0.05
0.08
3.20
3.40
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.1
31
C8051F388/9/A/B
Figure 3.9. QFN-32 Recommended PCB Land Pattern
Table 3.7. QFN-32 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
X1
4.80
4.80
4.90
4.90
X2
Y1
Y2
3.20
0.75
3.20
3.40
0.85
3.40
0.50 BSC
0.20
0.30
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure
the proper paste volume.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
32
Rev. 1.1
C8051F388/9/A/B
4. Typical Connection Diagrams
This section provides typical connection diagrams for C8051F388/9/A/B devices.
4.1. Power
Figure 4.1 shows a typical connection diagram for the power pins of the C8051F388/9/A/B devices when
the internal regulator is in use. The INT2 pin may be left floating.
Figure 4.1. Connection Diagram with Voltage Regulator Used
Figure 4.2 shows a typical connection diagram for the power pins of the C8051F388/9/A/B devices when
the internal regulator is not used.
Figure 4.2. Connection Diagram with Voltage Regulator Not Used
Rev. 1.1
33
C8051F388/9/A/B
5. Electrical Characteristics
5.1. Absolute Maximum Specifications
Table 5.1. Absolute Maximum Ratings
Parameter
Min
Typ
Max
Units
Junction Temperature Under Bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
VDD > 2.2 V
VDD < 2.2 V
–0.3
–0.3
—
—
5.8
VDD + 3.6
V
V
Regulator1 in Normal Mode
Regulator1 in Bypass Mode
–0.3
–0.3
—
—
4.2
1.98
V
V
Maximum Total Current through
VDD or GND
—
—
500
mA
Maximum Output Current sunk by
RST or any Port Pin
—
—
100
mA
Voltage on RST, INT2, or any Port
I/O Pin with Respect to GND
Voltage on VDD with Respect to
GND
Conditions
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
34
Rev. 1.1
C8051F388/9/A/B
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Test Condition
Digital Supply Voltage
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)1
Specified Operating
Temperature Range
Min
Typ
Max
Unit
VRST
—
3.3
1.5
3.6
—
V
V
0
–40
—
—
48
+85
MHz
°C
14
8
0.85
—
mA
mA
mA
μA
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD2
SYSCLK = 48 MHz, VDD = 3.3 V
SYSCLK = 24 MHz, VDD = 3.3 V
SYSCLK = 1 MHz, VDD = 3.3 V
SYSCLK = 80 kHz, VDD = 3.3 V
—
—
—
—
12
7
0.45
280
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle IDD2
Digital Supply Current
(Stop or Suspend Mode, shutdown)
SYSCLK = 48 MHz, VDD = 3.3 V
SYSCLK = 24 MHz, VDD = 3.3 V
SYSCLK = 1 MHz, VDD = 3.3 V
SYSCLK = 80 kHz, VDD = 3.3 V
Oscillator not running (STOP mode),
Internal Regulators OFF, VDD = 3.3 V
Oscillator not running (STOP or SUSPEND), REG0 and REG1 both in low
power mode, VDD = 3.3 V.
Oscillator not running (STOP or SUSPEND), REG0 OFF, VDD = 3.3 V.
—
—
—
—
—
6.5
3.5
0.35
220
1
8
5
—
—
—
mA
mA
mA
μA
μA
—
100
—
μA
—
150
—
μA
Notes:
1. SYSCLK must be at least 32 kHz to enable debugging.
2. Includes normal mode bias current for REG0 and REG1. Does not include current from internal oscillators or
other analog peripherals.
Rev. 1.1
35
C8051F388/9/A/B
Table 5.3. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
Output High Voltage
IOH = –3 mA, Port I/O push-pull
IOH = –10 μA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
VDD – 0.7
VDD – 0.1
—
—
—
VDD – 0.8
—
—
—
V
Output Low Voltage
IOL = 8.5 mA
IOL = 10 μA
IOL = 25 mA
—
—
—
—
—
1.0
0.6
0.1
—
V
Input High Voltage
2.0
—
—
V
Input Low Voltage
—
—
0.8
V
—
—
—
15
±1
50
μA
INT2 Detection Input
Low Voltage
—
—
1.0
INT2 Detection Input
High Voltage
3.0
—
—
Input Leakage
Current
Weak Pullup Off
Weak Pullup On, VIN = 0 V
V
V
Table 5.4. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
IOL = 8.5 mA,
VDD = 2.7 V to 3.6 V
—
—
0.6
V
RST Input High Voltage
0.7 x VDD
—
—
V
RST Input Low Voltage
—
—
0.3 x VDD
V
—
15
40
μA
2.60
2.65
2.70
V
Time from last system clock
rising edge to reset initiation
80
580
800
μs
Delay between release of any
reset source and code
execution at location 0x0000
—
—
250
μs
Minimum RST Low Time to
Generate a System Reset
15
—
—
μs
VDD Monitor Turn-on Time
—
—
100
μs
VDD Monitor Supply Current
—
15
50
μA
RST Output Low Voltage
RST Input Pullup Current
RST = 0.0 V
VDD Monitor Threshold (VRST)
Missing Clock Detector Timeout
Reset Time Delay
36
Rev. 1.1
C8051F388/9/A/B
Table 5.5. Internal Voltage Regulator Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
2.7
—
5.25
V
3.0
3.3
3.6
V
—
—
100
mA
—
1
—
mV/mA
1.8
—
3.6
V
Voltage Regulator (REG0)
Input Voltage Range1
Output
Output
Voltage (VDD)2
Current2
Output Current = 1 to 100 mA
3
Dropout Voltage (VDO)
Voltage Regulator (REG1)
Input Voltage Range
Notes:
1. Input range specified for regulation. When an external regulator is used, should be tied to VDD.
2. Output current is total regulator output, including any current required by the C8051F388/9/A/B.
3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater.
Table 5.6. Flash Electrical Characteristics
Parameter
Flash Size
Endurance
Erase Cycle Time
Write Cycle Time
Test Condition
Min
Typ
Max
Unit
C8051F388/9*
C8051F38A/B
65536*
32768
10k
10
10
—
—
100k
15
15
—
22.5
20
Bytes
Bytes
Erase/Write
ms
μs
25 MHz System Clock
25 MHz System Clock
Notes:
1. 1024 bytes at location 0xFC00 to 0xFFFF are not available for program storage.
2. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Rev. 1.1
37
C8051F388/9/A/B
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Test Condition
Min
Typ
Max
Unit
IFCN = 11b
47.3
48
48.7
MHz
Oscillator Supply Current
(from VDD)
25 °C, VDD = 3.0 V,
OSCICN.7 = 1,
OCSICN.5 = 0
—
900
—
μA
Power Supply Sensitivity
Constant Temperature
—
110
—
ppm/V
Temperature Sensitivity
Constant Supply
—
25
—
ppm/°C
Oscillator Frequency
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Test Condition
Min
Typ
Max
Unit
OSCLD = 11b
75
80
85
kHz
Oscillator Supply Current
(from VDD)
25 °C, VDD = 3.0 V,
OSCLCN.7 = 1
—
4
—
μA
Power Supply Sensitivity
Constant Temperature
—
0.05
—
%/V
Temperature Sensitivity
Constant Supply
—
65
—
ppm/°C
Min
Typ
Max
Unit
0.02
—
30
MHz
0
—
48
MHz
Oscillator Frequency
Table 5.9. External Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
External Crystal Frequency
External CMOS Oscillator
Frequency
38
Rev. 1.1
C8051F388/9/A/B
Table 5.10. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
DC Accuracy
Resolution
10
Integral Nonlinearity
bits
—
±0.5
±1
LSB
—
±0.5
±1
LSB
Offset Error
–2
0
2
LSB
Full Scale Error
–5
–2
0
LSB
Offset Temperature Coefficient
—
0.005
—
LSB/°C
Differential Nonlinearity
Guaranteed Monotonic
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion
55
58
—
dB
—
–73
—
dB
—
78
—
dB
—
—
8.33
MHz
13
11
—
—
—
—
clocks
clocks
300
—
—
ns
—
—
500
ksps
Single Ended (AIN+ – GND)
0
—
VREF
V
Differential (AIN+ – AIN–)
–VREF
—
VREF
V
Single Ended or Differential
0
—
VDD
V
Sampling Capacitance
—
30
—
pF
Input Multiplexer Impedance
—
5
—
k
—
750
1000
μA
—
1
—
mV/V
Total Harmonic Distortion
Up to the 5th harmonic
Spurious-Free Dynamic Range
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
Track/Hold Acquisition Time
Throughput Rate
Analog Inputs
ADC Input Voltage Range
Absolute Pin Voltage with respect
to GND
Power Specifications
Power Supply Current
(VDD supplied to ADC0)
Operating Mode, 500 ksps
Power Supply Rejection
Note: Represents one standard deviation from the mean.
Rev. 1.1
39
C8051F388/9/A/B
Table 5.11. Temperature Sensor Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
Linearity
—
± 0.5
—
°C
Slope
—
2.87
—
mV/°C
Slope Error*
—
±120
—
μV/°C
Offset
Temp = 0 °C
—
764
—
mV
Offset Error*
Temp = 0 °C
—
±15
—
mV
Note: Represents one standard deviation from the mean.
Table 5.12. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
25 °C ambient
2.38
2.42
2.46
V
VREF Short-Circuit Current
—
—
8
mA
VREF Temperature
Coefficient
—
35
—
ppm/°C
Load = 0 to 200 μA to GND
—
1.5
—
ppm/μA
VREF Turn-on Time 1
4.7 μF tantalum, 0.1 μF ceramic bypass
—
3
—
ms
VREF Turn-on Time 2
0.1 μF ceramic bypass
—
100
—
μs
—
140
—
ppm/V
1
—
VDD
V
—
9
—
μA
—
75
—
μA
Internal Reference (REFBE = 1)
Output Voltage
Load Regulation
Power Supply Rejection
External Reference (REFBE = 0)
Input Voltage Range
Input Current
Sample Rate = 500 ksps; VREF = 3.0 V
Power Specifications
Supply Current
40
Rev. 1.1
C8051F388/9/A/B
Table 5.13. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter
Response Time:
Mode 0, Vcm* = 1.5 V
Response Time:
Mode 1, Vcm* = 1.5 V
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V
Test Condition
Min
Typ
Max
Unit
CP0+ – CP0– = 100 mV
—
100
—
ns
CP0+ – CP0– = –100 mV
—
250
—
ns
CP0+ – CP0– = 100 mV
—
175
—
ns
CP0+ – CP0– = –100 mV
—
500
—
ns
CP0+ – CP0– = 100 mV
—
320
—
ns
CP0+ – CP0– = –100 mV
—
1100
—
ns
CP0+ – CP0– = 100 mV
—
1050
—
ns
CP0+ – CP0– = –100 mV
—
5200
—
ns
—
1.5
4
mV/V
Common-Mode Rejection Ratio
Positive Hysteresis 1
CP0HYP1–0 = 00
—
0
1
mV
Positive Hysteresis 2
CP0HYP1–0 = 01
2
5
10
mV
Positive Hysteresis 3
CP0HYP1–0 = 10
7
10
20
mV
Positive Hysteresis 4
CP0HYP1–0 = 11
15
20
30
mV
Negative Hysteresis 1
CP0HYN1–0 = 00
—
0
1
mV
Negative Hysteresis 2
CP0HYN1–0 = 01
2
5
10
mV
Negative Hysteresis 3
CP0HYN1–0 = 10
7
10
20
mV
Negative Hysteresis 4
CP0HYN1–0 = 11
15
20
30
mV
–0.25
—
VDD + 0.25
V
Input Capacitance
—
4
—
pF
Input Bias Current
—
0.001
—
nA
–10
—
+10
mV
Power Supply Rejection
—
0.1
—
mV/V
Power-up Time
—
10
—
μs
Mode 0
—
20
—
μA
Mode 1
—
10
—
μA
Mode 2
—
4
—
μA
Mode 3
—
1
—
μA
Inverting or Non-Inverting Input
Voltage Range
Input Offset Voltage
Power Supply
Supply Current at DC
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.1
41
C8051F388/9/A/B
6. 10-Bit ADC
ADC0 on the C8051F388/9/A/B is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold, and a programmable window detector. The ADC is fully configurable under software control via Special Function Registers. The ADC may be configured to measure various different signals using the analog multiplexer described in Section “6.5. ADC0 Analog Multiplexer” on page 55. The
voltage reference for the ADC is selected as described in Section “7. Voltage Reference Options” on
page 58. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 6.1. ADC0 Functional Block Diagram
42
Rev. 1.1
C8051F388/9/A/B
6.1. Output Code Formatting
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below for both right-justified
and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
Input Voltage
(Single-Ended)
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0x03FF
0x0200
0x0100
0x0000
0xFFC0
0x8000
0x4000
0x0000
When in Differential Mode, conversion codes are represented as 10-bit signed 2s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to 0.
Input Voltage
(Differential)
VREF x 511/512
VREF x 256/512
0
–VREF x 256/512
–VREF
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0x01FF
0x0100
0x0000
0xFF00
0xFE00
0x7FC0
0x4000
0x0000
0xC000
0x8000
Rev. 1.1
43
C8051F388/9/A/B
6.2.
Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 6.2. The output voltage (VTEMP) is the
positive ADC input when the temperature sensor is selected by bits AMX0P5-0 in register AMX0P.
Figure 6.2. Typical Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.10, “ADC0 Electrical Characteristics,” on page 39 for linearity specifications). For
absolute temperature measurements, gain and/or offset calibration is recommended. Typically a 1-point
calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile
memory for use with subsequent temperature sensor measurements.
Figure 6.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
44
Rev. 1.1
C8051F388/9/A/B
Figure 6.3. Temperature Sensor Error with 1-Point Calibration
Rev. 1.1
45
C8051F388/9/A/B
6.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
6.3.1. Starting a Conversion
A conversion can be initiated in one of several ways, depending on the programmed states of the ADC0
Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of
the following:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
7. A Timer 4 overflow
8. A Timer 5 overflow
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2, 3, 4, or 5 overflows are used as the conversion source, Low Byte overflows are used if the timer is in 8-bit mode; High byte overflows are used if the timer is in 16-bit mode. See
Section “25. Timers” on page 224 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the
CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digital Crossbar. See Section “20. Port Input/Output” on page 147 for details on Port I/O configuration.
46
Rev. 1.1
C8051F388/9/A/B
6.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR. See Figure 6.4 for track and convert timing details. Tracking can also be
disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-and-hold
mode is also useful when AMUX settings are frequently changed, due to the settling time requirements
described in Section “6.3.3. Settling Time Requirements” on page 48.
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing
Rev. 1.1
47
C8051F388/9/A/B
6.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any
external source resistance, and the accuracy required for the conversion. Note that in low-power tracking
mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these
three SAR clocks will meet the minimum tracking time requirements.
Figure 6.5 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 6.1. See Table 5.10 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
 2n 
t = ln  -------  R TOTAL C SAMPLE
 SA
Equation 6.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Figure 6.5. ADC0 Equivalent Input Circuits
48
Rev. 1.1
C8051F388/9/A/B
SFR Definition 6.1. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
AD0SC[4:0]
AD0LJST
Reserved
Type
R/W
R/W
R/W
Reset
1
1
1
1
1
0
0
0
SFR Address = 0xBC; SFR Page = All Pages
Bit
Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
SYSCLK
AD0SC = ------------------------ – 1
CLK SAR
Note: If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least
"00001" for proper ADC operation.
2
AD0LJST
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1:0
Reserved
Must Write 00b.
Rev. 1.1
49
C8051F388/9/A/B
SFR Definition 6.2. ADC0H: ADC0 Data Word MSB
Bit
7
6
5
4
3
Name
ADC0H[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xBE; SFR Page = All Pages
Bit
Name
2
1
0
0
0
0
Function
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data
Word.
SFR Definition 6.3. ADC0L: ADC0 Data Word LSB
Bit
7
6
5
4
3
Name
ADC0L[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xBD; SFR Page = All Pages
Bit
Name
0
2
1
0
0
0
0
Function
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
read 000000b.
50
Rev. 1.1
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SFR Definition 6.4. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
Name
AD0EN
AD0TM
AD0INT
Type
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
2
AD0BUSY AD0WINT
1
0
AD0CM[2:0]
R/W
0
0
0
SFR Address = 0xE8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
AD0EN
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6
AD0TM
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A start-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion. Note that there is not a tracking delay when
CNVSTR is used (AD0CM[2:0] = 100).
5
AD0INT
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4
AD0BUSY
3
AD0WINT
ADC0 Busy Bit.
Read:
0: ADC0 conversion is not in
progress.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if
AD0CM[2:0] = 000b
ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
110: ADC0 start-of-conversion source is overflow of Timer 4.
111: ADC0 start-of-conversion source is overflow of Timer 5.
Rev. 1.1
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C8051F388/9/A/B
6.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit
7
6
5
4
3
Name
ADC0GTH[7:0]
Type
R/W
Reset
1
1
1
1
1
SFR Address = 0xC4; SFR Page = All Pages
Bit
Name
2
1
0
1
1
1
2
1
0
1
1
1
Function
7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit
7
6
5
4
3
Name
ADC0GTL[7:0]
Type
R/W
Reset
1
1
1
1
SFR Address = 0xC3; SFR Page = All Pages
Bit
Name
7:0
52
1
Function
ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte
Bit
7
6
5
4
3
Name
ADC0LTH[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xC6; SFR Page = All Pages
Bit
Name
7:0
2
1
0
0
0
0
2
1
0
0
0
0
Function
ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit
7
6
5
4
3
Name
ADC0LTL[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xC5; SFR Page = All Pages
Bit
Name
7:0
0
Function
ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
Rev. 1.1
53
C8051F388/9/A/B
6.4.1. Window Detector Example
Figure 6.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 6.7 shows an example using left-justified data with the same comparison values.
Figure 6.6. ADC Window Compare Example: Right-Justified Data
Figure 6.7. ADC Window Compare Example: Left-Justified Data
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Rev. 1.1
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6.5. ADC0 Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to
individual Port pins, the on-chip temperature sensor, or the positive power supply (VDD). The negative
input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential Mode.
The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition
6.9 and SFR Definition 6.10.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1
the corresponding bit in register PnSKIP. See Section “20. Port Input/Output” on page 147 for more Port
I/O configuration details.
Rev. 1.1
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C8051F388/9/A/B
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select
Bit
7
6
5
4
Name
2
1
0
0
0
AMX0P[5:0]
Type
R
R
Reset
0
0
R/W
0
0
SFR Address = 0xBB; SFR Page = All Pages
Bit
Name
7:6
3
Unused
0
0
Function
Read = 00b; Write = don’t care.
5:0 AMX0P[5:0] AMUX0 Positive Input Selection.
AMX0P
56
32-pin
Packages
48-pin
Packages
AMX0P
000000: P1.0
P2.0
010010: P0.1
P0.4
000001: P1.1
P2.1
010011:
P0.4
P1.1
000010: P1.2
P2.2
010100: P0.5
P1.2
000011:
P1.3
P2.3
010101: Reserved
P1.0
000100: P1.4
P2.5
010110:
Reserved
P1.3
000101: P1.5
P2.6
010111:
Reserved
P1.6
000110:
P1.6
P3.0
011000:
Reserved
P1.7
000111:
P1.7
P3.1
011001:
Reserved
P2.4
001000: P2.0
P3.4
011010:
Reserved
P2.7
001001: P2.1
P3.5
011011:
Reserved
P3.2
001010: P2.2
P3.7
011100:
Reserved
P3.3
001011:
P2.3
P4.0
011101:
Reserved
P3.6
001100:
P2.4
P4.3
011110:
Temp Sensor
Temp Sensor
001101:
P2.5
P4.4
011111:
VDD
VDD
001110:
P2.6
P4.5
100000: Reserved
P4.1
001111:
P2.7
P4.6
100001: Reserved
P4.2
010000: P3.0
Reserved
100010: Reserved
P4.7
010001: P0.0
P0.3
100011 - Reserved
111111:
Reserved
Rev. 1.1
32-pin
Packages
48-pin
Packages
C8051F388/9/A/B
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select
Bit
7
6
5
4
Name
2
1
0
0
0
AMX0N[5:0]
Type
R
R
Reset
0
0
R/W
0
0
SFR Address = 0xBA; SFR Page = All Pages
Bit
Name
7:6
3
Unused
0
0
Function
Read = 00b; Write = don’t care.
5:0 AMX0N[5:0] AMUX0 Negative Input Selection.
AMX0N
32-pin
Packages
48-pin
Packages
AMX0N
000000: P1.0
P2.0
010010: P0.1
P0.4
000001: P1.1
P2.1
010011:
P0.4
P1.1
000010: P1.2
P2.2
010100: P0.5
P1.2
000011:
P1.3
P2.3
010101: Reserved
P1.0
000100: P1.4
P2.5
010110:
Reserved
P1.3
000101: P1.5
P2.6
010111:
Reserved
P1.6
000110:
P1.6
P3.0
011000:
Reserved
P1.7
000111:
P1.7
P3.1
011001:
Reserved
P2.4
001000: P2.0
P3.4
011010:
Reserved
P2.7
001001: P2.1
P3.5
011011:
Reserved
P3.2
001010: P2.2
P3.7
011100:
Reserved
P3.3
001011:
P2.3
P4.0
011101:
Reserved
P3.6
001100:
P2.4
P4.3
011110:
VREF
VREF
001101:
P2.5
P4.4
011111:
GND
GND
(Single-Ended (Single-Ended
Measurement) Measurement)
001110:
P2.6
P4.5
100000: Reserved
P4.1
001111:
P2.7
P4.6
100001: Reserved
P4.2
010000: P3.0
Reserved
100010: Reserved
P4.7
010001: P0.0
P0.3
100011 - Reserved
111111:
Reserved
Rev. 1.1
32-pin
Packages
48-pin
Packages
57
C8051F388/9/A/B
7. Voltage Reference Options
The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply voltage (VDD), or the regulated 1.8 V internal supply (see Figure 7.1). The REFSL bit in the Reference Control
register (REF0CN, SFR Definition 7.1) selects the reference source for the ADC. For an external source or
the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use VDD as the reference
source, REFSL should be set to 1. To override this selection and use the internal regulator as the reference
source, the REGOVR bit can be set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripherals
on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and it
does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the
BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in
Table 5.12.
The C8051F388/9/A/B devices also include an on-chip voltage reference circuit which consists of a 1.2 V,
temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier. The
buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN. On the 1x gain setting the
output voltage is nominally 1.2 V, and on the 2x gain setting the output voltage is nominally 2.4 V. The onchip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REF0CN to a 1.
The maximum load seen by the VREF pin must be less than 200 μA to GND. Bypass capacitors of 0.1 μF
and 4.7 μF are recommended from the VREF pin to GND, and a minimum of 0.1uF is required. If the onchip reference is not used, the REFBE bit should be cleared to 0. Electrical specifications for the on-chip
voltage reference are given in Table 5.12.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip reference circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “20. Port Input/Output” on page 147 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar.
Figure 7.1. Voltage Reference Functional Block Diagram
58
Rev. 1.1
C8051F388/9/A/B
SFR Definition 7.1. REF0CN: Reference Control
Bit
7
6
Name
REFBGS
Type
R/W
R
Reset
0
0
5
4
3
2
1
0
REGOVR
REFSL
TEMPE
BIASE
REFBE
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
SFR Address = 0xD1; SFR Page = All Pages
Bit
Name
7
6:5
4
Function
REFBGS Reference Buffer Gain Select.
This bit selects between 1x and 2x gain for the on-chip voltage reference buffer.
0: 2x Gain
1: 1x Gain
Unused
Read = 00b; Write = don’t care.
REGOVR Regulator Reference Override.
This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a reference source.
0: The voltage reference source is selected by the REFSL bit.
1: The internal regulator is used as the voltage reference.
3
REFSL
Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
2
TEMPE
Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
1
BIASE
Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0
REFBE
On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin.
Rev. 1.1
59
C8051F388/9/A/B
8. Comparator0 and Comparator1
C8051F388/9/A/B devices include two on-chip programmable voltage comparators: Comparator0 is shown
in Figure 8.1, Comparator1 is shown in Figure 8.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as described in Section “8.1. Comparator Multiplexers” on
page 67; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “20.2. Port I/O Initialization” on page 152). Comparator0 may also be used as a
reset source (see Section “17.5. Comparator0 Reset” on page 126).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“8.1. Comparator Multiplexers” on page 67.
Figure 8.1. Comparator0 Functional Block Diagram
60
Rev. 1.1
C8051F388/9/A/B
Figure 8.2. Comparator1 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “20.1. Priority Crossbar Decoder” on
page 148 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Section “5. Electrical Characteristics” on page 34.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition 8.2 and SFR Definition 8.4). Selecting a longer response time reduces the Comparator supply current.
Rev. 1.1
61
C8051F388/9/A/B
Figure 8.3. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN
(for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits 3–0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the
setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “16.1. MCU Interrupt Sources and Vectors” on page 113). The
CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Comparator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
62
Rev. 1.1
C8051F388/9/A/B
SFR Definition 8.1. CPT0CN: Comparator0 Control
Bit
7
6
5
4
Name
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
CP0HYN[1:0]
Type
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
SFR Address = 0x9B; SFR Page = All Pages
Bit
Name
3
2
0
0
1
0
0
0
Function
7
CP0EN
Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6
CP0OUT
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5
CP0RIF
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.1
63
C8051F388/9/A/B
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection
Bit
7
6
Name
5
4
CP0RIE
CP0FIE
3
2
R
R
R/W
R/W
R
R
Reset
0
0
0
0
0
0
Unused
Read = 00b, Write = don’t care.
5
CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
Unused
Read = 00b, Write = don’t care.
64
R/W
1
Function
7:6
1:0
0
CP0MD[1:0]
Type
SFR Address = 0x9D; SFR Page = All Pages
Bit
Name
1
CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.1
0
C8051F388/9/A/B
SFR Definition 8.3. CPT1CN: Comparator1 Control
Bit
7
6
5
4
Name
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP[1:0]
CP1HYN[1:0]
Type
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
SFR Address = 0x9A; SFR Page = All Pages
Bit
Name
3
2
0
0
1
0
0
0
Function
7
CP1EN
Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6
CP1OUT
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5
CP1RIF
Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4
CP1FIF
Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.1
65
C8051F388/9/A/B
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection
Bit
7
6
Name
5
4
CP1RIE
CP1FIE
3
2
R
R
R/W
R/W
R
R
Reset
0
0
0
0
0
0
Unused
Read = 00b, Write = don’t care.
5
CP1RIE
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4
CP1FIE
Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2
Unused
Read = 00b, Write = don’t care.
66
R/W
1
Function
7:6
1:0
0
CP1MD[1:0]
Type
SFR Address = 0x9C; SFR Page = All Pages
Bit
Name
1
CP1MD[1:0] Comparator1 Mode Select.
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.1
0
C8051F388/9/A/B
8.1. Comparator Multiplexers
C8051F388/9/A/B devices include an analog input multiplexer to connect Port I/O pins to the comparator
inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 8.5 and SFR Definition 8.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the CMXnN2–CMXnN0 bits
select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “20.3. General Purpose Port I/O” on page 155).
Figure 8.4. Comparator Input Multiplexer Block Diagram
Rev. 1.1
67
C8051F388/9/A/B
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection
Bit
7
6
Name
5
4
R
Reset
0
R/W
0
3
2:0
68
Unused
1
R
0
0
0
R/W
0
0
Function
Read = 0b; Write = don’t care.
CMX0N[2:0] Comparator0 Negative Input MUX Selection.
Unused
0
CMX0P[2:0]
SFR Address = 0x9F; SFR Page = All Pages
Bit
Name
6:4
2
CMX0N[2:0]
Type
7
3
Selection
32-pin Package
48-pin Package
000:
P1.1
P2.1
001:
P1.5
P2.6
010:
P2.1
P3.5
011:
P2.5
P4.4
100:
P0.1
P0.4
101-111:
Reserved
Reserved
Read = 0b; Write = don’t care.
CMX0P[2:0] Comparator0 Positive Input MUX Selection.
Selection
32-pin Package
48-pin Package
000:
P1.0
P2.0
001:
P1.4
P2.5
010:
P2.0
P3.4
011:
P2.4
P4.3
100:
P0.0
P0.3
101-111:
Reserved
Reserved
Rev. 1.1
0
C8051F388/9/A/B
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection
Bit
7
6
Name
5
4
R
Reset
0
R/W
0
3
2:0
Unused
1
R
0
0
CMX1P[2:0]
0
SFR Address = 0x9E; SFR Page = All Pages
Bit
Name
6:4
2
CMX1N[2:0]
Type
7
3
0
R/W
0
0
0
Function
Read = 0b; Write = don’t care.
CMX1N[2:0] Comparator1 Negative Input MUX Selection.
Unused
Selection
32-pin Package
48-pin Package
000:
P1.3
P2.3
001:
P1.7
P3.1
010:
P2.3
P4.0
011:
Reserved
P4.6
100:
P0.5
P1.2
101-111:
Reserved
Reserved
Read = 0b; Write = don’t care.
CMX1P[2:0] Comparator1 Positive Input MUX Selection.
Selection
32-pin Package
48-pin Package
000:
P1.2
P2.2
001:
P1.6
P3.0
010:
P2.2
P3.7
011:
Reserved
P4.5
100:
P0.4
P1.1
101-111:
Reserved
Reserved
Rev. 1.1
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C8051F388/9/A/B
9. Voltage Regulators (REG0 and REG1)
C8051F388/9/A/B devices include two internal voltage regulators: one regulates a voltage source on
REGIN to 3.3 V (REG0), and the other regulates the internal core supply to 1.8 V from a VDD supply of
1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the VDD pin and can be used to power
external devices. REG0 can be enabled/disabled by software using bit REG0DIS in register REG01CN
(SFR Definition 9.1). REG1 has two power-saving modes built into the regulator to help reduce current
consumption in low-power applications. These modes are accessed through the REG01CN register. Electrical characteristics for the on-chip regulators are specified in Table 5.5 on page 37.
9.1. Voltage Regulator (REG0)
See “4. Typical Connection Diagrams” for typical connection diagrams using the REG0 voltage regulator.
9.1.1. Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is
degraded. See Table 5.5 for normal and low power mode supply current specifications. The REG0 mode
selection is controlled via the REG0MD bit in register REG01CN.
9.1.2. External Interrupt 2 (INT2)
On C8051F388/9/A/B devices, the VBSTAT bit (register REG01CN) indicates the current logic level of the
INT2 signal. If enabled, a INT2 interrupt will be generated when the INT2 signal has either a falling or rising
edge. The INT2 interrupt is edge-sensitive, and has no associated interrupt pending flag. See Table 5.3 for
INT2 input parameters.
9.2. Voltage Regulator (REG1)
Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode.
This allows any enabled reset source to generate a reset for the device and bring the device out of STOP
mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin
and a full power cycle of the device are the only methods of generating a reset.
REG1 offers an additional low power mode intended for use when the device is in suspend mode. This low
power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled. See
Table 5.5 for normal and low power mode supply current specifications. The REG1 mode selection is controlled via the REG1MD bit in register REG01CN.
Important Note: At least 12 clock instructions must occur after placing REG1 in low power mode before
the Internal High Frequency Oscillator is Suspended (OSCICN.5 = 1b).
70
Rev. 1.1
C8051F388/9/A/B
SFR Definition 9.1. REG01CN: Voltage Regulator Control
Bit
7
6
5
Name REG0DIS INT2STAT Reserved
4
3
2
1
0
REG0MD
STOPCF
Reserved
REG1MD
Reserved
Type
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC9; SFR Page = All Pages
Bit
Name
Function
7
REG0DIS Voltage Regulator (REG0) Disable.
This bit enables or disables the REG0 Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
6
INT2STAT INT2 Signal Status.
This bit indicates the status of the INT2 pin.
0: INT2 pin is currently low.
1: INT2 pin is currently high.
5
Reserved Must Write 0b.
4
REG0MD Voltage Regulator (REG0) Mode Select.
This bit selects the Voltage Regulator mode for REG0. When REG0MD is set to 1, the
REG0 voltage regulator operates in lower power (suspend) mode.
0: REG0 Voltage Regulator in normal mode.
1: REG0 Voltage Regulator in low power mode.
3
STOPCF Stop Mode Configuration (REG1).
This bit configures the REG1 regulator’s behavior when the device enters STOP mode.
0: REG1 Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: REG1 Regulator is shut down in STOP mode. Only the RST pin or power cycle can
reset the device.
2
Reserved Must Write 0b.
1
REG1MD Voltage Regulator (REG1) Mode.
This bit selects the Voltage Regulator mode for REG1. When REG1MD is set to 1, the
REG1 voltage regulator operates in lower power mode.
0: REG1 Voltage Regulator in normal mode.
1: REG1 Voltage Regulator in low power mode.
This bit should not be set to '1' if the REG0 Voltage Regulator is disabled.
0
Reserved Must Write 0b.
Rev. 1.1
71
C8051F388/9/A/B
10. Power Management Modes
The C8051F388/9/A/B devices have three software programmable power management modes: Idle, Stop,
and Suspend. Idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is
an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Suspend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on a
transition of the INT2 pin. The CPU is not halted in suspend mode, so it can run on another oscillator, if
desired. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode and suspend
mode consume the least power because the majority of the device is shut down with no clocks active. SFR
Definition 10.1 describes the Power Control Register (PCON) used to control the C8051F388/9/A/B's Stop
and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 19.3).
Although the C8051F388/9/A/B has Idle, Stop, and suspend modes available, more control over the device
power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption
considerably, at the expense of reduced functionality.
10.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “17.6. PCA Watchdog Timer
72
Rev. 1.1
C8051F388/9/A/B
Reset” on page 127 for more information on the use and configuration of the WDT.
10.2. Stop Mode
Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be configured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition 9.1).
If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of
resetting the device.
10.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator
and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. The CPU is not halted in Suspend, so code can still be executed using an oscillator other than the internal high-frequency oscillator.
Suspend mode can be terminated by a rising or falling edge on the INT2 pin or a device reset event. When
suspend mode is terminated, if the oscillator source is the internal high-frequency oscillator, the device will
continue execution on the instruction following the one that set the SUSPEND bit. If the wake event was
configured to generate an interrupt, the interrupt will be serviced upon waking the device. If suspend mode
is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins
program execution at address 0x0000.
Rev. 1.1
73
C8051F388/9/A/B
SFR Definition 10.1. PCON: Power Control
Bit
7
6
5
4
3
2
1
0
Name
GF[5:0]
STOP
IDLE
Type
R/W
R/W
R/W
0
0
Reset
0
0
0
0
SFR Address = 0x87; SFR Page = All Pages
Bit
Name
0
0
Function
7:2
GF[5:0]
1
STOP
Stop Mode Select.
Setting this bit will place the CIP-51 in stop mode. This bit will always be read as 0.
1: CPU goes into stop mode (internal oscillator stopped).
0
IDLE
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
74
General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Rev. 1.1
C8051F388/9/A/B
11. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 11.1 for a block diagram).
The CIP-51 includes the following features:




Fully Compatible with MCS-51 Instruction Set
48 MIPS Peak Throughput with 48 MHz Clock
0 to 48 MHz Clock Frequency
Extended Interrupt Handler




Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Figure 11.1. CIP-51 Block Diagram
Rev. 1.1
75
C8051F388/9/A/B
With the CIP-51's maximum system clock at 48 MHz, it has a peak throughput of 48 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/4
3
3/5
4
5
4/6
6
8
Number of Instructions
26
50
5
10
6
5
2
2
2
1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “27. C2 Interface” on page 277.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
11.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
11.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 11.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
76
Rev. 1.1
C8051F388/9/A/B
Table 11.1. CIP-51 Instruction Set Summary
Mnemonic
Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Logical Operations
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
Description
Bytes
Clock
Cycles
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
Rev. 1.1
77
C8051F388/9/A/B
Table 11.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Boolean Manipulation
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
78
Description
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
3
1
1
1
1
1
1
1
Clock
Cycles
3
1
1
1
1
1
1
1
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
1
2
1
2
1
2
1
2
1
2
1
2
Rev. 1.1
Bytes
C8051F388/9/A/B
Table 11.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
2
2
2
2
2
2
ANL C, bit
AND direct bit to Carry
2
ANL C, /bit
AND complement of direct bit to Carry
2
ORL C, bit
OR direct bit to carry
2
ORL C, /bit
OR complement of direct bit to Carry
2
MOV C, bit
Move direct bit to Carry
2
MOV bit, C
Move Carry to direct bit
2
Program Flow
Timings are listed with the PFE on and FLRT = 0. Extra cycles are required for branches if FLRT = 1.
JC rel
Jump if Carry is set
2
2/4
JNC rel
Jump if Carry is not set
2
2/4
JB bit, rel
Jump if direct bit is set
3
3/5
JNB bit, rel
Jump if direct bit is not set
3
3/5
JBC bit, rel
Jump if direct bit is set and clear bit
3
3/5
ACALL addr11
Absolute subroutine call
2
4
LCALL addr16
Long subroutine call
3
5
RET
Return from subroutine
1
6
RETI
Return from interrupt
1
6
AJMP addr11
Absolute jump
2
4
LJMP addr16
Long jump
3
5
SJMP rel
Short jump (relative address)
2
4
JMP @A+DPTR
Jump indirect relative to DPTR
1
4
JZ rel
Jump if A equals zero
2
2/4
JNZ rel
Jump if A does not equal zero
2
2/4
CJNE A, direct, rel
Compare direct byte to A and jump if not equal
3
4/6
CJNE A, #data, rel
Compare immediate to A and jump if not equal
3
3/5
CJNE Rn, #data, rel
Compare immediate to Register and jump if not
3
3/5
equal
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
3
4/6
equal
DJNZ Rn, rel
Decrement Register and jump if not zero
2
2/4
DJNZ direct, rel
Decrement direct byte and jump if not zero
3
3/5
NOP
No operation
1
1
Rev. 1.1
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Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
80
Rev. 1.1
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11.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
SFR Definition 11.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
Name
DPL[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x82; SFR Page = All Pages
Bit
Name
7:0
DPL[7:0]
3
2
1
0
0
0
0
0
3
2
1
0
0
0
0
0
Function
Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
SFR Definition 11.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
Name
DPH[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x83; SFR Page = All Pages
Bit
Name
7:0
DPH[7:0]
Function
Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
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SFR Definition 11.3. SP: Stack Pointer
Bit
7
6
5
4
Name
SP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x81; SFR Page = All Pages
Bit
Name
7:0
SP[7:0]
3
2
1
0
0
1
1
1
Function
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 11.4. ACC: Accumulator
Bit
7
6
5
4
Name
ACC[7:0]
Type
R/W
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0]
Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 11.5. B: B Register
Bit
7
6
5
4
Name
B[7:0]
Type
R/W
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7:0
82
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 11.6. PSW: Program Status Word
Bit
7
6
5
Name
CY
AC
F0
Type
R/W
R/W
R/W
Reset
0
0
0
4
3
2
1
0
RS[1:0]
OV
F1
PARITY
R/W
R/W
R/W
R
0
0
0
0
0
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0]
2
OV
Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
Overflow Flag.
This bit is set to 1 under the following circumstances:
An
ADD, ADDC, or SUBB instruction causes a sign-change overflow.
MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
A
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
F1
0
PARITY
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.1
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C8051F388/9/A/B
12. Prefetch Engine
The C8051F388/9/A/B family of devices incorporate a 2-byte prefetch engine. Because the access time of
the Flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from Flash memory two bytes at a time by the
prefetch engine and given to the CIP-51 processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed. When a
code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code
bytes is retrieved from Flash memory. It is recommended that the prefetch be used for optimal code execution timing.
Note: The prefetch engine can be disabled when the device is in suspend mode to save power.
SFR Definition 12.1. PFE0CN: Prefetch Engine Control
Bit
7
6
Name
5
4
3
2
1
PFEN
0
FLBWE
Type
R
R
R/W
R
R
R
R
R/W
Reset
0
0
1
0
0
0
0
0
SFR Address = 0xAF; SFR Page = All Pages
Bit
Name
Function
7:6
Unused
5
PFEN
4:1
Unused
Read = 0000b. Write = don’t care.
0
FLBWE
Flash Block Write Enable.
This bit allows block writes to Flash memory from software.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
84
Read = 00b, Write = don’t care.
Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Rev. 1.1
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13. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 13.1 and Figure 13.2.
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F388/9)
Rev. 1.1
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Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F38A/B)
13.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F388/9/A/B implements 64 or 32 kB
of this program memory space as in-system, re-programmable Flash memory. Note that on the
C8051F388/9 (64 kB version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for nonvolatile data storage. Refer to Section “18. Flash Memory” on page 129 for further details.
13.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.
Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
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The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 13.1 illustrates the data memory organization of the CIP-51.
13.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 11.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
13.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
13.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
Rev. 1.1
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C8051F388/9/A/B
14. External Data Memory Interface and On-Chip XRAM
The chip includes 4 kB (C8051F388/9) or 2 kB (C8051F38A/B) of RAM on-chip, and is mapped into the
external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on
the C8051F388/A devices, which can be used to access off-chip data memories and memory-mapped
devices connected to the GPIO ports. The external memory space may be accessed using the external
move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using
R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte
of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in
SFR Definition 14.1). Note: the MOVX instruction can also be used for writing to the FLASH memory. See
Section “18. Flash Memory” on page 129 for details. The MOVX instruction accesses XRAM by default.
14.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
14.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV
MOVX
DPTR, #1234h
A, @DPTR
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
14.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
88
EMI0CN, #12h
R0, #34h
a, @R0
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.1
C8051F388/9/A/B
14.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
most common), and skip the associated pins in the crossbar.
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
5. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 14.4.
14.3. Port Configuration
The External Memory Interface appears on Ports 4, 3, 2, and 1 when it is used for off-chip memory access.
When the EMIF is used, the Crossbar should be configured to skip over the control lines P1.7 (WR), P1.6
(RD), and if multiplexed mode is selected P1.3 (ALE) using the P1SKIP register. For more information
about configuring the Crossbar, see Section “Figure 20.1. Port I/O Functional Block Diagram (Port 0
through Port 3)” on page 147.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar settings for those pins. See Section “20. Port Input/Output” on page 147 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
Rev. 1.1
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SFR Definition 14.1. EMI0CN: External Memory Interface Control
Bit
7
6
5
4
3
Name
PGSEL[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xAA; SFR Page = All Pages
Bit
Name
7:0
90
PGSEL[7:0]
0
2
1
0
0
0
0
Function
XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte
page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
Rev. 1.1
C8051F388/9/A/B
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration
Bit
7
Name
6
5
Reserved
4
3
2
1
0
EMD2
EMD[1:0]
EALE[1:0]
R/W
R/W
Type
R
R/W
R
R/W
Reset
0
0
0
0
SFR Address = 0x85; SFR Page = All Pages
Bit
Name
0
0
1
1
Function
7
Unused
Read = 0b; Write = don’t care.
6
Reserved
5
Unused
4
EMD2
3:2
EMD[1:0]
EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses
alias to on-chip memory space.
01: Split Mode without Bank Select: Accesses below the on-chip XRAM boundary
are directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the current contents of the Address
High port latches to resolve upper address byte. Note that in order to access
off-chip space, EMI0CN must be set to a page that is not contained in the on-chip
address space.
10: Split Mode with Bank Select: Accesses below the on-chip XRAM boundary are
directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine
the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.
1:0
EALE[1:0]
ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Read = 0b; Must Write 0b.
Read = 0b; Write = don’t care.
EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
Rev. 1.1
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14.4. Multiplexed and Non-multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
14.4.1. Multiplexed Configuration
In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in
Figure 14.1.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “14.6.2. Multiplexed Mode” on page 101 for more information.
Figure 14.1. Multiplexed Configuration Example
92
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C8051F388/9/A/B
14.4.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a
Non-multiplexed Configuration is shown in Figure 14.2. See Section “14.6.1. Non-multiplexed Mode” on
page 98 for more information about Non-multiplexed operation.
Figure 14.2. Non-multiplexed Configuration Example
Rev. 1.1
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14.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 14.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 14.4). These modes are summarized below.
More information about the different modes can be found in Section “14.6. Timing” on page 96.
Figure 14.3. EMIF Operating Modes
14.5.1. Internal XRAM Only
When EMI0CF.[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device.
Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending
on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to
address 0x0000 in on-chip XRAM space.

8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
14.5.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and
off-chip space.




94
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
Rev. 1.1
C8051F388/9/A/B
14.5.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and
off-chip space.

Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the
lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus
A[15:0] are driven in “Bank Select” mode.
 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
14.5.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.



8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
Rev. 1.1
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C8051F388/9/A/B
14.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 14.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 for ALE + 1 for RD or WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 14.1 lists the AC parameters for the External
Memory Interface, and Figure 14.4 through Figure 14.9 show the timing diagrams for the different External
Memory Interface modes and MOVX operations.
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SFR Definition 14.3. EMI0TC: External Memory Timing Control
Bit
7
6
5
4
3
2
1
0
Name
EAS[1:0]
EWR[3:0]
EAH[1:0]
Type
R/W
R/W
R/W
Reset
1
1
1
1
SFR Address = 0x84; SFR Page = All Pages
Bit
Name
1
1
1
1
Function
7:6
EAS[1:0]
EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
5:2
EWR[3:0]
EMIF WR and RD Pulse-Width Control Bits.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0
EAH[1:0]
EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
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C8051F388/9/A/B
14.6.1. Non-multiplexed Mode
14.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111
Figure 14.4. Non-Multiplexed 16-bit MOVX Timing
98
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14.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111
Figure 14.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing
Rev. 1.1
99
C8051F388/9/A/B
14.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110
Figure 14.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing
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14.6.2. Multiplexed Mode
14.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011
Figure 14.7. Multiplexed 16-bit MOVX Timing
Rev. 1.1
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C8051F388/9/A/B
14.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Figure 14.8. Multiplexed 8-bit MOVX without Bank Select Timing
102
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14.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010
Figure 14.9. Multiplexed 8-bit MOVX with Bank Select Timing
Rev. 1.1
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C8051F388/9/A/B
Table 14.1. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
Units
TACS
Address/Control Setup Time
0
3 x TSYSCLK
ns
TACW
Address/Control Pulse Width
1 x TSYSCLK
16 x TSYSCLK
ns
TACH
Address/Control Hold Time
0
3 x TSYSCLK
ns
TALEH
Address Latch Enable High Time
1 x TSYSCLK
4 x TSYSCLK
ns
TALEL
Address Latch Enable Low Time
1 x TSYSCLK
4 x TSYSCLK
ns
TWDS
Write Data Setup Time
1 x TSYSCLK
19 x TSYSCLK
ns
TWDH
Write Data Hold Time
0
3 x TSYSCLK
ns
TRDS
Read Data Setup Time
20
ns
TRDH
Read Data Hold Time
0
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
104
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15. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F388/9/A/B's resources and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F388/9/A/B. This allows the addition of new functionality while retaining compatibility with the MCS51™ instruction set. Table 15.1 lists the SFRs implemented in the C8051F388/9/A/B device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 15.2, for a detailed description of each register.
15.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F388/9/A/B devices utilize two SFR pages: 0x0, and 0xF.
Most SFRs are available on both pages. SFR pages are selected using the Special Function Register
Page Selection register, SFRPAGE. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
Important Note: When reading or writing SFRs that are not available on all pages within an ISR, it is recommended to save the state of the SFRPAGE register on ISR entry, and restore state on exit.
SFR Definition 15.1. SFRPAGE: SFR Page
Bit
7
6
5
4
3
Name
SFRPAGE[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xBF; SFR Page = All Pages
Bit
Name
7:0
SFRPAGE[7:0]
0
2
1
0
0
0
0
Function
SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
Rev. 1.1
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C8051F388/9/A/B
Page
Address
Table 15.1. Special Function Register (SFR) Memory Map
F8
F0
E8
E0
0
F
D8
D0
0
F
0
C0
F
0
B8
F
B0
A8
A0
98
0
90
F
88
80
C8
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
SPI0CN PCA0L
PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
B
P0MDIN
P1MDIN
P2MDIN
P3MDIN
P4MDIN
EIP1
EIP2
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
IT01CF
ACC
XBR0
XBR1
XBR2
SMOD1
EIE1
EIE2
CKCON1
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 P3SKIP
PSW
REF0CN
SCON1
SBUF1
P0SKIP
P1SKIP
P2SKIP
TMR2CN
TMR2RLL TMR2RLH
TMR2L
TMR2H SMB0ADM SMB0ADR
REG01CN
TMR5CN
TMR5RLL TMR5RLH
TMR5L
TMR5H SMB1ADM SMB1ADR
SMB0CN SMB0CF SMB0DAT
ADC0GTL ADC0GTH ADC0LTL ADC0LTH
P4
SMB1CN SMB1CF SMB1DAT
CLKMUL
ADC0CF
IP
AMX0N
AMX0P
ADC0L
ADC0H SFRPAGE
SMBTC
P3
OSCXCN OSCICN
OSCICL
SBRLL1
SBRLH1
FLSCL
FLKEY
IE
CLKSEL
EMI0CN
SBCON1
P4MDOUT PFE0CN
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT
SCON0
SBUF0
CPT1CN
CPT0CN
CPT1MD
CPT0MD
CPT1MX CPT0MX
TMR3CN TMR3RLL TMR3RLH
TMR3L
TMR3H
P1
TMR4CN TMR4RLL TMR4RLH
TMR4L
TMR4H
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
PSCTL
P0
SP
DPL
DPH
EMI0TC
EMI0CF
OSCLCN
PCON
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
Notes:
1. SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
2. Unless indicated otherwise, SFRs are available on both page 0 and page F.
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Table 15.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
ACC
Address
Page
0xE0
All Pages Accumulator
Description
Page
82
ADC0CF
0xBC
All Pages ADC0 Configuration
49
ADC0CN
0xE8
All Pages ADC0 Control
51
ADC0GTH
0xC4
All Pages ADC0 Greater-Than Compare High
52
ADC0GTL
0xC3
All Pages ADC0 Greater-Than Compare Low
52
ADC0H
0xBE
All Pages ADC0 High
50
ADC0L
0xBD
All Pages ADC0 Low
50
ADC0LTH
0xC6
All Pages ADC0 Less-Than Compare Word High
53
ADC0LTL
0xC5
All Pages ADC0 Less-Than Compare Word Low
53
AMX0N
0xBA
All Pages AMUX0 Negative Channel Select
57
AMX0P
0xBB
All Pages AMUX0 Positive Channel Select
56
B
0xF0
All Pages B Register
82
CKCON
0x8E
All Pages Clock Control
225
CKCON1
0xE4
F
Clock Control 1
226
CLKMUL
0xB9
0
Clock Multiplier
141
CLKSEL
0xA9
All Pages Clock Select
138
CPT0CN
0x9B
All Pages Comparator0 Control
63
CPT0MD
0x9D
All Pages Comparator0 Mode Selection
64
CPT0MX
0x9F
All Pages Comparator0 MUX Selection
68
CPT1CN
0x9A
All Pages Comparator1 Control
65
CPT1MD
0x9C
All Pages Comparator1 Mode Selection
66
CPT1MX
0x9E
All Pages Comparator1 MUX Selection
69
DPH
0x83
All Pages Data Pointer High
81
DPL
0x82
All Pages Data Pointer Low
81
EIE1
0xE6
All Pages Extended Interrupt Enable 1
117
EIE2
0xE7
All Pages Extended Interrupt Enable 2
119
EIP1
0xF6
All Pages Extended Interrupt Priority 1
118
EIP2
0xF7
All Pages Extended Interrupt Priority 2
120
EMI0CF
0x85
All Pages External Memory Interface Configuration
91
EMI0CN
0xAA
All Pages External Memory Interface Control
90
EMI0TC
0x84
All Pages External Memory Interface Timing
97
FLKEY
0xB7
All Pages Flash Lock and Key
134
FLSCL
0xB6
All Pages Flash Scale
135
Rev. 1.1
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C8051F388/9/A/B
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address
Page
Description
Page
IE
0xA8
All Pages Interrupt Enable
115
IP
0xB8
All Pages Interrupt Priority
116
IT01CF
0xE4
OSCICL
0xB3
All Pages Internal Oscillator Calibration
139
OSCICN
0xB2
All Pages Internal Oscillator Control
140
OSCLCN
0x86
All Pages Internal Low-Frequency Oscillator Control
142
OSCXCN
0xB1
All Pages External Oscillator Control
146
P0
0x80
All Pages Port 0 Latch
156
P0MDIN
0xF1
All Pages Port 0 Input Mode Configuration
156
P0MDOUT
0xA4
All Pages Port 0 Output Mode Configuration
157
P0SKIP
0xD4
All Pages Port 0 Skip
157
P1
0x90
All Pages Port 1 Latch
158
P1MDIN
0xF2
All Pages Port 1 Input Mode Configuration
158
P1MDOUT
0xA5
All Pages Port 1 Output Mode Configuration
159
P1SKIP
0xD5
All Pages Port 1 Skip
159
P2
0xA0
All Pages Port 2 Latch
160
P2MDIN
0xF3
All Pages Port 2 Input Mode Configuration
160
P2MDOUT
0xA6
All Pages Port 2 Output Mode Configuration
161
P2SKIP
0xD6
All Pages Port 2 Skip
161
P3
0xB0
All Pages Port 3 Latch
162
P3MDIN
0xF4
All Pages Port 3 Input Mode Configuration
162
P3MDOUT
0xA7
All Pages Port 3 Output Mode Configuration
163
P3SKIP
0xDF
All Pages Port 3Skip
163
P4
0xC7
All Pages Port 4 Latch
164
P4MDIN
0xF5
All Pages Port 4 Input Mode Configuration
164
P4MDOUT
0xAE
All Pages Port 4 Output Mode Configuration
165
PCA0CN
0xD8
All Pages PCA Control
272
PCA0CPH0
0xFC
All Pages PCA Capture 0 High
276
PCA0CPH1
0xEA
All Pages PCA Capture 1 High
276
PCA0CPH2
0xEC
All Pages PCA Capture 2 High
276
PCA0CPH3
0xEE
All Pages PCA Capture 3High
276
PCA0CPH4
0xFE
All Pages PCA Capture 4 High
276
PCA0CPL0
0xFB
All Pages PCA Capture 0 Low
276
PCA0CPL1
0xE9
All Pages PCA Capture 1 Low
276
108
0
INT0/INT1 Configuration
Rev. 1.1
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C8051F388/9/A/B
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address
Page
Description
Page
PCA0CPL2
0xEB
All Pages PCA Capture 2 Low
276
PCA0CPL3
0xED
All Pages PCA Capture 3 Low
276
PCA0CPL4
0xFD
All Pages PCA Capture 4 Low
276
PCA0CPM0
0xDA
All Pages PCA Module 0 Mode Register
274
PCA0CPM1
0xDB
All Pages PCA Module 1 Mode Register
274
PCA0CPM2
0xDC
All Pages PCA Module 2 Mode Register
274
PCA0CPM3
0xDD
All Pages PCA Module 3 Mode Register
274
PCA0CPM4
0xDE
All Pages PCA Module 4 Mode Register
274
PCA0H
0xFA
All Pages PCA Counter High
275
PCA0L
0xF9
All Pages PCA Counter Low
275
PCA0MD
0xD9
All Pages PCA Mode
273
PCON
0x87
All Pages Power Control
74
PFE0CN
0xAF
All Pages Prefetch Engine Control
84
PSCTL
0x8F
All Pages Program Store R/W Control
133
PSW
0xD0
All Pages Program Status Word
83
REF0CN
0xD1
All Pages Voltage Reference Control
59
REG01CN
0xC9
All Pages Voltage Regulator 0 and 1 Control
71
RSTSRC
0xEF
All Pages Reset Source Configuration/Status
128
SBCON1
0xAC
All Pages UART1 Baud Rate Generator Control
209
SBRLH1
0xB5
All Pages UART1 Baud Rate Generator High
209
SBRLL1
0xB4
All Pages UART1 Baud Rate Generator Low
210
SBUF0
0x99
All Pages UART0 Data Buffer
199
SBUF1
0xD3
All Pages UART1 Data Buffer
208
SCON0
0x98
All Pages UART0 Control
198
SCON1
0xD2
All Pages UART1 Control
206
SFRPAGE
0xBF
All Pages SFR Page Select
105
SMB0ADM
0xCE
0
SMBus0 Address Mask
180
SMB0ADR
0xCF
0
SMBus0 Address
179
SMB0CF
0xC1
0
SMBus0 Configuration
172
SMB0CN
0xC0
0
SMBus0 Control
176
SMB0DAT
0xC2
0
SMBus0 Data
182
SMB1ADM
0xCE
F
SMBus1 Address Mask
181
SMB1ADR
0xCF
F
SMBus1 Address
180
SMB1CF
0xC1
F
SMBus1 Configuration
172
Rev. 1.1
109
C8051F388/9/A/B
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address
Page
Description
Page
SMB1CN
0xC0
F
SMBus1 Control
177
SMB1DAT
0xC2
F
SMBus1 Data
183
SMBTC
0xB9
F
SMBus0/1 Timing Control
174
SMOD1
0xE5
All Pages UART1 Mode
207
SP
0x81
All Pages Stack Pointer
82
SPI0CFG
0xA1
All Pages SPI Configuration
218
SPI0CKR
0xA2
All Pages SPI Clock Rate Control
220
SPI0CN
0xF8
All Pages SPI Control
219
SPI0DAT
0xA3
All Pages SPI Data
220
TCON
0x88
All Pages Timer/Counter Control
231
TH0
0x8C
All Pages Timer/Counter 0 High
234
TH1
0x8D
All Pages Timer/Counter 1 High
234
TL0
0x8A
All Pages Timer/Counter 0 Low
233
TL1
0x8B
All Pages Timer/Counter 1 Low
233
TMOD
0x89
All Pages Timer/Counter Mode
232
TMR2CN
0xC8
0
Timer/Counter 2 Control
239
TMR2H
0xCD
0
Timer/Counter 2 High
241
TMR2L
0xCC
0
Timer/Counter 2 Low
240
TMR2RLH
0xCB
0
Timer/Counter 2 Reload High
240
TMR2RLL
0xCA
0
Timer/Counter 2 Reload Low
240
TMR3CN
0x91
0
Timer/Counter 3 Control
246
TMR3H
0x95
0
Timer/Counter 3 High
248
TMR3L
0x94
0
Timer/Counter 3 Low
247
TMR3RLH
0x93
0
Timer/Counter 3 Reload High
247
TMR3RLL
0x92
0
Timer/Counter 3 Reload Low
247
TMR4CN
0x91
F
Timer/Counter 4 Control
251
TMR4H
0x95
F
Timer/Counter 4 High
253
TMR4L
0x94
F
Timer/Counter 4 Low
252
TMR4RLH
0x93
F
Timer/Counter 4 Reload High
252
TMR4RLL
0x92
F
Timer/Counter 4 Reload Low
252
TMR5CN
0xC8
F
Timer/Counter 5 Control
256
TMR5H
0xCD
F
Timer/Counter 5 High
258
TMR5L
0xCC
F
Timer/Counter 5 Low
257
TMR5RLH
0xCB
F
Timer/Counter 5 Reload High
257
110
Rev. 1.1
C8051F388/9/A/B
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address
Page
Description
F
Timer/Counter 5 Reload Low
Page
TMR5RLL
0xCA
VDM0CN
0xFF
All Pages VDD Monitor Control
126
XBR0
0xE1
All Pages Port I/O Crossbar Control 0
153
XBR1
0xE2
All Pages Port I/O Crossbar Control 1
154
XBR2
0xE3
All Pages Port I/O Crossbar Control 2
155
Rev. 1.1
257
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C8051F388/9/A/B
16. Interrupts
The C8051F388/9/A/B include an extended interrupt system supporting multiple interrupt sources with two
priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE, EIE1, or EIE2). However, interrupts must first be globally enabled by setting the
EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0
disables all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. Using EA (global interrupt enable) as an example:
// in 'C':
EA = 0; // clear EA bit.
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction
which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the enable bit will return a 0 inside the interrupt service
routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
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16.1. MCU Interrupt Sources and Vectors
The C8051F388/9/A/B MCUs support several interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be
generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU
interrupt sources, associated vector addresses, priority order and control bits are summarized in
Table 16.1. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
16.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 16.1.
16.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write operations. Interrupt service latency will be increased for
interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the
standard interrupt service procedure (as described above) and the amount of time the CPU is stalled.
16.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Rev. 1.1
113
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Interrupt Source
Interrupt
Vector
Priority
Order
Reset
0x0000
Top
External Interrupt 0
(INT0)
Timer 0 Overflow
External Interrupt 1
(INT1)
Timer 1 Overflow
UART0
0x0003
0
0x000B
0x0013
Pending Flag
Enable
Flag
Priority
Control
N/A
N/A
IE0 (TCON.1)
Y
Y
Always
Always
Enabled
Highest
EX0 (IE.0) PX0 (IP.0)
1
2
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
0x001B
0x0023
3
4
Y
Y
Y
N
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
0x002B
5
Y
N
ET2 (IE.5) PT2 (IP.5)
SPI0
0x0033
6
Y
N
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
7
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
N
Reserved
ADC0 Window Compare
ADC0 Conversion
Complete
Programmable
Counter Array
Comparator0
0x0043
0x004B
8
9
N/A
Y
N/A
N
0x0053
10
N/A
AD0WINT
(ADC0CN.3)
AD0INT (ADC0CN.5)
Y
N
0x005B
11
Y
N
0x0063
12
N
N
Comparator1
0x006B
13
N
N
Timer 3 Overflow
0x0073
14
N
N
INT2 Level
0x007B
15
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N/A
N/A
N/A
UART1
0x0083
16
N
N
Reserved
SMB1
0x008B
0x0093
17
18
N/A
Y
N/A
N
Timer 4 Overflow
0x009B
19
N
N
Timer 5 Overflow
0x00A3
20
Y
N
ESMB0
(EIE1.0)
N/A
EWADC0
(EIE1.2)
EADC0
(EIE1.3)
EPCA0
(EIE1.4)
ECP0
(EIE1.5)
ECP1
(EIE1.6)
ET3
(EIE1.7)
EINT2
(EIE2.0)
ES1
(EIE2.1)
N/A
ESMB1
(EIE2.3)
ET4
(EIE2.4)
ET5
(EIE2.5)
PSMB0
(EIP1.0)
N/A
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PCP1
(EIP1.6)
PT3
(EIP1.7)
PINT2
(EIP2.0)
PS1
(EIP2.1)
N/A
PSMB1
(EIP2.3)
PT4
(E!P2.4)
PT5
(E!P2.5)
114
None
Bit
Address?
Cleared
by HW?
Table 16.1. Interrupt Summary
RI1 (SCON1.0)
TI1 (SCON1.1)
N/A
SI (SMB1CN.0)
TF4H (TMR4CN.7)
TF4L (TMR4CN.6)
TF5H (TMR5CN.7)
TF5L (TMR5CN.6)
Rev. 1.1
C8051F388/9/A/B
SFR Definition 16.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
Name
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
EA
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
ESPI0
5
ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4
ES0
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3
ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2
EX1
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1
ET0
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0
EX0
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
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SFR Definition 16.2. IP: Interrupt Priority
Bit
7
Name
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
0
0
SFR Address = 0xB8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
Unused
6
PSPI0
5
PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4
PS0
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3
PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2
PX1
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1
PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0
PX0
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
116
Read = 1b, Write = Don't Care.
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
Name
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0
Reserved
ESMB0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE6; SFR Page = All Pages
Bit
Name
Function
7
ET3
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6
ECP1
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
5
ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4
EPCA0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3
EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2
EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1
Reserved Read = 0b, Must Write 0b.
0
ESMB0
Enable SMBus0 Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.1
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C8051F388/9/A/B
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
Name
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0
Reserved
PSMB0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF6; SFR Page = All Pages
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
PCP1
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5
PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4
PPCA0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3
PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2
PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1
Reserved Read = 0b, Must Write 0b.
0
118
PSMB0
SMBus0 Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
Name
5
4
3
ET5
ET4
ESMB1
2
1
0
ES1
EINT2
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE7; SFR Page = All Pages
Bit
Name
Function
7:6
Unused
5
ET5
Enable Timer 5 Interrupt.
This bit sets the masking of the Timer 5 interrupt.
0: Disable Timer 5 interrupts.
1: Enable interrupt requests generated by the TF5L or TF5H flags.
4
ET4
Enable Timer 4 Interrupt.
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4interrupts.
1: Enable interrupt requests generated by the TF4L or TF4H flags.
3
ESMB1
2
Read = 00b, Write = Don't Care.
Enable SMBus1 Interrupt.
This bit sets the masking of the SMB1 interrupt.
0: Disable all SMB1 interrupts.
1: Enable interrupt requests generated by SMB1.
Reserved Must Write 0b.
1
ES1
0
EINT2
Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
Enable INT2 Level Interrupt.
This bit sets the masking of the INT2 interrupt.
0: Disable all INT2 interrupts.
1: Enable interrupt requests generated by the INT2 level sense.
Rev. 1.1
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C8051F388/9/A/B
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
Name
5
4
3
PT5
PT4
PSMB1
2
1
0
PS1
PINT2
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF7; SFR Page = All Pages
Bit
Name
Function
:6
Unused
5
PT5
Timer 5 Interrupt Priority Control.
This bit sets the priority of the Timer 5 interrupt.
0: Timer 5 interrupt set to low priority level.
1: Timer 5 interrupt set to high priority level.
4
PT4
Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low priority level.
1: Timer 4 interrupt set to high priority level.
3
PSMB1
2
Read = 00b, Write = Don't Care.
SMBus1 Interrupt Priority Control.
This bit sets the priority of the SMB1 interrupt.
0: SMB1 interrupt set to low priority level.
1: SMB1 interrupt set to high priority level.
Reserved Must Write 0b.
1
PS1
UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
0
PINT2
INT2 Level Interrupt Priority Control.
This bit sets the masking of the INT2 interrupt.
0: INT2 interrupt set to low priority level.
1: INT2 interrupt set to high priority level.
120
Rev. 1.1
C8051F388/9/A/B
16.3. INT0 and INT1 External Interrupt Sources
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 227) select level or
edge sensitive. The table below lists the possible configurations.
IT1
IN1PL
Active low, edge sensitive
1
0
Active low, edge sensitive
1
Active high, edge sensitive
1
1
Active high, edge sensitive
0
0
Active low, level sensitive
0
0
Active low, level sensitive
0
1
Active high, level sensitive
0
1
Active high, level sensitive
IT0
IN0PL
1
0
1
INT0 Interrupt
INT1 Interrupt
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 16.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register PnSKIP (see Section “20.1. Priority Crossbar
Decoder” on page 148 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
Rev. 1.1
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C8051F388/9/A/B
SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO
Bit
7
6
5
Name
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Type
R/W
R/W
R/W
R/W
Reset
0
0
0
4
0
SFR Address = 0xE4; SFR Page = 0
Bit
Name
7
6:4
3
2:0
122
IN1PL
3
0
2
0
1
0
0
1
Function
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
Rev. 1.1
C8051F388/9/A/B
17. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:




CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Program execution begins at location 0x0000.
Figure 17.1. Reset Sources
Rev. 1.1
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17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 17.2. plots the
power-on and VDD monitor event timing. The maximum VDD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than
1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
On exit from a power-on or VDD monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor
is enabled following a power-on reset.
Figure 17.2. Power-On and VDD Monitor Reset Timing
124
Rev. 1.1
C8051F388/9/A/B
17.2. Power-Fail Reset / VDD Monitor
When a powerdown transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When VDD returns to
a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the
VDD monitor will still be disabled after the reset.
Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the VDD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the VDD monitor to stabilize (see Table 5.4 for the VDD Monitor turn-on time).
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 17.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Table 5.4 for complete electrical characteristics of the VDD monitor.
Rev. 1.1
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SFR Definition 17.1. VDM0CN: VDD Monitor Control
Bit
7
6
5
4
3
2
1
0
Name
VDMEN
VDDSTAT
Type
R/W
R
R
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xFF; SFR Page = All Pages
Bit
Name
7
VDMEN
Function
VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 17.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source. See Table 5.4 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6
VDDSTAT
VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
5:0
Unused
Read = 000000b; Write = Don’t care.
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset,
the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads
0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of
the RST pin is unaffected by this reset.
17.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
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17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on
page 269; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash program read, write, or erase operation targets an illegal address, a system reset is generated.
This may occur due to any of the following:





Programming hardware attempts to write or erase a Flash location which is above the user code space
address limit.
A Flash read from firmware is attempted above user code space. This occurs when a MOVC operation
is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
A Flash read, write, or erase attempt is restricted due to a Flash security setting.
A Flash write or erase is attempted when the VDD monitor is not enabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
17.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset.
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SFR Definition 17.2. RSTSRC: Reset Source
Bit
7
Name Reserved
6
5
4
3
2
1
0
FERROR
C0RSEF
SWRSF
WDTRSF
MCDRSF
PORSF
PINRSF
Type
R/W
R
R/W
R/W
R
R/W
R/W
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xEF; SFR Page = All Pages
Bit
Name
Description
7
Reserved
Must Write 0b.
Read = 0b
6
FERROR Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
5
C0RSEF Comparator0 Reset Enable
and Flag.
Writing a 1 enables Com- Set to 1 if Comparator0
parator0 as a reset source caused the last reset.
(active-low).
4
SWRSF
Writing a 1 forces a system reset.
Software Reset Force and
Flag.
Write
3
WDTRSF Watchdog Timer Reset Flag. N/A
2
MCDRSF Missing Clock Detector
Enable and Flag.
Read
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Writing a 1 enables the
Set to 1 if Missing Clock
Missing Clock Detector.
Detector timeout caused
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1
PORSF
Power-On / VDD Monitor
Writing a 1 enables the
Reset Flag, and VDD monitor VDD monitor as a reset
source.
Reset Enable.
Writing 1 to this bit
before the VDD monitor
is enabled and stabilized
may cause a system
reset.
Set to 1 anytime a poweron or VDD monitor reset
occurs.
When set to 1 all other
RSTSRC flags are indeterminate.
0
PINRSF
HW Pin Reset Flag.
Set to 1 if RST pin caused
the last reset.
N/A
Note: Do not use read-modify-write operations on this register
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18. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would
typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation.
18.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “27. C2 Interface” on
page 277.
To ensure the integrity of Flash contents, it is strongly recommended that the VDD monitor be left enabled
in any system which writes or erases Flash memory from code. It is also crucial to ensure that the FLRT bit
in register FLSCL be set to '1' if a clock speed higher than 25 MHz is being used for the device.
18.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 18.2.
18.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) Writing the Flash key codes in sequence to the Flash Lock
register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this
directs the MOVX writes to target Flash memory). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed must be erased before a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
Disable interrupts (recommended).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Set the PSEE bit (register PSCTL).
Set the PSWE bit (register PSCTL).
Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
Clear the PSWE bit (register PSCTL).
Clear the PSEE bit (register PSCTI).
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18.1.3. Flash Write Procedure
Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register
PFE0CN (SFR Definition ) controls whether a single byte or a block of two bytes is written to Flash during
a write operation. When FLBWE is cleared to 0, the Flash will be written one byte at a time. When FLBWE
is set to 1, the Flash will be written in two-byte blocks. Block writes are performed in the same amount of
time as single-byte writes, which can save time when storing large amounts of data to Flash memory.During a single-byte write to Flash, bytes are written individually, and a Flash write will be performed
after each MOVX write instruction. The recommended procedure for writing Flash in single bytes is:
1. Disable interrupts.
2. Clear the FLBWE bit (register PFE0CN) to select single-byte write mode.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
9. Re-enable interrupts.
Steps 5-7 must be repeated for each byte to be written.
For block Flash writes, the Flash write procedure is only performed after the last byte of each block is written with the MOVX write instruction. A Flash write block is two bytes long, from even addresses to odd
addresses. Writes must be performed sequentially (i.e. addresses ending in 0b and 1b must be written in
order). The Flash write will be performed following the MOVX write that targets the address ending in 1b. If
a byte in the block does not need to be updated in Flash, it should be written to 0xFF. The recommended
procedure for writing Flash in blocks is:
1. Disable interrupts.
2. Set the FLBWE bit (register PFE0CN) to select block write mode.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write the first data byte to the even block location (ending in 0b).
8. Write the first key code to FLKEY: 0xA5.
9. Write the second key code to FLKEY: 0xF1.
10.Using the MOVX instruction, write the second data byte to the odd block location (ending in 1b).
11. Clear the PSWE bit.
12.Re-enable interrupts.
Steps 5–10 must be repeated for each block to be written.
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18.2. Non-Volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
18.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1s complement number represented by the Security Lock Byte. Note that the page
containing the Flash Security Lock Byte is also locked when any other Flash pages are locked. See example below.
Security Lock Byte:
1s Complement:
Flash pages locked:
Addresses locked:
11111101b
00000010b
3 (2 + Flash Lock Byte Page)
First two pages of Flash: 0x0000 to 0x03FF
Flash Lock Byte Page: (0xFA00 to 0xFBFF for 64k devices; 0x7E00 to
0x7FFF for 32k devices)
Figure 18.1. Flash Program Memory Map and Security Byte
The level of FLASH security depends on the FLASH access method. The three FLASH access methods
that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing
on unlocked pages, and user firmware executing on locked pages.
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Accessing FLASH from the C2 debug interface:
1.
2.
3.
4.
5.
6.
7.
Any unlocked page may be read, written, or erased.
Locked pages cannot be read, written, or erased.
The page containing the Lock Byte may be read, written, or erased if it is unlocked.
Reading the contents of the Lock Byte with no pages locked is always permitted.
Reading the contents of the Lock Byte with any pages locked is not permitted.
Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) requires the C2 Device Erase command,
which erases all FLASH pages including the page containing the Lock Byte and the Lock Byte itself.
8. The Reserved Area cannot be read, written, or erased.
Accessing FLASH from user firmware executing on an unlocked page:
1.
2.
3.
4.
5.
6.
7.
8.
Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
Locked pages cannot be read, written, or erased.
The page containing the Lock Byte cannot be erased. It may be read or written only if it is unlocked.
Reading the contents of the Lock Byte with no pages locked is always permitted.
Reading the contents of the Lock Byte with any pages locked is not permitted.
Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) is not permitted.
The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any
other locked page, will result in a FLASH Error device reset.
Accessing FLASH from user firmware executing on a locked page:
1.
2.
3.
4.
5.
6.
7.
Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
Any locked page except the page containing the Lock Byte may be read, written, or erased.
The page containing the Lock Byte cannot be erased. It may only be read or written.
Reading the contents of the Lock Byte is always permitted.
Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) is not permitted.
The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any
other locked page, will result in a FLASH Error device reset.
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SFR Definition 18.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
Name
1
0
PSEE
PSWE
Type
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address =0x8F; SFR Page = All Pages
Bit
Name
7:2
Function
Reserved Must write 000000b.
1
PSEE
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE
Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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SFR Definition 18.2. FLKEY: Flash Lock and Key
Bit
7
6
5
4
3
Name
FLKEY[7:0]
Type
R/W
Reset
0
0
0
0
0
2
1
0
0
0
0
SFR Address = 0xB7; SFR Page = All Pages
Bit
Name
Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be permanently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
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SFR Definition 18.3. FLSCL: Flash Scale
Bit
7
6
5
Name
FOSE
Reserved
FLRT
Reserved
Type
R/W
R/W
R/W
R/W
Reset
1
0
0
4
0
SFR Address = 0xB6; SFR Page = All Pages
Bit
Name
7
FOSE
6:5
Reserved
4
FLRT
3:0
Reserved
3
0
2
0
1
0
0
0
Function
Flash One-shot Enable.
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads. At system
clock frequencies below 10 MHz, disabling the Flash one-shot will increase system
power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
Must write 00b.
FLASH Read Time.
This bit should be programmed to the smallest allowed value, according to the system
clock speed.
0: SYSCLK <= 25 MHz.
1: SYSCLK <= 48 MHz.
Must write 0000b.
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19. Oscillators and Clock Selection
C8051F388/9/A/B devices include a programmable internal high-frequency oscillator, a programmable
internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 19.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register. The system clock can be sourced by the external oscillator circuit or either internal oscillator. Both internal oscillators offer a selectable post-scaling feature.
Figure 19.1. Oscillator Options
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19.1. System Clock Selection
The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillators and external
oscillator so long as the selected clock source is enabled and running.
The internal high-frequency and low-frequency oscillators require little start-up time and may be selected
as the system clock immediately following the register write which enables the oscillator. The external RC
and C modes also typically require no startup time.
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SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
Name
Type
R
Reset
0
0
5
4
3
2
1
Reserved
OUTCLK
CLKSL[2:0]
R/W
R/W
R/W
0
0
SFR Address = 0xA9; SFR Page = All Pages
Bit
Name
0
0
0
0
0
Function
7
Unused
Read = 0b; Write = don’t care
6:4
Reserved
Read = 0b; Must Write 000b.
3
OUTCLK
Crossbar Clock Out Select.
If the SYSCLK signal is enabled on the Crossbar, this bit selects between outputting
SYSCLK and SYSCLK synchronized with the Port I/O pins.
0: Enabling the Crossbar SYSCLK signal outputs SYSCLK.
1: Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the
Port I/O.
2:0
CLKSL[2:0]
138
System Clock Source Select Bits.
000: SYSCLK derived from the Internal High-Frequency Oscillator / 4 and scaled
per the IFCN bits in register OSCICN.
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the Internal High-Frequency Oscillator / 2.
011: SYSCLK derived from the Internal High-Frequency Oscillator.
100: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per
the OSCLD bits in register OSCLCN.
101-111: Reserved.
Rev. 1.1
C8051F388/9/A/B
19.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F388/9/A/B devices include a programmable internal high-frequency oscillator that defaults as
the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 19.2.
On C8051F388/9/A/B devices, OSCICL is factory calibrated to obtain a 48 MHz base frequency. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8 after a
divide by 4 stage, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following
a reset, which results in a 1.5 MHz system clock.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the system clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until a rising or falling edge occurs on the INT2 pin.
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation. The CPU resumes execution at the instruction following the write to the SUSPEND bit.
Note: The prefetch engine can be turned off in suspend mode to save power. Additionally, both Voltage
Regulators (REG0 and REG1) have low-power modes for additional power savings in suspend mode.
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration
Bit
7
6
5
4
Name
3
R
Reset
0
0
Varies
Varies
Varies
R/W
Varies
Varies
Varies
SFR Address = 0xB3; SFR Page = All Pages
Bit
Name
6:0
1
OSCICL[6:0]
Type
7
2
Unused
Varies
Function
Read = 0; Write = don’t care
OSCICL[6:0] Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 48 MHz. OSCICL should only be changed by firmware when the H-F oscillator is disabled (IOSCEN = 0).
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SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control
Bit
7
6
5
4
Name
IOSCEN
IFRDY
SUSPEND
Type
R/W
R
R/W
R
R
R
Reset
1
1
0
0
0
0
IOSCEN
6
IFRDY
5
SUSPEND
4:2
Unused
1:0
IFCN[1:0]
140
2
1
0
IFCN[1:0]
SFR Address = 0xB2; SFR Page = All Pages
Bit
Name
7
3
R/W
0
0
Function
Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
Read = 000b; Write = don’t care
Internal H-F Oscillator Frequency Divider Control Bits.
The Internal H-F Oscillator is divided by the IFCN bit setting after a divide-by-4 stage.
00: SYSCLK can be derived from Internal H-F Oscillator divided by 8 (1.5 MHz).
01: SYSCLK can be derived from Internal H-F Oscillator divided by 4 (3 MHz).
10: SYSCLK can be derived from Internal H-F Oscillator divided by 2 (6 MHz).
11: SYSCLK can be derived from Internal H-F Oscillator divided by 1 (12 MHz).
Rev. 1.1
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19.3. Clock Multiplier
The C8051F388/9/A/B device includes a 48 MHz high-frequency oscillator instead of a 12 MHz oscillator
and a 4x Clock Multiplier. For compatibility with C8051F34x and C8051F32x devices however, the CLKMUL register (SFR Definition 19.4) behaves as if the Clock Multiplier is present and working.
SFR Definition 19.4. CLKMUL: Clock Multiplier Control
Bit
7
6
5
4
Name
MULEN
MULINIT
MULRDY
Type
R
R
R
R
R
R
Reset
1
1
1
0
0
0
2
1
0
MULSEL[1:0]
SFR Address = 0xB9; SFR Page = 0
Bit
Name
R
0
0
Description
7
MULEN
Clock Multiplier Enable Bit.
This bit always reads 1.
6
MULINIT
Clock Multiplier Initialize Bit.
This bit always reads 1.
5
MULRDY
Clock Multiplier Ready Bit.
This bit always reads 1.
4:2
Unused
1:0
3
Read = 000b; Write = don’t care
MULSEL[1:0] Clock Multiplier Input Select Bits.
These bits always read 00.
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19.4. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051F388/9/A/B devices include a programmable low-frequency internal oscillator, which is calibrated
to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be
changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Definition 19.5). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’s output frequency.
19.4.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture
Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value
(TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.
SFR Definition 19.5. OSCLCN: Internal L-F Oscillator Control
Bit
7
6
5
Name
OSCLEN
OSCLRDY
OSCLF[3:0]
OSCLD[1:0]
Type
R/W
R
R.W
R/W
Reset
0
0
Varies
4
3
Varies
SFR Address = 0x86; SFR Page = All Pages
Bit
Name
7
OSCLEN
6
OSCLRDY
Varies
2
Varies
1
0
0
0
Function
Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Note: OSCLRDY is only set back to 0 in the event of a device reset or a change to the
OSCLD[1:0] bits.
5:2
OSCLF[3:0] Internal L-F Oscillator Frequency Control Bits.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the
L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator
operates at its slowest setting. The OSCLF bits should only be changed by firmware
when the L-F oscillator is disabled (OSCLEN = 0).
1:0
OSCLD[1:0] Internal L-F Oscillator Divider Select.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
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19.5. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. Figure 19.1 shows a block diagram of the four external oscillator options. The external oscillator is enabled and configured using the OSCXCN register (see SFR Definition 19.6).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2, respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pin used by the oscillator circuit; see Section “20.1. Priority Crossbar
Decoder” on page 148 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “20.2. Port
I/O Initialization” on page 152 for details on Port input mode selection.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g. Timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details. See
Section “5. Electrical Characteristics” on page 34 for complete oscillator specifications.
19.5.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 Mresistor must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 19.1. Appropriate
loading capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog
I/O with the digital output drivers disabled.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Refer to the
crystal data sheet when completing these calculations.
The equation for determining the load capacitance for two capacitors is
CA  CB
C L = ----------------------- + C S
CA + CB
Where:
CA and CB are the capacitors connected to the crystal leads.
CS is the total stray capacitance of the PCB.
The stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2-5 pF per
pin.
If CA and CB are the same (C), then the equation becomes
C
C L = ---- + C S
2
For example, a tuning-fork crystal of 32 kHz with a recommended load capacitance of 12.5 pF should use
the configuration shown in Figure 19.1, Option 1. With a stray capacitance of 3 pF per pin (6 pF total), the
13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 19.2.
Rev. 1.1
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Figure 19.2. External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for Crystal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Control value (XFCN) must also be specified based on the crystal frequency (see SFR Definition 19.6).
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to determine when the external system clock is valid and running. Switching to the external oscillator before the
crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the crystal is:
1. Configure XTAL1 and XTAL2 for analog I/O.
2. Disable the XTAL1 and XTAL2 digital output drivers by writing 1s to the appropriate bits in the Port
Latch register.
3. Configure and enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD > 1.
6. Switch the system clock to the external oscillator.
144
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19.5.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 19.1, “RC Mode”. The capacitor should be no greater than 100 pF; however, for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation 19.1,
where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor
value in k.
3
f = 1.23  10 §  R  C 
Equation 19.1. RC Mode Oscillator Frequency
For example: If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 19.6, the required XFCN setting is 010b.
19.5.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 19.1, “C Mode”. The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation according to Equation 19.2, where f = the frequency of
oscillation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in Volts.
f =  KF    C  V DD 
Equation 19.2. C Mode Oscillator Frequency
For example: Assume VDD = 3.0 V and f = 150 kHz:
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 19.6
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
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SFR Definition 19.6. OSCXCN: External Oscillator Control
Bit
7
6
Name XCLKVLD
Type
R
Reset
0
5
4
6:4
XCLKVLD
0
0
XFCN[2:0]
R/W
0
1
R
0
0
R/W
0
0
0
Function
External Oscillator Valid Flag.
Provides External Oscillator status and is valid at all times for all modes of operation except External CMOS Clock Mode and External CMOS Clock Mode with
divide by 2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide-by-2 stage.
100: RC Oscillator Mode with divide-by-2 stage.
101: Capacitor Oscillator Mode with divide-by-2 stage.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide-by-2 stage.
3
Unused
2:0
XFCN[2:0]
146
2
XOSCMD[2:0]
SFR Address = 0xB1; SFR Page = All Pages
Bit
Name
7
3
Read = 0; Write = don’t care
External Oscillator Frequency Control Bits.
Set according to the desired frequency for RC mode.
Set according to the desired K Factor for C mode.
XFCN
Crystal Mode
RC Mode
C Mode
000
f 20 kHz
f 25 kHz
K Factor = 0.87
001
20 kHz f 58 kHz
25 kHz f 50 kHz
K Factor = 2.6
010
58 kHz f 155 kHz
50 kHz f 100 kHz
K Factor = 7.7
011
155 kHz f 415 kHz
100 kHz f 200 kHz
K Factor = 22
100
415 kHz f 1.1 MHz
200 kHz f 400 kHz
K Factor = 65
101
1.1 MHz f 3.1 MHz
400 kHz f 800 kHz
K Factor = 180
110
3.1 MHz f 8.2 MHz
800 kHz f 1.6 MHz
K Factor = 664
111
8.2 MHz f 25 MHz
1.6 MHz f 3.2 MHz
K Factor = 1590
Rev. 1.1
C8051F388/9/A/B
20. Port Input/Output
Digital and analog resources are available through 40 I/O pins (C8051F388/A) or 25 I/O pins (C8051F389/
B). Port pins are organized as shown in Figure 20.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital
resources as shown in Figure 20.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 20.1, SFR
Definition 20.2, and SFR Definition 20.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4).
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
Rev. 1.1
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Figure 20.2. Port I/O Cell Block Diagram
20.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be
set. This applies to the VREF signal, external oscillator pins (XTAL1, XTAL2), the ADC’s external conversion start signal (CNVSTR), EMIF control signals, and any selected ADC or Comparator inputs. The
PnSKIP registers may also be used to skip pins to be used as GPIO. The Crossbar skips selected pins as
if they were already assigned, and moves to the next unassigned pin. Figure 20.3 shows all the possible
pins available to each peripheral. Figure 20.4 shows an example Crossbar configuration with no Port pins
skipped. Figure 20.5 shows the same Crossbar example with pins P0.2, P0.3, and P1.0 skipped.
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when either SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
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Figure 20.3. Peripheral Availability on Port I/O Pins
Rev. 1.1
149
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Figure 20.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped)
150
Rev. 1.1
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Figure 20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
Rev. 1.1
151
C8051F388/9/A/B
20.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals (XBR0, XBR1).
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended. To configure a Port pin for digital input, write 0 to the corresponding bit in
register PnMDOUT, and write 1 to the corresponding Port latch (register Pn).
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this are the SMBus (SDA, SCL, SDA1 and SCL1) pins, which are configured as open-drain
regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pull-up is enabled for
all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the
weak pull-up is turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
Important Note: The Crossbar must be enabled to use Ports P0, P1, P2, and P3 as standard Port I/O in
output mode. These Port output drivers are disabled while the Crossbar is disabled. Port 4 always functions as standard GPIO.
152
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SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0
Bit
7
6
5
4
3
2
1
0
Name
CP1AE
CP1E
CP0AE
CP0E
SYSCKE
SMB0E
SPI0E
URT0E
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE1; SFR Page = All Pages
Bit
Name
7
CP1AE
6
CP1E
5
CP0AE
4
CP0E
3
Function
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1A unavailable at Port pin.
1: Asynchronous CP1A routed to Port pin.
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0A unavailable at Port pin.
1: Asynchronous CP0A routed to Port pin.
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2
SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1
SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0
URT0E
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
Rev. 1.1
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SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
Bit
7
Name WEAKPUD
6
5
4
3
XBARE
T1E
T0E
ECIE
2
1
0
PCA0ME[2:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE2; SFR Page = All Pages
Bit
Name
Function
7
WEAKPUD
Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
XBARE
5
T1E
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
4
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
3
ECIE
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
2:0 PCA0ME[2:0] PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
11x: Reserved.
154
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SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2
Bit
7
6
5
4
3
2
Name
1
0
SMB1E
URT1E
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE3; SFR Page = All Pages
Bit
Name
Function
7:2
Reserved
Must write 000000b
1
SMB1E
SMBus1 I/O Enable.
0: SMBus1 I/O unavailable at Port pins.
1: SMBus1 I/O routed to Port pins.
0
URT1E
UART1 I/O Enable.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX1, RX1 routed to Port pins.
20.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that
are both byte addressable and bit addressable. Port 4 (C8051F388/A only) uses an SFR which is
byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output
data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the
XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can
always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write
instructions. The read-modify-write instructions when operating on a Port SFR are the following: ANL,
ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit
in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written
back to the SFR.
Rev. 1.1
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SFR Definition 20.4. P0: Port 0
Bit
7
6
5
4
Name
P0[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Address = 0x80; SFR Page = All Pages; Bit Addressable
Bit
Name
Description
Write
7:0
P0[7:0]
Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
Read
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 20.5. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
SFR Address = 0xF1; SFR Page = All Pages
Bit
Name
7:0
156
P0MDIN[7:0]
1
2
1
0
1
1
1
Function
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 20.6. P0MDOUT: Port 0 Output Mode
Bit
7
6
5
4
3
Name
P0MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xA4; SFR Page = All Pages
Bit
Name
2
1
0
0
0
0
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
SFR Definition 20.7. P0SKIP: Port 0 Skip
Bit
7
6
5
4
3
Name
P0SKIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xD4; SFR Page = All Pages
Bit
Name
7:0
P0SKIP[7:0]
0
2
1
0
0
0
0
Function
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
Rev. 1.1
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SFR Definition 20.8. P1: Port 1
Bit
7
6
5
4
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Address = 0x90; SFR Page = All Pages; Bit Addressable
Bit
Name
Description
Write
7:0
P1[7:0]
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
Read
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
SFR Definition 20.9. P1MDIN: Port 1 Input Mode
Bit
7
6
5
4
3
Name
P1MDIN[7:0]
Type
R/W
Reset
1*
1
1
1
SFR Address = 0xF2; SFR Page = All Pages
Bit
Name
7:0
158
P1MDIN[7:0]
1
2
1
0
1
1
1
Function
Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
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SFR Definition 20.10. P1MDOUT: Port 1 Output Mode
Bit
7
6
5
4
3
Name
P1MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xA5; SFR Page = All Pages
Bit
Name
2
1
0
0
0
0
Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
SFR Definition 20.11. P1SKIP: Port 1 Skip
Bit
7
6
5
4
3
Name
P1SKIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xD5; SFR Page = All Pages
Bit
Name
7:0
P1SKIP[7:0]
0
2
1
0
0
0
0
Function
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
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SFR Definition 20.12. P2: Port 2
Bit
7
6
5
4
Name
P2[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable
Bit
Name
Description
Write
7:0
P2[7:0]
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
Read
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
SFR Definition 20.13. P2MDIN: Port 2 Input Mode
Bit
7
6
5
4
3
Name
P2MDIN[7:0]
Type
R/W
Reset
1
1
1
1
SFR Address = 0xF3; SFR Page = All Pages
Bit
Name
7:0
160
P2MDIN[7:0]
1
2
1
0
1
1
1
Function
Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
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SFR Definition 20.14. P2MDOUT: Port 2 Output Mode
Bit
7
6
5
4
3
Name
P2MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xA6; SFR Page = All Pages
Bit
Name
2
1
0
0
0
0
Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
SFR Definition 20.15. P2SKIP: Port 2 Skip
Bit
7
6
5
4
3
Name
P2SKIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xD6; SFR Page = All Pages
Bit
Name
7:0
P2SKIP[3:0]
0
2
1
0
0
0
0
Function
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
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SFR Definition 20.16. P3: Port 3
Bit
7
6
5
4
Name
P3[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Address = 0xB0; SFR Page = All Pages; Bit Addressable
Bit
Name
Description
Write
7:0
P3[7:0]
Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
Read
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
SFR Definition 20.17. P3MDIN: Port 3 Input Mode
Bit
7
6
5
4
3
Name
P3MDIN[7:0]
Type
R/W
Reset
1
1
1
1
SFR Address = 0xF4; SFR Page = All Pages
Bit
Name
7:0
162
P3MDIN[7:0]
1
2
1
0
1
1
1
Function
Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
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SFR Definition 20.18. P3MDOUT: Port 3 Output Mode
Bit
7
6
5
4
3
Name
P3MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xA7; SFR Page = All Pages
Bit
Name
2
1
0
0
0
0
Function
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.7–P3.0 (respectively).
These bits are ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
SFR Definition 20.19. P3SKIP: Port 3 Skip
Bit
7
6
5
4
3
Name
P3SKIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xDF; SFR Page = All Pages
Bit
Name
7:0
P3SKIP[3:0]
0
2
1
0
0
0
0
Function
Port 3 Crossbar Skip Enable Bits.
These bits select Port 3 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P3.n pin is not skipped by the Crossbar.
1: Corresponding P3.n pin is skipped by the Crossbar.
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SFR Definition 20.20. P4: Port 4
Bit
7
6
5
4
Name
P4[7:0]
Type
R/W
Reset
1
1
1
1
SFR Address = 0xC7; SFR Page = All Pages
Bit
Name
Description
7:0
P4[7:0]
Port 4 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells configured for digital I/O.
3
2
1
0
1
1
1
1
Write
Read
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P4.n Port pin is logic
LOW.
1: P4.n Port pin is logic
HIGH.
SFR Definition 20.21. P4MDIN: Port 4 Input Mode
Bit
7
6
5
4
3
Name
P4MDIN[7:0]
Type
R/W
Reset
1
1
1
1
SFR Address = 0xF5; SFR Page = All Pages
Bit
Name
7:0
164
P4MDIN[7:0]
1
2
1
0
1
1
1
Function
Analog Configuration Bits for P4.7–P4.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P4.n pin is configured for analog mode.
1: Corresponding P4.n pin is not configured for analog mode.
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SFR Definition 20.22. P4MDOUT: Port 4 Output Mode
Bit
7
6
5
4
3
Name
P4MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xAE; SFR Page = All Pages
Bit
Name
0
2
1
0
0
0
0
Function
7:0 P4MDOUT[7:0] Output Configuration Bits for P4.7–P4.0 (respectively).
These bits are ignored if the corresponding bit in register P4MDIN is logic 0.
0: Corresponding P4.n Output is open-drain.
1: Corresponding P4.n Output is push-pull.
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21. SMBus0 and SMBus1 (I2C Compatible)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. The C8051F388/9/A/B
devices contain two SMBus interfaces, SMBus0 and SMBus1.
Reads and writes to the SMBus by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system
clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the
system clock used). A method of extending the clock-low duration is available to accommodate devices
with different speed capabilities on the same bus.
The SMBus may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration
logic, and START/STOP control and generation. The SMBus peripherals can be fully driven by software
(i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recognition and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the
SMBus0 peripheral and the associated SFRs is shown in Figure 21.1. SMBus1 is identical, with the exception of the available timer options for the clock source, and the timer used to implement the SCL low timeout feature. Refer to the specific SFR definitions for more details.
Figure 21.1. SMBus Block Diagram
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21.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
21.2. SMBus Configuration
Figure 21.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 21.2. Typical SMBus Configuration
21.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. It is not necessary to specify one device
as the Master in a system; any device who transmits a START and a slave address becomes the master
for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 21.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
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All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 21.3 illustrates a typical
SMBus transaction.
Figure 21.3. SMBus Transaction
21.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
21.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “21.3.5. SCL High (SMBus Free) Timeout” on
page 169). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
21.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
21.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition.
For the SMBus0 interface, Timer 3 is used to implement SCL low timeouts. Timer 4 is used on the SMBus1
interface for SCL low timeouts. The SCL low timeout feature is enabled by setting the SMBnTOE bit in
SMBnCF. The associated timer is forced to reload when SCL is high, and allowed to count when SCL is
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low. With the associated timer enabled and configured to overflow after 25 ms (and SMBnTOE set), the
timer interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an
SCL low timeout.
21.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 μs, the bus
is designated as free. When the SMBnFTE bit in SMBnCF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implementation.
21.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:








Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgment is disabled, the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgment is enabled,
these interrupts are always generated after the ACK cycle. See Section 21.5 for more details on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMBnCN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMBnCN register is described in Section 21.4.3;
Table 21.5 provides a quick SMBnCN decoding reference.
21.4.1. SMBus Configuration Register
The SMBus Configuration register (SMBnCF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
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Table 21.1. SMBus Clock Source Selection
SMBnCS1 SMBnCS0
0
0
0
1
1
0
1
1
SMBus0 Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus1 Clock Source
Timer 0 Overflow
Timer 5 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBnCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 21.1.The selected
clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus0 and SMBus1 clock rates simultaneously. Timer configuration is covered in Section “25. Timers” on page 224.
1
T HighMin = T LowMin = -----------------------------------------------------------------f ClockSourceOverflow
Equation 21.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 21.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 21.2.
f ClockSourceOverflow
BitRate = -----------------------------------------------------------------3
Equation 21.2. Typical SMBus Bit Rate
Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 21.1.
Figure 21.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min-
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imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 21.2. Minimum SDA Setup and Hold Times
EXTHOLD
0
1
Minimum SDA Setup Time
Tlow – 4 system clocks
or
1 system clock + s/w delay*
11 system clocks
Minimum SDA Hold Time
3 system clocks
12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgment, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBnTOE bit set, Timer 3 (SMBus0) and Timer 5 (SMBus1) should be configured to overflow
after 25 ms in order to detect SCL low timeouts (see Section “21.3.4. SCL Low Timeout” on page 168).
The SMBus interface will force the associated timer to reload while SCL is high, and allow the timer to
count when SCL is low. The timer interrupt service routine should be used to reset SMBus communication
by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBnFTE bit. When this bit is set, the bus
will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 21.4).
21.4.2. SMBus Timing Control Register
The SMBus Timing Control Register (SMBTC) is used to restrict the detection of a START condition under
certain circumstances. In some systems where there is significant mis-match between the impedance or
the capacitance on the SDA and SCL lines, it may be possible for SCL to fall after SDA during an address
or data transfer. Such an event can cause a false START detection on the bus. These kind of events are
not expected in a standard SMBus or I2C-compliant system. In most systems this parameter should
not be adjusted, and it is recommended that it be left at its default value.
By default, if the SCL falling edge is detected after the falling edge of SDA (i.e. one SYSCLK cycle or
more), the device will detect this as a START condition. The SMBTC register is used to increase the
amount of hold time that is required between SDA and SCL falling before a START is recognized. An additional 2, 4, or 8 SYSCLKs can be added to prevent false START detection in systems where the bus conditions warrant this.
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SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
Name
ENSMB0
INH0
BUSY0
Type
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
EXTHOLD0 SMB0TOE SMB0FTE
SFR Address = 0xC1; SFR Page = 0
Bit
Name
1
0
SMB0CS[1:0]
R/W
0
0
Function
7
ENSMB0
SMBus0 Enable.
This bit enables the SMBus0 interface when set to 1. When enabled, the interface
constantly monitors the SDA0 and SCL0 pins.
6
INH0
SMBus0 Slave Inhibit.
When this bit is set to logic 1, the SMBus0 does not generate an interrupt when
slave events occur. This effectively removes the SMBus0 slave from the bus. Master Mode interrupts are not affected.
5
BUSY0
SMBus0 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4
EXTHOLD0
SMBus0 Setup and Hold Time Extension Enable.
This bit controls the SDA0 setup and hold times according to Table 21.2.
0: SDA0 Extended Setup and Hold Times disabled.
1: SDA0 Extended Setup and Hold Times enabled.
3
SMB0TOE
SMBus0 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus0 forces
Timer 3 to reload while SCL0 is high and allows Timer 3 to count when SCL0 goes
low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in
reload while SCL0 is high. Timer 3 should be programmed to generate interrupts at
25 ms, and the Timer 3 interrupt service routine should reset SMBus0 communication.
2
SMB0FTE
SMBus0 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL0 and SDA0
remain high for more than 10 SMBus clock source periods.
1:0 SMB0CS[1:0] SMBus0 Clock Source Selection.
These two bits select the SMBus0 clock source, which is used to generate the
SMBus0 bit rate. The selected device should be configured according to
Equation 21.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
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SFR Definition 21.2. SMB1CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
Name
ENSMB1
INH1
BUSY1
Type
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
EXTHOLD1 SMB1TOE SMB1FTE
SFR Address = 0xC1; SFR Page = F
Bit
Name
1
0
SMB1CS[1:0]
R/W
0
0
Function
7
ENSMB1
SMBus1 Enable.
This bit enables the SMBus1 interface when set to 1. When enabled, the interface
constantly monitors the SDA1 and SCL1 pins.
6
INH1
SMBus1 Slave Inhibit.
When this bit is set to logic 1, the SMBus1 does not generate an interrupt when
slave events occur. This effectively removes the SMBus1 slave from the bus. Master Mode interrupts are not affected.
5
BUSY1
SMBus1 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4
EXTHOLD1
SMBus1 Setup and Hold Time Extension Enable.
This bit controls the SDA1 setup and hold times according to Table 21.2.
0: SDA1 Extended Setup and Hold Times disabled.
1: SDA1 Extended Setup and Hold Times enabled.
3
SMB1TOE
SMBus1 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus1 forces
Timer 4 to reload while SCL1 is high and allows Timer 4 to count when SCL1 goes
low. If Timer 4 is configured to Split Mode, only the High Byte of the timer is held in
reload while SCL1 is high. Timer 4 should be programmed to generate interrupts at
25 ms, and the Timer 4 interrupt service routine should reset SMBus1 communication.
2
SMB1FTE
SMBus1 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL1 and SDA1
remain high for more than 10 SMBus clock source periods.
1:0 SMB1CS[1:0] SMBus1 Clock Source Selection.
These two bits select the SMBus1 clock source, which is used to generate the
SMBus1 bit rate. The selected device should be configured according to
Equation 21.1.
00: Timer 0 Overflow
01: Timer 5 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
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SFR Definition 21.3. SMBTC: SMBus Timing Control
Bit
7
6
5
4
Name
Type
R
R
R
R
Reset
0
0
0
0
3
2
1
0
SMB1SDD[1:0]
SMB0SDD[1:0]
R/W
R/W
0
0
0
0
SFR Address = 0xB9; SFR Page = F
Bit
Name
Function
Read = 0000b; Write = don’t care.
7:4
Unused
3:2
SMB1SDD[1:0] SMBus1 Start Detection Window
These bits increase the hold time requirement between SDA falling and SCL falling for START detection.
00: No additional hold time requirement (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
1:0
SMB0SDD[1:0] SMBus0 Start Detection Window
These bits increase the hold time requirement between SDA falling and SCL falling for START detection.
00: No additional hold time window (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
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21.4.3. SMBnCN Control Register
SMBnCN is used to control the interface and to provide status information (see SFR Definition 21.4). The
higher four bits of SMBnCN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 21.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
21.4.3.1. Software ACK Generation
When the EHACK bit in register SMBnADM is cleared to 0, the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
21.4.3.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK generation is enabled. More detail about automatic slave address recognition can be found in Section 21.4.4.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 21.3 lists all sources for hardware changes to the SMBnCN bits. Refer to Table 21.5 for SMBus status decoding using the SMBnCN register.
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SFR Definition 21.4. SMB0CN: SMBus Control
Bit
7
6
5
4
Name MASTER0 TXMODE0
STA0
STO0
Type
R
R
R/W
R/W
R
Reset
0
0
0
0
0
SFR Address = 0xC0; SFR Page = 0; Bit-Addressable
Bit
Name
Description
3
2
1
0
ACK0
SI0
R
R/W
R/W
0
0
0
ACKRQ0 ARBLOST0
Read
Write
7
MASTER0 SMBus0 Master/Slave
Indicator. This read-only bit
indicates when the SMBus0 is
operating as a master.
0: SMBus0 operating in
slave mode.
1: SMBus0 operating in
master mode.
N/A
6
TXMODE0 SMBus0 Transmit Mode
Indicator. This read-only bit
indicates when the SMBus0 is
operating as a transmitter.
0: SMBus0 in Receiver
Mode.
1: SMBus0 in Transmitter
Mode.
N/A
5
STA0
SMBus0 Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4
STO0
SMBus0 Stop Flag.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or
pending (if in Master
Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmitted after the next ACK
cycle.
Cleared by Hardware.
3
ACKRQ0
SMBus0 Acknowledge
Request.
0: No ACK requested
1: ACK requested
N/A
0: No arbitration error.
1: Arbitration Lost
N/A
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
2
ARBLOST0 SMBus0 Arbitration Lost
Indicator.
1
ACK0
0
SI0
176
SMBus0 Acknowledge.
0: No interrupt pending
SMBus0 Interrupt Flag.
1: Interrupt Pending
This bit is set by hardware
under the conditions listed in
Table 15.3. SI0 must be
cleared by software. While SI0
is set, SCL0 is held low and
the SMBus0 is stalled.
Rev. 1.1
0: Clear interrupt, and initiate next state machine
event.
1: Force interrupt.
C8051F388/9/A/B
SFR Definition 21.5. SMB1CN: SMBus Control
Bit
7
6
5
4
Name MASTER1 TXMODE1
STA1
STO1
Type
R
R
R/W
R/W
R
Reset
0
0
0
0
0
SFR Address = 0xC0; SFR Page = F; Bit-Addressable
Bit
Name
Description
3
2
1
0
ACK1
SI1
R
R/W
R/W
0
0
0
ACKRQ1 ARBLOST1
Read
Write
7
MASTER1 SMBus1 Master/Slave
Indicator. This read-only bit
indicates when the SMBus1 is
operating as a master.
0: SMBus1 operating in
slave mode.
1: SMBus1 operating in
master mode.
N/A
6
TXMODE1 SMBus1 Transmit Mode
Indicator. This read-only bit
indicates when the SMBus1 is
operating as a transmitter.
0: SMBus1 in Receiver
Mode.
1: SMBus1 in Transmitter
Mode.
N/A
5
STA1
SMBus1 Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4
STO1
SMBus1 Stop Flag.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or
pending (if in Master
Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmitted after the next ACK
cycle.
Cleared by Hardware.
3
ACKRQ1
SMBus1 Acknowledge
Request.
0: No ACK requested
1: ACK requested
N/A
0: No arbitration error.
1: Arbitration Lost
N/A
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
2
ARBLOST1 SMBus1 Arbitration Lost
Indicator.
1
ACK1
0
SI1
SMBus1 Acknowledge.
0: No interrupt pending
SMBus1 Interrupt Flag.
1: Interrupt Pending
This bit is set by hardware
under the conditions listed in
Table 15.3. SI1 must be
cleared by software. While SI1
is set, SCL1 is held low and
the SMBus1 is stalled.
Rev. 1.1
0: Clear interrupt, and initiate next state machine
event.
1: Force interrupt.
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Table 21.3. Sources for Hardware Changes to SMBnCN
Bit
MASTERn

STAn



STOn


ACKRQn

ARBLOSTn


ACKn




SIn
START is generated.
SMBnDAT is written before the start of an
SMBus frame.

A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STAn is low (unwanted
repeated START).
SCLn is sensed low while attempting to
generate a STOP or repeated START
condition.
SDAn is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low
(ACKNOWLEDGE).
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.

Cleared by Hardware When:
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMBnDAT is not written before the
start of an SMBus frame.
Must be cleared by software.

A pending STOP is generated.

After each ACK cycle.

Each time SIn is cleared.

The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.



TXMODEn
Set by Hardware When:
A START is generated.






21.4.4. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 21.4.3.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register and the SMBus Slave Address Mask register. A single address or range of addresses
(including the General Call Address 0x00) can be specified using these two registers. The most-significant
seven bits of the two registers are used to define which addresses will be ACKed. A 1 in bit positions of the
slave address mask SLVM[6:0] enable a comparison between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit of the slave address mask means that bit will be
treated as a “don’t care” for comparison purposes. In this case, either a 1 or a 0 value are acceptable on
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the incoming slave address. Additionally, if the GCn bit in register SMBnADR is set to 1, hardware will recognize the General Call Address (0x00). Table 21.4 shows some example parameter settings and the
slave addresses that will be recognized by hardware under those conditions.
Table 21.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLVn[6:0]
0x34
0x34
0x34
0x34
0x70
Slave Address Mask
SLVMn[6:0]
0x7F
0x7F
0x7E
0x7E
0x73
GCn bit Slave Addresses Recognized by
Hardware
0
1
0
1
0
0x34
0x34, 0x00 (General Call)
0x34, 0x35
0x34, 0x35, 0x00 (General Call)
0x70, 0x74, 0x78, 0x7C
SFR Definition 21.6. SMB0ADR: SMBus0 Slave Address
Bit
7
6
5
4
3
2
1
0
Name
SLV0[6:0]
GC0
Type
R/W
R/W
Reset
0
0
0
0
SFR Address = 0xCF; SFR Page = 0
Bit
Name
0
0
0
0
Function
7:1
SLV0[6:0]
SMBus Hardware Slave Address.
Defines the SMBus0 Slave Address(es) for automatic hardware acknowledgment.
Only address bits which have a 1 in the corresponding bit position in SLVM0[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC0
General Call Address Enable.
When hardware address recognition is enabled (EHACK0 = 1), this bit will determine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
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SFR Definition 21.7. SMB0ADM: SMBus0 Slave Address Mask
Bit
7
6
5
4
3
2
1
0
Name
SLVM0[6:0]
EHACK0
Type
R/W
R/W
Reset
1
1
1
1
SFR Address = 0xCE; SFR Page = 0
Bit
Name
1
1
1
0
Function
7:1
SLVM0[6:0]
SMBus0 Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM0[6:0] enables comparisons with the corresponding bit in SLV0[6:0]. Bits set to 0 are ignored (can be
either 0 or 1 in the incoming address).
0
EHACK0
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
SFR Definition 21.8. SMB1ADR: SMBus1 Slave Address
Bit
7
6
5
4
3
2
1
0
Name
SLV1[6:0]
GC1
Type
R/W
R/W
Reset
0
0
0
0
SFR Address = 0xCF; SFR Page = F
Bit
Name
0
0
0
0
Function
7:1
SLV1[6:0]
SMBus1 Hardware Slave Address.
Defines the SMBus1 Slave Address(es) for automatic hardware acknowledgment.
Only address bits which have a 1 in the corresponding bit position in SLVM1[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC1
General Call Address Enable.
When hardware address recognition is enabled (EHACK1 = 1), this bit will determine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
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SFR Definition 21.9. SMB1ADM: SMBus1 Slave Address Mask
Bit
7
6
5
4
3
2
1
0
Name
SLVM1[6:0]
EHACK1
Type
R/W
R/W
Reset
1
1
1
1
SFR Address = 0xCE; SFR Page = F
Bit
Name
1
1
1
0
Function
7:1
SLVM1[6:0]
SMBus1 Slave Address Mask.
Defines which bits of register SMB1ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM1[6:0] enables comparisons with the corresponding bit in SLV1[6:0]. Bits set to 0 are ignored (can be
either 0 or 1 in the incoming address).
0
EHACK1
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
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21.4.5. Data Register
The SMBus Data register SMBnDAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SIn flag is set. Software should
not attempt to access the SMBnDAT register when the SMBus is enabled and the SIn flag is cleared to
logic 0, as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMBnDAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMBnDAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMBnDAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMBnDAT.
SFR Definition 21.10. SMB0DAT: SMBus Data
Bit
7
6
5
4
3
Name
SMB0DAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xC2; SFR Page = 0
Bit
Name
0
2
1
0
0
0
0
Function
7:0 SMB0DAT[7:0] SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0
serial interface or a byte that has just been received on the SMBus0 serial interface. The CPU can read from or write to this register whenever the SI0 serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable
as long as the SI0 flag is set. When the SI0 flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this register.
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SFR Definition 21.11. SMB1DAT: SMBus Data
Bit
7
6
5
4
3
Name
SMB1DAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xC2; SFR Page = F
Bit
Name
0
2
1
0
0
0
0
Function
7:0 SMB1DAT[7:0] SMBus1 Data.
The SMB1DAT register contains a byte of data to be transmitted on the SMBus1
serial interface or a byte that has just been received on the SMBus1 serial interface. The CPU can read from or write to this register whenever the SI1 serial interrupt flag (SMB1CN.0) is set to logic 1. The serial data in the register remains stable
as long as the SI1 flag is set. When the SI1 flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this register.
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21.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. The position of the ACK interrupt when operating as a receiver depends on
whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs before the
ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is
enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK generation
is enabled or not.
21.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. The interface will switch
to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 21.5
shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes
may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this
mode, regardless of whether hardware ACK generation is enabled.
Figure 21.5. Typical Master Write Sequence
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21.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 21.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after
the ACK when hardware ACK generation is enabled.
Figure 21.6. Typical Master Read Sequence
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21.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. The interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 21.7 shows a typical slave write
sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that
the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled.
Figure 21.7. Typical Slave Write Sequence
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21.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP.
The interface will switch to slave receiver mode if SMB0DAT is not written following a Slave Transmitter
interrupt. Figure 21.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though
any number of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur after
the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
Figure 21.8. Typical Slave Read Sequence
21.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 21.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 21.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
Rev. 1.1
187
C8051F388/9/A/B
Values to
Write
Master Receiver
188
ACKRQ
ARBLOST
0
0 X
0
0
0
1000
1
0
ACK
STO
1100
Typical Response Options
ACK
Status
Vector
1110
Current SMbus State
STA
Master Transmitter
Mode
Values Read
Next Status
Vector Expected
Table 21.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0)
0
0 X
1100
1
0 X
1110
0
1 X
—
Load next data byte into SMB0DAT.
0
0 X
1100
End transfer with STOP.
0
1 X
—
A master data or address byte End transfer with STOP and start 1
1 was transmitted; ACK
another transfer.
received.
Send repeated START.
1
1 X
—
0 X
1110
A master START was generated.
Load slave address + R/W into
SMB0DAT.
A master data or address byte Set STA to restart transfer.
0 was transmitted; NACK
Abort transfer.
received.
0 X
A master data byte was
received; ACK requested.
Switch to Master Receiver Mode 0
(clear SI without writing new data
to SMB0DAT).
0 X 1000
Acknowledge received byte;
Read SMB0DAT.
0
0
1
1000
Send NACK to indicate last byte, 0
and send STOP.
1
0
—
Send NACK to indicate last byte, 1
and send STOP followed by
START.
1
0
1110
Send ACK followed by repeated
START.
1
0
1
1110
Send NACK to indicate last byte, 1
and send repeated START.
0
0
1110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
1
1100
Send NACK and switch to Master Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
1100
Rev. 1.1
C8051F388/9/A/B
Values to
Write
ACK
STA
STO
0101
ARBLOST
0
0
0
A slave byte was transmitted; No action required (expecting
NACK received.
STOP condition).
0
0 X 0001
0
0
1
A slave byte was transmitted; Load SMB0DAT with next data
ACK received.
byte to transmit.
0
0 X 0100
0
1 X
A Slave byte was transmitted; No action required (expecting
error detected.
Master to end transfer).
0
0 X 0001
0
0 X
0
0
1
0000
If Read, Load SMB0DAT with
0
data byte; ACK received address
0
1
0100
NACK received address.
0
0
0
—
If Write, Acknowledge received
address
0
0
1
0000
If Read, Load SMB0DAT with
0
Lost arbitration as master;
1 X slave address + R/W received; data byte; ACK received address
ACK requested.
NACK received address.
0
0
1
0100
0
0
—
1
0
0
1110
0
0 X
—
Lost arbitration while attempt- No action required (transfer
ing a STOP.
complete/aborted).
0
0
0
—
Acknowledge received byte;
Read SMB0DAT.
0
0
1
0000
NACK received byte.
0
0
0
—
Current SMbus State
Typical Response Options
An illegal STOP or bus error
0 X X was detected while a Slave
Clear STO.
Transmission was in progress.
If Write, Acknowledge received
address
1
0 X
A slave address + R/W was
received; ACK requested.
Slave Receiver
0010
1
Reschedule failed transfer;
NACK received address.
0
A STOP was detected while
0 X addressed as a Slave Transmitter or Slave Receiver.
1
1 X
1
A slave byte was received;
0 X
ACK requested.
0001
0000
ACK
Status
Vector
0100
ACKRQ
Slave Transmitter
Mode
Values Read
Next Status
Vector Expected
Table 21.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
—
Clear STO.
Rev. 1.1
189
C8051F388/9/A/B
Values to
Write
Status
Vector
ACKRQ
ARBLOST
0010
0
1 X
Lost arbitration while attempt- Abort failed transfer.
ing a repeated START.
Reschedule failed transfer.
0001
0
1 X
Lost arbitration due to a
detected STOP.
0000
1
1 X
STO
0
0 X
—
1
0 X
1110
Abort failed transfer.
0
0 X
—
Reschedule failed transfer.
1
0 X
1110
Lost arbitration while transmit- Abort failed transfer.
ting a data byte as master.
Reschedule failed transfer.
0
0
0
—
1
0
0
1110
Values to
Write
Next Status
Vector Expected
ACK
Typical Response Options
ACK
Current SMbus State
STA
Bus Error Condition
Mode
Values Read
Next Status
Vector Expected
Table 21.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
Table 21.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1)
190
ACKRQ
ARBLOST
0
0 X
0
0
0
0
ACK
STO
1100
Typical Response Options
ACK
Status
Vector
1110
Current SMbus State
STA
Master Transmitter
Mode
Values Read
0
0 X
1100
1
0 X
1110
0
1 X
—
Load next data byte into SMB0DAT.
0
0 X
1100
End transfer with STOP.
0
1 X
—
End transfer with STOP and start 1
A master data or address byte
another transfer.
1 was transmitted; ACK
Send repeated START.
1
received.
Switch to Master Receiver Mode 0
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
1 X
—
0 X
1110
0
1000
A master START was generated.
Load slave address + R/W into
SMB0DAT.
A master data or address byte Set STA to restart transfer.
0 was transmitted; NACK
Abort transfer.
received.
Rev. 1.1
1
C8051F388/9/A/B
Values to
Write
0100
0101
A master data byte was
0 received; NACK sent (last
byte).
ACK
A master data byte was
received; ACK sent.
STO
0
Typical Response Options
ACK
1
1000
0
Slave Transmitter
0
Current SMbus State
STA
Master Receiver
0
ARBLOST
ACKRQ
Status
Vector
Mode
Values Read
Next Status
Vector Expected
Table 21.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Set ACK for next data byte;
Read SMB0DAT.
0
0
1
1000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
0
0
0
1000
Initiate repeated START.
1
0
0
1110
Switch to Master Transmitter
0
Mode (write to SMB0DAT before
clearing SI).
0 X
1100
Read SMB0DAT; send STOP.
0
1
0
—
Read SMB0DAT; Send STOP
followed by START.
1
1
0
1110
Initiate repeated START.
1
0
0
1110
0 X
1100
Switch to Master Transmitter
0
Mode (write to SMB0DAT before
clearing SI).
0
0
0
A slave byte was transmitted; No action required (expecting
NACK received.
STOP condition).
0
0 X 0001
0
0
1
A slave byte was transmitted; Load SMB0DAT with next data
ACK received.
byte to transmit.
0
0 X 0100
0
1 X
A Slave byte was transmitted; No action required (expecting
error detected.
Master to end transfer).
0
0 X 0001
0
0 X
An illegal STOP or bus error
0 X X was detected while a Slave
Clear STO.
Transmission was in progress.
Rev. 1.1
—
191
C8051F388/9/A/B
Values to
Write
ACKRQ
ARBLOST
0
A slave address + R/W was
0 X
received; ACK sent.
STO
ACK
If Write, Set ACK for first data
byte.
0
0
1
If Read, Load SMB0DAT with
data byte
0
0 X 0100
If Write, Set ACK for first data
byte.
0
0
0
0 X 0100
1
0 X
1110
0
0 X
—
Lost arbitration while attempt- No action required (transfer
ing a STOP.
complete/aborted).
0
0
0
—
Set ACK for next data byte;
Read SMB0DAT.
0
0
1
0000
Set NACK for next data byte;
Read SMB0DAT.
0
0
0
0000
0
0 X
—
1
0 X
1110
Abort failed transfer.
0
0 X
—
Bus Error Condition
Slave Receiver
0010
192
0
Typical Response Options
STA
Current SMbus State
ACK
Status
Vector
Mode
Values Read
Lost arbitration as master;
1 X slave address + R/W received; If Read, Load SMB0DAT with
ACK sent.
data byte
Reschedule failed transfer
0
A STOP was detected while
0 X addressed as a Slave Transmitter or Slave Receiver.
0
1 X
0001
Next Status
Vector Expected
Table 21.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
1
0000
0000
Clear STO.
0000
0
0 X A slave byte was received.
0010
0
1 X
Lost arbitration while attempt- Abort failed transfer.
ing a repeated START.
Reschedule failed transfer.
0001
0
1 X
Lost arbitration due to a
detected STOP.
Reschedule failed transfer.
1
0 X
1110
0 X
—
0
1 X
Lost arbitration while transmit- Abort failed transfer.
ting a data byte as master.
Reschedule failed transfer.
0
0000
1
0 X
1110
Rev. 1.1
C8051F388/9/A/B
22. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “22.1. Enhanced Baud Rate Generation” on page 194). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Figure 22.1. UART0 Block Diagram
Rev. 1.1
193
C8051F388/9/A/B
22.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 22.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Figure 22.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “25.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 228). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 22.1-A and
Equation 22.1-B.
A)
B)
UARTBaudRate = 1
---  T1_Overflow_Rate
2
T1 CLK
T1_Overflow_Rate = -------------------------256 – TH1
Equation 22.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “25. Timers” on page 224. A quick reference for typical baud rates and system clock frequencies is given in Table 22.1. The internal oscillator
may still generate the system clock when the external oscillator is driving Timer 1.
194
Rev. 1.1
C8051F388/9/A/B
22.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3.
Figure 22.3. UART Interconnect Diagram
22.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
Figure 22.4. 8-Bit UART Timing Diagram
Rev. 1.1
195
C8051F388/9/A/B
22.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
Figure 22.5. 9-Bit UART Timing Diagram
196
Rev. 1.1
C8051F388/9/A/B
22.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.1
197
C8051F388/9/A/B
SFR Definition 22.1. SCON0: Serial Port 0 Control
Bit
7
6
5
4
3
2
1
0
Name
S0MODE
-
MCE0
REN0
TB80
RB80
TI0
RI0
Type
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
0
0
0
0
0
0
SFR Address = 0x98; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6
Unused
5
MCE0
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4
REN0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
3
TB80
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2
RB80
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1
TI0
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0
RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
198
Read = 1b, Write = don’t care.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
Name
SBUF0[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0x99; SFR Page = All Pages
Bit
Name
7:0
2
1
0
0
0
0
Function
SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
SYSCLK = 48 MHz
SYSCLK = 24 MHz
SYSCLK = 12 MHz
Table 22.1. Timer Settings for Standard Baud Rates Using Internal Oscillator
Target
Actual
Baud
Baud
Rate (bps) Rate (bps)
230400
230769
115200
115385
57600
57692
28800
28846
14400
14423
9600
9615
2400
2404
1200
1202
230400
230769
115200
115385
57600
57692
28800
28846
14400
14423
9600
9615
2400
2404
1200
1202
230400
230769
115200
115385
57600
57692
28800
28846
14400
14388
9600
9615
2400
2404
Baud
Rate
Error
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.08%
0.16%
0.16%
Oscillator
Divide
Factor
52
104
208
416
832
1248
4992
9984
104
208
416
832
1664
2496
9984
19968
208
416
832
1664
3336
4992
19968
Timer Clock
Source
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 48
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
Rev. 1.1
SCA1-SCA0
(pre-scale
select*
XX
XX
XX
XX
01
01
00
10
XX
XX
XX
01
01
00
10
10
XX
XX
01
01
00
00
10
T1M
Timer 1
Reload
Value (hex)
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0xE6
0xCC
0x98
0x30
0x98
0x64
0x30
0x98
0xCC
0x98
0x30
0x98
0x30
0x98
0x98
0x30
0x98
0x30
0x98
0x30
0x75
0x30
0x30
199
C8051F388/9/A/B
Table 22.1. Timer Settings for Standard Baud Rates Using Internal Oscillator
Target
Actual
Baud
Baud
Rate (bps) Rate (bps)
Baud
Rate
Error
Oscillator Timer Clock
Divide
Source
Factor
Note: SCA1-SCA0 and T1M define the Timer Clock Source. X = Don’t care
200
Rev. 1.1
SCA1-SCA0
(pre-scale
select*
T1M
Timer 1
Reload
Value (hex)
C8051F388/9/A/B
23. UART1
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in Section “23.1. Baud Rate Generator” on page 202). A received data FIFO
allows UART1 to receive up to three data bytes before data is lost and an overflow occurs.
UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and
SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is
used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit
holding register and the receive FIFO. Writes to SBUF1 always access the Transmit Holding Register.
Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data
from the Transmit Holding Register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive
complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by
software.
Figure 23.1. UART1 Block Diagram
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23.1. Baud Rate Generator
The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock
(SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow
for a wide selection of baud rates over many SYSCLK frequencies.
The baud rate generator is configured using three registers: SBCON1, SBRLH1, and SBRLL1. The
UART1 Baud Rate Generator Control Register (SBCON1, SFR Definition ) enables or disables the baud
rate generator, and selects the prescaler value for the timer. The baud rate generator must be enabled for
UART1 to function. Registers SBRLH1 and SBRLL1 contain a 16-bit reload value for the dedicated 16-bit
timer. The internal timer counts up from the reload value on every clock tick. On timer overflows (0xFFFF
to 0x0000), the timer is reloaded. For reliable UART operation, it is recommended that the UART baud rate
is not configured for baud rates faster than SYSCLK/16. The baud rate for UART1 is defined in
Equation 23.1.
SYSCLK
1
Baud Rate = ------------------------------------------------------------------------------  1
---  ------------------------ 65536 – (SBRLH1:SBRLL1)  2 Prescaler
Equation 23.1. UART1 Baud Rate
A quick reference for typical baud rates and system clock frequencies is given in Table 23.1.
SYSCLK = 48 MHz
SYSCLK = 24 MHz
SYSCLK = 12 MHz
Table 23.1. Baud Rate Generator Settings for Standard Baud Rates
202
Target Baud
Rate (bps)
Actual Baud
Rate (bps)
Baud Rate
Error
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
2400
1200
230769
115385
57692
28846
14388
9600
2400
1200
230769
115385
57692
28777
14406
9600
2400
1200
230769
115385
57554
28812
14397
9600
2400
1200
0.16%
0.16%
0.16%
0.16%
0.08%
0.0%
0.0%
0.0%
0.16%
0.16%
0.16%
0.08%
0.04%
0.0%
0.0%
0.0%
0.16%
0.16%
0.08%
0.04%
0.02%
0.0%
0.0%
0.0%
Oscillator
Divide
Factor
52
104
208
416
834
1250
5000
10000
104
208
416
834
1666
2500
10000
20000
208
416
834
1666
3334
5000
20000
40000
Rev. 1.1
SB1PS[1:0]
(Prescaler Bits)
Reload Value in
SBRLH1:SBRLL1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
0xFFE6
0xFFCC
0xFF98
0xFF30
0xFE5F
0xFD8F
0xF63C
0xEC78
0xFFCC
0xFF98
0xFF30
0xFE5F
0xFCBF
0xFB1E
0xEC78
0xD8F0
0xFF98
0xFF30
0xFE5F
0xFCBF
0xF97D
0xF63C
0xD8F0
0xB1E0
C8051F388/9/A/B
23.2. Data Format
UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop
bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor communication mode is available for implementing networked UART buses. All of the data formatting options
can be configured using the SMOD1 register, shown in SFR Definition . Figure 23.2 shows the timing for a
UART1 transaction without parity or an extra bit enabled. Figure 23.3 shows the timing for a UART1 transaction with parity enabled (PE1 = 1). Figure 23.4 is an example of a UART1 transaction when the extra bit
is enabled (XBE1 = 1). Note that the extra bit feature is not available when parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits.
Figure 23.2. UART1 Timing Without Parity or Extra Bit
Figure 23.3. UART1 Timing With Parity
Figure 23.4. UART1 Timing With Extra Bit
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23.3. Configuration and Operation
UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point
serial communications application, or as a node on a multi-processor serial interface. To operate in a pointto-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be
cleared to 0. For operation as part of a multi-processor communications bus, the MCE1 and XBE1 bits
should both be set to 1. In both types of applications, data is transmitted from the microcontroller on the
TX1 pin, and received on the RX1 pin. The TX1 and RX1 pins are configured using the crossbar and the
Port I/O registers, as detailed in Section “20. Port Input/Output” on page 147.
In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX)
input of the other device, either directly or through a bus transceiver, as shown in Figure 23.5.
Figure 23.5. Typical UART Interconnect Diagram
23.3.1. Data Transmission
Data transmission is double-buffered, and begins when software writes a data byte to the SBUF1 register.
Writing to SBUF1 places data in the Transmit Holding Register, and the Transmit Holding Register Empty
flag (THRE1) will be cleared to 0. If the UARTs shift register is empty (i.e. no transmission is in progress)
the data will be placed in the shift register, and the THRE1 bit will be set to 1. If a transmission is in progress, the data will remain in the Transmit Holding Register until the current transmission is complete. The
TI1 Transmit Interrupt Flag (SCON1.1) will be set at the end of any transmission (the beginning of the stopbit time). If enabled, an interrupt will occur when TI1 is set.
If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the value of the
TBX1 (SCON1.3) bit will be sent in the extra bit position. When the parity function is enabled (PE1 = 1),
hardware will generate the parity bit according to the selected parity type (selected with S1PT[1:0]), and
append it to the data field. Note: when parity is enabled, the extra bit function is not available.
23.3.2. Data Reception
Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the
stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the
receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the
receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated
(OVR1 in register SCON1 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be
stored in the receive FIFO. If the reception conditions are met, the data is stored in the receive FIFO, and
the RI1 flag will be set. Note: when MCE1 = 1, RI1 will only be set if the extra bit was equal to 1. Data can
be read from the receive FIFO by reading the SBUF1 register. The SBUF1 register represents the oldest
byte in the FIFO. After SBUF1 is read, the next byte in the FIFO is immediately loaded into SBUF1, and
space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI1
is set. RI1 can only be cleared to '0' by software when there is no more information in the FIFO. The recommended procedure to empty the FIFO contents is:
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1. Clear RI1 to 0
2. Read SBUF1
3. Check RI1, and repeat at Step 1 if RI1 is set to 1.
If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the extra bit for
the oldest byte in the FIFO can be read from the RBX1 bit (SCON1.2). If the extra bit function is not
enabled, the value of the stop bit for the oldest FIFO byte will be presented in RBX1. When the parity function is enabled (PE1 = 1), hardware will check the received parity bit against the selected parity type
(selected with S1PT[1:0]) when receiving data. If a byte with parity error is received, the PERR1 flag will be
set to 1. This flag must be cleared by software. Note: when parity is enabled, the extra bit function is not
available.
23.3.3. Multiprocessor Communications
UART1 supports multiprocessor communication between a master processor and one or more slave processors by special use of the extra data bit. When a master processor wants to transmit to one or more
slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that
its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0.
Setting the MCE1 bit (SMOD1.7) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the extra bit is logic 1 (RBX1 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned address. If the addresses match, the slave will clear its MCE1 bit to
enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their
MCE1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring
the data. Once the entire message is received, the addressed slave resets its MCE1 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
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SFR Definition 23.1. SCON1: UART1 Control
Bit
7
6
5
4
3
2
1
0
Name
OVR1
PERR1
THRE1
REN1
TBX1
RBX1
TI1
RI1
Type
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
0
0
0
0
0
SFR Address = 0xD2; SFR Page = All Pages
Bit
Name
Function
7
OVR1
Receive FIFO Overrun Flag.
This bit indicates a receive FIFO overrun condition, where an incoming character is discarded
due to a full FIFO. This bit must be cleared to 0 by software.
0: Receive FIFO Overrun has not occurred.
1: Receive FIFO Overrun has occurred.
6
PERR1
Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1 when the
parity of the oldest byte in the FIFO does not match the selected Parity Type. This bit must be
cleared to 0 by software.
0: Parity Error has not occurred.
1: Parity Error has occurred.
5
THRE1
Transmit Holding Register Empty Flag.
0: Transmit Holding Register not Empty - do not write to SBUF1.
1: Transmit Holding Register Empty - it is safe to write to SBUF1.
4
REN1
Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read from the
receive FIFO.
0: UART1 reception disabled.
1: UART1 reception enabled.
3
TBX1
Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE1 = 1. This bit is
not used when Parity is enabled.
2
RBX1
Extra Receive Bit.
RBX1 is assigned the value of the extra bit when XBE1 = 1. If XBE1 is cleared to 0, RBX1 is
assigned the logic level of the first stop bit. This bit is not valid when Parity is enabled.
1
TI1
Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit. When
the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt
service routine. This bit must be cleared manually by software.
0
RI1
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART1 (set at the STOP bit sampling time). When the UART1 interrupt is enabled, setting this bit to 1 causes the CPU to vector
to the UART1 interrupt service routine. This bit must be cleared manually by software. Note that
RI1 will remain set to '1' as long as there is still data in the UART FIFO. After the last byte has
been shifted from the FIFO to SBUF1, RI1 can be cleared.
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SFR Definition 23.2. SMOD1: UART1 Mode
Bit
7
6
5
Name
MCE1
S1PT[1:0]
PE1
Type
R/W
R/W
R/W
Reset
0
0
0
4
0
SFR Address = 0xE5; SFR Page = All Pages
Bit
Name
7
6:5
4
3:2
MCE1
3
2
1
0
S1DL[1:0]
XBE1
SBL1
R/W
R/W
R/W
0
0
1
1
Function
Multiprocessor Communication Enable.
0: RI will be activated if stop bit(s) are 1.
1: RI will be activated if stop bit(s) and extra bit are 1 (extra bit must be enabled using
XBE1).
Note: This function is not available when hardware parity is enabled.
S1PT[1:0] Parity Type Bits.
00: Odd
01: Even
10: Mark
11: Space
PE1
Parity Enable.
This bit activates hardware parity generation and checking. The parity type is selected
by bits S1PT1-0 when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
S1DL[1:0] Data Length.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
1
XBE1
Extra Bit Enable.
When enabled, the value of TBX1 will be appended to the data field.
0: Extra Bit Disabled.
1: Extra Bit Enabled.
0
SBL1
Stop Bit Length.
0: Short—Stop bit is active for one bit time.
1: Long—Stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
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SFR Definition 23.3. SBUF1: UART1 Data Buffer
Bit
7
6
5
4
3
Name
SBUF1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xD3; SFR Page = All Pages
Bit
Name
Description
7:0
208
SBUF1[7:0] Serial Data Buffer Bits.
This SFR is used to both send
data from the UART and to
read received data from the
UART1 receive FIFO.
0
2
1
0
0
0
0
Write
Read
Writing a byte to SBUF1
initiates the transmission.
When data is written to
SBUF1, it first goes to the
Transmit Holding Register,
where it is held for serial
transmission. When the
transmit shift register is
available, data is transferred into the shift register, and SBUF1 may be
written again.
Reading SBUF1 retrieves
data from the receive
FIFO. When read, the oldest byte in the receive
FIFO is returned, and
removed from the FIFO.
Up to three bytes may be
held in the FIFO. If there
are additional bytes available in the FIFO, the RI1
bit will remain at logic 1,
even after being cleared
by software.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 23.4. SBCON1: UART1 Baud Rate Generator Control
Bit
7
Name
6
5
4
3
2
SB1RUN
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xAC; SFR Page = All Pages
Bit
Name
Reserved
SB1RUN
0
SB1PS[1:0]
Type
7
6
1
R/W
0
0
Function
Read = 0b. Must Write 0b.
Baud Rate Generator Enable.
0: Baud Rate Generator is disabled. UART1 will not function.
1: Baud Rate Generator is enabled.
5:2 Reserved Read = 0000b. Must Write 0000b.
1:0 SB1PS[1:0] Baud Rate Prescaler Select.
00: Prescaler = 12
01: Prescaler = 4
10: Prescaler = 48
11: Prescaler = 1
SFR Definition 23.5. SBRLH1: UART1 Baud Rate Generator High Byte
Bit
7
6
5
4
3
Name
SBRLH1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xB5; SFR Page = All Pages
Bit
Name
0
2
1
0
0
0
0
Function
7:0 SBRLH1[7:0] UART1 Baud Rate Reload High Bits.
High Byte of reload value for UART1 Baud Rate Generator.
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SFR Definition 23.6. SBRLL1: UART1 Baud Rate Generator Low Byte
Bit
7
6
5
4
3
Name
SBRLL1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xB4; SFR Page = All Pages
Bit
Name
0
2
1
0
0
0
0
Function
7:0 SBRLL1[7:0] UART1 Baud Rate Reload Low Bits.
Low Byte of reload value for UART1 Baud Rate Generator.
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24. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 24.1. SPI Block Diagram
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24.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
24.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
24.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
24.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
24.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-topoint communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 24.2, Figure 24.3, and Figure 24.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “20. Port Input/Output” on page 147 for general purpose
port I/O and crossbar information.
24.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
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1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 24.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 24.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 24.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
Figure 24.2. Multiple-Master Mode Connection Diagram
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
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Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
24.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 24.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.
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24.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.




The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
24.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 24.5. For slave mode, the clock and
data relationships are shown in Figure 24.6 and Figure 24.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 24.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
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Figure 24.5. Master Mode Data/Clock Timing
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0)
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Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1)
24.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
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SFR Definition 24.1. SPI0CFG: SPI0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
Type
R
R/W
R/W
R/W
R
R
R
R
Reset
0
0
0
0
0
1
1
1
SFR Address = 0xA1; SFR Page = All Pages
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
MSTEN
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5
CKPHA
SPI0 Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
4
CKPOL
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3
SLVSEL
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
2
NSSIN
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1
SRMT
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0
RXBMT
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 24.1 for timing parameters.
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SFR Definition 24.2. SPI0CN: SPI0 Control
Bit
7
6
5
4
Name
SPIF
WCOL
MODF
RXOVRN
Type
R/W
R/W
R/W
R/W
Reset
0
0
0
0
3
2
1
0
NSSMD[1:0]
TXBMT
SPIEN
R/W
R
R/W
1
0
0
1
SFR Address = 0xF8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
SPIF
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6
WCOL
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
5
MODF
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
4
RXOVRN
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2
NSSMD[1:0]
1
TXBMT
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPIEN
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 24.2 and Section 24.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
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SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
Name
SCR[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xA2; SFR Page = All Pages
Bit
Name
7:0
SCR[7:0]
3
2
1
0
0
0
0
0
Function
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
SYSCLK
f SCK = ------------------------------------------------------------2   SPI0CKR[7:0] + 1 
for 0  SPI0CKR  255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
f SCK = --------------------------2  4 + 1
f SCK = 200kHz
SFR Definition 24.4. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
Name
SPI0DAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xA3; SFR Page = All Pages
Bit
Name
7:0
220
0
2
1
0
0
0
0
Function
SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
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Figure 24.8. SPI Master Timing (CKPHA = 0)
Figure 24.9. SPI Master Timing (CKPHA = 1)
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Figure 24.10. SPI Slave Timing (CKPHA = 0)
Figure 24.11. SPI Slave Timing (CKPHA = 1)
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Table 24.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing (See Figure 24.8 and Figure 24.9)
TMCKH
SCK High Time
1 x TSYSCLK
—
ns
TMCKL
SCK Low Time
1 x TSYSCLK
—
ns
TMIS
MISO Valid to SCK Shift Edge
1 x TSYSCLK + 20
—
ns
TMIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing (See Figure 24.10 and Figure 24.11)
TSE
NSS Falling to First SCK Edge
2 x TSYSCLK
—
ns
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
—
ns
TSEZ
NSS Falling to MISO Valid
—
4 x TSYSCLK
ns
TSDZ
NSS Rising to MISO High-Z
—
4 x TSYSCLK
ns
TCKH
SCK High Time
5 x TSYSCLK
—
ns
TCKL
SCK Low Time
5 x TSYSCLK
—
ns
TSIS
MOSI Valid to SCK Sample Edge
2 x TSYSCLK
—
ns
TSIH
SCK Sample Edge to MOSI Change
2 x TSYSCLK
—
ns
TSOH
SCK Shift Edge to MISO Change
—
4 x TSYSCLK
ns
TSLH
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x TSYSCLK
8 x TSYSCLK
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
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25. Timers
Each MCU includes six counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and four are 16-bit auto-reload timer for use with the SMBus or for general purpose use.
These timers can be used to measure time intervals, count external events and generate periodic interrupt
requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2, 3, 4,
and 5 offer 16-bit and split 8-bit timer functionality with auto-reload.
Timer 0 and Timer 1 Modes:
Timer 2, 3, 4, and 5 Modes:
13-bit counter/timer
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0 only)
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 25.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2, 3, 4,
and 5 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock
source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
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SFR Definition 25.1. CKCON: Clock Control
Bit
7
6
5
4
3
2
Name
T3MH
T3ML
T2MH
T2ML
T1M
T0M
SCA[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0x8E; SFR Page = All Pages
Bit
Name
1
0
0
0
Function
7
T3MH
Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6
T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5
T2MH
Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4
T2ML
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3
T1
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2
T0
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0
SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
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SFR Definition 25.2. CKCON1: Clock Control 1
Bit
7
6
5
4
Name
3
2
1
0
T5MH
T5ML
T4MH
T4ML
Type
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE4; SFR Page = F
Bit
Name
Function
7:4
Unused
3
T5MH
Timer 5 High Byte Clock Select.
Selects the clock supplied to the Timer 5 high byte (split 8-bit timer mode only).
0: Timer 5 high byte uses the clock defined by the T5XCLK bit in TMR5CN.
1: Timer 5 high byte uses the system clock.
2
T5ML
Timer 5 Low Byte Clock Select.
Selects the clock supplied to Timer 5. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 5 low byte uses the clock defined by the T5XCLK bit in TMR5CN.
1: Timer 5 low byte uses the system clock.
1
T4MH
Timer 4 High Byte Clock Select.
Selects the clock supplied to the Timer 4 high byte (split 8-bit timer mode only).
0: Timer 4 high byte uses the clock defined by the T4XCLK bit in TMR4CN.
1: Timer 4 high byte uses the system clock.
0
T4ML
Timer 4 Low Byte Clock Select.
Selects the clock supplied to Timer 4. If Timer 4 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 4 low byte uses the clock defined by the T4XCLK bit in TMR4CN.
1: Timer 4 low byte uses the system clock.
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Read = 0000b; Write = don’t care
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25.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register; Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register. Both counter/timers operate
in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer
Mode register (TMOD). Each timer can be configured independently. Each operating mode is described
below.
25.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“20.1. Priority Crossbar Decoder” on page 148 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 25.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF. Setting GATE0 to 1 allows the timer
to be controlled by the external input signal INT0, facilitating pulse width measurements
TR0
GATE0
0
1
1
1
X
0
1
1
INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF.
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Figure 25.1. T0 Mode 0 Block Diagram
25.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 16.7 for details on the
external input signals INT0 and INT1).
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Figure 25.2. T0 Mode 2 Block Diagram
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals.
While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run
Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for
Mode 3.
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Figure 25.3. T0 Mode 3 Block Diagram
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SFR Definition 25.3. TCON: Timer Control
Bit
7
6
5
4
3
2
1
0
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x88; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
TF1
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6
TR1
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5
TF0
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
TR0
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3
IE1
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 16.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1
IE0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0
IT0
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 16.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
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SFR Definition 25.4. TMOD: Timer Mode
Bit
7
6
Name
GATE1
C/T1
Type
R/W
R/W
Reset
0
0
5
4
3
2
T1M[1:0]
GATE0
C/T0
T0M[1:0]
R/W
R/W
R/W
R/W
0
0
0
0
SFR Address = 0x89; SFR Page = All Pages
Bit
Name
7
GATE1
6
C/T1
5:4
T1M[1:0]
3
GATE0
2
C/T0
1:0
T0M[1:0]
232
1
0
0
0
Function
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 16.7).
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 16.7).
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.5. TL0: Timer 0 Low Byte
Bit
7
6
5
4
Name
TL0[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x8A; SFR Page = All Pages
Bit
Name
7:0
TL0[7:0]
3
2
1
0
0
0
0
0
3
2
1
0
0
0
0
0
Function
Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 25.6. TL1: Timer 1 Low Byte
Bit
7
6
5
4
Name
TL1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x8B; SFR Page = All Pages
Bit
Name
7:0
TL1[7:0]
Function
Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.1
233
C8051F388/9/A/B
SFR Definition 25.7. TH0: Timer 0 High Byte
Bit
7
6
5
4
Name
TH0[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x8C; SFR Page = All Pages
Bit
Name
7:0
TH0[7:0]
3
2
1
0
0
0
0
0
Function
Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 25.8. TH1: Timer 1 High Byte
Bit
7
6
5
4
Name
TH1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x8D; SFR Page = All Pages
Bit
Name
7:0
234
TH1[7:0]
3
2
1
0
0
0
0
0
Function
Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
Rev. 1.1
C8051F388/9/A/B
25.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or Low-Frequency Oscillator (LFO) Falling Edge capture mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3), T2CE
(TMR2CN.4) bits, and T2CSS (TMR2CN.1) bits.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
25.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 25.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
Figure 25.4. Timer 2 16-Bit Mode Block Diagram
Rev. 1.1
235
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25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
T2XCLK
0
0
0
1
TMR2H Clock Source
T2ML
T2XCLK
TMR2L Clock Source
SYSCLK / 12
0
0
SYSCLK / 12
1
External Clock / 8
0
1
External Clock / 8
X
SYSCLK
1
X
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
25.2.3. Timer 2 Capture Modes: LFO Falling Edge
When T2CE = 1, Timer 2 will operate in a special capture mode with the LFO (T2CSS is set to 1). The LFO
falling-edge capture mode can be used to calibrate the internal Low-Frequency Oscillator against the internal High-Frequency Oscillator or an external clock source. When T2SPLIT = 0, Timer 2 counts up and
overflows from 0xFFFF to 0x0000. Each time a capture event is received, the contents of the Timer 2 registers (TMR2H:TMR2L) are latched into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2
interrupt is generated if enabled.
236
Rev. 1.1
C8051F388/9/A/B
Figure 25.6. Timer 2 Capture Mode (T2SPLIT = 0)
When T2SPLIT = 1, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the contents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
Rev. 1.1
237
C8051F388/9/A/B
Figure 25.7. Timer 2 Capture Mode (T2SPLIT = 0)
238
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.9. TMR2CN: Timer 2 Control
Bit
7
6
5
4
3
2
1
0
Name
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2CSS
T2XCLK
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC8; SFR Page = 0; Bit-Addressable
Bit
Name
Function
7
TF2H
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5
TF2LEN
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4
TF2CEN
Timer 2 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 2 Low-Frequency Oscillator Capture Mode. If
TF2CEN is set and Timer 2 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL.
3
T2SPLIT
Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
2
TR2
1
T2CSS
Timer 2 Capture Source Select.
This bit selects the source of a capture event when bit T2CE is set to 1.
0: Reserved.
1: Capture source is falling edge of Low-Frequency Oscillator.
0
T2XCLK
Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between
the external clock and the system clock for either timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
Rev. 1.1
239
C8051F388/9/A/B
SFR Definition 25.10. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
Name
TMR2RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xCA; SFR Page = 0
Bit
Name
2
1
0
0
0
0
2
1
0
0
0
0
2
1
0
0
0
0
Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 25.11. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
3
Name
TMR2RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xCB; SFR Page = 0
Bit
Name
Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 25.12. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
Name
TMR2L[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xCC; SFR Page = 0
Bit
Name
7:0
240
0
Function
TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8bit mode, TMR2L contains the 8-bit low byte timer value.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.13. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
Name
TMR2H[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xCD; SFR Page = 0
Bit
Name
0
2
1
0
0
0
0
Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8bit mode, TMR2H contains the 8-bit high byte timer value.
Rev. 1.1
241
C8051F388/9/A/B
25.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or Low-Frequency Oscillator (LFO) Rising Edge capture mode. The Timer 3 operation mode is defined by the T3SPLIT (TMR3CN.3), T3CE
(TMR3CN.4) bits, and T3CSS (TMR3CN.1) bits.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
25.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 25.8,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow from 0xFF to 0x00.
Figure 25.8. Timer 3 16-Bit Mode Block Diagram
242
Rev. 1.1
C8051F388/9/A/B
25.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is 1 and T3CE = 0, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 25.9. TMR3RLL holds the reload value for TMR3L;
TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H.
TMR3L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
T3MH
T3XCLK
TMR3H Clock Source
T3ML
T3XCLK
TMR3L Clock Source
0
0
SYSCLK / 12
0
0
SYSCLK / 12
0
1
External Clock / 8
0
1
External Clock / 8
1
X
SYSCLK
1
X
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 25.9. Timer 3 8-Bit Mode Block Diagram
25.3.3. Timer 3 Capture Modes: LFO Falling Edge
When T3CE = 1, Timer 3 will operate in a special capture mode with the LFO (T3CSS is set to 1). The LFO
falling-edge capture mode can be used to calibrate the internal Low-Frequency Oscillator against the internal High-Frequency Oscillator or an external clock source. When T3SPLIT = 0, Timer 3 counts up and
overflows from 0xFFFF to 0x0000. Each time a capture event is received, the contents of the Timer 3 registers (TMR3H:TMR3L) are latched into the Timer 3 Reload registers (TMR3RLH:TMR3RLL). A Timer 3
interrupt is generated if enabled.
Rev. 1.1
243
C8051F388/9/A/B
Figure 25.10. Timer 3 Capture Mode (T3SPLIT = 0)
When T3SPLIT = 1, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the contents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
244
Rev. 1.1
C8051F388/9/A/B
Figure 25.11. Timer 3 Capture Mode (T3SPLIT = 0)
Rev. 1.1
245
C8051F388/9/A/B
SFR Definition 25.14. TMR3CN: Timer 3 Control
Bit
7
6
5
4
3
2
1
0
Name
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3CSS
T3XCLK
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x91; SFR Page = 0
Bit
Name
Function
7
TF3H
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF3L
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5
TF3LEN
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4
TF3CEN
Timer 3 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Low-Frequency Oscillator Capture Mode. If
TF3CEN is set and Timer 3 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL.
3
T3SPLIT
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
2
TR3
1
T3CSS
Timer 3 Capture Source Select.
This bit selects the source of a capture event when bit T2CE is set to 1.
0: Reserved.
1: Capture source is falling edge of Low-Frequency Oscillator.
0
T3XCLK
Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between
the external clock and the system clock for either timer.
0: Timer 3 clock is the system clock divided by 12.
1: Timer 3 clock is the external clock divided by 8 (synchronized with SYSCLK).
246
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.15. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
Name
TMR3RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0x92; SFR Page = 0
Bit
Name
2
1
0
0
0
0
2
1
0
0
0
0
2
1
0
0
0
0
Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 25.16. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
3
Name
TMR3RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0x93; SFR Page = 0
Bit
Name
Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
SFR Definition 25.17. TMR3L: Timer 3 Low Byte
Bit
7
6
5
4
3
Name
TMR3L[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x94; SFR Page = 0
Bit
Name
7:0
TMR3L[7:0]
0
Function
Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
Rev. 1.1
247
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SFR Definition 25.18. TMR3H Timer 3 High Byte
Bit
7
6
5
4
3
Name
TMR3H[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x95; SFR Page = 0
Bit
Name
7:0
248
TMR3H[7:0]
0
2
1
0
0
0
0
Function
Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
Rev. 1.1
C8051F388/9/A/B
25.4. Timer 4
Timer 4 is a 16-bit timer formed by two 8-bit SFRs: TMR4L (low byte) and TMR4H (high byte). Timer 4 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T4SPLIT bit (TMR4CN.3) defines
Timer 4 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system
clock.
25.4.1. 16-bit Timer with Auto-Reload
When T4SPLIT (TMR4CN.3) is zero, Timer 4 operates as a 16-bit timer with auto-reload. Timer 4 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 4
reload registers (TMR4RLH and TMR4RLL) is loaded into the Timer 4 register as shown in Figure 25.12,
and the Timer 4 High Byte Overflow Flag (TMR4CN.7) is set. If Timer 4 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 4 overflow. Additionally, if Timer 4 interrupts are enabled
and the TF4LEN bit is set (TMR4CN.5), an interrupt will be generated each time the lower 8 bits (TMR4L)
overflow from 0xFF to 0x00.
Figure 25.12. Timer 4 16-Bit Mode Block Diagram
Rev. 1.1
249
C8051F388/9/A/B
25.4.2. 8-bit Timers with Auto-Reload
When T4SPLIT is 1 and T4CE = 0, Timer 4 operates as two 8-bit timers (TMR4H and TMR4L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 25.13. TMR4RLL holds the reload value for
TMR4L; TMR4RLH holds the reload value for TMR4H. The TR4 bit in TMR4CN handles the run control for
TMR4H. TMR4L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 4 Clock Select bits (T4MH and T4ML in CKCON1) select either SYSCLK or
the clock defined by the Timer 4 External Clock Select bit (T4XCLK in TMR4CN), as follows:
T4MH
T4XCLK
TMR4H Clock Source
T4ML
T4XCLK
TMR4L Clock Source
0
0
SYSCLK/12
0
0
SYSCLK/12
0
1
External Clock/8
0
1
External Clock/8
1
X
SYSCLK
1
X
SYSCLK
The TF4H bit is set when TMR4H overflows from 0xFF to 0x00; the TF4L bit is set when TMR4L overflows
from 0xFF to 0x00. When Timer 4 interrupts are enabled, an interrupt is generated each time TMR4H overflows. If Timer 4 interrupts are enabled and TF4LEN (TMR4CN.5) is set, an interrupt is generated each
time either TMR4L or TMR4H overflows. When TF4LEN is enabled, software must check the TF4H and
TF4L flags to determine the source of the Timer 4 interrupt. The TF4H and TF4L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 25.13. Timer 4 8-Bit Mode Block Diagram
250
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.19. TMR4CN: Timer 4 Control
Bit
7
6
5
Name
TF4H
TF4L
TF4LEN
Type
R/W
R/W
R/W
Reset
0
0
0
4
3
2
T4SPLIT
TR4
R
R/W
R/W
R
R/W
0
0
0
0
0
SFR Address = 0x91; SFR Page = F
Bit
Name
1
0
T4XCLK
Function
7
TF4H
Timer 4 High Byte Overflow Flag.
Set by hardware when the Timer 4 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 4 overflows from 0xFFFF to 0x0000. When the
Timer 4 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 4
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF4L
Timer 4 Low Byte Overflow Flag.
Set by hardware when the Timer 4 low byte overflows from 0xFF to 0x00. TF4L will
be set when the low byte overflows regardless of the Timer 4 mode. This bit is not
automatically cleared by hardware.
5
TF4LEN
Timer 4 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 4 Low Byte interrupts. If Timer 4 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 4 overflows.
4
Unused
Read = 0b; Write = don’t care.
3
T4SPLIT
Timer 4 Split Mode Enable.
When this bit is set, Timer 4 operates as two 8-bit timers with auto-reload.
0: Timer 4 operates in 16-bit auto-reload mode.
1: Timer 4 operates as two 8-bit auto-reload timers.
2
TR4
1
Unused
Read = 0b; Write = don’t care.
0
T4XCLK
Timer 4 External Clock Select.
This bit selects the external clock source for Timer 4. However, the Timer 4 Clock
Select bits (T4MH and T4ML in register CKCON1) may still be used to select
between the external clock and the system clock for either timer.
0: Timer 4 clock is the system clock divided by 12.
1: Timer 4 clock is the external clock divided by 8 (synchronized with SYSCLK).
Timer 4 Run Control.
Timer 4 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR4H only; TMR4L is always enabled in split mode.
Rev. 1.1
251
C8051F388/9/A/B
SFR Definition 25.20. TMR4RLL: Timer 4 Reload Register Low Byte
Bit
7
6
5
4
3
Name
TMR4RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0x92; SFR Page = F
Bit
Name
2
1
0
0
0
0
2
1
0
0
0
0
2
1
0
0
0
0
Function
7:0 TMR4RLL[7:0] Timer 4 Reload Register Low Byte.
TMR4RLL holds the low byte of the reload value for Timer 4.
SFR Definition 25.21. TMR4RLH: Timer 4 Reload Register High Byte
Bit
7
6
5
4
3
Name
TMR4RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0x93; SFR Page = F
Bit
Name
Function
7:0 TMR4RLH[7:0] Timer 4 Reload Register High Byte.
TMR4RLH holds the high byte of the reload value for Timer 4.
SFR Definition 25.22. TMR4L: Timer 4 Low Byte
Bit
7
6
5
4
3
Name
TMR4L[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x94; SFR Page = F
Bit
Name
7:0
252
TMR4L[7:0]
0
Function
Timer 4 Low Byte.
In 16-bit mode, the TMR4L register contains the low byte of the 16-bit Timer 4. In
8-bit mode, TMR4L contains the 8-bit low byte timer value.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.23. TMR4H Timer 4 High Byte
Bit
7
6
5
4
3
Name
TMR4H[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x95; SFR Page = F
Bit
Name
7:0
TMR4H[7:0]
0
2
1
0
0
0
0
Function
Timer 4 High Byte.
In 16-bit mode, the TMR4H register contains the high byte of the 16-bit Timer 4. In
8-bit mode, TMR4H contains the 8-bit high byte timer value.
Rev. 1.1
253
C8051F388/9/A/B
25.5. Timer 5
Timer 5 is a 16-bit timer formed by two 8-bit SFRs: TMR5L (low byte) and TMR5H (high byte). Timer 5 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T5SPLIT bit (TMR5CN.3) defines
Timer 5 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system
clock.
25.5.1. 16-bit Timer with Auto-Reload
When T5SPLIT (TMR5CN.3) is zero, Timer 5 operates as a 16-bit timer with auto-reload. Timer 5 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 5
reload registers (TMR5RLH and TMR5RLL) is loaded into the Timer 5 register as shown in Figure 25.14,
and the Timer 5 High Byte Overflow Flag (TMR5CN.7) is set. If Timer 5 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 5 overflow. Additionally, if Timer 5 interrupts are enabled
and the TF5LEN bit is set (TMR5CN.5), an interrupt will be generated each time the lower 8 bits (TMR5L)
overflow from 0xFF to 0x00.
Figure 25.14. Timer 5 16-Bit Mode Block Diagram
254
Rev. 1.1
C8051F388/9/A/B
25.5.2. 8-bit Timers with Auto-Reload
When T5SPLIT is 1 and T5CE = 0, Timer 5 operates as two 8-bit timers (TMR5H and TMR5L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 25.15. TMR5RLL holds the reload value for
TMR5L; TMR5RLH holds the reload value for TMR5H. The TR5 bit in TMR5CN handles the run control for
TMR5H. TMR5L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 5 Clock Select bits (T5MH and T5ML in CKCON1) select either SYSCLK or
the clock defined by the Timer 5 External Clock Select bit (T5XCLK in TMR5CN), as follows:
T5MH
0
0
1
T5XCLK
0
1
X
TMR5H Clock Source
SYSCLK/12
External Clock/8
SYSCLK
T5ML
0
0
1
T5XCLK
0
1
X
TMR5L Clock Source
SYSCLK/12
External Clock/8
SYSCLK
The TF5H bit is set when TMR5H overflows from 0xFF to 0x00; the TF5L bit is set when TMR5L overflows
from 0xFF to 0x00. When Timer 5 interrupts are enabled, an interrupt is generated each time TMR5H overflows. If Timer 5 interrupts are enabled and TF5LEN (TMR5CN.5) is set, an interrupt is generated each
time either TMR5L or TMR5H overflows. When TF5LEN is enabled, software must check the TF5H and
TF5L flags to determine the source of the Timer 5 interrupt. The TF5H and TF5L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 25.15. Timer 5 8-Bit Mode Block Diagram
Rev. 1.1
255
C8051F388/9/A/B
SFR Definition 25.24. TMR5CN: Timer 5 Control
Bit
7
6
5
Name
TF5H
TF5L
TF5LEN
Type
R/W
R/W
R/W
Reset
0
0
0
4
3
2
T5SPLIT
TR5
R
R/W
R/W
R
R/W
0
0
0
0
0
SFR Address = 0xC8; SFR Page = F; Bit-Addressable
Bit
Name
1
0
T5XCLK
Function
7
TF5H
Timer 5 High Byte Overflow Flag.
Set by hardware when the Timer 5 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 5 overflows from 0xFFFF to 0x0000. When the
Timer 5 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 5
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF5L
Timer 5 Low Byte Overflow Flag.
Set by hardware when the Timer 5 low byte overflows from 0xFF to 0x00. TF5L will
be set when the low byte overflows regardless of the Timer 5 mode. This bit is not
automatically cleared by hardware.
5
TF5LEN
Timer 5 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 5 Low Byte interrupts. If Timer 5 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 5 overflows.
4
Unused
Read = 0b; Write = don’t care.
3
T5SPLIT
Timer 5 Split Mode Enable.
When this bit is set, Timer 5 operates as two 8-bit timers with auto-reload.
0: Timer 5 operates in 16-bit auto-reload mode.
1: Timer 5 operates as two 8-bit auto-reload timers.
2
TR5
1
Unused
Read = 0b; Write = don’t care.
0
T5XCLK
Timer 5 External Clock Select.
This bit selects the external clock source for Timer 5. However, the Timer 5 Clock
Select bits (T5MH and T5ML in register CKCON1) may still be used to select
between the external clock and the system clock for either timer.
0: Timer 5 clock is the system clock divided by 12.
1: Timer 5 clock is the external clock divided by 8 (synchronized with SYSCLK).
256
Timer 5 Run Control.
Timer 5 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR5H only; TMR5L is always enabled in split mode.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 25.25. TMR5RLL: Timer 5 Reload Register Low Byte
Bit
7
6
5
4
3
Name
TMR5RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xCA; SFR Page = F
Bit
Name
2
1
0
0
0
0
2
1
0
0
0
0
2
1
0
0
0
0
Function
7:0 TMR5RLL[7:0] Timer 5 Reload Register Low Byte.
TMR5RLL holds the low byte of the reload value for Timer 5.
SFR Definition 25.26. TMR5RLH: Timer 5 Reload Register High Byte
Bit
7
6
5
4
3
Name
TMR5RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Address = 0xCB; SFR Page = F
Bit
Name
Function
7:0 TMR5RLH[7:0] Timer 5 Reload Register High Byte.
TMR5RLH holds the high byte of the reload value for Timer 5.
SFR Definition 25.27. TMR5L: Timer 5 Low Byte
Bit
7
6
5
4
3
Name
TMR5L[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xCC; SFR Page = F
Bit
Name
7:0
TMR5L[7:0]
0
Function
Timer 5 Low Byte.
In 16-bit mode, the TMR5L register contains the low byte of the 16-bit Timer 5. In
8-bit mode, TMR5L contains the 8-bit low byte timer value.
Rev. 1.1
257
C8051F388/9/A/B
SFR Definition 25.28. TMR5H Timer 5 High Byte
Bit
7
6
5
4
3
Name
TMR5H[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xCD; SFR Page = F
Bit
Name
7:0
258
TMR5H[7:0]
0
2
1
0
0
0
0
Function
Timer 5 High Byte.
In 16-bit mode, the TMR5H register contains the high byte of the 16-bit Timer 5. In
8-bit mode, TMR5H contains the 8-bit high byte timer value.
Rev. 1.1
C8051F388/9/A/B
26. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section “26.3. Capture/Compare
Modules” on page 262). The external oscillator clock option is ideal for real-time clock (RTC) functionality,
allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 26.1
Important Note: The PCA Module 4 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 26.4 for details.
Figure 26.1. PCA Block Diagram
Rev. 1.1
259
C8051F388/9/A/B
26.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 26.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Table 26.1. PCA Timebase Input Options
CPS2
0
0
0
CPS1
0
0
1
CPS0
0
1
0
0
1
1
1
1
1
0
0
1
0
1
x
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
External oscillator source divided by 8*
Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
Figure 26.2. PCA Counter/Timer Block Diagram
260
Rev. 1.1
C8051F388/9/A/B
26.2. PCA0 Interrupt Sources
Figure 26.3 shows a diagram of the PCA interrupt tree. There are six independent event flags that can be
used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon
a 16-bit overflow of the PCA0 counter and the individual flags for each PCA channel (CCF0, CCF1, CCF2,
CCF3, and CCF4), which are set according to the operation mode of that module. These event flags are
always set when the trigger condition occurs. Each of these flags can be individually selected to generate
a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, and ECCFn for each CCFn).
PCA0 interrupts must be globally enabled before any individual interrupt sources are recognized by the
processor. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1.
Figure 26.3. PCA Interrupt Block Diagram
Rev. 1.1
261
C8051F388/9/A/B
26.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high-speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse
width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module and configure the module's mode
of operation. Table 26.2 summarizes the bit settings in the PCA0CPMn register used to select the PCA
capture/compare module’s operating mode. Setting the ECCFn bit in a PCA0CPMn register enables the
module's CCFn interrupt.
Table 26.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
Bit Number 7
X
X
X
X
X
X
0
1
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator
6
X
X
X
B
B
B
B
B
5
1
0
1
0
0
0
0
0
4
0
1
1
0
0
0
0
0
3
0
0
0
1
1
0
C
C
2
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
1
1
0
A
A
A
A
A
A
A
A
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = When set to 0, the digital comparator is off. For high speed and frequency output modes, the associated
pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
4. C = When set, a match event will cause the CCFn flag for the associated channel to be set.
262
Rev. 1.1
C8051F388/9/A/B
26.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused the capture.
Figure 26.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
Rev. 1.1
263
C8051F388/9/A/B
26.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 26.5. PCA Software Timer Mode Diagram
264
Rev. 1.1
C8051F388/9/A/B
26.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 26.6. PCA High-Speed Output Mode Diagram
Rev. 1.1
265
C8051F388/9/A/B
26.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 26.1.
F PCA
F CEXn = ------------------------------------------2  PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 26.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Figure 26.7. PCA Frequency Output Mode
266
Rev. 1.1
C8051F388/9/A/B
26.3.5. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag
for the module will be set each time an 8-bit comparator match (rising edge) occurs. The duty cycle for 8Bit PWM Mode is given in Equation 26.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 256 – PCA0CPHn 
Duty Cycle = ------------------------------------------------------256
Equation 26.2. 8-Bit PWM Duty Cycle
Using Equation 26.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 26.8. PCA 8-Bit PWM Mode Diagram
Rev. 1.1
267
C8051F388/9/A/B
26.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is
asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn
match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the
PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn
= 1) to help synchronize the capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for
the module will be set each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN
can be used to detect the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by
Equation 26.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 65536 – PCA0CPn 
Duty Cycle = --------------------------------------------------------65536
Equation 26.3. 16-Bit PWM Duty Cycle
Using Equation 26.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 26.9. PCA 16-Bit PWM Mode
268
Rev. 1.1
C8051F388/9/A/B
26.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Module 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and optionally re-configured and re-enabled if it is used in the system).
26.4.1. Watchdog Timer Operation
While the WDT is enabled:






PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 4 is forced into software timer mode.
Writes to the Module 4 mode register (PCA0CPM4) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is
loaded into PCA0CPH4 (See Figure 26.10).
Figure 26.10. PCA Module 4 with Watchdog Timer Enabled
Rev. 1.1
269
C8051F388/9/A/B
The 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first
PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given (in PCA clocks) by Equation 26.4, where PCA0L is the value of the PCA0L register at the
time of the update.
Offset =  256  PCA0CPL4  +  256 – PCA0L 
Equation 26.4. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.
26.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1.
2.
3.
4.
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL4 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
5. Enable the WDT by setting the WDTE bit to 1.
6. Reset the WDT timer by writing to PCA0CPH4.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 26.4, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 26.3 lists some example timeout intervals for typical system clocks.
270
Rev. 1.1
C8051F388/9/A/B
Table 26.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
PCA0CPL4
Timeout Interval (ms)
48,000,000
255
16.4
48,000,000
128
8.3
48,000,000
32
2.1
12,000,000
255
65.5
12,000,000
128
33.0
12,000,000
32
8.4
1,500,0002
255
524.3
1,500,0002
128
264.2
1,500,0002
32
67.6
32,768
255
24,000
32,768
128
12,094
32,768
32
3,094
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Rev. 1.1
271
C8051F388/9/A/B
26.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 26.1. PCA0CN: PCA Control
Bit
7
6
Name
CF
CR
Type
R/W
R/W
Reset
0
0
5
4
3
2
1
0
CCF4
CCF3
CCF2
CCF1
CCF0
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
SFR Address = 0xD8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5
Unused
2
CCF4
PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
1
CCF3
PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
2
CCF2
PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
1
CCF1
PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
0
CCF0
PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
272
Read = 0b, Write = Don't care.
Rev. 1.1
C8051F388/9/A/B
SFR Definition 26.2. PCA0MD: PCA Mode
Bit
7
6
5
4
Name
CIDL
WDTE
WDLCK
Type
R/W
R/W
R/W
R
Reset
0
1
0
0
SFR Address = 0xD9; SFR Page = All Pages
Bit
Name
3
0
2
1
0
CPS[2:0]
ECF
R/W
R/W
0
0
0
Function
7
CIDL
6
WDTE
5
WDLCK
Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
Unused
Read = 0b, Write = Don't care.
3:1
0
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Watchdog Timer Enable.
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
Rev. 1.1
273
C8051F388/9/A/B
SFR Definition 26.3. PCA0CPMn: PCA Capture/Compare Mode
Bit
7
6
5
4
3
2
1
0
Name
PWM16n
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Addresses: 0xDA (n = 0), 0xDB (n = 1), 0xDC (n = 2), 0xDD (n = 3), 0xDE (n = 4)
SFR Pages: All Pages (n = 0), All Pages (n = 1), All Pages (n = 2), All Pages (n = 3), All Pages (n = 4)
Bit
Name
Function
7
PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8-bit PWM selected.
1: 16-bit PWM selected.
6
ECOMn
Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5
CAPPn
Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4
CAPNn
Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3
MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2
TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode.
1
PWMn
Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n
is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is also set,
the module operates in Frequency Output Mode.
0
ECCFn
Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM4 register cannot be modified, and module 4 acts as the
watchdog timer. To change the contents of the PCA0CPM4 register or the function of module 4, the Watchdog
Timer must be disabled.
274
Rev. 1.1
C8051F388/9/A/B
SFR Definition 26.4. PCA0L: PCA Counter/Timer Low Byte
Bit
7
6
5
4
Name
3
2
1
0
PCA0[7:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF9; SFR Page = All Pages
Bit
Name
7:0
Function
PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 26.5. PCA0H: PCA Counter/Timer High Byte
Bit
7
6
5
Name
4
3
2
1
0
PCA0[15:8]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xFA; SFR Page = All Pages
Bit
Name
Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 26.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
Rev. 1.1
275
C8051F388/9/A/B
SFR Definition 26.6. PCA0CPLn: PCA Capture Module Low Byte
Bit
7
6
5
Name
4
3
2
1
0
PCA0CPn[7:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Addresses: 0xFB (n = 0), 0xE9 (n = 1), 0xEB (n = 2), 0xED (n = 3), 0xFD (n = 4)
SFR Pages: All Pages (n = 0), All Pages (n = 1), All Pages (n = 2), All Pages (n = 3), All Pages (n = 4)
Bit
Name
Function
7:0
PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 26.7. PCA0CPHn: PCA Capture Module High Byte
Bit
7
6
5
Name
4
3
2
1
0
PCA0CPn[15:8]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Addresses: 0xFC (n = 0), 0xEA (n = 1), 0xEC (n = 2), 0xEE (n = 3), 0xFE (n = 4)
SFR Pages: All Pages (n = 0), All Pages (n = 1), All Pages (n = 2), All Pages (n = 3), All Pages (n = 4)
Bit
Name
Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
Note: A write to this register will set the module’s ECOMn bit to a 1.
276
Rev. 1.1
C8051F388/9/A/B
27. C2 Interface
C8051F388/9/A/B devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between
the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
27.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 27.1. C2ADD: C2 Address
Bit
7
6
5
4
3
Name
C2ADD[7:0]
Type
R/W
Reset
Bit
0
0
0
0
Name
0
2
1
0
0
0
0
Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address
Description
0x00
Selects the Device ID register for Data Read instructions
0x01
Selects the Revision ID register for Data Read instructions
0x02
Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xAD
Selects the C2 Flash Programming Data register for Data
Read/Write instructions
Rev. 1.1
277
C8051F388/9/A/B
C2 Register Definition 27.2. DEVICEID: C2 Device ID
Bit
7
6
5
4
3
Name
DEVICEID[7:0]
Type
R/W
Reset
0
0
1
0
1
C2 Address: 0x00
Bit
Name
7:0
2
1
0
0
0
0
Function
DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x28 (C8051F388/9/A/B).
C2 Register Definition 27.3. REVID: C2 Revision ID
Bit
7
6
5
4
3
Name
REVID[7:0]
Type
R/W
Reset
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit
Name
7:0
278
Varies
2
1
0
Varies
Varies
Varies
Function
REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A
or Revision B.
Rev. 1.1
C8051F388/9/A/B
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control
Bit
7
6
5
4
3
Name
FPCTL[7:0]
Type
R/W
Reset
0
0
0
0
0
C2 Address: 0x02
Bit
Name
7:0
2
1
0
0
0
0
Function
FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data
Bit
7
6
5
4
3
Name
FPDAT[7:0]
Type
R/W
Reset
0
0
0
0
C2 Address: 0xAD
Bit
Name
7:0
0
2
1
0
0
0
0
Function
FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
Command
0x06
Flash Block Read
0x07
Flash Block Write
0x08
Flash Page Erase
0x03
Device Erase
Rev. 1.1
279
C8051F388/9/A/B
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 27.1.
Figure 27.1. Typical C2 Pin Sharing
The configuration in Figure 27.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
280
Rev. 1.1
C8051F388/9/A/B
28. Revision Specific Behavior
This chapter contains behavioral differences between the C8051F388/9/A/B hardware revisions and
behavior as stated in the data sheet.
28.1. Revision Identification
The Lot ID Code on the top side of the device package can be used for decoding device revision information. On C8051F388/9/A/B devices, the revision letter is the first letter of the Lot ID Code.
Figure 28.1, Figure 28.2, and Figure 28.3 show how to find the Lot ID Code on the top side of the device
package.
Figure 28.1. Device Package – TQFP48
Rev. 1.1
281
C8051F388/9/A/B
Figure 28.2. Device Package – LQFP32
Figure 28.3. Device Package – QFN32
282
Rev. 1.1
C8051F388/9/A/B
28.2. INT2 Pin Not Connected
Problem
The INT2 pin is non-functional on revision A C8051F388/9/A/B devices.
Impacts
The INT2 pin cannot be used to generate an interrupt.
Workaround
The /INT0 and /INT1 external interrupts are available on P0 and can still be used to generate an external pin
interrupt.
Resolution
This behavior has been corrected on revision B of this device.
Rev. 1.1
283
C8051F388/9/A/B
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.91









Updated “Power” on page 33 to mention the INT2 pin may be left floating if it’s not used.
Added INT2 to Table 5.1, “Absolute Maximum Ratings,” on page 34 and Table 5.3, “Port I/O DC
Electrical Characteristics,” on page 36.
Added INT2 to Table 3.1, “Pin Definitions for the C8051F388/9/A/B,” on page 21.
Updated Figure 3.1, Figure 3.4, and Figure 3.7 to show the INT2 pin.
Added “External Interrupt 2 (INT2)” on page 70.
Updated SFR Definition 9.1 to include INT2.
Added INT2 to Table 16.1, “Interrupt Summary,” on page 114.
Updated SFR Definition 16.5 and SFR Definition 16.6 to include INT2.
Updated “Internal Oscillator Suspend Mode” on page 139 to mention INT2.
Revision 0.91 to Revision 1.0


Updated Flash Endurance minimum specification, Flash Erase Cycle Time maximum specification, and
added a note to Table 5.6 on page 37.
Updated Figure 21.1 to show proper clock sources for SMBus0 and SMBus1.
Revision 1.0 to Revision 1.1


Added revision B.
Added “28. Revision Specific Behavior” .
284
Rev. 1.1
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