C8051F390-GDI Tested 50 MIPS 16 kB Flash Mixed-Signal MCU Die in Wafer Form

C8051F390-GDI
Tested 50 MIPS 16 kB Flash
Mixed-Signal MCU Die in Wafer Form
Analog Peripherals
- 10-Bit ADC
• Programmable throughput up to 500 ksps
• Up to 16 external inputs, programmable as single-
•
-
Two 10-Bit Current Output DACs
•
-
Supports output through resets for continuous 
operation
Comparator
•
•
-
ended or differential
Reference from on-chip voltage reference, VDD or
external VREF pin
Internal or external start of conversion sources
Programmable hysteresis and response time
Configurable as interrupt or reset source
Sectors
Digital Peripherals
- 21 Port I/O
- UART, 2 SMBus (I2C compatible), and SPI serial
Precision Temperature Sensor
•
Accurate to ±2 °C across temperature range with no
user calibration
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
Memory
- 1 kB internal data RAM (256 + 768)
- 16 kB Flash; In-system programmable in 512-byte
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping, 
inspect/modify memory and registers
Low Power
- 160 µA/MHz Active mode with 49 MHz internal 
precision oscillator
- 200 nA Stop mode current
Temperature Range
- –40 to +105 °C
Supply Voltage 1.8 to 3.6 V
- Built-in voltage supply monitor
ports
Six general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules and PWM functionality
Clock Sources
- 49 MHz ±2% precision internal oscillator
• Supports crystal-less UART operation
• Low-power suspend mode with fast wake time
- 80 kHz low-frequency, low-power oscillator
- External oscillator: Crystal, RC, C, or CMOS clock
- Can switch between clock sources on-the-fly; useful
in power saving modes
Full Technical Data Sheet
- C8051F39x-37x
ANALOG
PERIPHERALS
A
M
U
X
-
10-bit
500 ksps
ADC
10-bit
10-bit
Current
Current
DAC
DAC
+
VREF
–
Precision
Temp Sensor
VOLTAGE
COMPARATOR
49 MHz PRECISION INTERNAL
OSCILLATOR
DIGITAL I/O
UART
SMBus0
SMBus1
SPI
PCA0
PCA1
PCA2
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Port 0
CROSSBAR
•
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
Port 1
P2.0–
P2.4
80 KHz LOW FREQUENCY
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB
8051 CPU
1024 B
ISP FLASH
(50 MIPS)
SRAM
FLEXIBLE
DEBUG
POR WDT
INTERRUPTS
CIRCUITRY
Rev. 1.0 8/13
Copyright © 2013 by Silicon Laboratories
C8051F390-GDI
49 MHz Internal Oscillator
80 kHz Internal Oscillator
SMBus/I2C
UART
SPI
Timers (16-bit)
PWM / PCA Channels
Precision Temperature Sensor
Voltage Reference
IDAC Output Channels
Analog Comparators
C8051F390-A-G1DI 50 16
1
1
1
2
1
1
6
3
21 20
2
2
2
1
28.5433 mil /
725 µm
(No backgrind)
C8051F390-A-GDI
1
1
1
2
1
1
6
3
21 20
2
2
2
1
12 mil
(backgrind)
2
50 16
Rev. 1.0
Wafer Thickness
ADC Input Channels
Digital Port I/Os
Flash Memory (kBytes)
MIPS (Peak)
RAM (kBytes)
Ordering Part Number
C8051F390-GDI
1. Ordering Information
Table 1.1. Product Selection Guide
C8051F390-GDI
2. Pin Definitions
Table 2.1 lists the pin definitions for the C8051F390-GDI. For a full description of each pin, refer to the
C8051F39x-C8051F37x data sheet.
Table 2.1. Pin Definitions for the C8051F390-GDI
Name
Physical Pad
Number
VDD
5
Power Supply Voltage.
VDD
6
Power Supply Voltage.
GND
3
Ground.
This ground connection is required. The center pad may optionally
be connected to ground also.
GND
4
Ground.
This ground connection is required. The center pad may optionally
be connected to ground also.
RST/
7
C2CK
P2.4 /
8
C2D
P0.0/
2
VREF
P0.1
1
XTAL1
P0.3/
XTAL2
Device Reset. Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin low
for at least 10 µs.
D I/O
Clock signal for the C2 Debug Interface.
D I/O
P2.4.
D I/O
Bi-directional data signal for the C2 Debug Interface.
D I/O or Port 0.0.
A In
IDA0 Output.
D I/O or Port 0.2.
A In
A In
32
External VREF input.
D I/O or Port 0.1.
A In
A Out
33
Description
D I/O
A In
IDA0
P0.2/
Type
External Clock Input. This pin is the external oscillator return for a
crystal or resonator.
D I/O or Port 0.3.
A In
A I/O or External Clock Output. For an external crystal or resonator, this pin
is the excitation driver. This pin is the external clock input for
D In
CMOS, capacitor, or RC oscillator configurations.
Rev. 1.0
3
C8051F390-GDI
Table 2.1. Pin Definitions for the C8051F390-GDI
Name
Physical Pad
Number
P0.4
31
D I/O or Port 0.4.
A In
P0.5
30
D I/O or Port 0.5.
A In
P0.6/
29
D I/O or Port 0.6.
A In
CNVSTR
D In
Description
ADC0 External Convert Start or IDA0 Update Source Input.
P0.7
28
D I/O or Port 0.7.
A In
P1.0
26
D I/O or Port 1.0.
A In
P1.1
25
D I/O or Port 1.1.
A In
P1.2
24
D I/O or Port 1.2.
A In
IDA1
4
Type
A Out
IDA1 Output.
P1.3
23
D I/O or Port 1.3.
A In
P1.4
22
D I/O or Port 1.4.
A In
P1.5
20
D I/O or Port 1.5.
A In
P1.6
19
D I/O or Port 1.6.
A In
P1.7
18
D I/O or Port 1.7.
A In
P2.0
17
D I/O or Port 2.0.
A In
P2.1
14
D I/O or Port 2.1.
A In
P2.2
13
D I/O or Port 2.2.
A In
P2.3
9
D I/O or Port 2.3.
A In
Rev. 1.0
C8051F390-GDI
3. Bonding Instructions
Figure 3.1. Die Bonding Example (QFN-24)
Table 3.1. Bond Pad Coordinates (Relative to Center of Die)
Physical Pad
Number
Example Package
Pin
Number
(QFN-24)
Package Pin Name
Physical Pad X
(µm)
Physical Pad Y
(µm)
1
1
P0.1/IDA0
–696
–777
2
2
P0.0/VREF
–596
–777
3
3
GND
–31
–777
4
3
GND
57
–777
5
4
VDD
510
–777
6
4
VDD
602
–777
*Note: Pins marked “Reserved” should not be connected.
Rev. 1.0
5
C8051F390-GDI
Table 3.1. Bond Pad Coordinates (Relative to Center of Die) (Continued)
Physical Pad
Number
Example Package
Pin
Number
(QFN-24)
Package Pin Name
Physical Pad X
(µm)
Physical Pad Y
(µm)
7
5
RST/C2CK
698
–777
8
6
P2.4/C2D
877
–596
9
7
P2.3
877
–496
10
Reserved
877
–407
11
Reserved
877
–332
12
Reserved
877
–257
13
8
P2.2
877
–167
14
9
P2.1
877
–67
15
Reserved
877
38
16
Reserved
877
129
17
10
P2.0
877
235
18
11
P1.7
877
335
19
12
P1.6
877
435
20
13
P1.5
877
535
21
Reserved
702
777
22
14
P1.4
606
777
23
15
P1.3
506
777
24
16
P1.2/IDA1
406
777
25
17
P1.1
–506
777
26
18
P1.0
–606
777
27
Reserved
–702
777
28
19
P0.7
–877
592
29
20
P0.6/CNVSTR
–877
492
30
21
P0.5
–877
–21
31
22
P0.4
–877
–121
32
23
P0.3/XTAL2
–877
–221
33
24
P0.2/XTAL1
–877
–499
34
Reserved
–877
–599
*Note: Pins marked “Reserved” should not be connected.
6
Rev. 1.0
C8051F390-GDI
Table 3.2. Wafer and Die Information
C8051F390A
Wafer ID
8 in
Wafer Dimensions
1.72 mm x 1.92 mm
Die Dimensions
Wafer Thickness (No backgrind)
Wafer Thickness (With backgrind)
28.5433 mil ±1 mil
(725 µm)
12 mil ±1 mil
Wafer Identification
Notch
Scribe Line Width
60 µm
Contact Sales For Info
Die Per Wafer*
Passivation
Standard
Wafer Packaging Detail
Wafer Jar
Bond Pad Dimensions
60 µm x 60 µm
Maximum Processing Temperature
250 °C
Electronic Die Map Format
.txt
Bond Pad Pitch Minimum
75 µm
*Note: This is the Expected Known Good Die yielded per wafer and
represents the batch order quantity (one wafer).
Rev. 1.0
7
C8051F390-GDI
4. Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.
Wafers
may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
must be stored at a temperature of 18–24 °C.
Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%.
Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
Wafers
8
Rev. 1.0
C8051F390-GDI
5. Failure Analysis (FA) Guidelines
Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in
wafer form.
In
order to conduct failure analysis on a device in a customer-provided package, Silicon
Laboratories must be provided with die assembled in an industry standard package that is pin
compatible with existing packages Silicon Laboratories offers for the device. Initial response time
for FA requests that meet this requirements will follow the standard FA guidelines for packaged
parts.
If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole
wafer. Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or
are on tape. Initial response time for FA requests that meet this requirements will be 3 weeks.
Rev. 1.0
9
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
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