EFM8SB1 Data Sheet

EFM8 Sleepy Bee Family
EFM8SB1 Data Sheet
The EFM8SB1, part of the Sleepy Bee family of MCUs, is the
world’s most energy friendly 8-bit microcontrollers with a comprehensive feature set in small packages.
ENERGY FRIENDLY FEATURES
• Lowest MCU sleep current with supply
brownout (50 nA)
These devices offer lowest power consumption by combining innovative low energy techniques and short wakeup times from energy saving modes into small packages, making
them well-suited for any battery operated applications. With an efficient 8051 core, 14
high-quality capacitive sense channels, and precision analog, the EFM8SB1 family is also optimal for embedded applications.
• Lowest MCU active current (150 μA / MHz
at 24.5 MHz)
• Lowest MCU wake on touch average
current (< 1 μA)
• Lowest sleep current using internal RTC
and supply brownout (< 300 nA)
EFM8SB1 applications include the following:
Core / Memory
RAM Memory
(up to 512 bytes)
(up to 8 KB)
• Integrated LDO to maintain ultra-low active
current at all voltages
Clock Management
CIP-51 8051 Core
(25 MHz)
Flash Program
Memory
• Ultra-fast wake up for digital and analog
peripherals (< 2 μs)
• Instrumentation panels
• Battery-operated consumer electronics
• Touch pads / key pads
• Wearables
Debug Interface
with C2
Energy Management
External
Oscillator
Low Power 20 MHz
RC Oscillator
Low Frequency
RC Oscillator
High Frequency
24.5 MHz RC
Oscillator
Internal LDO
Regulator
Power-On Reset
Brown-Out Detector
External 32 kHz RTC Oscillator
8-bit SFR bus
Serial Interfaces
UART
SPI
I2C / SMBus
I/O Ports
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
Timers and Triggers
Timers
0/1/2/3
Watchdog
Timer
PCA/PWM
Real Time
Clock
Analog Interfaces
ADC
Comparator 0
Internal Current
Reference
Internal Voltage
Reference
Security
16-bit CRC
Capacitive Sense
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
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EFM8SB1 Data Sheet
Feature List
1. Feature List
The EFM8SB1 highlighted features are listed below.
• Core:
• Pipelined CIP-51 Core
• Fully compatible with standard 8051 instruction set
• 70% of instructions execute in 1-2 clock cycles
• 25 MHz maximum operating frequency
• Memory:
• Up to 8 kB flash memory, in-system re-programmable
from firmware.
• Up to 512 bytes RAM (including 256 bytes standard 8051
RAM and 256 bytes on-chip XRAM)
• Power:
• Internal LDO regulator for CPU core voltage
• Power-on reset circuit and brownout detectors
• I/O: Up to 17 total multifunction I/O pins:
• Flexible peripheral crossbar for peripheral routing
• 5 mA source, 12.5 mA sink allows direct drive of LEDs
• Clock Sources:
• Internal 20 MHz low power oscillator with ±10% accuracy
• Internal 24.5 MHz precision oscillator with ±2% accuracy
• Internal 16.4 kHz low-frequency oscillator or RTC 32 kHz
crystal (RTC crystal not available on CSP16 packages)
• External crystal, RC, C, and CMOS clock options
• Timers/Counters and PWM:
• 32-bit Real Time Clock (RTC)
• 3-channel Programmable Counter Array (PCA) supporting
PWM, capture/compare, and frequency output modes with
watchdog timer function
• 4 x 16-bit general-purpose timers
• Communications and Digital Peripherals:
• UART
• SPI™ Master / Slave
• SMBus™ / I2C™ Master / Slave
• 16-bit CRC unit, supporting automatic CRC of flash at 256byte boundaries
• Analog:
• Capacitive Sense (CS0)
• Programmable current reference (IREF0)
• 12-Bit Analog-to-Digital Converter (ADC0)
• 1 x Low-current analog comparator
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• Pre-loaded UART bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.8 to 3.6 V
• QSOP24, QFN24, QFN20, and CSP16 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8SB1 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field upgrades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Each device is specified for 1.8 to 3.6 V operation and is available in 16-pin CSP, 20-pin QFN, 24-pin QFN, or 24-pin
QSOP packages. All package options are lead-free and RoHS compliant.
Note: CSP devices can be handled and soldered using industry standard surface mount assembly techniques. However, because CSP
devices are essentially a piece of silicon and are not encapsulated in plastic, they are susceptible to mechanical damage and may be
sensitive to light. When CSP packages must be used in an environment exposed to light, it may be necessary to cover the top and
sides with an opaque material.
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EFM8SB1 Data Sheet
Ordering Information
2. Ordering Information
EFM8 SB1 0 F 8 G – A – QSOP24 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 8 KB
Memory Type (Flash)
Family Feature Set
Sleepy Bee 1 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8SB1 Part Numbering
All EFM8SB1 family members have the following features:
• CIP-51 Core running up to 25 MHz
• Three Internal Oscillators (24.5 MHz, 20 MHz, and 16 kHz)
• SMBus / I2C
• SPI
• UART
• 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• 4 16-bit Timers
• Analog Comparator
• 6-bit current sourc reference
• 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor
• 16-bit CRC Unit
• Pre-loaded UART bootloader
In addition to these features, each part number in the EFM8SB1 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Temperature Range
Package
14
Yes
-40 to +85 C
QSOP24
EFM8SB10F8G-A-QFN24
8
512
17
10
14
Yes
-40 to +85 C
QFN24
EFM8SB10F8G-A-QFN20
8
512
16
9
13
Yes
-40 to +85 C
QFN20
EFM8SB10F8G-A-CSP16
8
512
13
9
12
Yes
-40 to +85 C
CSP16
EFM8SB10F4G-A-QFN20
4
512
16
9
13
Yes
-40 to +85 C
QFN20
EFM8SB10F2G-A-QFN20
2
256
16
9
13
Yes
-40 to +85 C
QFN20
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(RoHS Compliant)
Capacitive
10
Pb-free
ADC0 Channels
17
Touch Inputs
Digital Port
512
I/Os (Total)
RAM (Bytes)
8
Number
EFM8SB10F8G-A-QSOP24
Ordering Part
Flash Memory (kB)
Table 2.1. Product Selection Guide
Rev. 1.2 | 2
EFM8SB1 Data Sheet
System Overview
3. System Overview
3.1 Introduction
CIP-51 8051 Controller
Core
Power On
Reset/PMU
Wake
Reset
C2CK/RSTb
Debug /
Programming
Hardware
Port I/O Configuration
Digital Peripherals
8/4/2 KB ISP Flash
Program Memory
UART
256 Byte SRAM
Timers 0,
1, 2, 3
256 Byte XRAM
Priority
Crossbar
Decoder
PCA/WDT
SMBus
C2D
SPI
VDD
VREG
SYSCLK
P0.n
Port 1
Drivers
P1.n
Port 2
Driver
P2.n
CRC
Digital
Power
System Clock
Configuration
Port 0
Drivers
Crossbar Control
SFR
Bus
Analog Peripherals
GND
Low Power
20 MHz
Oscillator
XTAL1
XTAL2
External
Oscillator
Circuit
6-bit
IREF
IREF0
Internal
External
VREF
VREF
12-bit
ADC
AMUX
Precision
24.5 MHz
Oscillator
14-Channel
Capacitance
To Digital
Converter
VDD
VREF
Temp
Sensor
GND
XTAL3
XTAL4
RTC
Oscillator
+
Comparator
Figure 3.1. Detailed EFM8SB1 Block Diagram
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EFM8SB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devices without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Details
Mode Entry
Wake-Up Sources
Normal
Core and all peripherals clocked and fully operational
—
—
Set IDLE bit in PCON0
Any interrupt
Idle
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend
• Core and digital peripherals halted
• Internal oscillators disabled
• Code resumes execution on wake event
Stop
• All internal power nets shut down
• Pins retain state
• Exit on any reset source
Sleep
•
•
•
•
•
Most internal power nets shut down
Select circuits remain powered
Pins retain state
All RAM and SFRs retain state
Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0 or LPOSC0
2. Set SUSPEND bit in
PMU0CF
Set STOP bit in PCON0
1. Disable unused analog peripherals
2. Set SLEEP bit in
PMU0CF
•
•
•
•
•
RTC0 Alarm Event
RTC0 Fail Event
CS0 Interrupt
Port Match Event
Comparator 0 Rising
Edge
Any reset source
•
•
•
•
RTC0 Alarm Event
RTC0 Fail Event
Port Match Event
Comparator 0 Rising
Edge
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.
•
•
•
•
•
Up to 17 multi-functions I/O pins, supporting digital and analog functions.
Flexible priority crossbar decoder for digital peripheral assignment.
Two drive strength settings for each pin.
Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 20 MHz low power oscillator divided by 8.
•
•
•
•
•
•
Provides clock to core and peripherals.
20 MHz low power oscillator (LPOSC0), accurate to ±10% over supply and temperature corners.
24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
16.4 kHz low-frequency oscillator (LFOSC0) or external RTC 32 kHz crystal.
External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).
Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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EFM8SB1 Data Sheet
System Overview
3.5 Counters/Timers and PWM
Real Time Clock (RTC0)
The RTC is an ultra low power, 36 hour 32-bit independent time-keeping Real Time Clock with alarm. The RTC has a dedicated 32 kHz
oscillator. No external resistor or loading capacitors are required, and a missing clock detector features alerts the system if the external
crystal fails. The on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystals.
The RTC module includes the following features:
• Up to 36 hours (32-bit) of independent time keeping.
• Support for internal 16.4 kHz low frequency oscillator (LFOSC0) or external 32 kHz crystal (crystal not available on CSP16 packages).
• Internal crystal loading capacitors with 16 levels.
• Operation in the lowest power mode and across the full supported voltage range.
• Alarm and oscillator failure events to wake from the lowest power mode or reset the device.
• Buffered clock output available for other system devices even in the lowest power mode.
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
•
•
•
•
•
•
•
•
•
16-bit time base.
Programmable clock divisor and clock source selection.
Up to three independently-configurable channels
8, 9, 10, 11 and 16-bit PWM modes (edge-aligned operation).
Frequency output mode.
Capture on rising, falling or any edge.
Compare function for arbitrary waveform generation.
Software timer (internal compare) mode.
Integrated watchdog timer.
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2 and Timer 3 are 16-bit timers including the following features:
• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• Comparator 0 or RTC0 capture (Timer 2)
• RTC0 or EXTCLK/8 capture (Timer 3)
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EFM8SB1 Data Sheet
System Overview
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software. The state of the RSTb pin is unaffected by this reset.
The Watchdog Timer integrated in the PCA0 peripheral has the following features:
• Programmable timeout interval
• Runs from the selected PCA clock source
• Automatically enabled after any system reset
3.6 Communications and Other Digital Peripherals
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 8- or 9-bit data
• Automatic start and stop generation
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
The SPI module includes the following features:
• Supports 3- or 4-wire operation in master or slave modes.
• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.
• Support for four clock phase and polarity options.
• 8-bit dedicated clock clock rate generator.
• Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
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EFM8SB1 Data Sheet
System Overview
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
3.7 Analog
Capacitive Sense (CS0)
The Capacitive Sense subsystem uses a capacitance-to-digital circuit to determine the capacitance on a port pin. The module can take
measurements from different port pins using the module’s analog multiplexer. The module can be configured to take measurements on
one port pin, a group of port pins one-by-one using auto-scan, or the total capacitance on multiple channels together. A selectable gain
circuit allows the designer to adjust the maximum allowable capacitance. An accumulator is also included, which can be configured to
average multiple conversions on an input channel. Interrupts can be generated when the CS0 peripheral completes a conversion or
when the measured value crosses a configurable threshold.
The Capacitive Sense module includes the following features:
• Measure multiple pins one-by-one using auto-scan or total capacitance on multiple channels together.
• Configurable input gain.
• Hardware auto-accumulate and average.
• Multiple internal start-of-conversion sources.
• Operational in Suspend when all other clocks are disabled.
• Interrupts available at the end of a conversion or when the measured value crosses a configurable threshold.
Programmable Current Reference (IREF0)
The programmable current reference (IREF0) module enables current source or sink with two output current settings: Low Power Mode
and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 µA steps) and the maximum current output in
High Current Mode is 504 µA (8 µA steps).
The IREF module includes the following features:
• Capable of sourcing or sinking current in programmable steps.
• Two operational modes: Low Power Mode and High Current Mode.
• Fine-tuning mode for higher output precision available in conjunction with the PCA0 module.
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EFM8SB1 Data Sheet
System Overview
12-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a programmable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external
reference sources.
•
•
•
•
•
•
•
•
•
•
•
Up to 10 external inputs.
Single-ended 12-bit and 10-bit modes.
Supports an output update rate of 75 ksps samples per second in 12-bit mode or 300 ksps samples per second in 10-bit mode.
Operation in low power modes at lower conversion speeds.
Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.
Output data window comparator allows automatic range checking.
Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time.
Conversion complete and window compare interrupts supported.
Flexible output data formatting.
Includes an internal 1.65 V fast-settling reference and support for external reference.
Integrated temperature sensor.
Low Current Comparator (CMP0)
An analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator module includes the following features:
• Input options in addition to the pins:
• Capacitive Sense Comparator output.
• VDD.
• VDD divided by 2.
• Internal connection to LDO output.
• Direct connection to GND.
• Synchronous and asynchronous outputs can be routed to pins via crossbar.
• Programmable hysteresis between 0 and ±20 mV.
• Programmable response time.
• Interrupts generated on rising, falling, or both edges.
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EFM8SB1 Data Sheet
System Overview
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include the following:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• RTC0 alarm or oscillator failure
3.9 Debugging
The EFM8SB1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
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EFM8SB1 Data Sheet
System Overview
3.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in the last page of flash and can be erased if it is
not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the bootloader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The bootloader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
0xFFFF
Reserved
0x1FFF
Lock Byte
0x1FFE
Bootloader Signature Byte
0x1FFD
Security Page
512 Bytes
0x1E00
Bootloader
0x2000
Bootloader Vector
8 KB Flash
(16 x 512 Byte pages)
0x0000
Reset Vector
Figure 3.2. Flash Memory Map with Bootloader—8 kB Devices
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EFM8SB1 Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page
11, unless stated otherwise.
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Operating Supply Voltage on VDD
VDD
Minimum RAM Data Retention
Voltage on VDD1
VRAM
System Clock Frequency
fSYSCLK
Operating Ambient Temperature
TA
Test Condition
Min
Typ
Max
Unit
1.8
2.4
3.6
V
Not in Sleep Mode
—
1.4
—
V
Sleep Mode
—
0.3
0.5
V
0
—
25
MHz
–40
—
85
°C
Min
Typ
Max
Units
Note:
1. All voltages with respect to GND.
Table 4.2. Power Consumption
Parameter
Symbol
Conditions
IDD
VDD = 1.8–3.6 V, fSYSCLK
= 24.5 MHz
—
3.6
4.5
mA
VDD = 1.8–3.6 V, fSYSCLK = 20
MHz
—
3.1
—
mA
VDD = 1.8–3.6 V, fSYSCLK = 32.768
kHz
—
84
—
µA
VDD = 1.8–3.6 V, T = 25 °C,
fSYSCLK < 14 MHz
—
174
—
µA/MHz
VDD = 1.8–3.6 V, T = 25 °C,
fSYSCLK > 14 MHz
—
88
—
µA/MHz
VDD = 1.8–3.6 V, fSYSCLK = 24.5
MHz
—
1.8
3.0
mA
VDD = 1.8–3.6 V, fSYSCLK = 20
MHz
—
1.4
—
mA
VDD = 1.8–3.6 V, fSYSCLK = 32.768
kHz
—
82
—
µA
Idle Mode Supply Current Frequen- IDDFREQ
cy Sensitivity1 ,6
VDD = 1.8–3.6 V, T = 25 °C
—
67
—
µA/MHz
Suspend Mode Supply Current
IDD
VDD = 1.8–3.6 V
—
77
—
µA
Sleep Mode Supply Current with
RTC running from 32.768 kHz
crystal
IDD
1.8 V, T = 25 °C
—
0.60
—
µA
3.6 V, T = 25 °C
—
0.80
—
µA
1.8 V, T = 85 °C
—
0.80
—
µA
3.6 V, T = 85 °C
—
1.00
—
µA
Digital Supply Current
Normal Mode supply current - Full
speed with code executing from
flash 3 , 4 , 5
Normal Mode supply current frequency sensitivity1, 3, 5
Idle Mode supply current - Core
halted with peripherals running4 , 6
IDDFREQ
IDD
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Conditions
Sleep Mode Supply Current with
RTC running from internal LFO
IDD
Sleep Mode Supply Current (RTC
off)
IDD
Min
Typ
Max
Units
1.8 V, T = 25 °C
—
0.30
—
µA
3.6 V, T = 25 °C
—
0.50
—
µA
1.8 V, T = 85 °C
—
0.50
—
µA
3.6 V, T = 85 °C
—
0.80
—
µA
1.8 V, T = 25 °C
—
0.05
—
µA
3.6 V, T = 25 °C
—
0.08
—
µA
1.8 V, T = 85 °C
—
0.20
—
µA
3.6 V, T = 85 °C
—
0.28
—
µA
—
7
—
µA
VDD Monitor Supply Current
IVMON
Oscillator Supply Current
IHFOSC0
25 °C
—
300
—
µA
ADC0 Always-on Power Supply
Current7
IADC
300 ksps, 10-bit conversions or
—
740
—
µA
—
400
—
µA
CPMD = 11
—
0.4
—
µA
CPMD = 10
—
2.6
—
µA
CPMD = 01
—
8.8
—
µA
CPMD = 00
—
23
—
µA
Normal Power Mode
—
260
—
µA
Low Power Mode
—
140
—
µA
—
35
—
µA
CS module bias current, 25 °C
—
50
60
µA
CS module alone, maximum code
output, 25 °C
—
90
125
µA
Wake-on-CS threshold (suspend
mode with regulator and CS module on)9
—
130
180
µA
75 ksps, 12-bit conversions
Normal bias settings
VDD = 3.0 V
150 ksps, 10-bit conversions or
37.5 ksps 12-bit conversions
Low power bias settings
VDD = 3.0 V
Comparator 0 (CMP0) Supply Cur- ICMP
rent
Internal Fast-Settling 1.65V ADC0
Reference, Always-on8
IVREFFS
Temp sensor Supply Current
ITSENSE
Capacitive Sense Module (CS0)
Supply Current
ICS0
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Programmable Current Reference
(IREF0) Supply Current10
IIREF0
Current Source, Either Power
Mode, Any Output Code
—
10
—
µA
Low Power Mode, Current Sink
—
1
—
µA
—
11
—
µA
—
12
—
µA
—
81
—
µA
IREF0DAT = 000001
Low Power Mode, Current Sink
IREF0DAT = 111111
High Current Mode, Current Sink
IREF0DAT = 000001
High Current Mode, Current Sink
IREF0DAT = 111111
Note:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the
flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and
the number of flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop
straddles a 64-byte flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries.
4. Includes supply current from regulator and oscillator source (24.5 MHz high-frequency oscillator, 20 MHz low-power oscillator, 1
MHz external oscillator, or 32.768 kHz RTC oscillator).
5. IDD can be estimated for frequencies < 14 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 84 µA. When using these numbers to estimate IDD for > 14 MHz, the estimate should
be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V;
F = 20 MHz, IDD = 3.6 mA – (25 MHz – 20 MHz) x 0.088 mA/MHz = 3.16 mA assuming the same oscillator setting.
6. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 1.75 mA – (25 MHz – 5 MHz) x 0.067 mA/MHz = 0.41 mA.
7. ADC0 always-on power excludes internal reference supply current.
8. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
9. Includes only current from regulator, CS module, and MCU in suspend mode.
10. IREF0 supply current only. Does not include current sourced or sunk from IREF0 output pin.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Supply Monitor Threshold
VVDDM
Reset Trigger
1.7
1.75
1.8
V
VWARN
Early Warning
1.8
1.85
1.9
V
—
300
—
ns
Rising Voltage on VDD
—
1.75
—
V
Falling Voltage on VDD
0.45
0.7
1.0
V
VDD Supply Monitor Turn-On Time tMON
Power-On Reset (POR) Monitor
Threshold
VPOR
VDD Ramp Time
tRMP
Time to VDD ≥ 1.8 V
—
—
3
ms
Reset Delay
tRST
Time between release of reset
source and code execution
—
10
—
µs
RST Low Time to Generate Reset
tRSTL
15
—
—
µs
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD
FSYSCLK > 1 MHz
100
650
1000
µs
Missing Clock Detector Trigger
Frequency
FMCD
—
7
10
kHz
Min
Typ
Max
Units
Table 4.4. Flash Memory
Parameter
Symbol
Test Condition
Write Time1
tWRITE
One Byte
57
64
71
µs
Erase Time1
tERASE
One Page
28
32
36
ms
Endurance (Write/Erase Cycles)
NWE
20 k
100 k
—
Cycles
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Table 4.5. Power Management Timing
Parameter
Symbol
Idle Mode Wake-up Time
tIDLEWK
Suspend Mode Wake-up Time
Sleep Mode Wake-up Time
Test Condition
tSUS-
CLKDIV = 0x00
PENDWK
Low Power or Precision Osc.
tSLEEPWK
Min
Typ
Max
Units
2
—
3
SYSCLKs
—
400
—
ns
—
2
—
µs
Min
Typ
Max
Unit
Table 4.6. Internal Oscillators
Parameter
Symbol
Test Condition
High Frequency Oscillator 0 (24.5 MHz)
Oscillator Frequency
fHFOSC0
Full Temperature and Supply
Range
24
24.5
25
MHz
fLPOSC
Full Temperature and Supply
Range
18
20
22
MHz
13.1
16.4
19.7
kHz
Min
Typ
Max
Unit
0.02
—
25
MHz
Low Power Oscillator (20 MHz)
Oscillator Frequency
Low Frequency Oscillator (16.4 kHz internal RTC oscillator)
Oscillator Frequency
fLFOSC
Full Temperature and Supply
Range
Table 4.7. Crystal Oscillator
Parameter
Symbol
Crystal Frequency
fXTAL
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Crystal Drive Current
IXTAL
XFCN = 0
—
0.5
—
µA
XFCN = 1
—
1.5
—
µA
XFCN = 2
—
4.8
—
µA
XFCN = 3
—
14
—
µA
XFCN = 4
—
40
—
µA
XFCN = 5
—
120
—
µA
XFCN = 6
—
550
—
µA
XFCN = 7
—
2.6
—
mA
Min
Typ
Max
Unit
Table 4.8. External Clock Input
Parameter
Symbol
Test Condition
External Input CMOS Clock
fCMOS
0
—
25
MHz
External Input CMOS Clock High
Time
tCMOSH
18
—
—
ns
External Input CMOS Clock Low
Time
tCMOSL
18
—
—
ns
Min
Typ
Max
Unit
Frequency (at EXTCLK pin)
Table 4.9. ADC
Parameter
Symbol
Test Condition
Resolution
Nbits
12 Bit Mode
12
Bits
10 Bit Mode
10
Bits
Throughput Rate
Tracking Time
fS
tTRK
Power-On Time
tPWR
SAR Clock Frequency
fSAR
12 Bit Mode
—
—
75
ksps
10 Bit Mode
—
—
300
ksps
Initial Acquisition
1.5
—
—
us
Subsequent Acquisitions (DC input, burst mode)
1.1
—
—
us
1.5
—
—
µs
High Speed Mode,
—
—
8.33
MHz
Low Power Mode
—
—
4.4
MHz
Conversion Time
TCNV
10-Bit Conversion
13
—
—
Clocks
Sample/Hold Capacitor
CSAR
Gain = 1
—
16
—
pF
Gain = 0.5
—
13
—
pF
Input Pin Capacitance
CIN
—
20
—
pF
Input Mux Impedance
RMUX
—
5
—
kΩ
Voltage Reference Range
VREF
1
—
VDD
V
Input Voltage Range1
VIN
Gain = 1
0
—
VREF
V
Gain = 0.5
0
—
2 x VREF
V
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Power Supply Rejection Ratio
Test Condition
Min
Typ
Max
Unit
PSRRADC Internal High Speed VREF
—
67
—
dB
External VREF
—
74
—
dB
12 Bit Mode
—
±1
±1.5
LSB
10 Bit Mode
—
±0.5
±1
LSB
12 Bit Mode
—
±0.8
±1
LSB
10 Bit Mode
—
±0.5
±1
LSB
12 Bit Mode, VREF = 1.65 V
–3
0
3
LSB
10 Bit Mode, VREF = 1.65 V
–2
0
2
LSB
—
0.004
—
LSB/°C
12 Bit Mode
—
±0.02
±0.1
%
10 Bit Mode
—
±0.06
±0.24
%
12 Bit Mode
62
65
—
dB
10 Bit Mode
54
58
—
dB
12 Bit Mode
62
65
—
dB
10 Bit Mode
54
58
—
dB
12 Bit Mode
—
-76
—
dB
10 Bit Mode
—
-73
—
dB
12 Bit Mode
—
82
—
dB
10 Bit Mode
—
75
—
dB
DC Performance
Integral Nonlinearity
INL
Differential Nonlinearity (Guaranteed Monotonic)
DNL
Offset Error
EOFF
Offset Temperature Coefficient
TCOFF
Slope Error
EM
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput
Signal-to-Noise
Signal-to-Noise Plus Distortion
SNR
SNDR
Total Harmonic Distortion (Up to
5th Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
Note:
1. Absolute input pin voltage is limited by the VDD supply.
2. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
3. The maximum code in 12-bit mode is 0xFFFC. The Full Scale Error is referenced from the maximum code.
Table 4.10. Voltage Reference
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1.62
1.65
1.68
V
Internal Fast Settling Reference
Output Voltage
VREFFS
Temperature Coefficient
TCREFFS
—
50
—
ppm/°C
Turn-on Time
tREFFS
—
—
1.5
µs
Power Supply Rejection
PSRRREF
—
400
—
ppm/V
1
—
VDD
V
—
5.25
—
µA
FS
External Reference
Input Voltage
VEXTREF
Input Current
IEXTREF
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EFM8SB1 Data Sheet
Electrical Specifications
Table 4.11. Temperature Sensor
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Offset
VOFF
TA = 0 °C
—
940
—
mV
Offset Error1
EOFF
TA = 0 °C
—
18
—
mV
Slope
M
—
3.40
—
mV/°C
Slope Error1
EM
—
40
—
µV/°C
—
±1
—
°C
—
1.8
—
µs
Min
Typ
Max
Unit
Linearity
Turn-on Time
tPWR
Note:
1. Represents one standard deviation from the mean.
Table 4.12. Comparators
Parameter
Symbol
Test Condition
Response Time, CPMD = 00
(Highest Speed)
tRESP0
+100 mV Differential
—
120
—
ns
–100 mV Differential
—
110
—
ns
Response Time, CPMD = 11 (Low- tRESP3
est Power)
+100 mV Differential
—
1.25
—
µs
–100 mV Differential
—
3.2
—
µs
Positive Hysterisis
CPHYP = 00
—
0.4
—
mV
CPHYP = 01
—
8
—
mV
CPHYP = 10
—
16
—
mV
CPHYP = 11
—
32
—
mV
CPHYN = 00
—
-0.4
—
mV
CPHYN = 01
—
–8
—
mV
CPHYN = 10
—
–16
—
mV
CPHYN = 11
—
–32
—
mV
CPHYP = 00
—
0.5
—
mV
CPHYP = 01
—
6
—
mV
CPHYP = 10
—
12
—
mV
CPHYP = 11
—
24
—
mV
CPHYN = 00
—
-0.5
—
mV
CPHYN = 01
—
–6
—
mV
CPHYN = 10
—
–12
—
mV
CPHYN = 11
—
–24
—
mV
CPHYP = 00
—
0.7
—
mV
CPHYP = 01
—
4.5
—
mV
CPHYP = 10
—
9
—
mV
CPHYP = 11
—
18
—
mV
HYSCP+
Mode 0 (CPMD = 00)
Negative Hysterisis
HYSCP-
Mode 0 (CPMD = 00)
Positive Hysterisis
HYSCP+
Mode 1 (CPMD = 01)
Negative Hysterisis
HYSCP-
Mode 1 (CPMD = 01)
Positive Hysterisis
HYSCP+
Mode 2 (CPMD = 10)
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Negative Hysterisis
HYSCP-
Mode 2 (CPMD = 10)
Positive Hysteresis
HYSCP+
Mode 3 (CPMD = 11)
Negative Hysteresis
HYSCP-
Mode 3 (CPMD = 11)
Min
Typ
Max
Unit
CPHYN = 00
—
-0.6
—
mV
CPHYN = 01
—
–4.5
—
mV
CPHYN = 10
—
–9
—
mV
CPHYN = 11
—
–18
—
mV
CPHYP = 00
—
1.5
—
mV
CPHYP = 01
—
4
—
mV
CPHYP = 10
—
8
—
mV
CPHYP = 11
—
16
—
mV
CPHYN = 00
—
-1.5
—
mV
CPHYN = 01
—
–4
—
mV
CPHYN = 10
—
–8
—
mV
CPHYN = 11
—
–16
—
mV
Input Range (CP+ or CP–)
VIN
-0.25
—
VDD+0.25
V
Input Pin Capacitance
CCP
—
12
—
pF
Common-Mode Rejection Ratio
CMRRCP
—
70
—
dB
Power Supply Rejection Ratio
PSRRCP
—
72
—
dB
Input Offset Voltage
VOFF
-10
0
10
mV
Input Offset Tempco
TCOFF
—
3.5
—
µV/°C
Typ
Max
Units
TA = 25 °C
Table 4.13. Programmable Current Reference (IREF0)
Parameter
Symbol
Conditions
Min
Static Performance
Resolution
Nbits
Output Compliance Range
VIOUT
6
bits
Low Power Mode, Source
0
—
VDD – 0.4
V
High Current Mode, Source
0
—
VDD – 0.8
V
Low Power Mode, Sink
0.3
—
VDD
V
High Current Mode, Sink
0.8
—
VDD
V
Integral Nonlinearity
INL
—
<±0.2
±1.0
LSB
Differential Nonlinearity
DNL
—
<±0.2
±1.0
LSB
Offset Error
EOFF
—
<±0.1
±0.5
LSB
Full Scale Error
EFS
Low Power Mode, Source
—
—
±5
%
High Current Mode, Source
—
—
±6
%
Low Power Mode, Sink
—
—
±8
%
High Current Mode, Sink
—
—
±8
%
Low Power Mode Sourcing 20 µA
—
<±1
±3
%
Absolute Current Error
EABS
Dynamic Performance
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Output Settling Time to 1/2 LSB
Startup Time
Conditions
Min
Typ
Max
Units
tSETTLE
—
300
—
ns
tPWR
—
1
—
µs
Note:
1. The PCA block may be used to improve IREF0 resolution by PWMing the two LSBs.
Table 4.14. Capacitive Sense (CS0)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Single Conversion Time1
tCNV
12-bit Mode
20
25
40
µs
13-bit Mode (default)
21
27
42.5
µs
14-bit Mode
23
29
45
µs
16-bit Mode
26
33
50
µs
Number of Channels
NCHAN
24-pin Packages
14
Channels
20-pin Packages
13
Channels
16-pin Packages
12
Channels
Capacitance per Code
CLSB
Default Configuration, 16-bit codes
—
1
—
fF
Maximum External Capacitive
Load
CEXTMAX
CS0CG = 111b (Default)
—
45
—
pF
CS0CG = 000b
—
500
—
pF
Maximum External Series Impedance
REXTMAX
CS0CG = 111b (Default)
—
50
—
kΩ
Note:
1. Conversion time is specified with the default configuration.
2. RMS Noise is equivalent to one standard deviation. Peak-to-peak noise encompasses ±3.3 standard deviations. The RMS noise
value is specified with the default configuration.
Table 4.15. Port I/O
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output High Voltage (High Drive)
VOH
IOH = –3 mA
VDD – 0.7
—
—
V
Output Low Voltage (High Drive)
VOL
IOL = 8.5 mA
—
—
0.6
V
Output High Voltage (Low Drive)
VOH
IOH = –1 mA
VDD – 0.7
—
—
V
Output Low Voltage (Low Drive)
VOL
IOL = 1.4 mA
—
—
0.6
V
Input High Voltage
VIH
VDD = 2.0 to 3.6 V
VDD – 0.6
—
—
V
VDD = 1.8 to 2.0 V
0.7 x VDD
—
—
V
VDD = 2.0 to 3.6 V
—
—
0.6
V
VDD = 1.8 to 2.0 V
—
—
0.3 x VDD
V
Input Low Voltage
VIL
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EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Weak Pull-Up Current
IPU
VDD = 1.8 V
Min
Typ
Max
Unit
—
–4
—
µA
–35
–20
—
µA
–1
—
1
µA
Min
Typ
Max
Unit
VIN = 0 V
VDD = 3.6 V
VIN = 0 V
Input Leakage
ILK
Weak pullup disabled or pin in analog mode
4.2 Thermal Conditions
Table 4.16. Thermal Conditions
Parameter
Symbol
Test Condition
Thermal Resistance*
θJA
QFN-24 Packages
—
35
—
°C/W
QFN-20 Packages
—
60
—
°C/W
QSOP-24 Packages
—
65
—
°C/W
Note:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
4.3 Absolute Maximum Ratings
Stresses above those listed in Table 4.17 Absolute Maximum Ratings on page 20 may cause permanent damage to the device. This
is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For
more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/
support/quality/pages/default.aspx.
Table 4.17. Absolute Maximum Ratings
Parameter
Symbol
Ambient Temperature Under Bias
Test Condition
Min
Max
Unit
TBIAS
–55
125
°C
Storage Temperature
TSTG
–65
150
°C
Voltage on VDD
VDD
GND–0.3
4.0
V
Voltage on I/O pins or RSTb
VIN
GND–0.3
VDD + 0.3
V
Total Current Sunk into Supply Pin
IVDD
—
400
mA
Total Current Sourced out of Ground
Pin
IGND
400
—
mA
Current Sourced or Sunk by Any I/O
Pin or RSTb
IIO
-100
100
mA
Maximum Total Current through all
Port Pins
IIOTOT
—
200
mA
Operating Junction Temperature
TJ
–40
105
°C
Exposure to maximum rating conditions for extended periods may affect device reliability.
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EFM8SB1 Data Sheet
Electrical Specifications
4.4 Typical Performance Curves
Figure 4.1. Typical Operating Supply Current (full supply voltage range)
Figure 4.2. Typical VOH Curves
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EFM8SB1 Data Sheet
Electrical Specifications
Figure 4.3. Typical VOL Curves
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EFM8SB1 Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Figure 5.1 Power Connection Diagram on page 23 shows a typical connection diagram for the power pins of the EFM8SB1 devices.
1.8-3.6 V (in)
1 µF and 0.1 µF bypass
capacitors required for
the power pins placed
as close to the pins as
possible.
VDD
EFM8SB1
Device
GND
Figure 5.1. Power Connection Diagram
5.2 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN203: "8-bit MCU Printed
Circuit Board Design Notes" contains detailed information on these connections. Application Notes can be accessed on the Silicon
Labs website (www.silabs.com/8bit-appnotes).
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EFM8SB1 Data Sheet
Pin Definitions
6. Pin Definitions
RSTb / C2CK
5
P0.3
P0.4
P0.5
19
18
17
GND
6
P1.7
P2.7 / C2D
(Top View)
10
4
P1.3
VDD
16
20 pin QFN
9
3
P1.5
GND
8
2
P1.6
P0.0
P0.2
1
7
P0.1
20
6.1 EFM8SB1x-QFN20 Pin Definitions
P0.6
15
P0.7
14
P1.0
13
P1.1
12
GND
11
P1.2
Figure 6.1. EFM8SB1x-QFN20 Pinout
Table 6.1. Pin Definitions for EFM8SB1x-QFN20
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.1
Multifunction I/O
Yes
P0MAT.1
ADC0.1
INT0.1
CS0.1
INT1.1
AGND
P0MAT.0
CS0.0
INT0.0
VREF
Number
1
2
P0.0
Multifunction I/O
Yes
INT1.0
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EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
3
GND
Ground
4
VDD
Supply Power Input
5
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
7
P1.7
Multifunction I/O
Yes
P1MAT.7
XTAL4
8
P1.6
Multifunction I/O
Yes
P1MAT.6
XTAL3
9
P1.5
Multifunction I/O
Yes
P1MAT.5
CS0.13
10
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
Number
6
CS0.11
11
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
CS0.10
12
GND
Ground
13
P1.1
Multifunction I/O
Yes
P1MAT.1
CMP0N.4
CS0.9
14
P1.0
Multifunction I/O
Yes
P1MAT.0
CMP0P.4
CS0.8
15
16
P0.7
P0.6
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.7
ADC0.7
INT0.7
CS0.7
INT1.7
IREF0
P0MAT.6
ADC0.6
CNVSTR
CS0.6
INT0.6
INT1.6
17
P0.5
Multifunction I/O
Yes
P0MAT.5
ADC0.5
INT0.5
CS0.5
INT1.5
18
P0.4
Multifunction I/O
Yes
P0MAT.4
ADC0.4
INT0.4
CS0.4
INT1.4
19
P0.3
Multifunction I/O
Yes
P0MAT.3
ADC0.3
EXTCLK
CS0.3
WAKEOUT
XTAL2
INT0.3
INT1.3
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EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.2
Multifunction I/O
Yes
P0MAT.2
ADC0.2
RTCOUT
CS0.2
INT0.2
XTAL1
Number
20
INT1.2
Center
GND
Ground
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EFM8SB1 Data Sheet
Pin Definitions
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
24
23
22
21
20
19
6.2 EFM8SB1x-QFN24 Pin Definitions
N/C
1
18
P0.6
GND
2
17
P0.7
VDD
3
16
P1.0
N/C
4
15
P1.1
N/C
5
14
P1.2
RSTb / C2CK
6
13
P1.3
24 pin QFN
(Top View)
11
P1.5
12
10
N/C
P1.4
9
P1.6
8
P2.7 / C2D
P1.7
7
VSS
Figure 6.2. EFM8SB1x-QFN24 Pinout
Table 6.2. Pin Definitions for EFM8SB1x-QFN24
Pin
Pin Name
Description
1
N/C
No Connection
2
GND
Ground
3
VDD
Supply Power Input
4
N/C
No Connection
5
N/C
No Connection
Number
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Crossbar Capability
Additional Digital
Functions
Analog Functions
Rev. 1.2 | 27
EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
8
P1.7
Multifunction I/O
Yes
P1MAT.7
XTAL4
9
P1.6
Multifunction I/O
Yes
P1MAT.6
XTAL3
10
N/C
No Connection
11
P1.5
Multifunction I/O
Yes
P1MAT.5
CS0.13
12
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
Number
6
7
CS0.12
13
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
CS0.11
14
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
CS0.10
15
P1.1
Multifunction I/O
Yes
P1MAT.1
CMP0N.4
CS0.9
16
P1.0
Multifunction I/O
Yes
P1MAT.0
CMP0P.4
CS0.8
17
18
P0.7
P0.6
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.7
ADC0.7
INT0.7
CS0.7
INT1.7
IREF0
P0MAT.6
ADC0.6
CNVSTR
CS0.6
INT0.6
INT1.6
19
P0.5
Multifunction I/O
Yes
P0MAT.5
ADC0.5
INT0.5
CS0.5
INT1.5
20
P0.4
Multifunction I/O
Yes
P0MAT.4
ADC0.4
INT0.4
CS0.4
INT1.4
21
P0.3
Multifunction I/O
Yes
P0MAT.3
ADC0.3
EXTCLK
CS0.3
WAKEOUT
XTAL2
INT0.3
INT1.3
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EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.2
Multifunction I/O
Yes
P0MAT.2
ADC0.2
RTCOUT
CS0.2
INT0.2
XTAL1
Number
22
INT1.2
23
24
P0.1
P0.0
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.1
ADC0.1
INT0.1
CS0.1
INT1.1
AGND
P0MAT.0
CS0.0
INT0.0
VREF
INT1.0
Center
GND
Ground
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EFM8SB1 Data Sheet
Pin Definitions
6.3 EFM8SB1x-QSOP24 Pin Definitions
P0.2
1
24
P0.3
P0.1
2
23
P0.4
P0.0
3
22
P0.5
N/C
4
21
P0.6
GND
5
20
P0.7
VDD
6
19
P1.0
N/C
7
18
P1.1
N/C
8
17
P1.2
RSTb / C2CK
9
16
P1.3
C2D / P2.7
10
15
P1.4
P1.7
11
14
P1.5
P1.6
12
13
N/C
24 pin QSOP
(Top View)
Figure 6.3. EFM8SB1x-QSOP24 Pinout
Table 6.3. Pin Definitions for EFM8SB1x-QSOP24
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.2
Multifunction I/O
Yes
P0MAT.2
ADC0.2
RTCOUT
CS0.2
INT0.2
XTAL1
Number
1
INT1.2
2
P0.1
Multifunction I/O
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Yes
P0MAT.1
ADC0.1
INT0.1
CS0.1
INT1.1
AGND
Rev. 1.2 | 30
EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.0
Multifunction I/O
Yes
P0MAT.0
CS0.0
INT0.0
VREF
Number
3
INT1.0
4
N/C
No Connection
5
GND
Ground
6
VDD
Supply Power Input
7
N/C
No Connection
8
N/C
No Connection
9
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
11
P1.7
Multifunction I/O
Yes
P1MAT.7
XTAL4
12
P1.6
Multifunction I/O
Yes
P1MAT.6
XTAL3
13
N/C
No Connection
14
P1.5
Multifunction I/O
Yes
P1MAT.5
CS0.13
15
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
10
CS0.12
16
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
CS0.11
17
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
CS0.10
18
P1.1
Multifunction I/O
Yes
P1MAT.1
CMP0N.4
CS0.9
19
P1.0
Multifunction I/O
Yes
P1MAT.0
CMP0P.4
CS0.8
20
21
P0.7
P0.6
Multifunction I/O
Multifunction I/O
Yes
Yes
P0MAT.7
ADC0.7
INT0.7
CS0.7
INT1.7
IREF0
P0MAT.6
ADC0.6
CNVSTR
CS0.6
INT0.6
INT1.6
22
P0.5
Multifunction I/O
Yes
P0MAT.5
ADC0.5
INT0.5
CS0.5
INT1.5
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EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.4
Multifunction I/O
Yes
P0MAT.4
ADC0.4
INT0.4
CS0.4
Number
23
INT1.4
24
P0.3
Multifunction I/O
Yes
P0MAT.3
ADC0.3
EXTCLK
CS0.3
WAKEOUT
XTAL2
INT0.3
INT1.3
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EFM8SB1 Data Sheet
Pin Definitions
6.4 EFM8SB1x-CSP16 Pin Definitions
CSP devices can be handled and soldered using industry standard surface mount assembly techniques. However, because CSP devices are essentially a piece of silicon and are not encapsulated in plastic, they are susceptible to mechanical damage and may be sensitive to light. When CSP packages must be used in an environment exposed to light, it may be necessary to cover the top and sides with
an opaque material.
A1
A2
A3
A4
P0.7
P0.5
P0.4
P0.0
B1
B2
B3
B4
P1.0
P0.3
P0.2
GND
C1
C2
C3
C4
P1.3
P0.6
P0.1
VDD
D1
D2
D3
D4
P1.1
P1.4
RSTb / C2CK P2.7 / C2D
16 pin CSP
(Top View)
Figure 6.4. EFM8SB1x-CSP16 Pinout
Table 6.4. Pin Definitions for EFM8SB1x-CSP16
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.7
Multifunction I/O
Yes
P0MAT.7
ADC0.7
INT0.7
CS0.7
INT1.7
IREF0
P0MAT.5
ADC0.5
INT0.5
CS0.5
Number
A1
A2
P0.5
Multifunction I/O
Yes
INT1.5
A3
P0.4
Multifunction I/O
Yes
P0MAT.4
ADC0.4
INT0.4
CS0.4
INT1.4
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EFM8SB1 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.0
Multifunction I/O
Yes
P0MAT.0
CS0.0
INT0.0
VREF
Number
A4
INT1.0
B1
P1.0
Multifunction I/O
Yes
P1MAT.0
CMP0P.4
CS0.8
B2
P0.3
Multifunction I/O
Yes
P0MAT.3
ADC0.3
EXTCLK
CS0.3
WAKEOUT
XTAL2
INT0.3
INT1.3
B3
P0.2
Multifunction I/O
Yes
P0MAT.2
ADC0.2
RTCOUT
CS0.2
INT0.2
XTAL1
INT1.2
B4
GND
Ground
C1
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
CS0.11
C2
P0.6
Multifunction I/O
Yes
P0MAT.6
ADC0.6
CNVSTR
CS0.6
INT0.6
INT1.6
C3
P0.1
Multifunction I/O
C4
VDD
Supply Power Input
D1
P1.1
Multifunction I/O
Yes
Yes
P0MAT.1
ADC0.1
INT0.1
CS0.1
INT1.1
AGND
P1MAT.1
CMP0N.4
CS0.9
D2
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
CS0.12
D3
D4
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
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EFM8SB1 Data Sheet
CSP16 Package Specifications
7. CSP16 Package Specifications
7.1 CSP16 Package Dimensions
Note: CSP devices can be handled and soldered using industry standard surface mount assembly techniques. However, because CSP
devices are essentially a piece of silicon and are not encapsulated in plastic, they are susceptible to mechanical damage and may be
sensitive to light. When CSP packages must be used in an environment exposed to light, it may be necessary to cover the top and
sides with an opaque material.
Figure 7.1. CSP16 Package Drawing
Table 7.1. CSP16 Package Dimensions
Dimension
Min
Typ
Max
A
0.491
0.55
0.609
A1
0.17
—
0.23
A2
0.036
0.040
0.044
b
0.23
—
0.29
S
0.3075
0.31
0.3125
D
1.781 BSC
E
1.659 BSC
e
0.40 BSC
D1
1.20 BSC
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EFM8SB1 Data Sheet
CSP16 Package Specifications
Dimension
Min
Typ
E1
1.20 BSC
SD
0.2
SE
0.2
n
16
aaa
0.03
bbb
0.06
ccc
0.05
ddd
0.015
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Primary datum “C” and seating plane are defined by the spherical crowns of the solder balls.
4. Dimension “b” is measured at the maximum solder bump diameter, parallel to primary datum “C”.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8SB1 Data Sheet
CSP16 Package Specifications
7.2 CSP16 PCB Land Pattern
Figure 7.2. CSP16 PCB Land Pattern Drawing
Table 7.2. CSP16 PCB Land Pattern Dimensions
Dimension
Min
Max
X
0.20
C1
1.20
C2
1.20
E1
0.40
E2
0.40
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.075 mm (3 mils).
7. A stencil of square aperture (0.22 x 0.22 mm) is recommended.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFM8SB1 Data Sheet
CSP16 Package Specifications
7.3 CSP16 Package Marking
PPPP
TTTT
YYWW
Figure 7.3. CSP16 Package Marking
The package marking consists of:
• PPPP – The part number designation.
• TTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
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EFM8SB1 Data Sheet
QFN20 Package Specifications
8. QFN20 Package Specifications
8.1 QFN20 Package Dimensions
Figure 8.1. QFN20 Package Drawing
Table 8.1. QFN20 Package Dimensions
Dimension
Min
Typ
Max
A
0.50
0.55
0.60
A1
0.00
—
0.05
b
0.20
0.25
0.30
b1
0.275
0.325
0.375
D
D2
3.00 BSC
1.6
1.70
e
0.50 BSC
e1
0.513 BSC
E
3.00 BSC
1.80
E2
1.60
1.70
1.80
L
0.35
0.40
0.45
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Rev. 1.2 | 39
EFM8SB1 Data Sheet
QFN20 Package Specifications
Dimension
Min
Typ
Max
L1
0.00
—
0.10
aaa
—
0.10
—
bbb
—
0.10
—
ddd
—
0.05
—
eee
—
—
0.08
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing is based upon JEDEC Solid State Product Outline MO-248 but includes custom features which are toleranced per
supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFM8SB1 Data Sheet
QFN20 Package Specifications
8.2 QFN20 PCB Land Pattern
Figure 8.2. QFN20 PCB Land Pattern Drawing
Table 8.2. QFN20 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
2.70
C2
2.70
C3
2.53
C4
2.53
E
0.50 REF
X1
0.20
0.30
X2
0.24
.034
X3
1.70
1.80
Y1
0.50
0.60
Y2
0.24
0.34
Y3
1.70
1.80
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EFM8SB1 Data Sheet
QFN20 Package Specifications
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
8. A 2x2 array of 0.75mm openings on a 0.95mm pitch should be used for the center pad to assure proper paste volume.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8.3 QFN20 Package Marking
PPPP
PPPP
TTTTTT
YYWW #
Figure 8.3. QFN20 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8SB1 Data Sheet
QFN24 Package Specifications
9. QFN24 Package Specifications
9.1 QFN24 Package Dimensions
Figure 9.1. QFN24 Package Drawing
Table 9.1. QFN24 Package Dimensions
Dimension
Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
—
0.05
b
0.18
0.25
0.30
D
3.90
4.00
4.10
D2
2.60
2.70
2.80
e
0.50 BSC
E
3.90
4.00
4.10
E2
2.60
2.70
2.80
L
0.35
0.40
0.45
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
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EFM8SB1 Data Sheet
QFN24 Package Specifications
Dimension
Min
Typ
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8SB1 Data Sheet
QFN24 Package Specifications
9.2 QFN24 PCB Land Pattern
Figure 9.2. QFN24 PCB Land Pattern Drawing
Table 9.2. QFN24 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
3.90
4.00
C2
3.90
4.00
E
0.50 BSC
X1
0.20
0.30
X2
2.70
2.80
Y1
0.65
0.75
Y2
2.70
2.80
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EFM8SB1 Data Sheet
QFN24 Package Specifications
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2 x 2 array of 1.10 mm x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
9.3 QFN24 Package Marking
PPPPPPPP
TTTTTT
YYWW #
Figure 9.3. QFN24 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.2 | 46
EFM8SB1 Data Sheet
QSOP24 Package Specifications
10. QSOP24 Package Specifications
10.1 QSOP24 Package Dimensions
Figure 10.1. QSOP24 Package Drawing
Table 10.1. QSOP24 Package Dimensions
Dimension
Min
Typ
Max
A
—
—
1.75
A1
0.10
—
0.25
b
0.20
—
0.30
c
0.10
—
0.25
D
8.65 BSC
E
6.00 BSC
E1
3.90 BSC
e
0.635 BSC
L
theta
silabs.com | Smart. Connected. Energy-friendly.
0.40
—
1.27
0º
—
8º
Rev. 1.2 | 47
EFM8SB1 Data Sheet
QSOP24 Package Specifications
Dimension
Min
Typ
aaa
0.20
bbb
0.18
ccc
0.10
ddd
0.10
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.2 | 48
EFM8SB1 Data Sheet
QSOP24 Package Specifications
10.2 QSOP24 PCB Land Pattern
Figure 10.2. QSOP24 PCB Land Pattern Drawing
Table 10.2. QSOP24 PCB Land Pattern Dimensions
Dimension
Min
Max
C
5.20
5.30
E
0.635 BSC
X
0.30
0.40
Y
1.50
1.60
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.2 | 49
EFM8SB1 Data Sheet
QSOP24 Package Specifications
10.3 QSOP24 Package Marking
EFM8
PPPPPPPP #
TTTTTTYYWW
Figure 10.3. QSOP24 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.2 | 50
EFM8SB1 Data Sheet
Revision History
11. Revision History
11.1 Revision 1.2
Added CSP16 package.
Updated the "C2D / P2.0" pin on the QSOP24 pinout diagram to "C2D / P2.7."
Added crystal oscillator drive current typical values to Table 4.7 Crystal Oscillator on page 14.
Corrected the number of capacitive sense channels for 24- and 20-pin packages in Table 4.14 Capacitive Sense (CS0) on page 19.
Corrected E dimension shown in Figure 8.2 QFN20 PCB Land Pattern Drawing on page 41.
Added more information to 3.10 Bootloader.
11.2 Revision 1.1
Initial release.
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Rev. 1.2 | 51
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Introduction.
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3.10 Bootloader
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4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.1 Electrical Characteristics .
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4.3 Absolute Maximum Ratings .
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4.4 Typical Performance Curves .
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5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .
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5.1 Power
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5.2 Other Connections .
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.23
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
6.1 EFM8SB1x-QFN20 Pin Definitions .
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.24
6.2 EFM8SB1x-QFN24 Pin Definitions .
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.27
6.3 EFM8SB1x-QSOP24 Pin Definitions .
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.30
6.4 EFM8SB1x-CSP16 Pin Definitions .
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.33
7. CSP16 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
35
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.35
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.38
8. QFN20 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
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8.1 QFN20 Package Dimensions
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8.2 QFN20 PCB Land Pattern
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.42
9. QFN24 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
43
Table of Contents
52
9.1 QFN24 Package Dimensions .
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9.3 QFN24 Package Marking .
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10.1 QSOP24 Package Dimensions
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10.2 QSOP24 PCB Land Pattern
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.50
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
10. QSOP24 Package Specifications
11.1 Revision 1.2 .
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11.2 Revision 1.1 .
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.51
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
Table of Contents
53
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