(2.5 kV) Si8410/Si8420/Si8421 Low-Power Single- and Dual-Channel Digital Isolators

Si8410/20/21
L OW -P OWER S INGLE A N D D UAL - C HANNEL
D IGITAL I SOLATORS
Features

High-speed operation
DC

to 150 Mbps
Up to 2500 VRMS isolation
 60-year life at rated working
No start-up initialization required
voltage
 Wide Operating Supply Voltage:  Precise timing (typical)
2.70–5.5 V
<10 ns worst case
 Ultra low power (typical)
1.5 ns pulse width distortion
5 V Operation:
0.5 ns channel-channel skew
<
<
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
2
2.1 mA per channel at 1 Mbps
6 mA per channel at 100 Mbps
2.70 V Operation:
6

ns propagation delay skew
ns minimum pulse width
Transient Immunity 25 kV/µs
1.8 mA per channel at 1 Mbps  Wide temperature range
< 4 mA per channel at 100 Mbps
–40 to 125 °C at 150 Mbps
<

High electromagnetic immunity

RoHS-compliant packages
SOIC-8
narrow body
Ordering Information:
See page 25.
Applications
Industrial automation systems
Hybrid electric vehicles
 Isolated switch mode supplies


Isolated ADC, DAC
Motor control
 Power inverters
 Communications systems


Safety Regulatory Approvals

UL 1577 recognized
Up

to 2500 VRMS for 1 minute
CSA component notice 5A
approval
IEC

VDE certification conformity
IEC
60747-5-2
(VDE0884 Part 2)
60950-1, 61010-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability,
and external BOM advantages when compared to legacy isolation
technologies. The operating parameters of these products remain stable
across wide temperature ranges throughout their service life. For ease of
design, only VDD bypass capacitors are required.
Data rates up to 150 Mbps are supported, and all devices achieve worstcase propagation delays of less than 10 ns. All products are safety
certified by UL, CSA, and VDE and support withstand voltages of up to
2.5 kVrms. These devices are available in an 8-pin narrow-body SOIC
package.
Rev. 1.5 9/13
Copyright © 2013 by Silicon Laboratories
Si8410/20/21
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Si8410/20/21
2
Rev. 1.5
Si8410/20/21
TABLE O F C ONTENTS
Section
Page
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1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . . 23
3.2. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.5
3
Si8410/20/21
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Ambient Operating Temperature*
TA
150 Mbps, 15 pF, 5 V
–40
25
125
°C
VDD1
2.70
—
5.5
V
VDD2
2.70
—
5.5
V
Supply Voltage
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*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
Max
Unit
TSTG
–65
—
150
°C
TA
–40
—
125
°C
Supply Voltage (Revision C)3
VDD1, VDD2
–0.5
—
5.75
V
3
VDD1, VDD2
–0.5
—
6.0
V
Input Voltage
VI
–0.5
—
VDD + 0.5
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
Output Current Drive Channel
IO
—
—
10
mA
Lead Solder Temperature (10 s)
—
—
260
°C
Maximum Isolation Voltage (1 s)
—
—
3600
VRMS
Storage Temperature
2
Operating Temperature
Supply Voltage (Revision D)
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "5. Ordering Guide" on page 25 for more information.
4
Rev. 1.5
Si8410/20/21
Table 3. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA =–40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
4.8
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—

Input Leakage Current
1
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Output Impedance
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
mA
mA
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—
1.3
0.9
2.0
1.4
mA
Si8420Ax, Bx
VDD1
VDD2
—
—
2.0
1.6
3.0
2.4
mA
Si8421Ax, Bx
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
5
Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA =–40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
—
—
1.3
1.2
2.0
1.8
mA
Si8420Bx
VDD1
VDD2
—
—
2.0
2.1
3.0
3.2
mA
Si8421Bx
VDD1
VDD2
—
—
3.3
3.3
mA
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Si8410Bx
VDD1
VDD2
2.2
2.2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—
1.4
4.6
2.1
5.8
mA
Si8420Bx
VDD1
VDD2
—
—
2.2
9.2
3.3
11.5
mA
Si8421Bx
VDD1
VDD2
—
—
5.8
5.8
7.3
7.3
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.5
Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA =–40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Si8410Bx, Si8420Bx, Si8421Bx
Propagation Delay
tPHL, tPLH
See Figure 1
3.0
6.0
9.5
ns
PWD
See Figure 1
—
1.5
2.5
ns
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.8
ns
Pulse Width Distortion
|tPLH - tPHL|
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Propagation Delay Skew2
Channel-Channel Skew
All Models
Output Rise Time
tr
CL = 15 pF
—
3.8
5.0
ns
Output Fall Time
tf
CL = 15 pF
—
2.8
3.7
ns
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
—
15
40
µs
Common Mode Transient
Immunity
Start-up Time3
tSU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
1.4 V
Typical
Output
tPHL
90%
90%
10%
10%
tr
tf
Figure 1. Propagation Delay Timing
Rev. 1.5
7
Si8410/20/21
Table 4. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
3.1
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—

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Input Leakage Current
Output Impedance1
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
mA
mA
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—
1.3
0.9
2.0
1.4
mA
Si8420Ax, Bx
VDD1
VDD2
—
—
2.0
1.6
3.0
2.4
mA
Si8421Ax, Bx
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.5
Si8410/20/21
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
—
—
1.3
1.2
2.0
1.8
mA
Si8420Bx
VDD1
VDD2
—
—
2.0
2.1
3.0
3.2
mA
Si8421Bx
VDD1
VDD2
—
—
3.3
3.3
mA
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Si8410Bx
VDD1
VDD2
2.2
2.2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—
1.3
3.3
2.0
4.9
mA
Si8420Bx
VDD1
VDD2
—
—
2.0
6.5
3.0
8.1
mA
Si8421Bx
VDD1
VDD2
—
—
4.4
4.4
5.5
5.5
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
9
Si8410/20/21
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Si8410Bx, Si8420Bx, Si8421Bx
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
See Figure 1
3.0
6.0
9.5
ns
PWD
See Figure 1
—
1.5
2.5
ns
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.8
ns
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Propagation Delay Skew2
tPHL, tPLH
Channel-Channel Skew
All Models
Output Rise Time
tr
CL = 15 pF
—
4.3
6.1
ns
Output Fall Time
tf
CL = 15 pF
—
3.0
4.3
ns
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
—
15
40
µs
Common Mode Transient
Immunity
Start-up Time3
tSU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.5
Si8410/20/21
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
2.3
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—

Input Leakage Current
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Output Impedance
2
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—
1.3
0.9
2.0
1.4
mA
Si8420Ax, Bx
VDD1
VDD2
—
—
2.0
1.6
3.0
2.4
mA
Si8421Ax, Bx
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
11
Si8410/20/21
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
—
—
1.3
1.2
2.0
1.8
mA
Si8420Bx
VDD1
VDD2
—
—
2.0
2.1
3.0
3.2
mA
Si8421Bx
VDD1
VDD2
—
—
3.3
3.3
mA
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VDD1
VDD2
2.2
2.2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—
1.3
2.7
2.0
4.0
mA
Si8420Bx
VDD1
VDD2
—
—
2.0
5.2
3.0
6.5
mA
Si8421Bx
VDD1
VDD2
—
—
3.7
3.7
4.6
4.6
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew3
Channel-Channel Skew
tPHL, tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.5
Si8410/20/21
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Si8410Bx, Si8420Bx, Si8421Bx
Propagation Delay
tPHL, tPLH
See Figure 1
3.0
6.0
9.5
ns
PWD
See Figure 1
—
1.5
2.5
ns
Pulse Width Distortion
|tPLH - tPHL|
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Propagation Delay Skew3
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.8
ns
Channel-Channel Skew
All Models
Output Rise Time
tr
CL = 15 pF
—
4.8
6.5
ns
Output Fall Time
tf
CL = 15 pF
—
3.2
4.6
ns
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
—
15
40
µs
Common Mode Transient
Immunity
Start-up Time4
tSU
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 Vpeak for basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 25.
Rev. 1.5
13
Si8410/20/21
Table 7. Insulation and Safety-Related Specifications
Parameter
Symbol
Nominal Air Gap (Clearance)1
Nominal External Tracking
(Creepage)1
Test Condition
Value
Unit
L(IO1)
4.9
mm
L(IO2)
4.01
mm
0.008
mm
600
VRMS
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
0.040
mm
Resistance (Input-Output)2
RIO
1012

1.0
pF
4.0
pF
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IEC60112
Capacitance
(Input-Output)2
Input Capacitance3
CIO
f = 1 MHz
CI
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in "6. Package Outline:
8-Pin Narrow Body SOIC" on page 26. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB
SOIC-8 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–4 are shorted
together to form the first terminal and pins 5–8 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Basic Isolation Group
Installation Classification
14
Test Condition
Material Group
Specification
I
Rated Mains Voltages < 150 VRMS
I-IV
Rated Mains Voltages < 300 VRMS
I-III
Rated Mains Voltages < 400 VRMS
I-II
Rated Mains Voltages < 600 VRMS
I-II
Rev. 1.5
Si8410/20/21
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Maximum Working Insulation Voltage
Symbol
Test Condition
Unit
560
V peak
VIORM
Input to Output Test Voltage
Transient Overvoltage
Characteristic
V peak
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm =1 sec,
Partial Discharge < 5 pC)
1050
VIOTM
t = 60 sec
4000
2
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Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO = 500 V
V peak
>109
RS

*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter
Case Temperature
Symbol
Test Condition
TS
Safety input, output, or supply current
IS
Device Power Dissipation2
PD
JA = 140 °C/W,
VI = 5.5 V,
TJ = 150 °C,
TA = 25 °C
Min
Typ
Max
Unit
—
—
150
°C
—
—
160
mA
—
—
150
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
2. The Si841x/2x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.5
15
Si8410/20/21
Table 11. Thermal Characteristics
Parameter
Symbol
JA
Min
Typ
Max
Unit
—
140
—
°C/W
400
320
VDD1, VDD2 = 2.70 V
300 270
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Safety-Limiting Values (mA)
IC Junction-to-Air Thermal Resistance
Test Condition
200
VDD1, VDD2 = 3.3 V
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
Case Temperature (ºC)
200
Figure 2. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.5
Si8410/20/21
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 3.
Transmitter
Receiver
A
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RF
OSCILLATOR
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
B
Figure 3. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 4 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 4. Modulation Scheme
Rev. 1.5
17
Si8410/20/21
2.2. Eye Diagram
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Figure 5 illustrates an eye-diagram taken on an Si8410. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8410 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 5. Eye Diagram
18
Rev. 1.5
Si8410/20/21
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12.
Table 12. Si84xx Logic Operation Table
VI Input1,4 VDDI State1,2,3 VDDO State1,2,3 VO Output1,4
P
P
H
L
P
P
L
X5
UP
P
L
X5
Normal operation.
Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less
than 1 µs.
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H
Comments
P
UP
Upon transition of VDDO from unpowered to powUndetermined ered, VO returns to the same state as VI within
1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.70 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
Rev. 1.5
19
Si8410/20/21
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 13 and Table 7 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting any design that uses a digital isolator.
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The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100  resistors in series with the VDD supply voltage source and 50 to
300  resistors in series with the digital inputs/outputs (see Figure 6). For more details, see "3. Errata and Design
Migration Guidelines" on page 23.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300  resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 4.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
V Source 1
R1 (50 – 100 )
V Source 2
R2 (50 – 100 )
VDD1
C1
VDD2
50 – 300 
0.1 F
A1
0.1 F
B1
C2
1 F
C4
50 – 300 
C3
Input/Output
Input/Output
1 F
Bx
Ax
50 – 300 
50 – 300 
GND1
GND2
Figure 6. Recommended Bypass Components for the Si84xx Digital Isolator Family
20
Rev. 1.5
Si8410/20/21
2.5. Typical Performance Characteristics
30
30
25
25
20
Current (mA)
Current (mA)
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 3, 4, and 5 for actual specification limits.
5V
15
3.3V
10
5
20
5V
15
3.3V
10
5
2.70V
2.70V
0
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0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 7. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
30
30
25
25
20
Current (mA)
Current (mA)
Figure 10. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
5V
15
3.3V
10
2.70V
5
0
0
20
2.70V
5
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 8. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 11. Si8420 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
10
25
15
3.3V
10
5
0
8
7
Rising Edge
6
2.70V
0
Falling Edge
9
5V
20
Delay (ns)
Current (mA)
3.3V
10
Data Rate (Mbps)
30
5V
15
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
5
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 9. Si8421 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Rev. 1.5
Figure 12. Propagation Delay
vs. Temperature
21
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Si8410/20/21
Figure 13. Si84xx Time-Dependent Dielectric Breakdown
22
Rev. 1.5
Si8410/20/21
3. Errata and Design Migration Guidelines
The following errata apply to Revision C devices only. See "5. Ordering Guide" on page 25 for more details. No
errata exist for Revision D devices.
3.1. Power Supply Bypass Capacitors (Revision C and Revision D)
When using the Si84xx isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.1.1. Resolution
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For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 20. Additionally, refer to "5.
Ordering Guide" on page 25 for current ordering information.
3.2. Latch Up Immunity (Revision C Only)
Si84xx latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latchup immunity. To increase latch-up immunity on these pins, 100  of equivalent resistance must be included in
series with all of the pins listed in Table 13. The 100  equivalent resistance can be comprised of the source
driver's output resistance and a series termination resistor. The Si8410 is not affected by the latch up immunity
issue described above.
3.2.1. Resolution
This issue has been corrected with Revision D of the device. Refer to “5. Ordering Guide” for current ordering
information.
Table 13. Affected Ordering Part Numbers (Revision C Only)
Affected Ordering Part Numbers*
SI8420SV-C-IS, SI8421SV-C-IS
Device
Revision
C
Pin#
Name
Pin Type
3
A2
Input or Output
7
B1
Output
*Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB).
Rev. 1.5
23
Si8410/20/21
4. Pin Descriptions
VDD1
RF
XMITR
A1
VDD1/NC
VDD2
RF
RCVR
GND2/NC
A1
RF
XMITR
B1
A2
RF
XMITR
GND2
Si8410 NB SOIC-8
VDD1
GND1
I
s
o
l
a
t
i
o
n
VDD2
VDD1
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
Si8420 NB SOIC-8
GND2
GND1
I
s
o
l
a
t
i
o
n
VDD2
RF
RCVR
B1
RF
RCVR
B2
Si8421 NB SOIC-8
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GND1
I
s
o
l
a
t
i
o
n
Name
SOIC-8 Pin#
Si8410
SOIC-8 Pin#
Si8420/21
Type
Description
VDD1/NC*
1,3
1
Supply
Side 1 power supply.
GND1
4
4
Ground
Side 1 ground.
A1
2
2
Digital I/O
Side 1 digital input or output.
A2
NA
3
Digital I/O
Side 1 digital input or output.
B1
6
7
Digital I/O
Side 2 digital input or output.
B2
NA
6
Digital I/O
Side 2 digital input or output.
VDD2
8
8
Supply
Side 2 power supply.
GND2/NC*
5,7
5
Ground
Side 2 ground.
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
24
Rev. 1.5
GND2
Si8410/20/21
5. Ordering Guide
These devices are not recommended for new designs. Please see the Si861x datasheet for replacement options.
Table 14. Ordering Guide for Valid OPNs1
Ordering Part
Number
(OPN)
Alternative
Part Number
(APN)
Number of
Inputs VDD1
Side
Number of
Inputs VDD2
Side
Maximum
Data Rate
(Mbps)
Si8410AB-D-IS
Si8610AB-B-IS
1
0
1
Si8410BB-D-IS
Si8610BB-B-IS
1
0
150
Si8420AB-D-IS
Si8620AB-B-IS
2
0
1
Si8420BB-D-IS
Si8620BB-B-IS
2
0
150
Si8421AB-D-IS
Si8621AB-B-IS
1
1
1
Si8421BB-D-IS
Si8621BB-B-IS
1
1
150
Si8410AB-C-IS
Si8610AB-B-IS
1
0
1
Si8410BB-C-IS
Si8610BB-B-IS
1
0
150
Si8420AB-C-IS
Si8620AB-B-IS
2
0
1
Si8420BB-C-IS
Si8620BB-B-IS
2
0
150
Si8421AB-C-IS
Si8621AB-B-IS
1
1
1
Si8421BB-C-IS
Si8621BB-B-IS
1
1
150
Isolation
Rating
Package
Type
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Revision D Devices2
2.5 kVrms
NB SOIC-8
2.5 kVrms
NB SOIC-8
Revision C Devices2
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C
according to the JEDEC industry standard classifications and peak solder temperature.
2. Revision C and Revision D devices are supported for existing designs.
Rev. 1.5
25
Si8410/20/21
6. Package Outline: 8-Pin Narrow Body SOIC
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Figure 14 illustrates the package details for the Si841x. Table 15 lists the values for the dimensions shown in the
illustration.

Figure 14. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
26
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27

0
8
Rev. 1.5
Si8410/20/21
7. Land Pattern: 8-Pin Narrow Body SOIC
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Figure 15 illustrates the recommended land pattern details for the Si841x in an 8-pin narrow-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 15. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 16. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.5
27
Si8410/20/21
8. Top Marking: 8-Pin Narrow Body SOIC
8.1. 8-Pin Narrow Body SOIC Top Marking
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Si84XYSV
YYWWRF
e3 AIXX
8.2. Top Marking Explanation
Table 17. Top Marking Explanations
Line 1 Marking:
Line 2 Marking:
Base Part Number
Ordering Options
(See Ordering Guide for more
information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A =1 kV; B =2.5 kV
YY = Year
WW = Workweek
Assigned by Assembly Contractor. Corresponds to the
year and workweek of the mold date.
R = Product (OPN) Revision
F =Wafer Fab
Line 3 Marking:
28
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol
First Two Characters of the Manufacturing Code
A = Assembly Site
I = Internal Code
XX = Serial Lot Number
Last Four Characters of the Manufacturing Code
Rev. 1.5
Si8410/20/21
DOCUMENT CHANGE LIST
Revision 1.2 to Revision 1.3
Revision 0.11 to Revision 0.21

Rev 0.21 is the first revision of this document that
applies to the new series of ultra low power isolators
featuring pinout and functional compatibility with
previous isolator products.
 Updated “1. Electrical Specifications”.
 Updated “5. Ordering Guide”.
 Added “8. Top Marking: 8-Pin Narrow Body SOIC”.

Revision 0.21 to Revision 0.22
Updated "2.4.1. Supply Bypass" on page 20.
Added Figure 6, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 20.
 Updated "3.1. Power Supply Bypass Capacitors
(Revision C and Revision D)" on page 23.


Updated all specs to reflect latest silicon.
Revision 0.22 to Revision 0.23
Updated all specs to reflect latest silicon.
 Added "3. Errata and Design Migration Guidelines"
on page 23.

Revision 1.3 to Revision 1.4
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
Updated " Features" on page 1.
Moved Tables 1 and 2 to page 4.
 Updated Tables 6, 7, 8, and 9.
 Updated Table 12 footnotes.
 Added Figure 13, “Si84xx Time-Dependent
Dielectric Breakdown,” on page 22.

Revision 1.4 to Revision 1.5

Revision 0.23 to Revision 1.0
Updated document to reflect availability of Revision
D silicon.
 Updated Tables 3,4, and 5.



Updated
all supply currents and channel-channel skew.
Updated
absolute maximum supply voltage.
Updated
clearance and creepage dimensions.
Updated "5. Ordering Guide" on page 25 to include
new title note and “ Alternative Part Number (APN)”
column.
Updated Table 2.
Updated Table 7.
Updated "3. Errata and Design Migration Guidelines"
on page 23.
 Updated "5. Ordering Guide" on page 25.

Revision 1.0 to Revision 1.1

Updated Tables 3, 4, and 5.
Updated
notes in tables to reflect output impedance of
85 .
Updated rise and fall time specifications.
Updated CMTI value.
Revision 1.1 to Revision 1.2
Updated document throughout to include MSL
improvements to MSL2A.
 Updated "5. Ordering Guide" on page 25.

Updated
Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Rev. 1.5
29
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