Datasheet Download

Digital Sound Processors for FPD TVs
28bit Audio DSP with Built-in
2ch ADC, 6ch DAC and ASRC
BD9406KS2
No.12083EAT01
●General Description
This LSI is the digital sound processor which made the use digital signal processing for FPD TVs.
DSP of ROHM original is used for the TV sound processor unit, and it excels in cost performance.
The asynchronous sampling rate converter is built in the digital input one line. The audio AD converter is built in
the analog input one line. The audio DA converters are built in the output three lines.
●Features
■ Digital Signal Processor unit
Word length:
28bit (Data RAM)
The fastest machine Cycle: 40.7ns (512fs, fs=48kHz)
Multiplier:
28x24 → 52 bit
Adder:
28+28 → 28bit
Data RAM:
256x28bit
Coefficient RAM:
128x24bit
Sampling Frequency:
fs=48kHz
Master Clock:
512fs (24.576Mhz, fs=48kHz)
■ Digital Signal Input (Stereo 4 lines): 16/20/24bit (I2S, Left-Justified, Right-Justified)
Digital Signal Output (Stereo 4 lines): 16/20/24bit (I2S, Left-Justified, Right-Justified, S/PDIF)
■ Asynchronous Sampling Rate Converter (Stereo 1 line): 32kHz/44.1kHz → 48kHz
■ Audio ADC: Stereo Input 1 line
20bit 64 x Over-sampling sigma delta ADC
S/N:
90dB
THD+N:
0.02% (Sine-wave 1kHz, -0.5dB)
Digital HPF (fc=1Hz)
■ Audio DAC: Stereo Output 2 lines
24bit 8x Over-sampling digital filter + 1bit sigma delta DAC
S/N:
96dB
THD+N:
0.005% (Sine-wave 1kHz, 0dB)
■ Audio 16bit DAC: Stereo Output 1 line
24bit 8x Over-sampling digital filter + Audio 16bit DAC
S/N:
90dB
THD+N:
0.03% (Sine-wave 1kHz, 0dB)
■
The sound signal processing function for FPD TVs
Pre-scaler, Channel Mixer, Pseudo Stereo, Surround, P2Bass, SAS,12-band parametric EQ, Master Volume,
L/R Balance, Compression, Post-scaler, Output Signal Clipper
(P2Bass and SAS are ROHM’s own sound effect functions.)
●Applications
Flat Panel TVs (LCD, Plasma)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
1/34
2012.03 - Rev.A
Technical Note
BU9406KS2
●Absolute Maximum Ratings (Ta=25℃)
Item
Power Supply Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Symbol
VDD
Pd
Topr
Tstg
Rating
4.5
950 (※1)
-40～+85
-55～+125
Unit
V
mW
℃
℃
Rating
3.0～3.6
Unit
V
*1 Use of this processor at Ta=25℃ and over is subject to reduction of 9.5mW per 1 .
*2Operation is not guaranteed.
●Recommendation Operating range (Ta=-40～+85℃)
Item
Symbol
Power Supply Voltage
VDD
*1This product is not designed for protection against radioactive rays.
●Electrical Characteristics (Digital system)
VDD=3.3V (Unless otherwise specified Ta=25℃)
Min.
Limit
Typ.
Max.
VIH
VIL
2.3
-
-
1.0
V
V
Relevant
Pins
*1
*1
VIH
VIL
2.5
-
-
0.8
V
V
*2,3,4
*2,3,4
II
IIL
-150
-100
±1
-50
µA
µA
VIN=0～3.3V
VIN=0V
*1,2
*3
IIH
35
70
105
µA
VIN=3.3V
*4
VOH
VOL
2.75
-
-
0.55
V
V
IO=-0.6mA
IO=0.6mA
*5
*5
Item
Symbol
H-level Voltage
Input
L-level Voltage
Voltage
H-level Voltage
Hysteresis
Input
L-level Voltage
Voltage
Input Current
Input L Current to Pull-up
Resistor
Input H Current to Pull-down
Resistor
H-level Voltage
Output
L-level Voltage
Voltage
Unit
Conditions
Relevant Pins
*1
CMOS input pin
XI (pin 60)
*2
CMOS hysteresis input pin
MODE (pin 2), SCANTEST (pin 3), SDA (pin 4), SCL (pin 5)
*3
CMOS hysteresis input pin with built-in pull-up resistance
RESETB (pin 8), DATAI1 (pin 52), BCKI1 (pin 53), LRCKI1 (pin 54), DATAI2 (pin 55), BCKI2 (pin 56),
LRCKI2 (pin 57), DATAI3 (pin 58), BCKI3 (pin 63), LRCKI3 (pin 64), DATAI4 (pin 65), BCKI4 (pin 66),
LRCKI4 (pin 67), AMCLKI1 (pin 68), AMCLKI2 (pin 69), AMCLKI3 (pin 75), AMCLKI4S (pin 76)
*4
CMOS input pin with built-in pull-down resistance
I2CADR1 (pin 6), I2CADR2 (pin 7)
*5
CMOS output pin
SDA (pin 4), ERROR (pin 39), DATAOC (pin 42), BCKOC (pin 43), LRCKOC (pin 44), DATAOB (pin 45),
BCKOB (pin 46), LRCKOB (pin 47), DATAOA (pin 48), BCKOA (pin 49), LRCKOA (pin 50), XO (pin 61),
AMCLKI4S (pin 76), AMCLKOA (pin 77), AMCLKOB (pin 78), AMCLKOC (pin 79)
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© 2012 ROHM Co., Ltd. All rights reserved.
2/34
2012.03 - Rev.A
Technical Note
BU9406KS2
●Electrical Characteristics (Analog system)
VDD=3.3V (Unless otherwise specified Ta=25℃, RL=10kΩ, Standard VC)
Standard Values
Item
Symbol
Unit
Min.
Typ.
Max.
Total
Circuit Current
Regulator
Output Voltage
PLL_ASRC
Lock Frequency
(8 times frequency multiplier)
Sigma-delta audio ADC
Maximum Input Amplitude
Distortion rate(THD+N)
S/N
Input Impedance
Sigma-delta audio DAC
Maximum Output Amplitude
Distortion rate(THD+N)
S/N
16bit DAC Section
Maximum Output Amplitude
Distortion rate(THD+N)
S/N
Applicable Pins/Conditions
DVDDIO1,DVDDIO2,DVDDIO3,DVDDREG
,
DVDDPLL,AVDDAD1,ADVDDAD2,
AVDDDA1,AVDDDAR2,AVDDDAL2,
AVDDDAR3,AVDDDAL3
IQ
-
60
90
mA
VREG
-
1.5
-
V
FLK8
-
24.576
-
MHz
BCK=3.072MHz (fs=48kHz)
VIMAX
THDAD
S/NAD
RI
42
0.02
90
60
0.7
0.05
78
Vrms
%
dB
kΩ
1kHz, -0.5dB
AIN=0.7Vrms,1kHz,A-weighted
VOMAX
THDDA
S/NDA
0.63
-
0.75
0.005
96
0.86
0.03
-
Vrms
%
dB
0dB,1kHz
0dB,1kHz,A-weighted
VOMAX
THDDA
S/NDA
0.65
-
0.77
0.03
90
0.88
-
Vrms
%
dB
0dB,1kHz
0dB,1kHz,A-weighted
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© 2012 ROHM Co., Ltd. All rights reserved.
3/34
IO=100mA
2012.03 - Rev.A
Technical Note
BU9406KS2
XI
DGNDIO1
DATAI3
LRCKI2
BCKI2
DATAI2
LRCKI1
BCKI1
DATAI1
LRCKOA
DVDDCOR2
BCKOA
DATAOA
LRCKOB
BCKOB
DATAOB
LRCKOC
BCKOC
DATAOC
DGNDIO3
●Block diagram
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
XO 61
40 DVDDIO3
DVDDIO1 62
39 ERROR
I/F Logic
Clock Gen.
BCKI3 63
38 AVDDDAL3
37 AOUTL3
LRCKI3 64
Data RAM
Coef. RAM
DATAI4 65
ASRC
ΔΣ
Stereo
DAC
BCKI4 66
36 AGNDDAL3
35 VREFDA3
34 AGNDDAR3
LRCKI4 67
AMCLKI1 68
x8 Over
Sampling
Digital Filter
DSP
AMCLKI2 69
33 AOUTR3
32 AVDDDAR3
DVDDCOR１ 70
31 AVDDDAL2
x8 Over
Sampling
Digital Filter
REG15 71
DVDDREG 72
LDO
15
LDOPOFF 73
DSP Program
Logic
(G/A)
DGNDREG 74
30 AOUTL2
ΔΣ
Stereo
DAC
x8 Over
Sampling
Digital Filter
29 AGNDDAL2
28 VREFDA2
27 AGNDDAR2
26 AOUTR2
AMCLKI3 75
AMCLKI4S 76
25 AVDDDAR2
AMCLKOA 77
Monitor
&
Command
I/F
AMCLKOB 78
PLL_ASRC
I/F
Logic
16bit
Stereo
DAC
Stereo
ADC
PLL_ASRC
24 AVDDDA1
23 AOUTL1
AMCLKOC 79
22 AOUTR1
21 AGNDDA1
I2CADR1
I2CADR2
RESETB
13
14
15
16
17
18
19
20
AVDDAD2
SCL
12
AGNDAD2
SDA
11
AINR
SCANTEST
10
VREFAD
MODE
9
AINL
8
AGNDAD1
7
AVDDAD1
6
ANATEST
5
FILT2
4
DGNDPLL
3
FILT1
2
DVDDPLL
1
DGNDIO2
DVDDIO2 80
Fig.2 Block diagram
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© 2012 ROHM Co., Ltd. All rights reserved.
4/34
2012.03 - Rev.A
Technical Note
BU9406KS2
●Pin Description(s)
Type
－
A
A
No.
41
42
43
Name
DGNDIO3
DATAOC
BCKOC
I2C data I/O pin
D
44
LRCKOC
SCL
I2CADR1
I2C transfer clock input pin
I2C slave address select pin 1
D
B
45
46
DATAOB
BCKOB
7
I2CADR2
I2C slave address select pin 2
B
47
LRCKOB
8
9
RESETB
DVDDPLL
“L” -> Reset condition
PLL power supply
C
－
48
49
DATAOA
BCKOA
10
FILT1
connect G
50
DVDDCOR2
11
DGNDPLL
PLL_ASRC
terminal 1
PLL GND
－
51
LRCKOA
12
FILT2
52
DATAI1
13
14
ANATEST
AVDDAD1
PLL_ASRC
filter
connect G
terminal 2
Analog test mode select pin
G
Audio ADC power supply 1
－
53
54
BCKI1
LRCKI1
15
16
17
AGNDAD1
AINL
VREFAD
Audio ADC GND 1
Analog signal Lch input pin
ADC reference voltage pin
－
G
G
55
56
57
DATAI2
BCKI2
LRCKI2
18
19
20
21
22
23
24
AINR
AGNDAD2
AVDDAD2
AGNDDA1
AOUTR1
AOUTL1
AVDDDA1
Analog signal Rch input pin
Audio ADC GND 2
Audio ADC power supply 2
Audio DAC GND 1
Audio DAC Rch output pin 1
Audio DAC Lch output pin 1
Audio DAC power supply 1
G
－
－
－
G
G
－
58
59
60
61
62
63
64
DATAI3
DGNDIO1
XI
XO
DVDDIO1
BCKI3
LRCKI3
25
26
27
AVDDDAR2
AOUTR2
AGNDDAR2
Audio DAC Rch power supply 2 －
Audio DAC Rch output pin 2
G
Audio DAC Rch GND 2
－
65
66
67
DATAI4
BCKI4
LRCKI4
28
29
30
31
32
33
VREFDA2
AGNDDAL2
AOUTL2
AVDDDAL2
AVDDDAR3
AOUTR3
DAC reference voltage 2
G
Audio DAC Lch GND 2
－
Audio DAC Lch output pin 2
G
Audio DAC Lch power supply 2 －
Audio DAC Rch power supply 3 －
Audio DAC Rch output pin3
G
68
69
70
71
72
73
AMCLKI1
AMCLKI2
DVDDCOR1
REG15
DVDDREG
LDOPOFF
34
35
36
AGNDDAR3
VREFDA3
AGNDDAL3
Audio DAC Rch GND 3
DAC reference voltage 3
Audio DAC Lch GND 3
－
G
－
74
75
76
DGNDREG
AMCLKI3
AMCLKI4S
37
38
39
AOUTL3
AVDDDAL3
ERROR
G
－
D
77
78
79
AMCLKOA
AMCLKOB
AMCLKOC
40
DVDDIO3
Audio DAC Lch output pin 3
Audio DAC Lch power supply 3
Sampling frequency input error
pin
Digital I/O power supply 3
I2S audio bit transfer clock input 1
I2S audio LR sampling clock input
1
I2S audio data input 2
I2S audio bit transfer clock input 2
I2S audio LR sampling clock input
2
I2S audio data input 3
Digital I/O GND1
X’tal connecting (input) terminal
X’tal connecting terminal
Digital I/O power supply 1
I2S audio bit transfer clock input 3
I2S audio LR sampling clock input
3
I2S audio data input 4
I2S audio bit transfer clock input 4
I2S audio LR sampling clock input
4
I2S synchronous clock input 1
I2S synchronous clock input 2
Connects with REG15 Pin
Built in regulator voltage output
Power supply for built in regulator
Power off signal input for
regulator
GND for built in regulator
I2S synchronous clock input 3
I2S synchronous clock Input 4 or
S/PDIF output
I2S synchronous clock output A
I2S synchronous clock output B
I2S synchronous clock output C
－
80
DVDDIO2
Digital I/O power supply 2
No.
1
2
3
Name
DGNDIO2
MODE
SCANTEST
Description of terminals
Digital I/O GND2
Test mode select pin
Digital test mode select pin
4
SDA
5
6
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© 2012 ROHM Co., Ltd. All rights reserved.
filter
5/34
Description of terminals
Digital I/O GND 3
I2S audio data output C
I2S audio bit transfer clock output
C
I2S audio LR sampling clock
output C
I2S audio data output B
I2S audio bit transfer clock output
B
I2S audio LR sampling clock
output B
I2S audio data output A
I2S audio bit transfer clock output
A
Connects with REG15 Pin
Type
－
D
D
D
D
D
D
D
D
－
I2S audio LR sampling clock D
output A
I2S audio data input 1
E
E
E
E
E
E
E
－
F
F
－
E
E
E
E
E
E
E
－
G
－
G
－
E
E
D
D
D
－
2012.03 - Rev.A
Technical Note
BU9406KS2
● Pin Equivalent Circuit Diagrams
A
B
DVDDIO
C
DVDDIO
DVDDIO
DGNDIO
D
DVDDIO
DGNDIO
DGNDIO
E
F
DVDDIO
DVDDIO
XI
DGNDIO
DGNDIO
DGNDIO
DVDDIO
XO
DGNDIO
G
AVDD,DVDDIO
AGND,DGNDIO
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© 2012 ROHM Co., Ltd. All rights reserved.
6/34
2012.03 - Rev.A
Technical Note
BU9406KS2
1.
Command Interface
BU9406KS2 uses the I2C bus format for the command interface with the host CPU.
With BU9406KS2, in addition to write mode, read mode read-out is possible with many registers.
BU9406KS2 assigns a 1-byte select address in addition to the slave address and performs write-in and read-out.
2
The I C bus slave mode format is as follows:
S
MSB
LSB
Slave Address
A
MSB
Select Address
LSB
MSB
Data
A
LSB
A
P
S: Start Condition
Slave Address:
Adds either a read mode (H”) or write mode (L”) bit to the slave address (7bit) configured by
I2CADR1 and I2CADR2, sending a total of 8 bits of data. (MSB first)
A: Acknowledge An acknowledge bit is added on to each bit of data transmitted.
When data transmission is being done correctly, “L” is transmitted.
“H” transmission means there was no acknowledge.
Select Address:
BU9406KS2 uses a 1-byte select address. (MSB first)
Data:
Data byte, transmitted data (MSB first)
P:
Stop condition
MSB
SDA
6
5
LSB
SCL
Start Condition
When SDA↓ , SCL=”H”
Stop Condition
When SDA↑ , SCL=”H”
1-1. Data Write-In
S
Slave Address
A
Select Address
A
Data
A
: Master to Slave
MSB
A6
1
A5
0
A4
0
S Slave Address
(Ex.)
80h
A3
0
A
A2
0
A1
0
A0
0
Select Address
20h
A
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© 2012 ROHM Co., Ltd. All rights reserved.
LSB
R/W
0
Data
: Slave to Master
Slave Address Configuration for BU9406KS2
Pin Configuration
Write Mode
Slave
Address
I2CADR2
I2CADR1
0
0
80h
0
1
82h
1
0
84h
1
1
86h
A Data
00h
00h
: Master to Slave
7/34
P
A
Data
A
P
00h
: Slave to Master
2012.03 - Rev.A
Technical Note
BU9406KS2
Write-in Procedure
Step
Clock
1
Master
Slave(BU9406KS2)
Note
Start Condition
2
7
Slave Address
3
1
R/W (0)
4
1
5
8
6
1
7
8
8
1
9
&h80 (&h82, &h84, &h86)
Acknowledge
Select Address
Write-in target register: 8bit
Acknowledge
Data
8bit write-in data
Acknowledge
Stop Condition
○When transmitting continuous data, the auto-increment function moves the select address up by one.
Repeat steps 7 and 8.
1-2. Data Read-out
During read-out, the corresponding read-out address is first written into the &hD0 address register (&h20h in the example).
In the following stream, the data is read out after the slave address. Do not return an acknowledge after completing the
reception.
S Slave Address
A Request Address A Select Address
A P
（ex.）
S
80h
Slave Address
（ex.）
D0h
A
20h
Data 1
81h
A
Data 2
**h
A
A
Data N
**h
Ā
P
**h
: Slave to Master, A: With acknowledge, Ā: Without acknowledge
: Master to Slave,
Read-out Procedure
Step
Clock
1
Master
Slave(BU9406KS2)
Start Condition
2
7
Slave Address
3
1
R/W (0)
4
1
5
8
6
1
7
8
8
1
9
1
Stop Condition
10
1
Start Condition
&h80 (&h82, &h84, &h86)
Acknowledge
I2C read-out address
Request Address
&hD0
Acknowledge
Select Address
Read-out target register: 8bit
Acknowledge
11
7
Slave Address
12
1
R/W (1)
13
1
Acknowledge
14
8
Data
15
1
16
Note
&h81 (&h82, &h85, &h87)
8bit read-out data
Acknowledge
Stop Condition
○When transmitting continuous data, the auto-increment function moves up the select address by one.
Repeat steps 14 and 15.
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8/34
2012.03 - Rev.A
Technical Note
BU9406KS2
1-3. Control Signal Specifications
○ Electrical Characteristics and Timing for Bus Line and I/O Stage
SDA
t
BUF
tF
tLOW
tHD;STA
tR
SCL
t
HD;STA
P
tHIGH
t
HD;DAT
tSU;DAT
tSU;STA
S
tSU;STO
Sr
P
Fig.1-1: Timing Chart
Chart 1-1: SDA and SCL Bus Line Characteristics (Unless specified, Ta=25℃ and VDD=3.3V)
Parameters
1
2
Symbol
Max.
0
400
kHz
BUF
1.3
－
μS
HD;STA
0.6
－
μS
LOW
1.3
－
μS
HIGH
0.6
－
μS
SU;STA
0.6
－
μS
HD;DAT
1)
0
－
μS
100
－
ns
SCL clock frequency
fSCL
Bus free time between “stop” condition and
t
Hold time (re-transmit) “start” condition.
t
After this period, the first clock pulse is generated.
4
5
6
7
8
Unit
Min.
“start” condition
3
High-Speed Mode
SCL clock LOW state hold time
t
SCL clock HIGH state hold time
t
Re-transmit set-up time of “start” condition
t
Data hold time
t
Data setup time
t
SU;DAT
9
SDA and SCL signal stand-up time
t
R
20+Cb
300
ns
10
SDA and SCL signal stand-down time
t
F
20+Cb
300
ns
11
Set-up time for “stop” condition
SU;STO
0.6
－
μS
12
Each bus line’s capacitive load
Cb
－
400
pF
t
The values above correspond with VIH min and VIL max levels.
1)
Because the transmission device exceeds the undefined domain of the SCL fall edge, it is necessary to internally
provide a minimum 300ns
hold time for the SDA signal (of VIH min of SCL signal).
The characteristics above are logical values for design; guarantees in the form of delivery inspections are not offered.
In the event of a problem, comprehensive consultation and support will be provided.
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© 2012 ROHM Co., Ltd. All rights reserved.
9/34
2012.03 - Rev.A
Technical Note
BU9406KS2
2.
Data and Clock Switching
Below is the in/output system diagram for BU9406KS2.
Audio DSP
(BU9406KS2)
ADC
ASRC
I2S S-P
Conve
rsion1
SEL10
I2S OUT A
DATAOA,
BCKOA,
LRCKOA
AMCLK
OUT C
AMCLK IN4
SEL9
AMCLKOC
AMCLK IN3
SEL8
AMCLK OUT B
AMCLKI3
AMCLKI4S
S 3-State
E
L
7
AMCLK OUT A
AMCLKI2
AMCLK IN2
AMCLKOA
AMCLK IN1
AMCLKOB
AMCLKI1
②
P-S
Conve
rsion1
CG
Control I/F
RESET
I2S_IN_
SEL2
DATAI4,BCKI4,LRCKI4
S-P
I2S Conve
rsion2
PLL2
I2C
I2S IN4
S
E
L
6
EVR
DSP CLK
I2S IN3
DATAI3,BCKI3,LRCKI3
I2S OUT B
I2S IN2
DATAI2,BCKI2,LRCKI2
Parame
tric EQ
I2S
OUT C
P-S
Conve
rsion2
SPDIF
Conver
sion
S
E
L
11
S/PDIF
DATAOC,BCKOC,LRCKOC
AMCLKI4S
④
S
E
L
3
DF1
S
E
L
4
S
E
L
5
ΔΣ SP OUT
DAC1
AOUTL3,AOUTR3
DF2
ΔΣ LINE OUT
DAC2
AOUTL2,AOUTR2
DF3
⑥ 16bit REC OUT
DAC
AOUTL1,AOUTR1
⑤
・・・
DATAOB,
BCKOB,
LRCKOB
I2S IN1
Func.
Main
S
E
L
2
S
E
L
1
PLL1
DATAI1,BCKI1,LRCKI1
AGC
SYS CLK
Analog IN
This section is actualized by hardware.
I2S_IN_SEL1
AINL,AINR
DSP Computing Section
③
①
BU9406KS2 has a 4-line digital stereo input, 1-line analog stereo input, 4-line digital stereo output and 3-line analog stereo
output.
The digital data input to the DSP computing section is first changed to fs=48kHz data at the ASRC (asynchronous sampling
rate converter).
DSP computing section output is changed to either I2S format digital output, S/PDIF format digital serial output or analog
output.
2-1. ASRC Input Selection (SEL1）
Default = 0
Select Address
Value
Operation Description
&h03 [ 5：4 ]
0
Inputs analog signals converted to digital data
1
Inputs via S-P conversion 1 (refer to &h05[5:4])
2
Inputs via S-P conversion 2 (refer to &h05[1:0])
2
S-P conversions 1 and 2 convert I C format serial data to 24bit parallel data.
2-2. DF1 Input Selection (SEL1, SEL2, SEL3)
Default = 0
Select Address
Value
&h03 [ 2：0 ]
0
Inputs analog signals converted to digital data
1
Inputs via S-P conversion 1 (refer to &h05[5:4])
2
Inputs via S-P conversion 2 (refer to &h05[1:0])
3
Inputs data before DSP processing
4
Inputs data after DSP processing
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Operation Description
10/34
2012.03 - Rev.A
Technical Note
BU9406KS2
2-3. DF2 Input Selection (SEL1, SEL2, SEL4)
Default = 0
Select Address
Value
Operation Description
&h04 [ 6：4 ]
0
Inputs analog signals converted to digital data
1
Inputs via S-P conversion 1 (refer to &h05[5:4])
2
Inputs via S-P conversion 2 (refer to &h05[1:0])
3
Inputs data before DSP processing
4
Inputs data after DSP processing
2-4. DF3 Input Selection (SEL1, SEL2, SEL5)
Default = 0
Select Address
Value
Operation Description
&h04 [ 2：0 ]
0
Inputs analog signals converted to digital data
1
Inputs via S-P conversion 1 (refer to &h05[5:4])
2
Inputs via S-P conversion 2 (refer to &h05[1:0])
3
Inputs data before DSP processing
4
Inputs data after DSP processing
2-5. S-P Conversion 1 Input Selection (SEL6）
Default = 0
Select Address
Value
Operation Description
&h05 [ 5：4 ]
0
Inputs data from I2S_IN1
1
Inputs data from I2S_IN2
2
Inputs data from I2S_IN3
3
Inputs data from I2S_IN4
2-6. S-P Conversion 2 Input Selection (SEL6)
Default = 0
Select Address
Value
Operation Description
&h05 [ 1：0 ]
0
Inputs data from I2S_IN1
1
Inputs data from I2S_IN2
2
Inputs data from I2S_IN3
3
Inputs data from I2S_IN4
2-7. Clock Output Selection (SEL&) to AMCLKOA Pin
Default = 0
Select Address
Value
&h06 [ 6：4 ]
0
Outputs Hi-z
1
Outputs 256fs (12.288MHz) clock used in DSP
2
Outputs clock from AMCLK_IN1
3
Outputs clock from AMCLK_IN2
4
Outputs clock from AMCLK_IN3
5
Outputs clock from AMCLK_IN4
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Operation Description
11/34
2012.03 - Rev.A
Technical Note
BU9406KS2
2-8. Clock Output Selection to AMCLKOB Pin (SEL7)
Default = 0
Select Address
Value
Operation Description
&h06 [ 2：0 ]
0
Outputs Hi-z
1
Outputs 256fs (12.288MHz) clock used in DSP
2
Outputs clock from AMCLK_IN1
3
Outputs clock from AMCLK_IN2
4
Outputs clock from AMCLK_IN3
5
Outputs clock from AMCLK_IN4
2-9. Clock Output Selection to AMCLKOC Pin (SEL8)
Default = 0
Select Address
Value
&h07 [ 5：4 ]
0
Outputs 256fs (12.288MHz) clock used in DSP
1
Outputs 256fs clock extracted by S-P conversion 1 PLL1
2
Outputs 256fs clock extracted by S-P conversion 2 PLL2
Operation Description
2-10. Output Selection to DATAOA Pin (SEL6, SEL9)
Default = 0
Select Address
Value
&h08 [ 6：4 ]
0
Outputs data from I2S_IN1
Operation Description
1
Outputs data from I2S_IN2
2
Outputs data from I2S_IN3
3
Outputs data from I2S_IN4
4
Outputs data from P-S conversion 1 (refer to &h09[7])
P-S conversion 1 converts 24bit parallel data to I2C format serial data.
2-11. Output Selection to DATAOB Pin (SEL6, SEL9)
Default = 0
Select Address
Value
&h08 [ 2：0 ]
0
Outputs data from I2S_IN1
Operation Description
1
Outputs data from I2S_IN2
2
Outputs data from I2S_IN3
3
Outputs data from I2S_IN4
4
Outputs data from P-S conversion 1 (refer to &h09[7])
2-12. Output Selection to DATAOC Pin (SEL2)
Default = 0
Select Address
Value
&h09 [ 4 ]
0
Inputs data before DSP processing
1
Outputs data after DSP processing
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
12/34
2012.03 - Rev.A
Technical Note
BU9406KS2
2-13. Input Selection to P-S Conversion 1 (SEL10)
Default = 0
Select Address
Value
&h09 [ 7 ]
0
Outputs data from AD conversion
1
Outputs data after conversion to fs=48kHz at ASRC
Operation Description
2-15. Output Selection When Configuring AMCLK4S Pin to S/PDIF Output (SEL2, SEL6, SEL11)
Default = 0
2-16.
Select Address
Value
Operation Description
&h09 [ 2：0 ]
0
Inputs data before DSP processing
1
Outputs data after DSP processing
2
Outputs data from I2S_IN1 (Only output data in S/PDIF format)
3
Outputs data from I2S_IN2 (Only output data in S/PDIF format)
4
Outputs data from I2S_IN3 (Only output data in S/PDIF format)
5
Outputs data from I2S_IN4 (Only output data in S/PDIF format)
AMCLK4S Pin In/Output Switching (SEL2)
Default = 0
Select Address
Value
&h09 [ 3 ]
0
Clock input
Operation Description
1
S/PDIF data output (refer to &h11, &h12 and &h13)
There are three types of system clocks used by the DSP or DF+DAC sections of BU9406KS2.
One is the 24.576MHz (512fs) system clock from the XI pin, and the other two are 512fs clocks generated by PLL1
andPLL2 from the input clocks BCKI1~3.
2-17. System Clock Selection of ASRC Input Section (used for up-sampling) (Dotted line ①)
Default = 0
Select Address
Value
Operation Description
&h0A [ 7：6 ]
0
24.576MHz (512fs) system clock from XI pin
1
512fs clock extracted from S-P conversion 1 PLL1
2
512fs clock extracted from S-P conversion 2 PLL2
2-18. System Clock Selection for ASRC Output Section (used for down-sampling), P-S Conversion 2 and S/PDIF Output
(Dotted line ③)
Default = 0
Select Address
Value
Operation Description
&h0A [ 1：0 ]
0
24.576MHz (512fs) system clock from XI pin
1
512fs clock extracted from S-P conversion 1 PLL1
2
512fs clock extracted from S-P conversion 2 PLL2
2-19. System Clock Selection for P-S Conversion 1 (Dotted line ②)
Default = 0
Select Address
Value
&h0A [ 5：4 ]
0
24.576MHz (512fs) system clock from XI pin
1
512fs clock extracted from S-P conversion 1 PLL1
2
512fs clock extracted from S-P conversion 2 PLL2
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Operation Description
13/34
2012.03 - Rev.A
Technical Note
BU9406KS2
2-20. System Clock Selection of DF1 and ΔΣDAC１ (Dotted line ④)
Default = 0
Select Address
Value
Operation Description
&h0B[ 7：6 ]
0
24.576MHz (512fs) system clock from XI pin
1
512fs clock extracted from S-P conversion 1 PLL1
2
512fs clock extracted from S-P conversion 2 PLL2
2-21. System Clock Selection of DF2 and ΔΣDAC2 (Dotted line ⑤)
Default = 0
Select Address
Value
Operation Description
&h0B[ 5：4 ]
0
24.576MHz (512fs) system clock from XI pin
1
512fs clock extracted from S-P conversion 1 PLL1
2
512fs clock extracted from S-P conversion 2 PLL2
2-22. System Clock Selection of DF3 and 16bit DAC (Dotted line ⑥)
Default = 0
Select Address
Value
&h0B[ 3：2 ]
0
24.576MHz (512fs) system clock from XI pin
1
512fs clock extracted from S-P conversion 1 PLL1
2
512fs clock extracted from S-P conversion 2 PLL2
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Operation Description
14/34
2012.03 - Rev.A
Technical Note
BU9406KS2
3.
S-P Conversion 1 and S-P Conversion 2
BU9406KS2 has two built-in serial-parallel conversion circuits. (S-P Conversion 1 and S-P Conversion 2)
S-P conversions 1 and 2 are blocks which receive 3-line serial input audio data from pins and convert it to parallel data.
Input from DATAI1, BCKI1 and LRCKI1 (pins 52,53 and 54), DATAI2, BCKI2 and LRCKI2 (pins 55, 56, and 57), DATAI3,
BCKI3 and LRCKI3 (pins 58, 63 and 64), and DATAI4, BCKI4 and LRCKI4 (pins 65, 66 and 67) are selected.
The three input formats are IIS, left-justified and right-justified.
The bit clock frequency may be selected from either 64fs or
48fs, but when 48fs is selected, the input format is always right-justified.
16bit, 20bit and 24bit output may be selected for
each format.
Below are the timing charts for each transfer format.
IIS Format
LRCKI
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
DATAI
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
LSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
S
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Left-Justified Format
LRCKI
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
DATAI
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
S
15
16
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Right-Justified Format
LRCKI
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MSB
DATAI
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LSB
MSB
S
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
48fs
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MSB
DATAO
18
19
20
21
22
23
24
1
2
3
4
5
6
7
LSB
8
9
10
11
12
13
14
15
16
17
MSB
S
18
19
20
21
22
23
24
LSB
S
16bit
16bit
20bit
20bit
24bit
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© 2012 ROHM Co., Ltd. All rights reserved.
24bit
15/34
2012.03 - Rev.A
Technical Note
BU9406KS2
3-1. Input Selection for S-P Conversions 1 and 2
Default = 0
Select Address
Value
Operation Description
S-P Conversion 1 &h05[5:4]
0
Input data from I2S_IN1
S-P Conversion 2 &h05[1:0]
1
Input data from I2S_IN2
2
Input data from I2S_IN3
3
Input data from I2S_IN4
3-2. Bit Clock Frequency Configuration for 3-line Serial Input
Default = 0
3-3.
Select Address
Value
Operation Description
S-P Conversion 1 &h0C [4]
0
64fs format
S-P Conversion 2 &h0D [4]
1
48fs format
Format Configuration for 3-line Serial Input
Default = 0
3-4.
Select Address
Value
Operation Description
S-P Conversion 1 &h0C[3:2]
0
IIS format
S-P Conversion 2 &h0D[3:2]
1
Left-justified format
2
Right-justified format
Data Bit Width Configuration for 3-line Serial Input
Default = 0
Select Address
Value
S-P Conversion 1 &h0C[1:0]
0
16 bit
S-P Conversion 2 &h0D[1:0]
1
20 bit
2
24 bit
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
16/34
2012.03 - Rev.A
Technical Note
BU9406KS2
4.
Digital Sound Processing (DSP)
BU9406KS2’s digital sound processing (DSP) section is constructed with specific hardware optimal for FPD TVs.
BU9406KS2 uses this special DSP to perform the following processes:
2
2
Pre-scaler, Channel Mixer, Pseudo-Stereo, Surround, P 2Bass, P2Treble, Parametric Equalizer,
EVR & Balance, Compression, Post-scaler, Clipper
4-1. Overview and Signal Flow of DSP Section
Data
RAM
Word length:
28 bit (DATA RAM)
Machine Cycle:
40.7ns
Multiplier:
28×24 → 52 bit
MUX
(512fs, fs=48kHz)
Adder:
28＋28 → 28 bit
Data RAM:
256×28 bit
Coefficient RAM:
128×24 bit
0
Coefficient
M
U
X
MUX
Sampling Frequency:fs=48kHz
Master Clock:
Input
RAM
Decoder
Circuit
ADD
512fs (24.576MHz, fs=48kHz)
Acc
16bit and 24bit digital signals are input to the DSP, but there is an
Output
overflow margin of +4bit (+24dB) on the top side.
For processes that exceed this range, there is a clipping process within the DSP.
PreScaler
Input
Channel
Mixer
Pseudo
Stereo
Surround
P2Bass
Parametric
P2Treble
EQ
EVR
＆
Balance
Compressi
on
PostScaler
Clipper
Output
Digital Audio Processing Signal Flow
4-2. Pre-Scaler
When the digital signals are input to the sound DSP the level may be full-scale input, causing overflow from surround or
equalizer treatment, so the pre-scaler adjusts the input gain.
Analog signals are changed to digital values with the A/D converter, and the gain can be adjusted with the pre-scaler even
when the input level is low.
The adjustment range can be configured in 2dB increments from +16dB to -44dB.
Default = 00
Select Address
&h20 [ 4：0 ]
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
Command Value
Gain
Command Value
Gain
Command Value
Gain
Command Value
Gain
00
01
02
03
04
05
06
07
0dB
-2dB
-4dB
-6dB
-8dB
-10dB
-12dB
-14dB
08
09
0A
0B
0C
0D
0E
0F
-16dB
-18dB
-20dB
-22dB
-24dB
-26dB
-28dB
-30dB
10
11
12
13
14
15
16
17
-32dB
-34dB
-36dB
-38dB
-40dB
-42dB
-44dB
-∞
18
19
1A
1B
1C
1D
1E
1F
+16dB
+14dB
+12dB
+10dB
+8dB
+6dB
+4dB
+2dB
17/34
2012.03 - Rev.A
Technical Note
BU9406KS2
4-3. Channel Mixer
Performs the mixing configuration of the left and right channel sounds of digital signals input to the sound DSP.
Stereo signals can be changed to monaural here.
Mixes DSP Lch input data.
Default = 0
Select Address
Value
Operation Description
&h2A [ 7：6 ]
0
Inputs Lch data
1
Inputs (Lch+Rch)/2 data
2
Inputs (Lch+Rch)/2 data
3
Inputs Rch data
Mixes DSP Rch input data.
Default = 0
Select Address
Value
Operation Description
&h2A [ 5：4 ]
0
Inputs Rch data
1
Inputs (Lch+Rch)/2 data
2
Inputs (Lch+Rch)/2 data
3
Inputs Lch data
4-4. Pseudo-Stereo 2
Recreates stereo feel in monaural sound through signal treatment.
The quality of this pseudo-stereo treatment is higher than that of the pseudo-stereo of “5-5 Surround and Pseudo-Stereo 1”.
Selection of Pseudo-Stereo 2 Filter Effect
Default = 0
Select Address
Value
Operation Description
&h71 [ 1：0 ]
0
Pseudo-stereo OFF
1
Effect configured to “weak”
2
Effect configured to “strong”
Sound is further enhanced when used together with surround (&h70[7]=1).
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2012.03 - Rev.A
Technical Note
BU9406KS2
4-5. Surround (Matrix Surround 3D) and Pseudo-Stereo 1
Actualizes surround sound with a vast sweet spot, which allows longer viewing with less fatigue.
Recreates natural mid- and high-range sound, actualizing sound field that does not take away from the stability of the vocal.
Using the loop function simulates extra steps of the phase shifter.
Turning Surround Function ON/OFF
Default = 0
Select Address
Value
&h70 [ 7 ]
0
Turns surround effect OFF
Operation Description
1
Turns surround effect ON
Turning Pseudo-Stereo Function 1 ON/OFF (Different function from 5-4 pseudo-stereo 2)
Default = 0
Select Address
Value
Operation Description
&h70 [ 6 ]
0
Turns pseudo-stereo effect OFF
1
Turns pseudo-stereo effect ON
Loop Usage Configuration
Default = 0
Select Address
Value
Operation Description
&h70 [ 5 ]
0
Loop OFF
1
Loop ON
Delay Length Configuration in Loop use
Default = 0
Select Address
Value
&h71 [ 7：6 ]
0
1 sample
1
64 samples
2
128 samples
3
255 samples
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Operation Description
19/34
2012.03 - Rev.A
Technical Note
BU9406KS2
Surround Gain Configuration
Default = 0
Select Address
&h70 [ 3：0 ]
Operation Description
Command Value
Gain
Command Value
Gain
0
1
2
3
4
5
6
7
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
8
9
A
B
C
D
E
F
-8dB
-9dB
-10dB
-11dB
-12dB
-13dB
-14dB
-15dB
Simultaneous use of surround (Matrix Surround 3D) and pseudo-stereo 1 will not produce optimal results.
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2012.03 - Rev.A
Technical Note
BU9406KS2
4-6. P2Bass (Perfect Pure Bass: Deep Bass Equalizer)
The deep bass equalizer recreates dynamic bass and realistic sound, even with FPD TVs which have limited speaker
enclosure.
It actualizes clear, heavy bass with low distortion. Rich and natural bass is obtained, and the vocal range is not affected
even when with bass boost.
Gain
Vocal range
P2Bass Gain
f
LPF cut-off frequency
HPF cut-off frequency
2
Turning P Bass Function ON/OFF
Default = 0
Select Address
&h72 [ 7 ]
Value
Operation Description
2
0
P Bass function OFF
1
P2Bass function ON
2
P Bass HPF Cut-off Frequency Configuration
Default = 0
Select Address
Value
Operation Description
&h72 [ 3：2 ]
0
60Hz
1
80Hz
2
100Hz
3
120Hz
2
P Bass LPF Cut-off Frequency Configuration
Default = 0
Select Address
Value
Operation Description
&h72 [ 1：0 ]
0
120Hz
1
160Hz
2
200Hz
3
240Hz
2
P Bass Deep Bass Gain Configuration
Default = 0
Select Address
&h73 [ 6：4 ]
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
Command Value
Gain
Command Value
Gain
0
1
2
3
+6dB
+7dB
+8dB
+9dB
4
5
6
7
+10dB
+11dB
+12dB
+13dB
21/34
2012.03 - Rev.A
Technical Note
BU9406KS2
4-7. P2Treble (Perfect Pure Treble: Mid-/High-range equalizer）
Actualizes clear, crisp and extensive sound.
With sets which have speakers placed near the bottom, the effect will allow the sound to feel “lifted”.
Turning P2Treble Function ON/OFF
Default = 0
Select Address
Value
Operation Description
&h72 [ 6 ]
0
SAS function OFF
1
SAS function ON
2
P Treble Mid-/High-Range Gain Configuration
Default = 0
Select Address
Operation Description
&h73 [ 3：0 ]
Command Value
Gain
Command Value
Gain
0
1
2
3
4
5
6
7
+1dB
+2dB
+3dB
+4dB
+5dB
+6dB
+7dB
+8dB
8
9
A
B
C
D
+9dB
+10dB
+11dB
+12dB
+13dB
+14dB
E
+15dB
4-8. Parametric Equalizer
BU9406KS2 has a 2-channel, 12-band parametric equalizer. This is used either to control bass and treble or as an
equalizer to improve the frequency characteristics of speakers.
Data Width:
28 bit
Coefficient: :
24 bit (-4~+4)
The first 5 bands configure common coefficients for both Lch and Rch. They are used chiefly to control tone.
The latter 7 bands are used as independent parametric equalizers for Lch and Rch.
There is a built-in soft transition function to change the audio characteristics while sound is being played back.
The configuration diagrams of Lch and Rch parametric equalizers are on the following page.
Collective Load of Coefficients to Coefficient RAM
Default = 0
Select Address
Value
&h40 [ 7 ]
0
Load stop
Operation Description
1
Load start
Monitor for State of Parametric Equalizer (for read-out)
Select Address
&h46 [ 7 ]
Definition
BUSY signal monitor during coefficient
transition
&h46 [ 6 ]
BUSY monitor during coefficient load
State
Displays “H” during transition
Displays “H” during load
Time Configuration for Soft Transition Completion
Default = 0
Select Address
Value
&h45 [ 5：4 ]
0
21.3ms
（1024fs）
1
42.6ms
（2048fs）
2
10.6ms
（512fs）
3
5.3ms
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
（256fs）
22/34
2012.03 - Rev.A
Technical Note
BU9406KS2
Lch
Coefficient Number
28
Z
-1
Z
-1
+
2D
-1
Z
29
+
+
0
+
+
5
Z
+
+
2
19
Z
+
-1
Z
1A
+
+
Z-1
1B
+
38
+
+
F
C
Z
+
+
+
+
Z-1
+
+
17
Z-1
Z-1
16
18
A
Z-1
24
+
+
26
Z-1
22
C
6C
5
+
Z
21
6B
Z-1
15
13
9
+
Z
+
-1
12
-1
Z-1
20
+
-1
+
+
6A
Z-1
11
-1
69
Z
+
+
Z-1
14
Z-1
E
8
Z
-1
+
Z
10
Z-1
Z
-1
Z
-1
3B
4
+
Z
-1
3A
-1
D
Z-1
+
Z
+
Z
B
+
39
-1
68
-1
23
Z-1
1D
B
35
-1
+
Z
36
3
+
-1
+
Z
1F
+
Z
9
7
+
Z
37
-1
8
-1
1C
Z-1
+
Z-1
1E
-1
+
+
34
Z
7
+
33
-1
+
Z
A
Z-1
4
6
Z
-1
+
-1
+
Z
6
Z-1
Z
-1
Z
-1
31
2
+
Z
-1
30
-1
3
Z-1
+
Z
2F
-1
1
+
Filter Number
-1
32
-1
2C
1
+
Z
2E
Z
+
-1
2B
-1
2A
Z
+
Z-1
25
27
Transition Filter
※Coefficient Numbers and Filter Numbers are hexadecimal
Rch(Latter 7 bands and transition filter coefficients differ from Lch）
Coefficient Number
28
Z
-1
Z
-1
+
Z
+
Z
+
2F
45
+
59
+
5E
-1
Z
5A
+
+
5B
B
5D
Z
-1
Z
Z
-1
+
38
Z
+
4F
Z
+
4C
8
+
+
C
Z
-1
6B
Z-1
6C
5
+
+
Z-1
55
+
+
57
Z-1
56
A
58
Z-1
64
+
+
66
Z-1
62
Z
-1
Z
-1
+
+
Z
Z-1
Z
-1
+
+
6A
53
9
+
69
52
-1
61
Z-1
+
+
Z-1
54
Z
63
-1
+
51
Z
-1
+
-1
4E
Z
-1
Z
-1
3B
4
+
Z
-1
3A
Z
50
Z
+
-1
4D
-1
68
Z
+
+
+
39
-1
+
-1
36
3
+
Z
35
-1
4B
Z
60
37
-1
+
Z
5F
Z-1
+
Z
-1
49
7
+
34
-1
+
Z
33
48
-1
5C
Z-1
+
+
-1
4A
Z
+
-1
+
47
Z
-1
+
-1
44
6
Z
-1
Z
-1
31
2
+
Z
-1
30
Z
46
Z
+
-1
43
-1
42
+
Z
+
+
32
-1
Filter Number
Z
41
Z
2E
-1
+
Z
2C
1
+
-1
2B
Z
40
-1
+
-1
2A
Z
2D
-1
29
-1
+
Z-1
65
67
Transition Filter
※Coefficient Number and Filter Numbers are hexadecimal
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© 2012 ROHM Co., Ltd. All rights reserved.
23/34
2012.03 - Rev.A
Technical Note
BU9406KS2
4-8-1. Parametric EQ Coefficient Configuration Method
① Set &h40[7] to “L”.
② Configure the address (7bits) of the coefficient number to be converted at &h41[6:0].
Configure the data (24bits) at &h42[7:0], &h43[7:0] and &h44[7:0].
③ Set &h40[7] to “H”. Data can be collectively written into the coefficient RAM of the appointed coefficient numbers.
④ The write-in to the coefficient RAM completes when &h46[6] is read out and confirmed to be “L”, or after a 20µs wait.
Afterwards, set &h40[7] to “L”.
⑤ With coefficients, h7FFFFF (maximum value) refers to +4-1LSB and h800000 (minimum value) refers to -4. In addition,
h200000 refers to +1, h00000 refers to 0, and hE00000 refers to -1.
4-8-2. Soft Transition Usage Method During Coefficient Switching of Parametric EQ
① Configure the transition time at &h45[5:4].
② New coefficients are set to the transition filters of two channels. To transit the first 5 bands (same coefficients for both
channels), the same coefficients must be set to the transition filters of both channels.
③ Set the filter number to transit at &h45[3:0]. Transition begins.
④ seni_busy (signal read out at &h46[7]) becomes “H”, and turns to “L” when transition is complete.
⑤ 0 must be set to &h45[3:0] when transition is complete, finishing the soft transition operation.
4-9. EVR (Electrical Volume) and Balance
The volume can be selected in 0.5dB increments from +24dB to -103dB.
Soft transition is performed when volume is changed. It takes approximately 21ms to go from 0dB to mute.
The balance can be decreased in 1dB increments from the volume configuration value. Soft transition is performed at
switch.
Volume Configuration
Default = 00h
Select Address
Operation Description
&h24 [ 7：0 ]
L/R Balance Configuration
Default = 80h
Select Address
Operation Description
Balance Configuration
Command Value
Lch
00
0dB
01
0dB
&h25 [ 7：0 ]
…
…
7E
7F
80
81
0dB
0dB
0dB
-1dB
-1dB
0dB
0dB
0dB
…
…
…
24/34
…
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© 2012 ROHM Co., Ltd. All rights reserved.
Rch
-∞
-126dB
FE
FF
-126dB
-∞
0dB
0dB
2012.03 - Rev.A
Technical Note
BU9406KS2
4-10. Compression
This function automatically adjusts the volume when sound suddenly increases, such as with explosion sounds in TV
commercials or movies, in order to prevent shocking the listener.
AGCONTIME
Input
AGC_MAX
Volume
Output出力
AGC_MIN
AGCOFFTIME
A_RATE
R_RATE
&h21[7] should be set to “H” when the compression function is used.
Default = 0
Select Address
Value
Operation Description
&h21 [ 7 ]
0
Compression function OFF
1
Compression function ON
AGC_MAX is the input level configuration for turning compression ON. It is configured at &h21[6:4].
Default = 0
Select Address
Operation Description
&h26 [ 6：4 ]
When the time and input level configured at AGCONTIME exceeds AGC_MAX, compression is turned ON.
AGCONTIME is configured at &h22[6:4].
Default = 0
Select Address
Operation Description
&h22 [ 6：4 ]
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25/34
2012.03 - Rev.A
Technical Note
BU9406KS2
A_RATE is the configuration for the speed of volume decrease.
It is configured at &h23[6:4].
Default = 0
Select Address
Operation Description
&h23 [ 6：4 ]
AGC_MIN is the configuration for level output when compression is turned ON. It is configured at &h21[2:0].
Default = 0
Select Address
Operation Description
&h21 [ 2：0 ]
When the time and output level configured at AGCOFFTIME goes under AGC_MIN, compression turns OFF.
AGCOFFTIME is configured at &h22[2:0].
Default = 0
Select Address
Operation Description
&h22 [ 2：0 ]
R_RATE is the configuration of the speed of volume increase. It is configured at &h23[3:0].
Default = 0h
Select Address
Operation Description
&h23 [ 3：0 ]
4-11. Post-Scaler
When outputting 28bit-wide data computed by the DSP, the first 4 bits that were added on at input as overflow margin are
removed before the output; however, if the post-scaler is used when the DSP performs a variety of calculations and adjusts
the level for output, the level adjustments are made simpler.
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26/34
2012.03 - Rev.A
Technical Note
BU9406KS2
Default = 0
Select Address
Value
&h26 [ 2：0 ]
0
0dB (removes top 4 bits added on at input)
Operation Description
1
-6dB
2
-12dB
3
-18dB
4
-24dB
4-12. Clipper
The rated output (actual maximum output) of a TV is measured when the combined distortion (THD+N) is at 10%. The
clipper function allows the user to clip the output amplitude freely, for example to get a rated output of 10W or 5W using an
amplifier with 15W output.
Clip Level
Set &h27[7] to “H” when using the clipper function.
Default = 0
Select Address
Value
Operation Description
&h27 [ 7 ]
0
Clipper function OFF
1
Clipper function ON
The clip level is configured at the upper 8 bits &h28[7:0] and lower 8 bits &h29[7:0].
Decreasing the configured value decreases the clip level.
Negative clip level configures the opposite data of positive clip level.
(Note) The clipper function must be used when DSP output is output to DF1, DF2 or DF3.
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© 2012 ROHM Co., Ltd. All rights reserved.
27/34
2012.03 - Rev.A
Technical Note
BU9406KS2
5.
P-S Conversion 1 and P-S Conversion 2
BU9406KS2 has two built-in parallel-serial conversion circuits (P-S Conversion 1 and P-S Conversion 2). P-S conversion 1
converts the output from the AD converter or ASRC to 3-line serial data before sending it from DATAOA, BCKOA and
LRCKOA (pins 48, 49 and 51) or DATAOB, BCKOB and LRCKOB (pins 45, 46 and 47). (Refer to &h08[6:4] and &h08[2:0])
P-S conversion 2 converts the ASRC or DSP output into 3-line serial data before transmitting it from DATAOC, BCKOC and
LRCKOC (pins 42, 43 and 44).
The system clock for P-S conversion 1 is configured at &h0A[5:4], however, when outputting an AD converter, SYSCLK
should be selected. When outputting ASRC, the same selection should be made as with &h0A[1:0].
The three output formats are IIS, left-justified and right-justified. 16bit, 20bit and 24bit output can be selected for each
format.
The timing charts for each transfer format are as follows:
IISIISFormat
Format
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
DATAO
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
LSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
S
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Left-Justified Format
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
DATAO
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
S
15
16
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Right-Justified Format
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSB
DATAO
26
27
28
29
30
31
32
1
LSB
S
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB
LSB
S
16bit
16bit
20bit
20bit
24bit
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© 2012 ROHM Co., Ltd. All rights reserved.
24bit
28/34
2012.03 - Rev.A
Technical Note
BU9406KS2
5-1. P-S Conversion 1 Output Selection
Default = 0
Select Address
Value
Operation Description
&h09 [ 7 ]
0
Outputs AD converter data
1
Outputs data after ASRC
5-2. P-S Conversion 2 Output Selection
Default = 0
Select Address
Value
&h09 [4 ]
0
Outputs data after ASRC (before DSP processing)
Operation Description
1
Outputs data after DSP processing
5-3. P-S Conversion 1 System Clock Selection
Default = 0
5-4.
Select Address
Value
Operation Description
&h0A [ 5：4 ]
0
SYSCLK (512fs)
1
PLL1_512fs
2
PLL2_512fs
3-line Serial Output Format Configuration
Default = 0
5-5.
Select Address
Value
Operation Description
P-S Conversion 1 &h0E[3:2]
0
IIS format
P-S Conversion 2 &h0F[3:2]
1
Left-justified format
2
Right-justified format
3-line Serial Output Data Bit Width Configuration
Default = 0
Select Address
Value
P-S Conversion 1 &h0C[1:0]
0
16 bit
P-S Conversion 2 &h0D[1:0]
1
20 bit
2
24 bit
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
29/34
2012.03 - Rev.A
Technical Note
BU9406KS2
6.
8x Over-Sampling Digital Filter (DF)
In each BU9406KS2 audio analog signal output DAC, an 8x over-sampling digital filter is inserted into the previous step of
the DAC input.
In addition to filter calculations, this block also performs pre-scaler, volume and Lch/Rch mix functions.
BU9406KS2’s DF+DAC configurations are as follows:
DF1
DF2
DF3
Pre-Scaler
Pre-Scaler
Pre-Scaler
Volume
Volume
Volume
Channel Mixer
Channel Mixer
Channel Mixer
8x Over-sampling
Filter
8x Over-sampling
Filter
8x Over-sampling
Filter
ΔΣDAC
ΔΣDAC
16bitDAC
AOUTL3
(37PIN)
AOUTR3
(33PIN)
AOUTL2
(30PIN)
AOUTR2
(26PIN)
AOUTL1
(23PIN)
AOUTR1
(22PIN)
6-1. Pre-Scaler Function
The signal levels are adjusted in order to bring out the audio DAC performance.
For DF1, refer to &h80[7:0] and &h81[7:0]. The default value is h4000.
For DF2, refer to &h83[7:0] and &h84[7:0]. The default value is h4000.
For DF3, refer to &h86[7:0] and &h87[7:0]. The default value is h4000.
6-2. Volume Function
The volume value can be configured in 0.5dB increments from +6dB to -121dB.
To change the volume value, coefficient soft transition takes place. The transition time from 0dB to mute is approximately
21ms.
Default = 0Ch
Select Address
Operation Description
DF1 &h82 [ 7：0 ]
DF2 &h85 [ 7：0 ]
DF3 &h88 [ 7：0 ]
Calculation format: (12-command value)x0.5dB
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30/34
2012.03 - Rev.A
Technical Note
BU9406KS2
6-3. Channel Mixer
Performs mixing configuration of left and right channel sounds of digital signals input to the DAC.
Stereo signals are converted to monaural here.
Mixes DAC Lch input data.
Default = 0
Select Address
Value
Operation Description
DF1 &h2A [ 3：2 ]
0
Inputs Lch data
DF2 &h2B [ 7：6 ]
1
Inputs (Lch+Rch)/2 data
DF3 &h2B [ 3：2 ]
2
Inputs (Lch+Rch)/2 data
3
Inputs Rch data
Mixes DAC Rch input data.
Default = 0
Select Address
Value
Operation Description
DF1 &h2A [ 1：0 ]
0
Inputs Rch data
DF2 &h2B [ 5：4 ]
1
Inputs (Lch+Rch)/2 data
DF2 &h2B [ 1：0 ]
2
Inputs (Lch+Rch)/2 data
3
Inputs Lch data
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31/34
2012.03 - Rev.A
Technical Note
BU9406KS2
7.
Commands Transmitted after Reset Release
(1) The following commands must be transmitted after reset release, including after power supply stand-up.
0．Turn power on.
↓
○Wait approximately 1ms until oscillation is stable. (The time to stabilization should be adjusted according to the
pendulum product.)
↓
1 Reset release
↓
○Wait approximately 500us until RAM initialization is complete.
↓
2．&h01[7] = 0: The internal RAM is cleared, resulting in usable state.
↓
3．&hF1[2] = 0: Signals from the analog block are connected to the digital block.
↓
4．&hF5[5:4] = 0: Configure PLL clock to regular use state. (&hF5=00)
↓
5．&hF6[7:0] = AAh: Performs phase focusing of the clock output from PLL.
↓
6．Configure the default value (24’h200000) to parametric equalizer coefficient b0 (refer to (2) for procedure).
↓
○Wait approximately 10ms until PLL is stable.
↓
7．Configuration of other registers.
（２） 6．Procedure to configure default value (24’h200000) to parametric equalizer coefficient b0
6-1．&h42[7:0] = 20h
: Configure 20h to bit [23:16] of 24bit coefficient to be loaded.
↓
6-2．&h41[7:0] = **h : Appoint coefficient address. (i.e.) Configure 28h to b0 of filter number 1.
↓
6-3．&h40[7] = 1
: Begin coefficient load.
↓
○Wait approximately 20us
↓
6-4．&h40[7] = 0
: Stop coefficient load.
Repeat steps 6-2 through 6-4 19 times, each time changing the filter coefficient b0 address.
N0.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
&h41[7:0] = **h
28h
2Dh
32h
37h
68h
00h
05h
0Ah
0Fh
14h
19h
1Eh
40h
45h
4Ah
4Fh
54h
59h
5Eh
Parametric Equalizer Filter Numbers
Filter Number 1 (Lch/Rch common coefficient b0)
Filter Number 2 (Lch/Rch common coefficient b0)
Filter Number 3 (Lch/Rch common coefficient b0)
Filter Number 4 (Lch/Rch common coefficient b0)
Filter Number 5 (Lch/Rch common coefficient b0)
Filter Number 6 (Lch coefficient b0)
Filter Number 7 (Lch coefficient b0)
Filter Number 8 (Lch coefficient b0)
Filter Number 9 (Lch coefficient b0)
Filter Number A (Lch coefficient b0)
Filter Number B (Lch coefficient b0)
Filter Number C (Lch coefficient b0)
Filter Number 6 (Rch coefficient b0)
Filter Number 7 (Rch coefficient b0)
Filter Number 8 (Rch coefficient b0)
Filter Number 9 (Rch coefficient b0)
Filter Number A (Rch coefficient b0)
Filter Number B (Rch coefficient b0)
Filter Number C (Rch coefficient b0)
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© 2012 ROHM Co., Ltd. All rights reserved.
32/34
2012.03 - Rev.A
Technical Note
BU9406KS2
●Operational Notes
(1) ABSOLUTE MAXIMUM RATINGS
Permanent device damage may occur and break mode (open or short) can not be specified if power supply, operating
temperature, and those of ABSOLUTE MAXIMUM RATINGS are exceeded. If such a special condition is expected,
components for safety such as fuse must be used.
(2) Power Supply
Power and Ground line must be designed as low impedance in the PCB. Print patterns if digital power supply and analog
power supply must be separated even if these have same voltage level. Print patterns for ground must be designed as same
as power supply. These considerations avoid analog circuits from the digital circuit noise. All pair of power supply and ground
must have their own de-coupling capacitor. Those capacitor should be checked about their specification, etc. (nominal
electrolytic capacitor degrades its capacity at low temperature) and choose the constant of an electrolytic capacitor.
(3) Functionality in the strong electro-magnetic field
Malfunction may occur if in the strong electro-magnetic field.
(4) Input terminals
All LSI contain parasitic components. Some are junctions which normally reverse bias. When these junctions forward bias,
currents flows on unwanted path, malfunction or device damage may occur. To prevent this, all input terminal voltage must be
between ground and power supply, or in the range of guaranteed value in the Electrical characteristics. And no voltage should
be supplied to all input terminal when power is not supplied.
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© 2012 ROHM Co., Ltd. All rights reserved.
33/34
2012.03 - Rev.A
Technical Note
BU9406KS2
●Ordering Information
B
U
9
4
0
6
K
S
2
Package
KS2: SQFP-T80C
Part Number
Packaging and forming specification
None: Tray, Tube
●Physical Dimension Tape and Reel Information
SQFP-T80C
<Tape and Reel information>
16.0±0.3
14.0±0.2
41
40
80
21
Tray (with dry pack)
Quantity
500pcs
Direction of feed
Direction of product is fixed in a tray
14.0±0.2
1.4±0.1
1
1pin
0.5
16.0±0.3
60
61
Container
20
0.1±0.1
0.125±0.1
0.3±0.1
0.65
0.1
∗ Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
●Marking Diagram(s)(TOP VIEW)
16.0 ± 0.3
14.0 ± 0.2
60
41
61
40
16.0 ± 0.3
14.0 ± 0.2
BU9406KS2
21
80
1
0.5
Lot No.
20
1.4 ± 0.1
0.1±0.1
0.125 ± 0.1
0.65
0.1
0.3 ± 0.1
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© 2012 ROHM Co., Ltd. All rights reserved.
34/34
2012.03 - Rev.A
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001