Si53152

Si53152
P C I - E X P R E S S G EN 1, G E N 2 , G EN 3, A N D G E N 4
FANOUT BUFFER
Features





PCI-Express Gen 1, Gen 2, Gen 3, 
and Gen 4 common clock
compliant

Supports Serial ATA (SATA) at
100 MHz

100–210 MHz operation

Low power, push pull, differential
output buffers

Internal termination for maximum
integration

Dedicated output enable pin for
each clock
Two PCI-Express buffered clock
outputs
Supports LVDS outputs
I2C support with readback
capabilities
Extended temperature:
–40 to 85 °C
3.3 V Power supply
 24-pin QFN package
Ordering Information:
See page 17
Applications
Wireless access point
Routers
24
22
21
20
19
VDD
1
18 OE_DIFF1*
NC
2
17 VDD
VDD
3
VSS
4
OE_DIFF0*
5
VDD
6
16 DIFF1
25
GND
15 DIFF1
14 DIFF0
8
9
10
11
12
NC
NC
NC
VDD
13 DIFF0
7
NC
The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source
two PCIe clocks simultaneously. The device has two hardware output enable
inputs for enabling the respective differential outputs on the fly. The device
also features output enable control through I2C communication. I2C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at www.silabs.com/pcie-learningcenter.
23
SCLK
Description
SDATA
Pin Assignments
DIFFIN

VDD

DIFFIN
Network attached storage
Multi-function Printer
VSS

NC

*Note: Internal 100 kohm pull-up.
Patents pending
Functional Block Diagram
DIFF0
DIFFIN
DIFFIN
DIFF1
SCLK
SDATA
OE [1:0]
Rev. 1.2 4/16
Control & Memory
Control
RAM
Copyright © 2016 by Silicon Laboratories
Si53152
Si53152
2
Rev. 1.2
Si53152
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Rev. 1.2
3
Si53152
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3.3 V Operating Voltage
VDD core
3.3 ± 5%
3.135
3.3
3.465
V
3.3 V Input High Voltage
VIH
Control input pins
2.0
—
VDD + 0.3
V
3.3 V Input Low Voltage
VIL
Control input pins
VSS – 0.3
—
0.8
V
Input High Voltage
VIHI2C
SDATA, SCLK
2.2
—
—
V
Input Low Voltage
VILI2C
SDATA, SCLK
—
—
1.0
V
Input High Leakage Current
IIH
Except internal pull-down
resistors, 0 < VIN < VDD
—
—
5
A
Input Low Leakage Current
IIL
Except internal pull-up resistors, 0 < VIN < VDD
–5
—
—
A
3.3 V Output High Voltage
(Single-Ended Outputs)
VOH
IOH = –1 mA
2.4
—
—
V
3.3 V Output Low Voltage
(Single-Ended Outputs)
VOL
IOL = 1 mA
—
—
0.4
V
High-impedance Output
Current
IOZ
–10
—
10
µA
Input Pin Capacitance
CIN
1.5
—
5
pF
COUT
—
—
6
pF
LIN
—
—
7
nH
—
—
20
mA
Output Pin Capacitance
Pin Inductance
Dynamic Supply Current
4
IDD_3.3V
All outputs enabled. Differential clock with 5” traces
and 2 pF load at 100 MHz.
Rev. 1.2
Si53152
Table 2. AC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100
—
210
MHz
0.6
—
4
V/ns
DIFFIN at 0.7 V
Input Frequency Range
Rising and Falling Slew Rates for
Each Clock Output Signal in a
Given Differential Pair
fin
TR / TF
Single ended measurement:
VOL = 0.175 to VOH = 0.525 V
(Averaged)
Differential Input High Voltage
VIH
150
—
—
mV
Differential Input Low Voltage
VIL
—
—
–150
mV
Crossing Point Voltage at 0.7 V
Swing
VOX
Single-ended measurement
250
—
550
mV
Vcross Variation over all edges
VOX
Single-ended measurement
—
—
140
mV
Differential Ringback Voltage
VRB
–100
—
100
mV
Time before ringback allowed
TSTABLE
500
—
—
ps
—
1.15
V
–0.3
—
—
V
Absolute Maximum Input
Voltage
VMAX
Absolute Minimum Input
Voltage
VMIN
Duty Cycle for Each Clock
Output Signal in a Given
Differential Pair
TDC
Measured at crossing point VOX
45
—
55
%
Rise/Fall Matching
TRFM
Determined as a fraction of
2 x (TR – TF)/(TR + TF)
—
—
20
%
Duty Cycle
TDC
Measured at 0 V differential
45
—
55
%
Clock Skew
TSKEW
Measured at 0 V differential
—
—
50
ps
Additive Peak Jitter
Pk-Pk
0
—
10
ps
Additive PCIe Gen 2
Phase Jitter
RMSGEN2
10 kHz < F < 1.5 MHz
0
—
0.5
ps
1.5 MHz< F < Nyquist Rate
0
—
0.5
ps
Additive PCIe Gen 3
Phase Jitter
RMSGEN3
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
0
—
0.10
ps
PCIe Gen 4
—
—
0.10
ps
DIFF at 0.7 V
Additive PCIe Gen 4 Phase Jitter RMSGEN4
Additive Cycle to Cycle Jitter
TCCJ
Measured at 0 V differential
—
—
50
ps
Long Term Accuracy
LACC
Measured at 0 V differential
—
—
100
ppm
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.2
5
Si53152
Table 2. AC Electrical Specifications (Continued)
Parameter
Rising/Falling Slew Rate
Crossing Point Voltage at 0.7 V
Swing
Symbol
Test Condition
Min
Typ
Max
Unit
TR / TF
Measured differentially from
±150 mV
2.5
—
8
V/ns
300
—
550
mV
—
—
5
ms
10.0
—
—
ns
VOX
Enable/Disable and Set-Up
Clock Stabilization from
Power-up
TSTABLE
Stopclock Set-up Time
TSS
Measured from the point when
both VDD and clock input are valid
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Table 3. Absolute Maximum Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD_3.3V
Functional
—
—
4.6
V
Input Voltage
VIN
Relative to VSS
–0.5
—
4.6
VDC
Temperature, Storage
TS
Non-functional
–65
—
150
°C
Temperature, Operating Ambient
TA
Functional
–40
—
85
°C
Temperature, Junction
TJ
Functional
—
—
150
°C
Dissipation, Junction to Case
ØJC
JEDEC (JESD 51)
—
—
35
°C/W
Dissipation, Junction to Ambient
ØJA
JEDEC (JESD 51)
—
—
37
°C/W
ESDHBM
JEDEC (JESD 22-A114)
2000
—
—
V
UL-94
UL (Class)
Main Supply Voltage
ESD Protection (Human Body Model)
Flammability Rating
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up.
Power supply sequencing is not required.
6
Rev. 1.2
Si53152
2. Functional Description
2.1. OE Pin Definition
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE
pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable
the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins are required
to be driven at all times even though they have an internal 100 k resistor.
2.2. OE Assertion
The OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks respectively
while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high
causes stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses are
produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two
to six output clock cycles.
2.3. OE Deassertion
When the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final output
state is driven low.
Rev. 1.2
7
Si53152
3. Test and Measurement Setup
This diagram shows the test load configuration for differential clock signals.
M e a s u re m e n t
P o in t
L1
O U T+
5 0
2 pF
L1 = 5"
M e a s u re m e n t
P o in t
L1
O U T-
5 0
2 pF
Figure 1. 0.7 V Differential Load Configuration
Figure 2. Differential Output Signals (for AC Parameters Measurement)
8
Rev. 1.2
Si53152
VMIN = –0.30V
VMIN = –0.30V
Figure 3. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
Rev. 1.2
9
Si53152
4. Control Registers
4.1. I2C Interface
To enhance the flexibility and function of the clock buffer, an I2C interface is provided. Through the I2C Interface,
various device functions are available, such as individual clock output enable. The registers associated with the I2C
Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register
changes are normally made at system initialization, if any are required. Power management functions can only be
programed in program mode and not in normal operation modes.
4.2. Data Protocol
The I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block
write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller
can access individually indexed bytes.
The block write and block read protocol is outlined in Table 4 while Table 5 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Bit
1
Start
8:2
Slave address—7 bits
Description
Start
Slave address—7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code—8 bits
18:11
Command Code—8 bits
19
Acknowledge from slave
19
Acknowledge from slave
Byte Count—8 bits
20
Repeat start
27:20
28
36:29
37
45:38
10
Block Read Protocol
Acknowledge from slave
27:21
Slave address—7 bits
Data byte 1—8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2—8 bits
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N—8 bits
....
Acknowledge from slave
....
Stop
37:30
38
46:39
47
55:48
Rev. 1.2
Byte Count from slave—8 bits
Acknowledge
Data byte 1 from slave—8 bits
Acknowledge
Data byte 2 from slave—8 bits
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Si53152
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Byte Read Protocol
Description
Bit
Start
1
Slave address–7 bits
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
18:11
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
28
Read
29
Acknowledge from slave
37:30
Rev. 1.2
Slave address–7 bits
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
11
Si53152
Control Register 0. Byte 0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Type
Reset settings = 00000000
Bit
Name
Function
7:0
Reserved
Control Register 1. Byte 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Type
Reset settings = 00000000
12
Bit
Name
7:0
Reserved
Function
Rev. 1.2
Si53152
Control Register 2. Byte 2
Bit
D7
D6
Name
DIFF0_OE
DIFF1_OE
Type
R/W
R/W
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
Reset settings = 11000000
Bit
Name
Function
7
DIFF0_OE
Output Enable for DIFF0.
0: Output disabled.
1: Output enabled.
6
DIFF1_OE
Output Enable for DIFF1
0: Output disabled.
1: Output enabled.
5:0
Reserved
Control Register 3. Byte 3
Bit
D7
D6
Name
Type
D5
D4
D3
Rev Code[3:0]
R/W
R/W
R/W
Vendor ID[3:0]
R/W
R/W
R/W
R/W
R/W
D3
D2
D1
D0
R/W
R/W
R/W
R/W
Reset settings = 00001000
Bit
Name
Function
7:4
Rev Code[3:0]
Program Revision Code.
3:0
Vendor ID[3:0]
Vendor Identification Code.
Control Register 4. Byte 4
Bit
D7
D6
D5
D4
Name
Type
BC[7:0]
R/W
R/W
R/W
R/W
Reset settings = 00000110
Bit
Name
7:0
BC[7:0]
Function
Byte Count Register.
Rev. 1.2
13
Si53152
Control Register 5. Byte 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type
R/W
R/W
R/W
R/W
Reset settings = 11011000
Bit
Name
7
DIFF_Amp_Sel
Function
Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
14
6
DIFF_Amp_Cntl[2]
5
DIFF_Amp_Cntl[1]
4
DIFF_Amp_Cntl[0]
3:0
Reserved
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV
100: 700 mV 101: 800 mV 110: 900 mV
Rev. 1.2
011: 600 mV
111: 1000 mV
Si53152
DIFFIN
VDD
23
22
21
20
SCLK
DIFFIN
24
SDATA
VSS
5. Pin Descriptions: 24-Pin QFN
19
VDD
1
18 OE_DIFF1*
NC
2
17 VDD
VDD
3
VSS
4
OE_DIFF0*
5
VDD
6
16 DIFF1
25
GND
15 DIFF1
14 DIFF0
7
8
9
10
11
12
NC
NC
NC
NC
NC
VDD
13 DIFF0
*Note: Internal 100 kohm pull-up.
Figure 4. 24-Pin QFN
Table 6. Si53152 24-Pin QFN Descriptions
Pin #
Name
Type
Description
1
VDD
2
NC
3
VDD
PWR 3.3 V power supply.
4
VSS
GND
Ground.
5
OE_DIFF0
I,PU
Active high input pin enables DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
6
VDD
7
NC
NC
No connect.
8
NC
NC
No connect.
9
NC
NC
No connect.
10
NC
NC
No connect.
11
NC
NC
No connect.
12
VDD
13
DIFF0
O, DIF 0.7 V, 100 MHz differential clock.
14
DIFF0
O, DIF 0.7 V, 100 MHz differential clock.
15
DIFF1
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
NC
No connect.
PWR 3.3 V power supply.
PWR 3.3 V power supply.
Rev. 1.2
15
Si53152
Table 6. Si53152 24-Pin QFN Descriptions (Continued)
Pin #
Name
16
DIFF1
17
VDD
18
OE_DIFF1
I,PU
19
SCLK
I
20
SDATA
I/O
21
VDD
22
DIFFIN
I
0.7 V Differential True Input, typically 100 MHz. Input frequency range
100 to 210 MHz.
23
DIFFIN
O
0.7 V Differential Complement Input, typically 100 MHz. Input frequency
range 100 to 210 MHz.
24
VSS
GND
Ground.
25
GND
GND
Ground for bottom pad of the IC.
16
Type
Description
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
Active high input pin enables DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
SMBus compatible SCLOCK.
SMBus compatible SDATA.
PWR 3.3 V power supply.
Rev. 1.2
Si53152
6. Ordering Guide
Part Number
Package Type
Temperature
Si53152-A01AGM
24-pin QFN
Extended, –40 to 85 C
Si53152-A01AGMR
24-pin QFN—Tape and Reel
Extended, –40 to 85 C
Lead-free
Rev. 1.2
17
Si53152
7. Package Outline
Figure 5 illustrates the package details for the Si53152. Table 7 lists the values for the dimensions shown in the
illustration.
Figure 5. 24-Pin Quad Flat No Lead (QFN) Package
Table 7. Package Diagram Dimensions
Symbol
Millimeters
Min
Nom
Max
A
0.70
0.75
0.80
A1
0.00
0.025
0.05
b
0.20
0.25
0.30
D
D2
4.00 BSC
2.60
2.70
e
0.50 BSC
E
4.00 BSC
2.80
E2
2.60
2.70
2.80
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.07
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components
18
Rev. 1.2
Si53152
8. PCB Land Pattern
Figure 6. Si53152 24-Pin TDFN Land Pattern
Table 8. Si53152 24-Pin Land Pattern Dimensions
Dimension
mm
C1
4.0
C2
4.0
E
0.50 BSC
X1
0.30
X2
2.70
Y1
0.80
Rev. 1.2
19
Si53152
Table 8. Si53152 24-Pin Land Pattern Dimensions (Continued)
Y2
2.70
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication Allowance of
0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all the
way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
20
Rev. 1.2
Si53152
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0

Updated Features and Description.
Updated Table 2.
 Updated Table 3.
 Updated Section 4.1.

Revision 1.0 to Revision 1.1

Updated Features on page 1.
 Updated Description on page 1.
 Updated specs in Table 2, “AC Electrical
Specifications,” on page 5.
Revision 1.1 to Revision 1.2

Added condition for Clock Stabilization from Powerup, TSTABLE, in Table 2.
Rev. 1.2
21
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent
of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in
weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand
names mentioned herein are trademarks of their respective holders.
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