SL18860

SL18860DC
3-Channel Clock Distribution Buffer
Key Features
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Description
The SL18860DC product is a high performance 3 output
clock distribution buffer and provides 3 outputs from a
single input clock by using SLI proprietary low phase
noise and low power dissipation circuit design.
Low current consumption
- 2.7mA-typ (VDD=1.8V and CL=0)
1.7V to 3.65V power supply operation
10MHz to 52MHz CLKIN
Supports LVCMOS and clipped sine wave inputs
Suports 3 single-ended LVCMOS square wave
outputs
OE1/2/3 functions for each CLKOUT1/2/3 outputs
OE_OSC control pin to enable external TCXO/XO
Ultra-Low phase noise
Ultra low standby current
10-pin TDFN package (1.4x2.0x0.75 mm)
Industrial -40 ºC to 85 ºC temperature range
The SL18860DC can be used in baseband mobile RF
applications including WLAN, Bluetooth and DVB-H as an
input clock reference. The product designed to isolate
each device driven by their clock outputs to minimize
interference between these devices.
Each of the clock buffer outputs can be individually
disabled by using OE1/2/3 control pins to reduce the
power consumption if the connected device does not need
the clock. The device operates from single power supply
from 1.7V to 3.65V and from -40 ºC to 85 ºC.
Application
Benefits
• Fast Time-to-market
• Cost Reduction
• Low Power Dissipation
• Low Phase Noise
• Smart Mobile Handsets
• Multi-mode RF Clock Distribution
• Baseband Peripheral Clock Distribution
Block Diagram
CLKIN
3
OE_OSC
4
8
CLKOUT1
9
CLKOUT2
10
CLKOUT3
CONTROL LOGIC
6
7
5
2
1
OE1
OE2
OE3
VDD
VSS
Rev 1.8, March 16 , 2012
400 West Cesar Chavez, Austin, TX 78701
Page 1 of 12
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL18860DC
Pin Configuration
VSS
1
10
CLKOUT3
VDD
2
9
CLKOUT2
CLKIN
3
8
CLKOUT1
OE_OSC
4
7
OE2
OE3
5
6
OE1
10-Pin TDFN Package Pinout
Pin Description
Pin
Number
Pin Name
Pin Type
1
VSS
Power
Power supply ground.
2
VDD
Power
2.25 to 3.65V or 1.8V +/-5% positive power supply
3
CLKIN
Input
External clock input pin. VSS to VDD CMOS level.
4
OE_OSC
Output
5
OE3
Input
Output enable pin for CLKOUT3. The input has 150kΩ-typ on-chip pulldown resistor.
6
OE1
Input
Output enable pin for CLKOUT1. The input has 150kΩ-typ on-chip pulldown resistor.
7
OE2
Input
Output enable pin for CLKOUT2. The input has 150kΩ-typ on-chip pulldown resistor.
8
CLKOUT1
Output
Clock output-1. Clock frequency is the same as CLKIN.
9
CLKOUT2
Output
Clock output-2. Clock frequency is the same as CLKIN.
10
CLKOUT3
Output
Clock output-3. Clock frequency is the same as CLKIN.
Pin Description
Crystal oscillator enable pin. If OE1=OE2=OE3=0 then OE_OSC=0.
OE_OSC=1 for all the other OE1/2/3 logic states.
OE1
(Input)
OE2
(Input)
OE3
(Input)
OE_OSC
(Output)
CLKOUT1
CLKOUT2
CLKOUT3
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
1
0
0
1
CLOCK
Hi-Z
Hi-Z
1
1
0
1
CLOCK
CLOCK
Hi-Z
…
…
…
…
…
…
…
1
1
1
1
CLOCK
CLOCK
CLOCK
Table 1. Truth Table for OE1/2/3, OE_OSC and CLKOUT1/2/3
Rev 1.8, March 16 , 2012
Page 2 of 12
SL18860DC
Absolute Maximum Ratings
Description
Condition
Min
Max
Unit
Supply voltage, VDD (Absolute)
-0.5
4.6
V
Supply voltage, VDD (Operation)
1.70
3.65
V
All Inputs and Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
In operation, C-Grade
-40
85
°C
Storage Temperature
No power is applied
-65
150
°C
Junction Temperature
In operation, power is applied
-
125
°C
-
260
°C
Soldering Temperature
ESD Rating (Human Body Model)
JEDEC22-A114D
-4,000
4,000
V
ESD Rating (Charge Device Model)
JEDEC22-C101C
-1,500
1,500
V
ESD Rating (Machine Model)
JEDEC22-A115D
-200
200
V
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 1.8V+/- 5% and Operation Temperature Range -40 to +85°C
Description
Operating Voltage
Symbol
Condition
Min
Typ
Max
Unit
VDD
Operation range, 1.8V+/-5%
1.70
1.80
1.90
V
Operating Temperature
TA
I-Grade
-40
25
85
ºC
Input Low Voltage
VIL
CMOS Level, Pins 3,5, 6 and 7
VSS
-
0.3VDD
V
Input High Voltage
VIH
CMOS Level, Pins 3,5, 6 and 7
0.7VDD
-
VDD
V
Output High Voltage
VOH
IOH=-4mA , Pins 4, 8, 9 and 10
VDD-0.4
-
-
V
Output Low Voltage
VOL
IOL=-4mA, Pins 4, 8, 9 and 10
-
-
0.4
V
Input Leakage Current
ILH
VIN=VDD, Pins 5, 6 and 7
-25
-
25
μA
Input Leakage Current
ILL
VIN=GND, Pins 5, 6 and 7
-10
-
10
μA
Pins 5, 6 and 7
100
150
250
kΩ
-
2.7
-
mA
-
-
1.0
µA
Pull-Down Resistor
RPD
Operating Supply Current
IDD1
Operating Supply Current
IDD2
Input Capacitance
CIN
Pins 5, 6 and 7
-
3
5
pF
Load Capacitance
CL
CLKOUT1/2/3, Pins 8, 9 and 10
-
10
20
pF
Rev 1.8, March 16 , 2012
CLKIN=26MHz,
OE1=OE2=OE3=1
OE1=OE2=OE3=0
CLKIN=Low or High
Page 3 of 12
SL18860DC
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 1.8V+/- 5% and Operation Temperature Range -40 to +85°C
Parameter
Min
Typ
Max
10
26.000
52
MHz
10
26.000
52
MHz
0.72
1
-
Vpp
30
50
70
%
-
2.0
4.00
ns
-
2.0
4.00
ns
-
-140
-
dBc/Hz
-
-150
-
dBc/Hz
-
-159
-
dBc/Hz
tPU
Time duration until CLKOUT1/2/3
frequency reaches valid frequency
after power supply reaches 0.9xVDD
value
-
100
200
Ns
Output Enable Time
tOE1
Time from OE raising edge to active
at outputs CLKOUT1/2/3
(Asynchronous)
-
25
-
ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs CLKOUT1/2/3
(Asynchronous)
-
25
-
ns
Output Enable Time
tOE2
Active recovery time from standby
(CLKIN=0 or 1) to active at outputs
CLKOUT1/2/3
-
100
-
Ns
Input Clock Range
Output Clock Range
Symbol
CLKIN
Condition
External Clock, CMOS square wave
External Clock, CMOS square wave
CLKOUT
CLKOUT1/2/3
Input Clock Voltage
Swing Level
VINpp
VDD=1.8V
Input Duty Cycle
DCIN
CLKIN, Pin 3
Output Clock Rise
Time
Output Clock Fall
Time
Additive Phase Noise
VDD=1.8, CL=10pF, measured from
tr
tf
APN-1
APN-2
Additive Phase Noise
APN-3
Rev 1.8, March 16 , 2012
10 to 90% of VDD, Pins 4, 8, 9 and
10
Additive Phase Noise
Power-up Time
Unit
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
CLKIN=26MHz and 1 kHz offset
CLKOUT1/2/3
CLKIN=26MHz and 10 kHz offset
CLKOUT1/2/3
CLKIN=26MHz and 100 kHz offset
CLKOUT1/2/3
Page 4 of 12
SL18860DC
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C
Description
Symbol
Condition
VDD
Operation range, 2.5V+/-10%
2.25
2.50
2.75
V
Operating Voltage
Min
Typ
Max
Unit
Operating Temperature
TA
I-Grade
-40
25
85
ºC
Input Low Voltage
VIL
CMOS Level, Pins 3,5, 6 and 7
VSS
-
0.3VDD
V
Input High Voltage
VIH
CMOS Level, Pins 3,5, 6 and 7
0.7VDD
-
VDD
V
Output High Voltage
VOH
IOH=-4mA , Pins 4, 8, 9 and 10
VDD-0.4
-
-
V
Output Low Voltage
VOL
IOL=-4mA, Pins 4, 8, 9 and 10
-
-
0.4
V
Input Leakage Current
ILH
VIN=VDD, Pins 5, 6 and 7
-30
-
30
μA
Input Leakage Current
ILL
VIN=GND, Pins 5, 6 and 7
-15
-
15
μA
Pins 5, 6 and 7
100
150
250
kΩ
-
3.0
-
mA
-
-
1.5
µA
Pull-Down Resistor
RPD
CLKIN=26MHz,
OE1=OE2=OE3=1
OE1=OE2=OE3=0
CLKIN=Low or High
Operating Supply Current
IDD1
Operating Supply Current
IDD2
Input Capacitance
CIN
Pins 5, 6 and 7
-
3
5
pF
Load Capacitance
CL
CLKOUT1/2/3, Pins 8, 9 and 10
-
10
20
pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C
Parameter
Input Clock Range
Output Clock Range
Symbol
CLKIN
VINpp
Input Duty Cycle
DCIN
Time
Output Clock Fall
Time
Additive Phase Noise
Min
Typ
Max
10
26.000
52
MHz
10
26.000
52
MHz
VDD=2.5V, connect to CLKIN directly
1.0
1.2
-
V
VDD=2.5V, connect to CLKIN through
AC coupling and bias circuit
0.6
-
-
V
CLKIN, Pin 3
30
50
70
%
-
2.0
4.00
ns
-
2.0
4.00
ns
-
-142
-
dBc/Hz
External Clock, CMOS square wave
Unit
External Clock, CMOS square wave
CLKOUT
Input Clock Voltage
Swing Level
Output Clock Rise
Condition
CLKOUT1/2/3
VDD=1.8, CL=10pF, measured from
tr
10 to 90% of VDD, Pins 4, 8, 9 and
10
tf
APN-1
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
CLKIN=26MHz and 1 kHz offset
CLKOUT1/2/3
Rev 1.8, March 16 , 2012
400 West Cesar Chavez, Austin, TX 78701
Page 1 of 12
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL18860DC
Additive Phase Noise
APN-2
Additive Phase Noise
APN-3
CLKIN=26MHz and 10 kHz offset
CLKOUT1/2/3
CLKIN=26MHz and 100 kHz offset
CLKOUT1/2/3
-
-156
-
dBc/Hz
-
-164
-
dBc/Hz
tPU
Time for CLKOUT1/2/3 frequency to
reach valid frequency after power
supply reaches 0.9xVDDvalue
-
100
200
ns
Output Enable Time
tOE1
Time from OE raising edge to active
at outputs CLKOUT1/2/3
(Asynchronous)
-
25
-
ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs CLKOUT1/2/3
(Asynchronous)
-
25
-
ns
Output Enable Time
tOE2
Active recovery time from standby
(CLKIN=0 or 1) to active at outputs
CLKOUT1/2/3
-
100
-
ns
Power-up Time
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10% and Operation Temperature Range -40 to +85°C
Description
Operating Voltage
Symbol
Condition
Min
Typ
Max
Unit
VDD
Operation range , 3.3V+/-10%
2.95
3.3
3.65
V
Operating Temperature
TA
I-Grade
-40
25
85
ºC
Input Low Voltage
VIL
CMOS Level, Pins 3.5, 6 and 7
VSS
-
0.3VDD
V
Input High Voltage
VIH
CMOS Level, Pins 3.5, 6 and 7
0.7VDD
-
VDD
V
Output High Voltage
VOH
IOH=-4mA , Pins 4, 8, 9 and 10
VDD-0.4
-
-
V
Output Low Voltage
VOL
IOL=-4mA, Pins 4, 8, 9 and 10
-
-
0.5
V
Input Leakage Current
ILH
VIN=VDD, Pins 5, 6 and 7
-35
-
35
μA
Input Leakage Current
ILL
VIN=GND, Pins 5, 6 and 7
-20
-
20
μA
Pins 5, 6 and 7
100
150
250
kΩ
-
3.4
-
mA
-
-
2.0
µA
Pull-Down Resistor
RPD
CLKIN=26MHz,
OE1=OE2=OE3=1
OE1=OE2=OE3=0
CLKIN=Low or High
Operating Supply Current
IDD1
Operating Supply Current
IDD2
Input Capacitance
CIN
Pins 5, 6 and 7
-
3
5
pF
Load Capacitance
CL
CLKOUT1/2/3, Pins 8, 9 and 10
-
10
25
pF
Rev 1.8, March 16 , 2012
Page 2 of 12
SL18860DC
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10% and Operation Temperature Range -40 to +85°C
Parameter
Min
Typ
Max
10
26.000
52
MHz
10
26.000
52
MHz
VDD=3.3V, connect to CLKIN directly
1.32
1.4
-
V
VDD=3.3V, connect to CLKIN through
AC coupling and bias circuit
0.6
-
-
V
CLKIN, Pin 3
30
50
70
%
-
1.2
2.2
ns
-
1.2
2.2
ns
-
-138
-
dBc/Hz
-
-157
-
dBc/Hz
-
-165
-
dBc/Hz
tPU
Time duration until CLKOUT1/2/3
frequency reaches valid frequency
after power supply reaches 0.9xVDD
value
-
100
200
ns
Output Enable Time
tOE1
Time from OE raising edge to active
at outputs CLKOUT1/2/3
(Asynchronous)
-
25
-
ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs CLKOUT1/2/3
(Asynchronous)
-
25
-
ns
Output Enable Time
tOE2
Active recovery time from standby
(CLKIN=0 or 1) to active at outputs
CLKOUT1/2/3
-
100
-
ns
Input Clock Range
Output Clock Range
Symbol
CLKIN
External Clock, CMOS square wave
Unit
External Clock, CMOS square wave
CLKOUT
Input Clock Voltage
Swing Level
VINpp
Input Duty Cycle
DCIN
CLKOUT1/2/3
VDD=1.8, CL=10pF, measured from
Output Clock Rise
Time
Condition
tr
10 to 90% of VDD, Pins 4, 8, 9 and
10
Output Clock Fall
Time
tf
Additive Phase Noise
APN-1
Additive Phase Noise
APN-2
Additive Phase Noise
Power-up Time
Rev 1.8, March 16 , 2012
APN-3
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
CLKIN=26MHz and 1 kHz offset
CLKOUT1/2/3
CLKIN=26MHz and 10 kHz offset
CLKOUT1/2/3
CLKIN=26MHz and 100 kHz offset
CLKOUT1/2/3
Page 3 of 12
SL18860DC
SL18860DC CLKOUT1/2/3
Phase Noise (dBc/Hz) CL=15pF.
VDD(V)
100hz
1Khz
10Khz
100Khz
1Mhz
5Mhz
1.8
2.5
3.3
-115.52
-125.16
-116.60
-139.85
-142.67
-138.06
-150.79
-156.37
157.41
-159.31
-164.02
-164.88
-160.52
-166.45
-167.21
-162.52
-167.02
-168.57
Fig #
1
2
3
Table 2. Output Phase Noise Summary Table
Figure 1. Output Phase Noise VDD=1.8V, CL=15pF
Rev 1.8, March 16 , 2012
Page 4 of 12
SL18860DC
Figure 2. Output Phase Noise VDD=2.5V, CL=15pF
Figure 3. Output Phase Noise VDD=3.3V, CL=15pF
Rev 1.8, March 16 , 2012
Page 5 of 12
SL18860DC
Typical Application Circuit
VDD=1.8V to 3.3V
R1 (50Ω)
C1 (10μF)
(26.000MHz-typ)
C2 (0.1μF)
2
CLKIN
3
CLKOUT1 (26.000MHz-typ)
8
OE_OSC
4
CLKOUT2 (26.000MHz-typ)
SL18860DC
OE1
OE2
OE3
9
CLKOUT3 (26.000MHz-typ)
6
10
7
5
1
VSS
AC coupling and bias circuit
Vcc
C1
R
TCXO
SL18860
22nF
Rev 1.8, March 16 , 2012
VDD
R2
Page 6 of 12
SL18860DC
Package Outline and Package Dimensions
10-Pin TDFN Package (1.4x2.0x0.75 mm)
Top View
Side View
Bottom View
Side View
Rev 1.8, March 16 , 2012
Page 7 of 12
SL18860DC
Ordering Information
Ordering Number
Marking
Shipping Package
Package
Temperature
SL18860DC
860
Tube
10-pin TDFN
-40 to 85°C
SL18860DCT
860
Tape and Reel
10-pin TDFN
-40 to 85°C
Note:
The SL18860 is RoHS compliant
Marking Diagram:
860
YWW
Pin 1
YWW:
Y = Last Digit of Year
WW = Work Week
The information in this document is believed to be accurate in all respects at the time of publication but is subject to
change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims
responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon
Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon
Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon
Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories
products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for
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damages.
Rev 1.8, March 16 , 2012
Page 8 of 12