SCH322X SCH3227/SCH3226/SCH3224/SCH3222 Silicon Errata and Data Sheet Clarification TABLE 1: SILICON DEV/REV VALUES Part Number STRAPOPT (3) (1) Device ID Revision ID for Silicon Revision(2) A SCH3222 -- 7Fh 02h SCH3224 -- 7Fh 02h SCH3226 0 (low) 7Dh 02h SCH3226 1 (high) 7Fh 02h SCH3227 0 (low) 7Dh 02h 1 (high) 7Fh 02h SCH3227 Note 1: 2: 3: The Device ID is visible as an 8-bit number at Plug and Play Configuration Index 20h. The HW Revision Number is visible as an 8-bit number at Plug and Play Configuration Index 21h and Version/Stepping Number Register 3Fh. STRAPOPT is a pin that is present on the SCH3226 and SCH3227 devices only. It affects the pinout and also the Device ID code, as shown above. TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A Serial Port Note 1: Reset 1. Resetting UART 3 and UART 4 with PCI_RST X If there are multiple revision-letter columns under this one, only those issues indicated in the last column apply to the current silicon revision. 2016 Microchip Technology Inc. DS80000694A-page 1 SCH322X Silicon Errata Issues 1. Module: Serial Port UART 3 and UART 4 do not tri-state their outputs on a PCI_RESET as do UART 1 and UART 2. UART 3 and UART 4 outputs are not controlled by the Configuration Register 0x30 ACTIVATE bit. END USER IMPLICATIONS UART 3 and UART 4 outputs will drive High when PCI_RESET goes active or when the ACTIVATE bit is cleared, and if the platform uses RTS to control an RS485 transceiver this may interrupt communication. Work Around Use GPIO pin to disable RS485 transceiver when ACTIVATE bit is cleared. Note: Drive GPIO pin low to disable transceiver. Drive GPIO pin high to allow transceiver control by nRTS SCH322x GPIO* nRTS ENB TXD * Possible GPIO GP15, GP32, GP57 DS80000694A-page 2 R1 RS485 Transceiver Note: Ensure R1 will pull-down the GPIO when it is a tri-state condition 2016 Microchip Technology Inc. SCH322X Data Sheet Clarifications Note: The following typographic corrections and clarifications apply to Data Sheet Document #00002121A, which is at Revision A, and specifies only the family members SCH3222, SCH3224, SCH3226 and SCH3227. Other members of the SCH322x family have separate data sheets, and separate errata sheets. TABLE 3: DATA SHEET CLARIFICATION SUMMARY Module Item Number Issue Summary Temp Monitor and Fan Control 1. Incorrect offset for PME_EN1 Temp Monitor and Fan Control 2. No Support for HWM SMI Events Power Control 3. 32KHz Clock Required for PB_IN# and PB_OUT# 8042 Keyboard Controller 4. Incorrect Register for Keyboard/Mouse Swap Programmable Clock Output 5. Misleading Label in Figure Temp Monitor and Fan Control 6. Incorrect Values in Table Temp Monitor and Fan Control 7. No Hardware Monitor Interrupt Event on SERIRQ Runtime Registers 8. Inconsistent Default for Keyboard PWRBTN Runtime Register Runtime Registers 9. Inconsistent Default for Runtime Registers LPC Timing Diagrams 10. Inconsistent PCI Clock Max Period 1. Module: Temperature Monitoring and Fan Control The section “Interrupt as a PME Event,” refers to the PME_EN1 register at offset 0Ah. The offset for PME_EN1 is 08h. 2. Module: Temperature Monitoring and Fan Control The section “Interrupt as an SMI Event,” is incorrect. Hardware monitoring interrupts are not routed to the SMI block and do not generate SMI events. The section will be removed in its entirety. 3. Module: Power Control Features A clock is required on CLKI32 (pin 99) to clock in and debounce PB_IN# and to assert PB_OUT#. If CLKI32 is either not connected or is not connected to an active clock, PB_OUT# will not be asserted. CLKI32 should be connected to a 32KHz clock. A clock can be provided for PB_IN# by connecting CLKI32 to the SUSCLK output from the core logic south bridge. 4. Module: 8042 Keyboard Controller The section “Keyboard/Mouse Swap Bit” says that there is a bit in the Keyboard Select configuration register at 0xF1 in logical device 7, used for swapping the keyboard and mouse pins. There is no such register. The keyboard/mouse swap bit is located in bit[6] of Runtime Register 0x5, which is correctly documented. 5. Module: Programmable Clock Output In the figure “Reset Generation Circuit”, there is a signal labeled “RESETB”. The figure implies that the signal comes in from an input pin. This is incorrect. The figure should indicate that the signal is an internally generated Power On Reset signal. 2016 Microchip Technology Inc. DS80000694A-page 3 SCH322X 6. Module: Temperature Monitoring and Fan Control The Nominal Voltage and Maximum Voltage numbers in the table "Voltage Limits vs. Register Setting" are incorrect for the row labeled 2.5V. The table indicates the nominal voltage is 5.0V and the maximum voltage is 6.64V. These two values are incorrect. The correct nominal voltage is 2.5V, matching the signal name. The maximum voltage is 3.32V. 7. Module: Temperature Monitoring and Fan Control In the subsection titled "Interrupt Event on Serial IRQ", in chapter "Temperature Monitoring and Fan Control", it is stated that the interrupt can be routed to the SERIRQ using configuration register 0x70 in Logical Device A. This is not correct. The Hardware Monitor Interrupt cannot be directly routed to a SERIRQ and there is no configuration register 0x70 in Logical Device A. This subsection will be deleted in subsequent releases of the data sheet. As described in the subsections that precede this one, the Hardware Monitor interrupt can be routed onto a pin, onto an SMI or onto a PME. If it is required to route the HWM interrupt to a SERIRQ, it can be routed to an SMI, which can in turn be routed on SERIRQ2. 8. Module: Runtime Registers The Description column of the Keyboard PWRBTN/SPEKEY runtime register specification states that the default value for bits[5:4], Keyboard Power Button Release, is 00b (De-assert KB_PB_STS 0.5sec after it is asserted). This is inconsistent with the Name column, which states that the VBAT POR default value for bits[5:4] is 10b. The actual default value is 10b. The system must set bits[5:4] to 00b if that is the desired behavior. 9. Module: Runtime Registers The default POR values listed in the table "Runtime Register POR Summary" are incorrect in two cases. In addition, the default POR value for an additional register is incorrect in both this Summary table and also in the table "Detailed Runtime Register Description". Also, this Register table incorrectly states that register 0x10, PME_STS7, is reset on VBAT POR. The PME_STS7 register is reset on VTR POR, as stated in Summary table. The following table shows the correct POR values for the registers in question: Runtime Register Description VTR POR Default, Summary Table VTR POR Default, Register Table Actual VTR POR Default 0x10 PME_EN7 0x00 VBAT POR 0x00 0x00 0x13 SP34 0x00 0x44 0x44 0x4E GP4 0x00 0xF0 0x05 0x6E GP44 0x00 0x80 0x80 10. Module: LPC Timing Diagrams In the chapter “Timing Diagrams”, section “LPC Interface Timing”: In the table underneath the first figure “PCI Clock Timing”, the parameter t1 (Period) is given an incorrect value in the MAX column. It shows 33.3ns, and should instead be 52.6ns, which represents the lowest tested LPC frequency of 19MHz. DS80000694A-page 4 2016 Microchip Technology Inc. SCH322X APPENDIX A: DOCUMENT REVISION HISTORY Revision Level and Date DS80000694A (04-11-16) Description Initial Draft Version 2016 Microchip Technology Inc. DS80000694A-page 5 SCH3227/SCH3226/SCH3224/SCH3222 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support DS80000694A-page 6 2016 Microchip Technology Inc. SCH322X Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781522404736 QUALITYMANAGEMENTSYSTEM CERTIFIEDBYDNV == ISO/TS16949== 2016 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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