AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 A zero delay clock generator or buffer is one whose outputs are edge-aligned with a reference clock. This should not be confused with phase-lock, as phase-lock refers to two clocks that are on average aligned in phase with some (often unknown) initial phase offset. A zero delay clock, on the other hand, has no or minimal initial phase offset. Applications of the Si5340/41/42/44/45/80 zero delay feature exist in many synchronous systems, such as SONET/SDH networks, synchronous Ethernet, PCIe and other highspeed interconnects, and any application requiring known and predictable delay between a reference and one or more output clocks. silabs.com | Smart. Connected. Energy-friendly. KEY FEATURES • Zero delay removes (minimizes) input-tooutput propagation delays to produce outputs phase-aligned to the input clocks for applications requiring minimal, known, and/or predictable delays • Supported on Si5340/41/42/44/45 and Si5380 • Easy to set up using ClockBuilder Pro Rev. 0.1 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Introduction 1. Introduction In a typical clock generator or jitter attentuator there is usually some propagation delay from the input reference clock to the outputs. This delay can have uncertainty due to frequency plan differences, variations across process and temperature, and variations between subsequent device resets. Using the zero delay feature available in the Si5340/41/42/44/45/80 family of clock generators and jitter attenuators we can zero out any input-to-output propagation delay and minimize uncertainty. This application note provides details on setting up a zero delay frequency plan and testing it on an evaluation board. A ClockBuilder Pro example is shown using the Si5345; however, other devices can also be set up similarly. silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 1 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Theory of Operation 2. Theory of Operation The figure below shows a high-level block diagram of the Si5342/44/45 devices. The PLL works to zero out steady-state phase error between the two inputs of its phase detector (PD), a reference clock input and a feedback input. This is not very useful in terms of inputto-output edge alignment; any edge alignment information is lost due to the fixed and variable delays in the feedback M divider, output Multisynth and R dividers, and the input P divider. 48-54 MHz XTAL or REFCLK XA OSC IN_SEL[1:0] IN0 IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3/FB_ INb XB ÷ P0n P0d ÷ P1n P1d ÷ P2n P2d ÷ P3n P3d DSPLL PD Optional External Feedback LPF ÷ M _ NUM M _ DEN Fvco Multi N1_ NUM Synth ÷ N1_ DEN ÷R1 VDDO1 OUT1 OUT1b Multi N2_ NUM ÷ N2_ DEN Synth ÷R2 VDDO2 OUT2 OUT2b Multi N3_ NUM ÷ N3_ DEN Synth ÷R3 VDDO3 OUT3 OUT3b ÷R4 VDDO4 OUT4 OUT4b ÷R5 VDDO5 OUT5 OUT5b ÷R6 VDDO6 OUT6 OUT6b ÷R7 VDDO7 OUT7 OUT7b ÷R8 VDDO8 OUT8 OUT8b ÷R9 VDDO9 OUT9 OUT9b Multi Synth N4_ NUM ÷ N4_ DEN Si5345 VDDO0 OUT0 OUT0b Si5344 ÷R0 Si5342 N0_ NUM Multi ÷ N0_ DEN Synth Figure 2.1. Si5342/44/45 in Standard PLL Mode silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 2 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Theory of Operation If we replace the feedback input of the PD with one of the output clocks, as shown in the figure below, we can edge align all related outputs with the input clocks. Note that edge alignment occurs at the PD input. Care was taken in the design of the Si534x/8x family to match propagation delays between multiple input paths and output dividers. This allows multiple outputs to be zero delay with respect to any one of the inputs. IN0 Si5345/44/42 ÷P0 IN0b IN1 DSPLL ÷P1 IN1b IN2 PD ÷P2 IN2b 15GHz LPF ÷M IN3/FB_IN 100 ÷P3 IN3 /FB_INb ÷R0 VDDO0 OUT0 OUT0b ÷N0 t0 ÷R1 VDDO1 OUT1 OUT1b ÷N1 t1 ÷R2 VDDO2 OUT2 OUT2b ÷N2 t2 ÷N3 t3 ÷R7 VDDO7 OUT7 OUT7b ÷N4 t4 ÷R8 VDDO8 OUT8 OUT8b ÷R9 VDDO9 OUT9 OUT9b External Feedback Path Figure 2.2. Si5345 Zero Delay Mode Set-up silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 3 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Setup 3. Setup Any of the Si5340/41/42*/44*/45/80 devices can be configured for zero delay mode using Clock Builder Pro. The output closest to the IN3/FBIN pins (OUT2, OUT3, or OUT9 depending on the device variant) must be tied to IN3/FBIN. Care must be taken in layout to minimize trace length and any exposure to noise sources on the PCB. Note: Zero delay mode is not available on the Si5342H/44H. 3.1 Setting up zero delay mode using ClockBuilder Pro In the Zero Delay Mode tab of the ClockBuilder Pro wizard check Enable Zero Delay Mode. Leave external feedback output selection to its default value. Figure 3.1. ClockBuilder Pro Wizard--Zero Delay Step silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 4 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Setup This will block out IN3 as an input clock. Note that automatic input clock switching is not available if there are multiple input clocks and zero delay mode is enabled. One of the manual input clock selections must be used, registers or pins (see the figure below). Figure 3.2. ClockBuilder Pro Wizard--Define Input Clocks Step silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 5 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Setup In the Define Output Frequencies Step, the Clockbuilder Pro frequency planning algorithm will attempt to derive all related frequencies from the N0/ZDM Multisynth divider. This will ensure edge alignment for integer-related frequencies such as 19.44 MHz and 155.52 MHz as shown in the figure below. Zero-delayed outputs can also be explicitly selected by using the N divider/DCO/ZDM pull-down selection. Figure 3.3. ClockBuilder Pro Wizard--Define Output Frequencies Step 3.2 Zero Delay Mode Registers 3.2.1 Si5340/41 Zero Delay Mode Registers Table 3.1. Si5340/41 Zero Delay Mode Registers Reg Address Bit Field Type Setting Name 0x091C 2:0 R/W ZDM_EN Description 3=Zero delay mode 4=Normal mode All other values must not be written. 0x0021 0 R/W IN_SEL_REGCTRL 0: pin controlled clock selection 1: register controlled clock selection 0x0140[3:0] 3:0 0x0139[3:0] 7:0 R/W OUTX_ALWAYS_ON 0x100: Si5340 (OUT3) 0x800: Si5341 (OUT9) Output tied to IN3/FBIN must be configured to always on. silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 6 AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 Setup 3.2.2 Si5342/44/45/80 Zero Delay Mode Registers Table 3.2. Si5342/44/45/80 Zero Delay Mode Registers Reg Address Bit Field Type Setting Name 0x0140 3:0 R/W OUTX_ALWAYS_ON 0x0139 7:0 Description 0x10: Si5342 (OUT2) 0x100: Si5344 (OUT3) 0x800: Si3545/80 Output tied to IN3/FBIN must be configured to always on. 0x0487 0 R/W ZDM_EN 0: Disable zero delay mode. 1: Enable zero delay mode. 0x0487 2:1 R/W ZDM_IN_SEL When zero delay is enabled, this register parameter selects the input clock in manual register controlled mode. Ignore if device set up in pin controlled mode. 0: IN0 1: IN1 2: IN2 3: A register value of 3 is not allowed. 0x052A 0 R/W IN_SEL_REGCTRL 0: pin controlled clock 1: register controlled clock selection When ZDM_EN is high the IN_SEL register bits become unused. Instead ZDM_IN_SEL register bits must be used. If ZDM_EN and IN_SEL_REGCTRL are both high, clock selection is pin-controlled and neither IN_SEL or ZDM_IN_SEL are used. silabs.com | Smart. Connected. Energy-friendly. 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