Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 1 of 9 8-Output Quad DSPLL Any-Frequency Jitter Attenuating Clock Multiplier Overview ======== Part: Design ID: Created By: Timestamp: Si5347 5347BP2 ClockBuilder Pro v1.7 [2015-03-26] 2015-03-26 09:25:02 GMT-05:00 Device Grade ============ Device Grade --------Si5347A Si5347B* Output Clock Frequency Range ------------------100 Hz to 710.4 MHz 100 Hz to 350 MHz Typical Jitter -------------< 150 fs " * Device Grade Design ====== Host Interface: I/O Power Supply: VDD (Core) SPI Mode: 4-Wire I2C Address Range: 108d to 111d / 0x6C to 0x6F (selected via A0/A1 pins) XA/XB: 48 MHz (XTAL - Crystal) Inputs: IN0: IN1: IN2: IN3: Unused Unused Unused Unused Outputs: OUT0: OUT1: OUT2: OUT3: OUT4: OUT5: OUT6: OUT7: Unused Unused Unused Unused Unused Unused Unused Unused Frequency Plan ============== No plan Settings ======== Location -----------0x000B[0:6] 0x0016[0] 0x0016[1] 0x0016[2] 0x0016[3] 0x0017[0] 0x0017[1] Setting Name -----------------------I2C_ADDR LOL_ON_HOLD_PLLA LOL_ON_HOLD_PLLB LOL_ON_HOLD_PLLC LOL_ON_HOLD_PLLD SYSINCAL_INTR_MSK LOSXAXB_INTR_MSK Decimal Value ------------108 1 1 1 1 0 0 Hex Value ---------------0x6C 0x1 0x1 0x1 0x1 0x0 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 2 of 9 0x0017[5] 0x0018[0:3] 0x0018[4:7] 0x0019[0] 0x0019[1] 0x0019[2] 0x0019[3] 0x0019[4] 0x0019[5] 0x0019[6] 0x0019[7] 0x001A[4] 0x001A[5] 0x001A[6] 0x001A[7] 0x002B[3] 0x002C[0:3] 0x002C[4] 0x002D[0:1] 0x002D[2:3] 0x002D[4:5] 0x002D[6:7] 0x002E[0:15] 0x0030[0:15] 0x0032[0:15] 0x0034[0:15] 0x0036[0:15] 0x0038[0:15] 0x003A[0:15] 0x003C[0:15] 0x003F[0:3] 0x003F[4:7] 0x0040[0:2] 0x0041[0:4] 0x0042[0:4] 0x0043[0:4] 0x0044[0:4] 0x0045[0:4] 0x0046[0:7] 0x0047[0:7] 0x0048[0:7] 0x0049[0:7] 0x004A[0:7] 0x004B[0:7] 0x004C[0:7] 0x004D[0:7] 0x004E[0:2] 0x004E[4:6] 0x004F[0:2] 0x004F[4:6] 0x0051[0:3] 0x0052[0:3] 0x0053[0:3] 0x0054[0:3] 0x0055[0:3] 0x0056[0:3] 0x0057[0:3] 0x0058[0:3] 0x0059[0:1] 0x0059[2:3] 0x0059[4:5] 0x0059[6:7] 0x005A[0:25] 0x005E[0:25] SMB_TMOUT_INTR_MSK LOS_INTR_MSK OOF_INTR_MSK LOL_INTR_MSK_PLLA LOL_INTR_MSK_PLLB LOL_INTR_MSK_PLLC LOL_INTR_MSK_PLLD HOLD_INTR_MSK_PLLA HOLD_INTR_MSK_PLLB HOLD_INTR_MSK_PLLC HOLD_INTR_MSK_PLLD CAL_INTR_MSK_PLLA CAL_INTR_MSK_PLLB CAL_INTR_MSK_PLLC CAL_INTR_MSK_PLLD SPI_3WIRE LOS_EN LOSXAXB_DIS LOS0_VAL_TIME LOS1_VAL_TIME LOS2_VAL_TIME LOS3_VAL_TIME LOS0_TRG_THR LOS1_TRG_THR LOS2_TRG_THR LOS3_TRG_THR LOS0_CLR_THR LOS1_CLR_THR LOS2_CLR_THR LOS3_CLR_THR OOF_EN FAST_OOF_EN OOF_REF_SEL OOF0_DIV_SEL OOF1_DIV_SEL OOF2_DIV_SEL OOF3_DIV_SEL OOFXO_DIV_SEL OOF0_SET_THR OOF1_SET_THR OOF2_SET_THR OOF3_SET_THR OOF0_CLR_THR OOF1_CLR_THR OOF2_CLR_THR OOF3_CLR_THR OOF0_DETWIN_SEL OOF1_DETWIN_SEL OOF2_DETWIN_SEL OOF3_DETWIN_SEL FAST_OOF0_SET_THR FAST_OOF1_SET_THR FAST_OOF2_SET_THR FAST_OOF3_SET_THR FAST_OOF0_CLR_THR FAST_OOF1_CLR_THR FAST_OOF2_CLR_THR FAST_OOF3_CLR_THR FAST_OOF0_DETWIN_SEL FAST_OOF1_DETWIN_SEL FAST_OOF2_DETWIN_SEL FAST_OOF3_DETWIN_SEL OOF0_RATIO_REF OOF1_RATIO_REF 0 15 15 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0xF 0xF 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0 0x0 0x4 0x00 0x00 0x00 0x00 0x0C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0000000 0x0000000 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 3 of 9 0x0062[0:25] 0x0066[0:25] 0x0092[0] 0x0092[1] 0x0092[2] 0x0092[3] 0x0093[0:3] 0x0093[4:7] 0x0094[0:3] 0x0094[4:7] 0x0095[0:1] 0x0095[2:3] 0x0095[4:5] 0x0095[6:7] 0x0096[0:3] 0x0096[4:7] 0x0097[0:3] 0x0097[4:7] 0x0098[0:3] 0x0098[4:7] 0x0099[0:3] 0x0099[4:7] 0x009A[0] 0x009A[1] 0x009A[2] 0x009A[3] 0x009B[0:3] 0x009B[4:7] 0x009C[0:3] 0x009C[4:7] 0x009D[0:1] 0x009D[2:3] 0x009D[4:5] 0x009D[6:7] 0x009E[0:3] 0x009E[4:7] 0x009F[0:3] 0x009F[4:7] 0x00A0[0:3] 0x00A0[4:7] 0x00A1[0:3] 0x00A1[4:7] 0x00A2[0] 0x00A2[1] 0x00A2[2] 0x00A2[3] 0x00A3[0:34] 0x00A8[0:34] 0x00AD[0:34] 0x00B2[0:34] 0x0102[0] 0x0108[0] 0x0108[1] 0x0108[2] 0x0109[0:2] 0x0109[3] 0x0109[4:5] 0x0109[6:7] 0x010A[0:3] 0x010A[4:6] 0x010B[0:2] 0x010B[6:7] 0x010C[0:2] 0x0112[0] OOF2_RATIO_REF OOF3_RATIO_REF LOL_FST_EN_PLLA LOL_FST_EN_PLLB LOL_FST_EN_PLLC LOL_FST_EN_PLLD LOL_FST_DETWIN_SEL_PLLA LOL_FST_DETWIN_SEL_PLLB LOL_FST_DETWIN_SEL_PLLC LOL_FST_DETWIN_SEL_PLLD LOL_FST_VALWIN_SEL_PLLA LOL_FST_VALWIN_SEL_PLLB LOL_FST_VALWIN_SEL_PLLC LOL_FST_VALWIN_SEL_PLLD LOL_FST_SET_THR_SEL_PLLA LOL_FST_SET_THR_SEL_PLLB LOL_FST_SET_THR_SEL_PLLC LOL_FST_SET_THR_SEL_PLLD LOL_FST_CLR_THR_SEL_PLLA LOL_FST_CLR_THR_SEL_PLLB LOL_FST_CLR_THR_SEL_PLLC LOL_FST_CLR_THR_SEL_PLLD LOL_SLOW_EN_PLLA LOL_SLOW_EN_PLLB LOL_SLOW_EN_PLLC LOL_SLOW_EN_PLLD LOL_SLW_DETWIN_SEL_PLLA LOL_SLW_DETWIN_SEL_PLLB LOL_SLW_DETWIN_SEL_PLLC LOL_SLW_DETWIN_SEL_PLLD LOL_SLW_VALWIN_SEL_PLLA LOL_SLW_VALWIN_SEL_PLLB LOL_SLW_VALWIN_SEL_PLLC LOL_SLW_VALWIN_SEL_PLLD LOL_SLW_SET_THR_PLLA LOL_SLW_SET_THR_PLLB LOL_SLW_SET_THR_PLLC LOL_SLW_SET_THR_PLLD LOL_SLW_CLR_THR_PLLA LOL_SLW_CLR_THR_PLLB LOL_SLW_CLR_THR_PLLC LOL_SLW_CLR_THR_PLLD LOL_TIMER_EN_PLLA LOL_TIMER_EN_PLLB LOL_TIMER_EN_PLLC LOL_TIMER_EN_PLLD LOL_CLR_DELAY_PLLA LOL_CLR_DELAY_PLLB LOL_CLR_DELAY_PLLC LOL_CLR_DELAY_PLLD OUTALL_DISABLE_LOW OUT0_PDN OUT0_OE OUT0_RDIV_FORCE2 OUT0_FORMAT OUT0_SYNC_EN OUT0_DIS_STATE OUT0_CMOS_DRV OUT0_CM OUT0_AMPL OUT0_MUX_SEL OUT0_INV OUT0_DIS_SRC OUT1_PDN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 11 3 0 0 0 1 0x0000000 0x0000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x000000000 0x000000000 0x000000000 0x000000000 0x1 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 4 of 9 0x0112[1] 0x0112[2] 0x0113[0:2] 0x0113[3] 0x0113[4:5] 0x0113[6:7] 0x0114[0:3] 0x0114[4:6] 0x0115[0:2] 0x0115[6:7] 0x0116[0:2] 0x0117[0] 0x0117[1] 0x0117[2] 0x0118[0:2] 0x0118[3] 0x0118[4:5] 0x0118[6:7] 0x0119[0:3] 0x0119[4:6] 0x011A[0:2] 0x011A[6:7] 0x011B[0:2] 0x011C[0] 0x011C[1] 0x011C[2] 0x011D[0:2] 0x011D[3] 0x011D[4:5] 0x011D[6:7] 0x011E[0:3] 0x011E[4:6] 0x011F[0:2] 0x011F[6:7] 0x0120[0:2] 0x0126[0] 0x0126[1] 0x0126[2] 0x0127[0:2] 0x0127[3] 0x0127[4:5] 0x0127[6:7] 0x0128[0:3] 0x0128[4:6] 0x0129[0:2] 0x0129[6:7] 0x012A[0:2] 0x012B[0] 0x012B[1] 0x012B[2] 0x012C[0:2] 0x012C[3] 0x012C[4:5] 0x012C[6:7] 0x012D[0:3] 0x012D[4:6] 0x012E[0:2] 0x012E[6:7] 0x012F[0:2] 0x0130[0] 0x0130[1] 0x0130[2] 0x0131[0:2] 0x0131[3] OUT1_OE OUT1_RDIV_FORCE2 OUT1_FORMAT OUT1_SYNC_EN OUT1_DIS_STATE OUT1_CMOS_DRV OUT1_CM OUT1_AMPL OUT1_MUX_SEL OUT1_INV OUT1_DIS_SRC OUT2_PDN OUT2_OE OUT2_RDIV_FORCE2 OUT2_FORMAT OUT2_SYNC_EN OUT2_DIS_STATE OUT2_CMOS_DRV OUT2_CM OUT2_AMPL OUT2_MUX_SEL OUT2_INV OUT2_DIS_SRC OUT3_PDN OUT3_OE OUT3_RDIV_FORCE2 OUT3_FORMAT OUT3_SYNC_EN OUT3_DIS_STATE OUT3_CMOS_DRV OUT3_CM OUT3_AMPL OUT3_MUX_SEL OUT3_INV OUT3_DIS_SRC OUT4_PDN OUT4_OE OUT4_RDIV_FORCE2 OUT4_FORMAT OUT4_SYNC_EN OUT4_DIS_STATE OUT4_CMOS_DRV OUT4_CM OUT4_AMPL OUT4_MUX_SEL OUT4_INV OUT4_DIS_SRC OUT5_PDN OUT5_OE OUT5_RDIV_FORCE2 OUT5_FORMAT OUT5_SYNC_EN OUT5_DIS_STATE OUT5_CMOS_DRV OUT5_CM OUT5_AMPL OUT5_MUX_SEL OUT5_INV OUT5_DIS_SRC OUT6_PDN OUT6_OE OUT6_RDIV_FORCE2 OUT6_FORMAT OUT6_SYNC_EN 0 0 1 1 0 0 11 3 0 0 0 1 0 0 1 1 0 0 11 3 0 0 0 1 0 0 1 1 0 0 11 3 0 0 0 1 0 0 1 1 0 0 11 3 0 0 0 1 0 0 1 1 0 0 11 3 0 0 0 1 0 0 1 1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 5 of 9 0x0131[4:5] 0x0131[6:7] 0x0132[0:3] 0x0132[4:6] 0x0133[0:2] 0x0133[6:7] 0x0134[0:2] 0x013A[0] 0x013A[1] 0x013A[2] 0x013B[0:2] 0x013B[3] 0x013B[4:5] 0x013B[6:7] 0x013C[0:3] 0x013C[4:6] 0x013D[0:2] 0x013D[6:7] 0x013E[0:2] 0x013F[0:11] 0x0141[0] 0x0141[1] 0x0141[2] 0x0141[3] 0x0141[5] 0x0141[6] 0x0141[7] 0x0142[0] 0x0142[1] 0x0142[2] 0x0142[3] 0x0142[4] 0x0142[5] 0x0142[6] 0x0142[7] 0x0202[0:31] 0x0206[0:1] 0x0208[0:47] 0x020E[0:31] 0x0212[0:47] 0x0218[0:31] 0x021C[0:47] 0x0222[0:31] 0x0226[0:47] 0x022C[0:31] 0x0231[0:3] 0x0231[4] 0x0232[0:3] 0x0232[4] 0x0233[0:3] 0x0233[4] 0x0234[0:3] 0x0234[4] 0x0235[0:43] 0x023B[0:31] 0x0240[0] 0x0240[1] 0x0241[0:43] 0x024A[0:23] 0x0250[0:23] 0x0253[0:23] 0x0256[0:23] 0x025C[0:23] 0x025F[0:23] OUT6_DIS_STATE OUT6_CMOS_DRV OUT6_CM OUT6_AMPL OUT6_MUX_SEL OUT6_INV OUT6_DIS_SRC OUT7_PDN OUT7_OE OUT7_RDIV_FORCE2 OUT7_FORMAT OUT7_SYNC_EN OUT7_DIS_STATE OUT7_CMOS_DRV OUT7_CM OUT7_AMPL OUT7_MUX_SEL OUT7_INV OUT7_DIS_SRC OUTX_ALWAYS_ON OUT_DIS_MSK_PLLA OUT_DIS_MSK_PLLB OUT_DIS_MSK_PLLC OUT_DIS_MSK_PLLD OUT_DIS_LOL_MSK OUT_DIS_LOSXAXB_MSK OUT_DIS_MSK_LOS_PFD OUT_DIS_MSK_LOL_PLLA OUT_DIS_MSK_LOL_PLLB OUT_DIS_MSK_LOL_PLLC OUT_DIS_MSK_LOL_PLLD OUT_DIS_MSK_HOLD_PLLA OUT_DIS_MSK_HOLD_PLLB OUT_DIS_MSK_HOLD_PLLC OUT_DIS_MSK_HOLD_PLLD XAXB_FREQ_OFFSET PXAXB P0_NUM P0_DEN P1_NUM P1_DEN P2_NUM P2_DEN P3_NUM P3_DEN P0_FRACN_MODE P0_FRACN_EN P1_FRACN_MODE P1_FRACN_EN P2_FRACN_MODE P2_FRACN_EN P3_FRACN_MODE P3_FRACN_EN MXAXB_NUM MXAXB_DEN MXAXB_FSTEP_MSK MXAXB_FSTEP_DEN MXAXB_FSTEPW R0_REG R1_REG R2_REG R3_REG R4_REG R5_REG 0 0 11 3 0 0 0 1 0 0 1 1 0 0 11 3 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 3 0 3 0 3 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x0 0x000 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x00000000 0x0 0x000000000000 0x00000000 0x000000000000 0x00000000 0x000000000000 0x00000000 0x000000000000 0x00000000 0x3 0x0 0x3 0x0 0x3 0x0 0x3 0x0 0x00000000000 0x00000000 0x0 0x0 0x00000000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 6 of 9 0x0262[0:23] 0x0268[0:23] 0x026B[0:7] 0x026C[0:7] 0x026D[0:7] 0x026E[0:7] 0x026F[0:7] 0x0270[0:7] 0x0271[0:7] 0x0272[0:7] 0x0302[0:43] 0x0308[0:31] 0x030D[0:43] 0x0313[0:31] 0x0318[0:43] 0x031E[0:31] 0x0323[0:43] 0x0329[0:31] 0x0339[0:4] 0x033B[0:43] 0x0341[0:43] 0x0347[0:43] 0x034D[0:43] 0x0402[0] 0x0402[1] 0x0402[2] 0x0402[3] 0x0402[4] 0x0408[0:5] 0x0409[0:5] 0x040A[0:5] 0x040B[0:5] 0x040C[0:5] 0x040D[0:5] 0x040E[0:5] 0x040F[0:5] 0x0410[0:5] 0x0411[0:5] 0x0412[0:5] 0x0413[0:5] 0x0415[0:55] 0x041C[0:31] 0x0421[0:3] 0x0421[4] 0x0422[0] 0x0422[1] 0x0423[0:55] 0x042A[0:2] 0x042B[0] 0x042B[1] 0x042C[0] 0x042C[3] 0x042C[5:7] 0x042D[1] 0x042E[0:4] 0x042F[0:4] 0x0431[0:4] 0x0432[0:23] 0x0436[0:1] 0x0436[2] 0x0436[3] 0x0437[0:3] 0x0437[4:7] 0x0438[0:2] R6_REG R7_REG DESIGN_ID0 DESIGN_ID1 DESIGN_ID2 DESIGN_ID3 DESIGN_ID4 DESIGN_ID5 DESIGN_ID6 DESIGN_ID7 N0_NUM N0_DEN N1_NUM N1_DEN N2_NUM N2_DEN N3_NUM N3_DEN N_FSTEP_MSK N0_FSTEPW N1_FSTEPW N2_FSTEPW N3_FSTEPW PFD_PDNB_PLLA PFD_RST_PLLA M_RST_PLLA PFD_CLKM_STOP_PLLA ADD_DIV256_PLLA BW0_PLLA BW1_PLLA BW2_PLLA BW3_PLLA BW4_PLLA BW5_PLLA FAST_BW0_PLLA FAST_BW1_PLLA FAST_BW2_PLLA FAST_BW3_PLLA FAST_BW4_PLLA FAST_BW5_PLLA M_NUM_PLLA M_DEN_PLLA M_FRAC_MODE_PLLA M_FRAC_EN_PLLA M_FSTEP_MSK_PLLA M_FSTEPW_DEN_PLLA M_FSTEPW_PLLA IN_SEL_PLLA FASTLOCK_AUTO_EN_PLLA FASTLOCK_MAN_PLLA HOLD_EN_PLLA HOLD_RAMP_BYP_PLLA HOLD_RAMP_RATE_PLLA HOLD_RAMPBYP_NOHIST_PLLA HOLD_HIST_LEN_PLLA HOLD_HIST_DELAY_PLLA HOLD_REF_COUNT_FRC_PLLA HOLD_15M_CYC_COUNT_PLLA CLK_SWITCH_MODE_PLLA HSW_EN_PLLA HSW_RAMP_BYP_PLLA IN_LOS_MSK_PLLA IN_OOF_MSK_PLLA IN0_PRIORITY_PLLA 0 0 53 51 52 55 66 80 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 0 0 0 1 0 1 1 0 1 0 0 0 1024 2 1 1 0 0 0 0x000000 0x000000 0x35 0x33 0x34 0x37 0x42 0x50 0x32 0x00 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00 0x00000000000 0x00000000000 0x00000000000 0x00000000000 0x1 0x0 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00000000000000 0x00000000 0x3 0x0 0x1 0x0 0x00000000000000 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x00 0x00 0x00 0x000400 0x2 0x1 0x1 0x0 0x0 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 7 of 9 0x0438[4:6] 0x0439[0:2] 0x0439[4:6] 0x0502[4] 0x0508[0:5] 0x0509[0:5] 0x050A[0:5] 0x050B[0:5] 0x050C[0:5] 0x050D[0:5] 0x050E[0:5] 0x050F[0:5] 0x0510[0:5] 0x0511[0:5] 0x0512[0:5] 0x0513[0:5] 0x0515[0:55] 0x051C[0:31] 0x0521[0:3] 0x0521[4] 0x0522[0] 0x0522[1] 0x0523[0:55] 0x052A[0] 0x052A[1:3] 0x052B[0] 0x052B[1] 0x052C[0] 0x052C[3] 0x052C[5:7] 0x052D[1] 0x052E[0:4] 0x052F[0:4] 0x0531[0:4] 0x0532[0:23] 0x0536[0:1] 0x0536[2] 0x0536[3] 0x0537[0:3] 0x0537[4:7] 0x0538[0:2] 0x0538[4:6] 0x0539[0:2] 0x0539[4:6] 0x0602[4] 0x0608[0:5] 0x0609[0:5] 0x060A[0:5] 0x060B[0:5] 0x060C[0:5] 0x060D[0:5] 0x060E[0:5] 0x060F[0:5] 0x0610[0:5] 0x0611[0:5] 0x0612[0:5] 0x0613[0:5] 0x0615[0:55] 0x061C[0:31] 0x0621[0:3] 0x0621[4] 0x0622[0] 0x0622[1] 0x0623[0:55] IN1_PRIORITY_PLLA IN2_PRIORITY_PLLA IN3_PRIORITY_PLLA ADD_DIV256_PLLB BW0_PLLB BW1_PLLB BW2_PLLB BW3_PLLB BW4_PLLB BW5_PLLB FAST_BW0_PLLB FAST_BW1_PLLB FAST_BW2_PLLB FAST_BW3_PLLB FAST_BW4_PLLB FAST_BW5_PLLB M_NUM_PLLB M_DEN_PLLB M_FRAC_MODE_PLLB M_FRAC_EN_PLLB M_FSTEP_MSK_PLLB M_FSTEPW_DEN_PLLB M_FSTEPW_PLLB IN_SEL_REGCTRL_PLLB IN_SEL_PLLB FASTLOCK_AUTO_EN_PLLB FASTLOCK_MAN_PLLB HOLD_EN_PLLB HOLD_RAMP_BYP_PLLB HOLD_RAMP_RATE_PLLB HOLD_RAMPBYP_NOHIST_PLLB HOLD_HIST_LEN_PLLB HOLD_HIST_DELAY_PLLB HOLD_REF_COUNT_FRC_PLLB HOLD_15M_CYC_COUNT_PLLB CLK_SWITCH_MODE_PLLB HSW_EN_PLLB HSW_RAMP_BYP_PLLB IN_LOS_MSK_PLLB IN_OOF_MSK_PLLB IN0_PRIORITY_PLLB IN1_PRIORITY_PLLB IN2_PRIORITY_PLLB IN3_PRIORITY_PLLB ADD_DIV256_PLLC BW0_PLLC BW1_PLLC BW2_PLLC BW3_PLLC BW4_PLLC BW5_PLLC FAST_BW0_PLLC FAST_BW1_PLLC FAST_BW2_PLLC FAST_BW3_PLLC FAST_BW4_PLLC FAST_BW5_PLLC M_NUM_PLLC M_DEN_PLLC M_FRAC_MODE_PLLC M_FRAC_EN_PLLC M_FSTEP_MSK_PLLC M_FSTEPW_DEN_PLLC M_FSTEPW_PLLC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1024 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 0 0 0x0 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00000000000000 0x00000000 0x3 0x0 0x1 0x0 0x00000000000000 0x1 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x00 0x00 0x00 0x000400 0x2 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00000000000000 0x00000000 0x3 0x0 0x1 0x0 0x00000000000000 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 8 of 9 0x062A[0:2] 0x062B[0] 0x062B[1] 0x062C[0] 0x062C[3] 0x062C[5:7] 0x062D[1] 0x062E[0:4] 0x062F[0:4] 0x0631[0:4] 0x0632[0:23] 0x0636[0:1] 0x0636[2] 0x0636[3] 0x0637[0:3] 0x0637[4:7] 0x0638[0:2] 0x0638[4:6] 0x0639[0:2] 0x0639[4:6] 0x0702[4] 0x0709[0:5] 0x070A[0:5] 0x070B[0:5] 0x070C[0:5] 0x070D[0:5] 0x070E[0:5] 0x070F[0:5] 0x0710[0:5] 0x0711[0:5] 0x0712[0:5] 0x0713[0:5] 0x0714[0:5] 0x0716[0:55] 0x071D[0:31] 0x0722[0:3] 0x0722[4] 0x0723[0] 0x0723[1] 0x0724[0:55] 0x072B[0:2] 0x072C[0] 0x072C[1] 0x072D[0] 0x072D[3] 0x072D[5:7] 0x072E[1] 0x072F[0:4] 0x0730[0:4] 0x0732[0:4] 0x0733[0:23] 0x0737[0:1] 0x0737[2] 0x0737[3] 0x0738[0:3] 0x0738[4:7] 0x0739[0:2] 0x0739[4:6] 0x073A[0:2] 0x073A[4:6] 0x090E[0] 0x0943[0] 0x0949[0:3] 0x0949[4:7] IN_SEL_PLLC FASTLOCK_AUTO_EN_PLLC FASTLOCK_MAN_PLLC HOLD_EN_PLLC HOLD_RAMP_BYP_PLLC HOLD_RAMP_RATE_PLLC HOLD_RAMPBYP_NOHIST_PLLC HOLD_HIST_LEN_PLLC HOLD_HIST_DELAY_PLLC HOLD_REF_COUNT_FRC_PLLC HOLD_15M_CYC_COUNT_PLLC CLK_SWITCH_MODE_PLLC HSW_EN_PLLC HSW_RAMP_BYP_PLLC IN_LOS_MSK_PLLC IN_OOF_MSK_PLLC IN0_PRIORITY_PLLC IN1_PRIORITY_PLLC IN2_PRIORITY_PLLC IN3_PRIORITY_PLLC ADD_DIV256_PLLD BW0_PLLD BW1_PLLD BW2_PLLD BW3_PLLD BW4_PLLD BW5_PLLD FAST_BW0_PLLD FAST_BW1_PLLD FAST_BW2_PLLD FAST_BW3_PLLD FAST_BW4_PLLD FAST_BW5_PLLD M_NUM_PLLD M_DEN_PLLD M_FRAC_MODE_PLLD M_FRAC_EN_PLLD M_FSTEP_MSK_PLLD M_FSTEPW_DEN_PLLD M_FSTEPW_PLLD IN_SEL_PLLD FASTLOCK_AUTO_EN_PLLD FASTLOCK_MAN_PLLD HOLD_EN_PLLD HOLD_RAMP_BYP_PLLD HOLD_RAMP_RATE_PLLD HOLD_RAMPBYP_NOHIST_PLLD HOLD_HIST_LEN_PLLD HOLD_HIST_DELAY_PLLD HOLD_REF_COUNT_FRC_PLLD HOLD_15M_CYC_COUNT_PLLD CLK_SWITCH_MODE_PLLD HSW_EN_PLLD HSW_RAMP_BYP_PLLD IN_LOS_MSK_PLLD IN_OOF_MSK_PLLD IN0_PRIORITY_PLLD IN1_PRIORITY_PLLD IN2_PRIORITY_PLLD IN3_PRIORITY_PLLD XAXB_EXTCLK_EN IO_VDD_SEL IN_EN IN_PULSED_CMOS_EN 0 1 0 1 1 0 1 0 0 0 1024 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 0 0 0 1 0 1 1 0 1 0 0 0 1024 2 1 1 0 0 0 0 0 0 0 0 0 0 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x00 0x00 0x00 0x000400 0x2 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00000000000000 0x00000000 0x3 0x0 0x1 0x0 0x00000000000000 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x00 0x00 0x00 0x000400 0x2 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5347B Datasheet Addendum Device Configuration Summary for Si5347B-B-GM Page 9 of 9 0x094A[0:3] 0x0A03[0:4] 0x0A04[0:4] 0x0A05[0:4] 0x0B44[0:3] 0x0B44[4] 0x0B44[5] 0x0B44[6] 0x0B44[7] 0x0B45[0] 0x0B45[1] 0x0B45[2] 0x0B45[3] 0x0B46[0:3] 0x0B47[0:4] 0x0B48[0:4] 0x0B4A[0:4] INX_TO_PFD_EN N_CLK_TO_OUTX_EN N_PIBYP N_PDNB PDIV_FRACN_CLK_DIS FRACN_CLK_DIS_PLLA FRACN_CLK_DIS_PLLB FRACN_CLK_DIS_PLLC FRACN_CLK_DIS_PLLD CLK_DIS_PLLA CLK_DIS_PLLB CLK_DIS_PLLC CLK_DIS_PLLD LOS_CLK_DIS OOF_CLK_DIS OOF_DIV_CLK_DIS N_CLK_DIS 15 15 0 15 0 0 0 0 0 0 0 0 0 0 0 15 0 0xF 0x0F 0x00 0x0F 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00 0x0F 0x00 This datasheet addendum is provided as supplemental information to the Si5347B datasheet, located at www.silabs.com/timing. You can search for and download any datasheet addendum for Si534x/8x part numbers. Go to http://www.silabs.com/custom-timing for more information. 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