S i 5 3 5 / 5 36 修訂 D 超 低抖動 晶 體 振 盪 器 (XO) 特點 可選取從 100 MHz 至 312.5 MHz 的 可透過 LVPECL 和 LVDS 選項 各種頻率 使用 ® 第三代 DSPLL ，有卓越的抖動性能 3.3 和 2.5 V 電源選項 和高電源噪音抑制 業界標準 5 x 7 mm 封裝和插 腳引線 頻率穩定性是 SAW 振盪器的三倍 符合無鉛 / RoHS 要求 Si5602 應用 訂購資訊： 10/40/100G 資料中心 10G 乙太網交換機 / 路由器 光纖通道 /SAS/ 存儲 見 第 7 頁。 企業伺服器 網路 電信 引腳分配： 見 第 6 頁。 描述 Si535/536 XO 利用 Silicon Laboratories 先進的 DSPLL® 電路在高速差分頻 率 下 提 供 超 低 抖 動 時 鐘。傳 統 晶 體 振 盪 器 對 不 同 頻 率 需 要 不 同 的 晶 體， Si535/536 與之不同，能使用一個固定的晶體提供廣泛的輸出頻率。這種基於 IC 的方法能使晶體諧振器具有超強的頻率穩定性和可靠性。此外，DSPLL 時 鐘合成能提供卓越的電源噪音抑制能力，簡化通訊系統中經常需要在噪音環境 下生成低抖動時鐘的任務。Si535/536 基於 IC 的振盪器在發貨時由工廠程式設 計，消除了與定制頻率振盪器有關的長交付週期。 原理框圖 (Top View) NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Si535 VDD Fixed Frequency XO CLK– CLK+ 100–312.5 MHz DSPLL® Clock Synthesis OE 1 6 VDD NC 2 5 CLK– GND 3 4 CLK+ Si536 OE Rev 1.0 9/14 GND Copyright © 2014 by Silicon Laboratories Si535/536 Si535/536 1. 电气规格 Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Supply Current Symbol Test Condition Min Typ Max Unit VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V Output enabled LVPECL LVDS — — 111 90 121 98 mA Tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 °C IDD Output Enable (OE)2 Operating Temperature Range TA Notes: 1. Selectable parameter specified by part number. See Section 第 7 頁上的 3. 「訂購資訊」 for further details. 2. OE pin includes a 17 k pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1 Initial Accuracy Symbol Test Condition Min Typ Max Unit fO LVPECL/LVDS 100 — 312.5 MHz fi Measured at +25 °C at time of shipping — ±1.5 — ppm –7 –20 — — +7 +20 ppm Frequency drift over first year — — ±3 ppm Frequency drift over 20 year life — — ±10 ppm Temp stability = ±20 ppm — — ±31.5 Temp stability = ±7 ppm — — 20 TA = –40°C — +85°C — — 10 Temperature Stability1,2 Aging fa Total Stability2 ppm Powerup Time3 tOSC Notes: 1. See Section 第 7 頁上的 3. 「訂購資訊」for the list of available frequencies. 2. Selectable parameter specified by part number. 3. Time from powerup or tristate mode to fO. 2 Rev 1.0 ms Si535/536 Table 3. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Unit VO Mid-level VDD – 1.42 — VDD – 1.25 V VOD Swing (diff) 1.1 — 1.9 VPP VSE Swing (Single-ended) 0.55 — 0.95 VPP VO Mid-level 1.125 1.20 1.275 V VOD Swing (diff) 0.5 0.7 0.9 VPP — — 350 ps 45 — 55 % LVPECL Output Option1 LVDS Output Option 2 Rise/Fall time (20/80%) tR, tF Symmetry (duty cycle) SYM Differential Notes: 1. 50 to VDD – 2.0 V. 2. Rterm = 100 (differential). Rev 1.0 3 Si535/536 Table 4. CLK± Output Phase Jitter Parameter LVPECL/LVDS Phase Jitter* (RMS) Symbol Test Condition Min Typ Max Unit J 10 kHz to 1 MHz (data center) — 0.19 0.35 ps 12 kHz to 20 MHz brickwall — 0.25 0.40 ps Symbol Test Condition Min Typ Max Unit JPER RMS — 2 — ps Peak-to-Peak — 14 — ps *Note: Applies to output frequencies: 156.25 MHz. Table 5. CLK± Output Period Jitter Parameter LVPECL/LVDS Period Jitter* *Note: N = 1000 cycles. Figure 1. Si535/536 Typical Phase Noise at 156.25 MHz 4 Rev 1.0 Si535/536 Table 6. Environmental Compliance The Si535/536 meets the following qualification test requirements. Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross & Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level J-STD-020, MSL1 Gold over Nickel Contact Pads Table 7. Thermal Characteristics (Typical values TA = 25 ºC, VDD = 3.3 V) Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W Ambient Temperature TA –40 — 85 °C Junction Temperature TJ — — 125 °C Table 8. Absolute Maximum Ratings1 Parameter Symbol Rating Unit Maximum Operating Temperature TAMAX 85 °C Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V Input Voltage (any input pin) VI –0.5 to VDD + 0.3 V Storage Temperature TS –55 to +125 °C ESD 2500 V TPEAK 260 °C tP 20–40 seconds ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Rev 1.0 5 Si535/536 2. 引腳描述 (Top View) NC 1 6 VDD OE 1 6 VDD OE 2 5 CLK– NC 2 5 CLK– GND 3 4 CLK+ GND 3 4 CLK+ Si536 Si535 Table 9. Pinout for Si535 Series Pin Symbol Function 1 NC No connection 2 OE Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK– Complementary Output 6 VDD Power Supply Voltage *Note: OE includes a 17 k pullup resistor to VDD. Table 10. Pinout for Si536 Series Pin Symbol Function 1 OE Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 No connection No connection 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK– Complementary output 6 VDD Power Supply Voltage *Note: OE includes a 17 k pullup resistor to VDD. 6 Rev 1.0 Si535/536 3. 訂購資訊 Si535/536 XO 支援許多選項，包括頻率、溫度穩定性、輸出格式和 VDD。Si535 和 Si536 XO 系列發貨時使用業界標準 符合 RoHS 要求的 6 墊 5 x 7 mm 封裝。Si536 系列支援 LVPECL 和 LVDS 輸出格式下的補充 OE 插腳引線（引腳 #1）。 Si535 和 Si536 的插腳引線差異請見表 9 和 10。 53x X X XXXMXXX D G R Tape & Reel Packaging Blank = Trays Device Output Enable 535 pin 2 536 pin 1 Operating Temp Range (°C) G -40 to +85 °C Part Revision Letter 1st Option Code A B E F VDD 3.3 3.3 2.5 2.5 Output Format Output Enable Polarity LVPECL High LVDS High LVPECL High LVDS High Frequency (e.g., 156M250 is 156.250 MHz) Select frequencies available in the frequency range 100 to 312.5 MHz are listed below. Frequencies requiring greater than 6 digit resolution are assigned a six digit code. Available Frequencies 106.250 MHz 125.000 MHz 150.000 MHz 155.520 MHz 156.250 MHz 156.2578 MHz 156.2539 MHz 156.26953 MHz 159.375 MHz 161.1328 MHz 166.6286 MHz 167.3316 MHz 212.500 MHz 312.500 MHz Frequency Order Code 106M250 125M000 150M000 155M520 156M250 000305 000335 000338 159M375 000174 000118 000119 212M500 312M500 2nd Option Code Code Temperature Stability (ppm, max, ±) B 20 C 7 Total Stablility (ppm, max, ±) 31 .5 20 Example P/N: 535AB156M250DGR is a 5 x 7 XO in a 6 pad package. The frequency is 156.250 MHz, with a 3.3 V supply, LVPECL output, and Output Enable active high polarity. Temperature stability is specifed as ±20 ppm. The part is specified for –40 to +85 °C ambient temperature range operation and is shipped in tape and reel format. Figure 2. Part Number Convention Rev 1.0 7 Si535/536 4. 封裝外形 圖 3 說明 Si535/536 的封裝詳細資訊。表 11 列出插圖中尺寸值。 Figure 3. Si535/536 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 H L p R aaa bbb ccc ddd eee 8 Min 1.50 1.30 0.50 4.30 6.10 0.55 1.17 1.80 Nom 1.65 1.40 0.60 5.00 BSC 4.40 2.54 BSC 7.00 BSC 6.20 0.65 1.27 — 0.70 REF 0.15 0.15 0.10 0.10 0.05 Rev 1.0 Max 1.80 1.50 0.70 4.50 6.30 0.75 1.37 2.60 Si535/536 5. 6 引腳 PCB 焊盤模式 圖 4 说明 6 引腳 PCB 焊盤模式。表 12 列出插圖中尺寸值。 Figure 4. Si535/536 PCB Land Pattern Table 12. PCB Land Pattern Dimensions (mm) Dimension Min C1 4.20 E 2.54 X1 1.55 Y1 1.95 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. Rev 1.0 9 Si535/536 6. Si535/Si536 標記規范 圖 5 說明 Si535/Si536 的標記規范。表 13 列出線路資訊。 Figure 5. Mark Specification Table 13. Si53x Top Mark Description Line Position Description 1 1–10 “SiLabs”+ Part Family Number, 53x (First 3 characters in part number where x = 5 indicates a 535 device and x = 6 indicates a 536 device). 2 1–10 Si535, Si536: Option1 + Option2 + Freq(7) + Temp Si535/Si536 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 10 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2013 = 3) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Rev 1.0 Si535/536 文件變更清單 修訂版 0.2 至修訂版 0.3 更新了 第 5 頁上的表 7。 修訂版 0.3 至修訂版 0.5 更新了第 2 頁上的表 2 中的備註 1。 更新了第 3 頁上的表 3 中的 「對稱測試條件」。。 更新了第 4 頁上的表 4。 更新了第 4 頁上的表 5。 更新了第 7 頁上圖 2 中的 XXXMXXX 文字。 更新了第 8 頁上的 4. 「封裝外形」。 更新了第 7 頁上圖 2. 中的 XXXMXXX 文字。 更新了 第 8 頁上的 4. 「封裝外形」。 修訂版 0.5 至修訂版 0.6 更新了 第 7 頁上圖 2。 更新了第 10 頁上的焊盤圖案資訊。 修訂版 0.6 到修訂版 0.7 更新了第 2 頁表 2 中的上電時間測試條件。 在第 7 頁上圖 2 上新增了頻率選項。 修订版 0.7 至修订版 1.0 更新了第 4 頁上的表 4。 Rev 1.0 11 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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