19-2268; Rev 2; 1/03 Dual 1.25Gbps Transceiver ♦ CML Interface Exceeds all PECL AC Specifications for 1000Base-SX/LX, GBIC, or SFP Serial Data ♦ Tx Data Retiming with <0.1UI Total Output Jitter as per IEEE802.3z ♦ Rx Data and Clock Recovery with 0.75UI Jitter Tolerance as per IEEE802.3z ♦ On-Chip Forward and Back Termination Using CML I/O and Integrated Termination/Bias Resistors ♦ PLL Lock Status Indicator ♦ System Loopback ♦ JTAG I/O Scan for Board-Level Testing Ordering Information PART TEMP RANGE PINPACKAGE PKG CODE MAX3782UGK -5°C to +85°C 68 QFN-EP* G6800-4 *EP = exposed pad. Applications 63 62 61 60 59 58 VCC6 RESET TCLK1+ TCLK1- TDAT1+ TDAT1- GND REFCLK+ REFCLK- VCC6 GND RCLK1- RCLK1+ 67 66 65 64 RDAT1+ 68 RDAT1- TOP VIEW VCC5 Pin Configuration TDO-JTAG The receive path converts the CML signaling to LVDS and locks on to the data stream to recover the sourcesynchronous clock (RCLK). The receive section contains a CML input buffer, clock recovery circuit, and LVDS output buffers. The receiver accepts a CML serial data stream. The clock recovery phase-locked loop (PLL) locks on to the incoming serial data stream and generates a 625MHz LVDS DDR clock. RCLK edges are at the center of the “eye” of RDAT data. Features ♦ 1000Base-SX/LX, GBIC, or SFP Serial Data Conversion to/from 1.25Gbps LVDS Serial Data and DDR Clock 57 56 55 54 53 52 GND 1 51 GND 1000Base-SX/LX Optical Links TCLK2+ 2 50 VCC1 TCLK2- 3 49 TXFIL GBIC Modules TDAT2+ 4 48 GND TDAT2- 5 47 VCC4 GND 6 46 TX2+ TRST-JTAG 7 45 TX2- VCC5 8 44 VCC4 RCLK2+ 9 43 GND RCLK2- 10 42 VCC4 RDAT2+ 11 41 TX1+ RDAT2- 12 40 TX1- GND 13 39 VCC4 LOCK 14 38 VCC6 VCC3 15 37 RXFIL1 RXFIL2 16 36 VCC2 GND 17 35 GND SFP Fiber Transceiver Modules Typical Application Circuit appears at end of data sheet. MAX3782 LOOPEN TEMPSENS VCCTEMP GND RX2- VCC5 RX2+ VCC5 GND RX1- VCC5 RX1+ VCC5 GND TCLK-JTAG TDI-JTAG TMS-JTAG 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 QFN* * THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION OF THE MAX3782. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3782 General Description The MAX3782 is a dual 1.25Gbps data retiming and clock recovery transceiver. It interfaces 1.25Gbps LVDS data and clock to a 1.25Gbps serial interface compatible with 1000Base-SX/LX (IEEE 802.3z-2000) standards, GBIC, and small form-factor pluggable (SFP) module interface recommendations. The serial differential transmitter and receiver are PECL compatible using an ACcoupled CML interface with on-chip termination/bias resistors for superior forward and back terminations. The transmit path converts the LVDS signaling to CML and retimes the serial data to a low-jitter reference clock. The transmitter section contains LVDS buffers, FIFO, clock multiplier, and CML output buffers. The transmitter accepts a single 1.25Gbps serial-data channel and a 625MHz double-data-rate (DDR) clock that are compatible with IEEE Std 1596-1996 DC specifications. Serial LVDS data is clocked into the FIFO on both edges of the 625MHz source-synchronous TCLK. Data is clocked out of the FIFO using an internal 1.25GHz clock derived from a low-jitter 125MHz reference. Serial data is then clocked out as differential CML. MAX3782 Dual 1.25Gbps Transceiver ABSOLUTE MAXIMUM RATINGS TEMPSENS, RXFIL1, RXFIL2, TXFIL Voltage .........................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 68-Pin QFN (derate 38.5mW/°C above +85°C) ...............2.5W Operating Ambient Temperature Range ...............-5°C to +85°C Operating Junction Temperature Range .............-5°C to +150°C Storage Ambient Temperature Range...............-55°C to +150°C ESD Human Body Model (any pin) ....................................2000V Supply Voltage (VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCCTEMP) ......................-0.5V to +4.0V LVDS Input and Output Voltage .................-0.5V to (VCC + 0.5V) LVTTL Input or Output Voltage...................-0.5V to (VCC + 0.5V) CML Input Voltage......................................-0.5V to (VCC + 0.5V) Continuous CML Output Current ......................-10mA to +25mA Momentary CML Output Voltage (duration <1min, +25°C)...............................0 to (VCC + 0.5V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, TA = -5°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Supply Current Power Dissipation Supply Noise Tolerance DC-500kHz, single-ended REFCLK (Note 1) TYP MAX UNITS 440 620 mA 1.45 2.23 50 W mVP-P LVTTL INPUTS AND OUTPUTS (except REFCLK±) Input High Voltage 2.0 V Input Low Voltage 0.8 V Input High Current -250 µA -500 µA Input Low Current Output High Voltage (Note 2) Output Low Voltage (Note 2) Output Three-State Current Three-state enabled, 0.4V ≤ VOUT ≤ VCC 2.4 V 0.4 -100 +100 Three-state enabled, GND ≤ VOUT < 0.4V 400 V µA REFCLK INPUTS Differential Input Amplitude REFCLK± AC-coupled 200 2000 mVP-P Single-Ended Input High Voltage REFCLK- connected through 0.01µF to GND 2.0 Single-Ended Input Low Voltage REFCLK- connected through 0.01µF to GND 0.8 V REFCLK Input High Current 2.0V ≤ VIN ≤ VCC 440 µA REFCLK Input Low Current GND ≤ VIN ≤ 0.8V -227 µA 2000 mVP-P 115 Ω 2000 mVP-P 115 Ω V CML INPUTS (Note 3) Differential Input Voltage Range 802.3z and GBIC compatible Common-Mode Voltage Inputs open or AC-coupled Input Impedance (Note 4) 370 VCC - 0.3 85 100 V CML OUTPUTS (Note 3) Differential Output Voltage 1100 Output Common-Mode Voltage Differential Output Impedance 2 VCC - 0.4 (Note 4) 85 100 _______________________________________________________________________________________ V Dual 1.25Gbps Transceiver (VCC = 3.0V to 3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, TA = -5°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2000 mV 500 mV LVDS INPUTS Input Voltage Range VI Differential Input Voltage |VID| Differential Input Impedance RIN Input Common-Mode Current |VGPD| < 925mV |VGPD| < 925mV 0 150 85 VOS = 1.2V, inputs tied together 100 115 Ω 270 400 µA 400 mV LVDS OUTPUTS Differential Output Voltage |VOD| Output High Voltage VOH Output Low Voltage VOL Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance 250 1.475 0.925 ∆|VOD| VOS 1.125 ∆|VOS| ROD Short-Circuit Current 80 V V 100 Short to supply or ground 25 mV 1.275 V 25 mV 120 Ω 40 mA Note 1: Supply noise tolerance is the amount of noise allowable on the power supply. The intent of this is to specify the conditions whereby the CML I/O jitter performance remains compliant with IEEE802.3z jitter specifications. Note 2: The LOCK output is open collector and requires a 10kΩ pullup to VCC. TDO output load ≥ 11kΩ to VCC or to GND. Note 3: CML differential signal amplitudes are specified as the total signal across the load (V+ - V-). CML inputs and outputs are designed to be AC-coupled. Note 4: 100Ω is standard for SFP, nonstandard for IEEE802.3z and GBIC. AC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, REFCLK = 125MHz, TA = -5°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data input to clock positive edge 15 7 15 MHz ns Hold Time Clock positive edge to data input 13 5 ns Propagation Delay Clock negative edge to data output (C ≤ 20pF) 2 30 ns TDO Output Rise Time C ≤ 20pF, measured 20% to 80% 2 20 ns TDO Output Fall Time C ≤ 20pF, measured 20% to 80% 1 20 ns TDO Output Three-State to Active Time C ≤ 20pF, measured as rise or fall time 1 30 ns JTAG PARAMETERS Clock Frequency Setup Time _______________________________________________________________________________________ 3 MAX3782 DC ELECTRICAL CHARACTERISTICS (continued) MAX3782 Dual 1.25Gbps Transceiver AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.0V to 3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, REFCLK = 125MHz, TA = -5°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOCK DETECT PARAMETERS Assert Time To assert, the Tx and Rx PLL internal lock indicators must be high (lock achieved) for this period. 394 µs Deassert Time To deassert, the Tx or Rx PLL internal lock indicators must be low for this period 1053 µs TRANSMITTER PARAMETERS TCLK Frequency 625 REFCLK Input Rise/Fall Time Single ended, 20% to 80% Transmitter Latency From TDAT to Tx MHz 2 ns 5 ns ±1 ns LVDS INPUTS Accumulated Phase Error at TCLK1 or TCLK2 Relative to REFCLK Setup Time tSU Figure 1 100 42 ps Hold Time tH Figure 1 100 42 ps CML OUTPUTS Differential Skew 25 ps Tx Output Jitter, Total (Notes 6, 8) 32 73 psP-P Tx Output Jitter, Deterministic (Notes 6, 8) 9 20 psP-P Tx Output Jitter, Random (Notes 6, 8) 23 53 psP-P RECEIVER PARAMETERS (Notes 7, 8) Input Data Rate PLL Lock Time Input Jitter Tolerance (Note 9) Differential Skew Tolerance K28.5 pattern applied to Rx inputs, REFCLK must be applied and stable 4 Gbps 1 ms Pattern = 27 - 1, differential skew = 0, 0.45UIP-P of data-dependent jitter 0.938 Pattern = CRPAT, differential skew = 0ps, 0.45UIP-P of data-dependent jitter 0.885 UIP-P Pattern = CRPAT, differential skew = 218ps, 0.45UIP-P of data-dependent jitter 0.776 0.838 Pattern = CJTPAT, differential skew = 218ps, 0.248UIP-P of pulse-width distortion (Note 10) 0.595 0.694 802.3z and GBIC compliant Jitter Generation Receiver Latency 1.25 205 ps 20 From Rx to RDAT 5 _______________________________________________________________________________________ 100 psP-P ns Dual 1.25Gbps Transceiver (VCC = 3.0V to 3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, REFCLK = 125MHz, TA = -5°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +32 ps 50 psP-P LVDS OUTPUTS Clock Duty-Cycle Distortion Variation of 50% crossing from ideal time Deterministic Jitter Measured with K28.5 pattern at RDAT_ outputs Edge Speed tr, tf Clock-to-Data Delay τCLK-Q -32 8 20% to 80% Figure 2 268 200 250 ps 400 532 ps +100 ppm REFERENCE CLOCK REQUIREMENTS REFCLK Frequency 125 REFCLK Frequency Tolerance -100 REFCLK Duty Cycle 40 f < 5kHz, jitter assumed Gaussian REFCLK Jitter f > 5kHz, jitter is assumed deterministic, caused by power-supply noise and buffer jitter MHz 60 % 210 psP-P 15 psRMS 20 psP-P Note 5: AC characteristics are guaranteed by design and characterization. Note 6: Tx output jitter, total, is the sum of both deterministic (20psP-P max) and random (53psP-P max at BER = 10-12), as per IEEE802.3z. Measured with K28.5 pattern and one-pole 637kHz highpass filter weighting. Note 7: JITTER TEST METHODS: These are described in the draft technical report by ANSI T11.2/Project 1230, document FC-MJS, “Fibre Channel - Methodologies for Jitter Specification.” The maximum BER used to specify both Fibre Channel links, as well as IEEE802.3z links is 10-12. Note 8: JITTER TEST CONDITIONS: The difference between the MAX3782 jitter specifications and the IEEE802.3z standards (see Table 1) represents the margin that must absorb all impairments such as jitter transfer from REFCLK, power-supply noise, and oscillator pulling (due to different Tx and Rx frequencies). Note 9: Input jitter tolerance is the total amount of high-frequency jitter at the inputs. Total jitter = deterministic jitter (DJ) + random jitter (RJ) + 5MHz sinusoidal jitter (SJ). Random jitter = 2psRMS (35mUIRMS). Note 10: CJTPAT is a unique pattern, which toggles between high transition-density sections to low transition-density sections at a rate within the loop bandwidth of a CDR. Passing this signal through a band-limited channel results in data-dependent jitter (DDJ) that has instantaneous phase jumps occurring at the rate of transition-density change. The phase vs. time looks like a low-frequency square wave. A 0.5UIP-P low-frequency square wave of jitter is the maximum that can be tolerated by an ideal CDR. In other words, 0.5UIP-P low-frequency square-wave jitter produces an equivalent stress as 1.0UIP-P high-frequency square-wave jitter. _______________________________________________________________________________________ 5 MAX3782 AC ELECTRICAL CHARACTERISTICS (continued) MAX3782 Dual 1.25Gbps Transceiver DIFFERENTIAL AMPLITUDE tH = 100ps 1000mVP-P MAXIMUM INPUT 300mVP-P MINIMUM INPUT τCLK-Q τCLK-Q tSU = 100ps CENTER OF RISING OR FALLING CLOCK EDGE Figure 1. LVDS Receiver Input Eye Mask Figure 2. Definition of Clock-to-Data Delay Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) TRANSMITTER JITTER TRANSFER (REFLCK TO TX_) 650 600 550 -4 -6 -2 -4 -6 -8 -8 -10 20 30 40 50 60 70 80 -10 0.1 1 10 100 1k 100 1k JITTER FREQUENCY (Hz) TEMPSENS VOLTAGE vs. TEMPERATURE RECEIVER POWER-SUPPLY REJECTION RATIO TRANSMIT CLOCK SYNTHESIZER POWER-SUPPLY REJECTION RATIO MAX3782 toc04 410 390 370 350 330 310 290 270 250 1 0.1 0.01 0.001 60 80 100 120 140 JUNCTION TEMPERATURE (°C) 1 10k WITHOUT HIGHPASS WEIGHTING 0.1 637kHz HIGHPASS WEIGHTING AS PER IEEE802.3z METHOD 0.01 0.0001 40 ADDED DETERMINISTIC JITTER (psP-P/mVP-P) JITTER FREQUENCY (Hz) 430 20 10 AMBIENT TEMPERATURE (°C) 450 0 1 10k MAX3782 toc05 10 ADDED DETERMINISTIC JITTER (psP-P/mVP-P) 0 MAX3782 toc06 400 TEMPSENS VOLTAGE (mV) -2 500 450 6 0 JITTER TRANSFER (dB) 0 JITTER TRANSFER (dB) 700 2 MAX3782 toc02 750 SUPPLY CURRENT (mA) 2 MAX3782 toc01 800 RECEIVER JITTER TRANSFER (RX_ TO RCLK) MAX3782 toc03 SUPPLY CURRENT vs. TEMPERATURE 0.1 1 10 100 NOISE FREQUENCY (MHz) 1000 100 1k 10k FREQUENCY (Hz) _______________________________________________________________________________________ 100k Dual 1.25Gbps Transceiver VCOTX AND VCORX1 PULLING TO VCORX2 10 8 6 4 2 10 8 6 4 2 0 0 100 200 300 400 500 600 0 100 FREQUENCY DIFFERENCE (ppm) 200 300 400 500 15 10 5 637kHz HIGHPASS WEIGHTING AS PER IEEE802.3z METHOD 600 0 100 200 300 400 500 FREQUENCY DIFFERENCE (ppm) RECOVERED EYE SINUSOIDAL JITTER TOLERANCE vs. FREQUENCY MAX3782 toc11 100mV/ div MAX3782 toc09 20 FREQUENCY DIFFERENCE (ppm) MAX3782 toc10 INPUT EYE (DJ = 0.4UIP-P, SJ = 0.5UIP-P AT 5MHz, 27-1 PRBS) 100mV/ div WITHOUT HIGHPASS WEIGHTING 25 0 600 100 SINUSOIDAL JITTER AMPLITUDE (UIP-P) 0 12 30 WITH 0.4 UIP-P OF DATA-DEPENDENT JITTER PRESENT, PATTERN = 27 - 1 PRBS MAX3782 toc12 12 MAX3782 toc08 14 14 ADDED DETERMINISTIC JITTER (psP-P) MAX3782 toc07 ADDED DETERMINISTIC JITTER (psP-P) 16 VCORX1 AND VCORX2 PULLING TO VCOTX ADDED DETERMINISTIC JITTER (psP-P) VCOTX AND VCORX2 PULLING TO VCORX1 10 1 0.1 200ps/div 10k 200ps/div 100k 1M 10M JITTER FREQUENCY (Hz) 5MHz JITTER TOLERANCE vs. INPUT AMPLITUDE 0.1 MAX3782 toc14 2000 VARIATION OF DELAY AFTER RESET (ps) SINUSOIDAL JITTER AMPLITUDE (UIP-P) WITH 0.4UIP-P OF DATA-DEPENDENT JITTER PRESENT, PATTERN = 27 - 1 PRBS MAX3782 toc13 1 REFCLK TO TCLK ACCUMULATED PHASE-ERROR TOLERANCE 1500 1000 ERROR-FREE OPERATION 500 0 -500 -1000 REFCLK ALIGNED TO TCLK -1500 -2000 -2500 1 10 100 1000 INPUT AMPLITUDE (mVP-P) 10,000 0 100 200 300 400 500 600 700 800 PHASE AT RESET (ps) _______________________________________________________________________________________ 7 MAX3782 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) Dual 1.25Gbps Transceiver MAX3782 Pin Description PIN NAME 1, 6, 13, 17, 21, 26, 31, 35, 43, 48, 51, 58, 62 GND 2 TCLK2+ Transmitter Positive Clock Input 2, LVDS. Input data is clocked on both the rising and falling edges of the 625MHz clock. 3 TCLK2- Transmitter Negative Clock Input 2, LVDS. Input data is clocked on both the rising and falling edges of the 625MHz clock. 4 TDAT2+ Transmitter Positive Data Input 2, LVDS 5 TDAT2- Transmitter Negative Data Input 2, LVDS 7 TRST-JTAG 8, 22, 25, 27, 30, 67 VCC5 9 RCLK2+ Receiver Positive Clock Output 2, LVDS. Output data is clocked on both the rising and falling edges of the 625MHz clock. 10 RCLK2- Receiver Negative Clock Output 2, LVDS. Output data is clocked on both the rising and falling edges of the 625MHz clock. 11 RDAT2+ Receiver Positive Data Output 2, LVDS 12 RDAT2- 14 8 LOCK 15 VCC3 16 RXFIL2 FUNCTION Supply Ground JTAG Test Reset Input, LVTTL. Momentarily connect TRST to GND to reset JTAG test circuitry. Internally pulled high through 15kΩ resistor. 3.3V Supply for Receiver Digital Functions and JTAG Circuitry Receiver Negative Data Output 2, LVDS Lock Status Indicator Output, LVTTL. This output goes high when the transmit PLL and receiver PLLs are in lock. Because this output is open-collector TTL, the LOCK pins from multiple MAX3782s can be connected in parallel to form a single LOCK signal. 3.3V Supply for RX2 Receiver VCO, Analog Receiver Functions, and External Loop-Filter Connection RX2 Receiver Loop-Filter Connection. Connect a 0.1µF capacitor between RXFIL2 and VCC3. 18 TDI-JTAG JTAG Test Data Input, LVTTL. Internally pulled high through 15kΩ resistor. 19 TMS-JTAG JTAG Test Mode Select Input, LVTTL. Internally pulled high through 15kΩ resistor. 20 TCLK-JTAG 23 RX1+ Receiver Positive Input 1, CML 24 RX1- Receiver Negative Input 1, CML 28 RX2+ Receiver Positive Input 2, CML 29 RX2- Receiver Negative Input 2, CML 32 VCCTEMP 3.3V Supply for TEMPSENS. Connect to ground to disable the temperature-sensing function. 33 TEMPSENS Junction Temperature Sensor Output, Analog. TEMPSENS corresponds to the junction temperature of the die. Leave open for normal use. 34 LOOPEN 36 VCC2 JTAG Test Clock Input, LVTTL. Internally pulled high through 15kΩ resistor. Loopback Enable Input, LVTTL. Force low to enable system loopback. Internally pulled high through 15kΩ. 3.3V Supply for RX1 Receiver VCO, Analog Receiver Functions, and External Loop-Filter Connection 37 RXFIL1 38, 53, 61 VCC6 RX1 Receiver Loop-Filter Connection. Connect a 0.1µF capacitor between RXFIL1 and VCC2. 3.3V Supply for Transmitter Digital Functions 39, 42, 44, 47 VCC4 3.3V Supply for CML Outputs _______________________________________________________________________________________ Dual 1.25Gbps Transceiver PIN NAME FUNCTION 40 TX1- 41 TX1+ Transmitter Negative Output 1, CML Transmitter Positive Output 1, CML 45 TX2- Transmitter Negative Output 2, CML 46 TX2+ Transmitter Positive Output 2, CML 49 TXFIL Transmitter Loop-Filter Connection. Connect a 0.1µF capacitor between TXFIL and VCC1. 50 VCC1 3.3V Supply for Transmitter VCO, Analog Transmitter Functions, and External Loop-Filter Connection 52 RESET Reset Input, LVTTL. Connect low for >80ns to reset FIFO and receiver components. Internally pulled high through 15kΩ. 54 TCLK1+ Transmitter Positive Clock Input 1, LVDS. Input data is clocked on both the rising and falling edges of the 625MHz clock. 55 TCLK1- Transmitter Negative Clock Input 1, LVDS. Input data is clocked on both the rising and falling edges of the 625MHz clock. 56 TDAT1+ Transmitter Positive Data Input 1, LVDS 57 TDAT1- Transmitter Negative Data Input 1, LVDS 59 REFCLK+ Reference Clock Positive Input. See specification table for differential or single-ended use. 60 REFCLK- Reference Clock Negative Input. See specification table for differential or single-ended use. 63 RCLK1+ Receiver Positive Clock Output 1, LVDS. Output data is clocked on both the rising and falling edges of the 625MHz clock. 64 RCLK1- Receiver Negative Clock Output 1, LVDS. Output data is clocked on both the rising and falling edges of the 625MHz clock. 65 RDAT1+ Receiver Positive Data Input 1, LVDS 66 RDAT1- Receiver Negative Data Input 1, LVDS 68 TDO-JTAG EP Exposed Pad JTAG Test Data Output, Three-State LVTTL Supply Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. See Exposed-Pad Package. The MAX3782 uses exposed pad variation G6800-4 in the package outline drawing. _______________________________________________________________________________________ 9 MAX3782 Pin Description (continued) MAX3782 Dual 1.25Gbps Transceiver VCC GND + REFCLK TXFIL TDIJTAG TRSTJTAG TCLKJTAG TTL TTL TTL TTL 1.25GHz PLL CLOCK MULTIPLIER TTL - TMSJTAG TTL TDO-TJAG CML TX1 CML TX2 JTAG CONTROL CIRCUITRY TX_LOCK (INTERNAL) REFCLK (INTERNAL) + TDAT1 LVDS TCLK1 LVDS RESET TTL TDAT2 LVDS D Q - D FIFO Q + 625MHz DDR - RESET (INTERNAL) + D - Q D FIFO Q + TCLK2 LVDS 625MHz DDR - RDAT1 RCLK1 Q LVDS 0 D + 1 LVDS 625MHz DDR CML - PLL CLOCK RECOVERY DIVIDE BY 2 RX1 RXFIL1 REFCLK (INTERNAL) LOOPEN TTL LOCK TX_LOCK (INTERNAL) RDAT2 Q LVDS MAX3782 RESET (INTERNAL) 0 D 1 RCLK2 LVDS 625MHz DDR + CML PLL CLOCK RECOVERY DIVIDE BY 2 REFCLK (INTERNAL) Figure 3. Functional Diagram 10 ______________________________________________________________________________________ - RX2 RXFIL2 Dual 1.25Gbps Transceiver The MAX3782 dual 1.25Gbps transceiver is a data retimer and clock recovery device for 1000Base-SX/LX, GBIC, and SFP applications. In the transmitter, an integrated clock synthesizer generates a clean 1.25GHz clock. This clock is used with a FIFO to retime the data before transmission. CML output buffers provide excellent performance with minimal external components. The receiver has two separate PLL clock recovery circuits, allowing independent recovery of each received data signal. The receiver has CML inputs, easing system design and decreasing component count. JTAG functionality is included to help with board-level testing. A LOCK pin indicates the status of the internal PLLs. System loopback may be asserted with the LOOPEN input. LVDS Inputs and Outputs The MAX3782 LVDS interface includes two differential data inputs at 1.25Gbps, two half-rate differential clock inputs at 625MHz, two differential data outputs at 1.25Gbps, and two half-rate differential clock outputs at 625MHz. The MAX3782 LVDS-compatible interface is designed to work with the user’s ASICs, minimize power dissipation, speed transition time, and improve noise immunity. The LVDS outputs also have shortcircuit protection in case of shorts to VCC or GND. The LVDS inputs must be DC-coupled for proper biasing. AC-coupling these inputs results in unreliable opera- tion. The LVDS outputs are designed to drive 100Ω differential loads and are not designed to drive 50Ω to ground. PLL Clock Multiplier The PLL clock multiplier uses the 125MHz reference clock to synthesize the 1.25GHz clock that synchronizes the transmitter functions. The reference clock also aids frequency acquisition in the receiver. To achieve proper jitter performance and BER benchmarks, using a high-quality, low-jitter reference clock is critical. REFCLK inputs can be driven differentially or single ended. Differential operation is recommended for its superior jitter performance and noise immunity. PLL Clock Recovery Both receive channels (RX1 and RX2) use PLLs to recover synchronous clocks from the incoming serial data. The recovered clocks are then used to retime the serial data. The typical loop bandwidth of the PLL clock recovery circuits is 1.5MHz. CML Inputs and Outputs The CML inputs and outputs of the MAX3782 offer low power dissipation, excellent performance, and integrated termination resistors. AC-coupling capacitors should be used for PECL and IEEE802.3z compatibility. Figure 4 shows interface examples. The CML output structure is shown in Figure 5, and the CML input structure is shown in Figure 6. For more information, refer to 0.01µF CML W/ 100Ω BACK TERM OPTIONAL ECL OR PECL Z0 = 100Ω 0.01µF CML TO PECL 50Ω 50Ω BIAS 0.01µF ECL OR PECL CURRENT SET OPTIONAL CURRENT SET 0.01µF OPTIONAL PECL TO CML 0.01µF CML W/ 100Ω BACK TERM OPTIONAL Z0 = 100Ω 0.01µF CML W/ 100Ω END TERM Z0 = 100Ω CML W/ 100Ω END TERM CML TO CML Figure 4. CML I/O Interconnect Examples ______________________________________________________________________________________ 11 MAX3782 Detailed Description MAX3782 Dual 1.25Gbps Transceiver MAX3782 VCC VCC 50Ω 2kΩ 50Ω MAX3782 OUT+ OUT- 50Ω 50Ω IN+ 32mA IN- Figure 5. CML Output Structure the applications note HFAN-01.0, Introduction to LVDS, PECL, and CML. GND Lock Detection The LOCK output indicates the state of the transmitter and receiver PLLs. For lock detect to be asserted high, the transmitter and receiver internal lock indicators must be high for 394µs. The internal lock signals go high once frequency lock has been achieved. For lock detect to be asserted low, either the transmitter or receiver internal lock indicators must be low for a minimum of 1053µs. Lock detect also is asserted low when the external reset pin is forced low. LOCK stays low for a minimum of 394µs. For the lock detector to function properly, there must be data transitions at the RX1 and RX2 inputs and a valid reference clock input. Note: The LOCK output is not an accurate indicator of signal presence at the receiver inputs. With no data input, the LOCK output can be high, low, or toggling. The output structure of the LOCK pin is shown in Figure 7. RESET Input RESET must be held low for a minimum of four reference clock cycles for it to be properly asserted. Approximately 10ms or longer after power up, the RESET input should be asserted low. RESET resets the LOCK state and FIFO clock logic. Figure 6. CML Input Structure portional to the die junction temperature (1mV per Kelvin). The temperature of the die can be calculated as: T(°C) ≈ VTEMPSENS (mV) × 1°C − 273°C mV VCC MAX3782 100Ω LOCK Temperature Sensor To help evaluate thermal performance, a temperature sensor is incorporated into the MAX3782. The temperature sensor may be powered on or off regardless of the state of the rest of the chip. The VCCTEMP pin provides supply voltage for the temperature sensor circuit. The TEMPSENS output is designed to output a voltage pro12 RLOAD = 10kΩ Figure 7. LOCK Output Structure ______________________________________________________________________________________ Dual 1.25Gbps Transceiver Jitter Budget Example for Optical Link The MAX3782 outperforms IEEE802.3z jitter specifications. See Figure 8 and Table 1. JTAG JTAG functionality is compliant with IEEE1149.1 specifications. The BSDL file is available on request. Table 2 provides JTAG pin assignments. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance 50Ω transmission lines to interface with the MAX3782 high-speed inputs and outputs. Place power-supply decoupling capacitors as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals. TP1 TP2 O/E E/O MAX3782 MAX3782 Figure 8. Optical Link Table 1. Comparison of IEEE802.3z and MAX3782 Jitter Budget TOTAL JITTER (psP-P) COMPLIANCE POINT IEEE802.3z SPECIFICATION TP1 192 COMPLIANCE POINT IEEE802.3z SPECIFICATION MAX3782 SPECIFICATION 73 (max) 32 (typ) DETERMINISTIC JITTER (psP-P) IEEE802.3z SPECIFICATION MAX3782 SPECIFICATION 20 (max) 100 9 (typ) TOTAL JITTER TOLERANCE (psP-P) TP2 600 MAX3782 SPECIFICATION — 620 (min, CRPAT) 670 (typ, CRPAT) ______________________________________________________________________________________ 13 MAX3782 Applications Information MAX3782 Dual 1.25Gbps Transceiver Table 2. JTAG Pin Assignments MAX3782 PIN NAME I/O TYPE LOCK lock Open Collector Output RX2+ rx2p CML Input Observe 2 RX2- rx2n CML Input Observe 2 RX1+ rx1p CML Input Observe 3 RX1- rx1n CML Input Observe 3 LOOPEN loopen_bar LVTTL Input Observe 4 TDAT2+ tdat2p LVDS Input Observe 5 TDAT2- tdat2n LVDS Input Observe 5 TCLK2+ tck2p LVDS Input Observe 6 6 CELL TYPE IN Observe and Control OUT 1 TCLK2- tck2n LVDS Input Observe TDAT1+ tdat1p LVDS Input Observe 7 TDAT1- tdat1n LVDS Input Observe 7 TCLK1+ tck1p LVDS Input Observe 8 TCLK1- tck1n LVDS Input Observe 8 TX1+ tx1p CML Output Observe and Control 9 TX1- tx1n CML Output Observe and Control 9 TX2+ tx2p CML Output Observe and Control 10 TX2- tx2n CML Output Observe and Control RESET reset_bar LVTTL Input Observe REFCLK+ refckp LVTTL Input Observe 12 REFCLK- refckn LVTTL Input Observe 12 RCLK1+ rck1p LVDS Output Observe and Control 10 11 13 RCLK1- rck1n LVDS Output Observe and Control 13 RDAT1+ rdat1p LVDS Output Observe and Control 14 RDAT1- rdat1n LVDS Output Observe and Control 14 RCLK2+ rck2p LVDS Output Observe and Control 15 RCLK2- rck2n LVDS Output Observe and Control 15 RDAT2+ rdat2p LVDS Output Observe and Control 16 RDAT2- rdat2n LVDS Output Observe and Control 16 JTAG CONTROL PINS 14 ROUTING BOUNDARY SCAN PORT NAME TCLK-JTAG tck LVTTL Input TDI-JTAG tdi LVTTL Input TDO-JTAG tdo LVTTL Output TMS-JTAG tms LVTTL Input TRST-JTAG trst_bar LVTTL Input ______________________________________________________________________________________ Dual 1.25Gbps Transceiver MAX3782 Table 3. JTAG Instructions INSTRUCTION JTAG OPCODE ACTION EXTEST 000 b External boundary test mode SAMPLE/PRELOAD 001 b Initialization for boundary test mode BYPASS 111 b Connects bypass register between TDI and TDO IDCODE 010 b 32-bit device ID register selected (see Table 4) Table 4. Device Identification Code CODE VERSION Binary 0001 b PART NO. 0000 1110 1100 0110 b [ = 3782 base10 ] Exposed-Pad Package The exposed-pad, 68-pin QFN-EP incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The EP and EP ring are electrical ground on the MAX3782 and must be soldered to the circuit board for proper thermal and electrical performance. Refer to HFAN 08.10, Thermal Considerations of QFN and Other Exposed-Pad Packages, for more information. MANUFACTURER = MAXIM 00011001011 b [ ref: JEDEC JEP106-I ] LSB 1b Chip Information TRANSISTOR COUNT: 14329 PROCESS: Silicon bipolar ______________________________________________________________________________________ 15 Dual 1.25Gbps Transceiver MAX3782 Typical Application Circuit 1.25Gbps GBIC AND IEEE802.3z 1000BASE-SX/LX COMPATIBLE 1.25Gbps LVDS CMOS ASIC TCLK1± TDAT1± TX1± TCLK2± TDAT2± RX1± RCLK1± RDAT1± RCLK2± RDAT2± GBIC OR SFP OPTICAL MODULE TX2± GBIC OR SFP OPTICAL MODULE RX2± MAX3782 VCC2 VCC3 LOOPEN RESET RXFIL1 LOCK RXFIL2 0.1µF VCC1 0.1µF 0.1µF TXFIL 125MHz REFERENCE CLOCK REFCLK± TMS-JTAG TDI-TJAG TCLK-JTAG 16 TRST-JTAG TDO-JTAG ______________________________________________________________________________________ Dual 1.25Gbps Transceiver 68L QFN, 10x10x09,EPS ______________________________________________________________________________________ 17 MAX3782 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3782 Dual 1.25Gbps Transceiver Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.