19-5005; Rev 0; 10/09 KIT ATION EVALU E L B A IL AVA Low-Jitter, Precision Clock Generator with Four Outputs Features ♦ Crystal Oscillator Interface: 19.375MHz to 27MHz The MAX3624A is a low-jitter, precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, Fibre Channel, SONET/SDH, and other networking applications. Maxim’s proprietary PLL design features ultra-low jitter (0.36psRMS) and excellent power-supply noise rejection, minimizing design risk for network equipment. ♦ CMOS Input: 19MHz to 40.5MHz ♦ Output Frequencies Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz Fibre Channel: 106.25MHz, 159.375MHz, 212.5MHz, 318.5MHz SONET/SDH: 77.76MHz, 155.52MHz, 311.04MHz ♦ Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) The MAX3624A has three LVPECL outputs and one LVCMOS output. Selectable output dividers and a selectable feedback divider allow a range of output frequencies. ♦ Excellent Power-Supply Noise Rejection ♦ No External Loop Filter Capacitor Required Applications Ethernet Networking Equipment Ordering Information Fibre Channel Storage Area Network SONET/SDH Network PART TEMP RANGE PIN-PACKAGE MAX3624AETJ+ -40°C to +85°C 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration and Typical Application Circuit appear at end of data sheet. Block Diagram MR IN_SEL BYPASS SELA[1:0] QAC_OE LVCMOS BUFFER SELA[1:0] SELB[1:0] FB_SEL[1:0] BYPASS RESET LOGIC/POR RESET DIVIDER NA RESET 0 LVPECL BUFFER QA QA 620MHz TO 648MHz PFD 27pF 1 X_IN QA_OE 0 LVCMOS REF_IN QA_C FILTER VCO QB1_OE 1 RESET RESET CRYSTAL OSCILLATOR DIVIDER M X_OUT LVPECL BUFFER DIVIDER NB QB1 QB1 QB0_OE 33pF DIVIDERS: M = 16, 24, 25, 32 NA = 1, 2, 3, 4, 5, 6, 8, 10, 12 NB = 1, 2, 3, 4, 5, 6, 8, 10, 12 LVPECL BUFFER MAX3624A FB_SEL[1:0] QB0 QB0 SELB[1:0] ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3624A General Description MAX3624A Low-Jitter, Precision Clock Generator with Four Outputs ABSOLUTE MAXIMUM RATINGS Supply Voltage Range VCC, VCCA, VDDO_A, VCCO_A, VCCO_B ................................-0.3V to +4.0V Voltage Range at REF_IN, IN_SEL, FB_SEL[1:0], SELA[1:0], SELB[1:0], QAC_OE, QA_OE, QB0_OE, QB1_OE, MR, BYPASS ..........................................-0.3V to (VCC + 0.3V) Voltage Range at X_IN ..........................................-0.3V to +1.2V Voltage Range at GNDO_A...................................-0.3V to +0.3V Voltage Range at X_OUT ............................-0.3V to (VCC - 0.6V) Current into QA_C ...........................................................±50mA Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW Operating Junction Temperature Range ...........-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER Power-Supply Current SYMBOL ICC CONDITIONS MIN (Note 4) TYP MAX UNITS 82 100 mA CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], FB_SEL[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins) Input Capacitance Input Pulldown Resistor Input Logic Bias Resistor Input Pullup Resistor CIN RPULLDOWN Pins MR, FB_SEL[1:0] RBIAS RPULLUP 2 pF 75 k Pins SELA[1:0], SELB[1:0], QB0_OE 50 k Pins QAC_OE, QA_OE, QB1_OE, IN_SEL, BYPASS 75 k LVPECL OUTPUT SPECIFICATIONS (QA, QA, QB0, QB0, QB1, QB1 Pins) Output High Voltage VOH VCC 1.18 VCC 0.98 VCC 0.83 V Output Low Voltage VOL VCC 1.90 VCC 1.7 VCC 1.55 V Peak-to-Peak Output-Voltage Swing (Single-Ended) (Note 2) 0.6 0.72 0.9 VP-P Clock Output Rise/Fall Time 20% to 80% (Note 2) 200 350 600 ps PLL enabled 48 50 52 PLL bypassed (Note 5) 45 50 55 Output Duty-Cycle Distortion % LVCMOS/LVTTL INPUT SPECIFICATIONS (SELA[1:0], SELB[1:0], FB_SEL[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins) Input-Voltage High VIH Input-Voltage Low VIL Input High Current I IH VIN = VCC Input Low Current I IL VIN = 0V 2 2.0 -80 _______________________________________________________________________________________ V 0.8 V 80 μA μA Low-Jitter, Precision Clock Generator with Four Outputs (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REF_IN SPECIFICATIONS (Input DC- or AC-Coupled) Reference Clock Frequency Input-Voltage High VIH Input-Voltage Low VIL Input High Current I IH Input Low Current I IL Reference Clock Duty Cycle PLL enabled 40.5 PLL bypassed 320 2.0 V VIN = VCC VIN = 0V PLL enabled 0.8 V 240 μA -240 μA 30 Input Capacitance MHz 70 2.5 % pF QA_C SPECIFICATIONS Output High Voltage VOH QA_C sourcing 12mA Output Low Voltage VOL QA_C sinking 12mA Output Rise/Fall Time Output Duty-Cycle Distortion 2.6 V 0.4 V ps (Notes 3 and 6) 250 500 1000 PLL enabled 42 50 58 PLL bypassed (Note 5) 40 50 60 Output Impedance % 14 CLOCK OUTPUT AC SPECIFICATIONS VCO Frequency Range Random Jitter (Note 7) Spurs Induced by Power-Supply Noise (Notes 8, 9, 10) Deterministic Jitter Induced by Power-Supply Noise 620 RJRMS 0.36 1.875MHz to 20MHz 0.14 LVPECL output -59 LVCMOS output -47 (Note 11) 4.6 psP-P -70 dBc Clock Output SSB Phase Noise at 125MHz (Note 12) Note 1: Note 2: Note 3: Note 4: Between QB0 and QB1 15 Between QA and QB0 or QB1, PECL outputs 20 f = 1kHz -124 f = 10kHz -125 f = 100kHz -130 f = 1MHz -145 f > 10MHz -153 1.0 MHz 12kHz to 20MHz Nonharmonic and Subharmonic Spurs Output Skew 648 psRMS dBc ps dBc/Hz A series resistor of up to 10.5Ω is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V ±5%. See Figure 2. Guaranteed up to 320MHz for LVPECL output. Guaranteed up to 160MHz for LVCMOS output. All outputs enabled and unloaded. IN_SEL set high. _______________________________________________________________________________________ 3 MAX3624A ELECTRICAL CHARACTERISTICS (continued) MAX3624A Low-Jitter, Precision Clock Generator with Four Outputs ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C unless otherwise noted.) (Notes 1, 2, and 3) Measured with crystal or AC-coupled, 50% duty-cycle signal on REF_IN. Measured using setup shown in Figure 1 with VCC = 3.3V ±5%. Measured with crystal source. Measured with 40mVP-P, 100kHz sinusoidal signal on the supply. Measured at 156.25MHz output. Measured using setup shown in Figure 2. Calculated based on measured spurs induced by power-supply noise (refer to Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers). Note 12: Measured with 25MHz crystal or 25MHz reference clock at LVCMOS input with a slew rate of 0.5V/ns or greater. Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: 36Ω MAX3624A 499Ω OSCILLOSCOPE 0.1μF Z0 = 50Ω QA_C 4.7pF 50Ω Figure 1. LVCMOS Output Measurement Setup 4 _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Four Outputs SUPPLY CURRENT vs. TEMPERATURE DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVPECL OUTPUT) MAX3624A toc02 MAX3624A toc03 MAX3624A toc01 250 175 ALL OUTPUTS ACTIVE AND TERMINATED 150 125 100 ALL OUTPUTS ACTIVE AND UNTERMINATED 75 AMPLITUDE (50mV/div) 200 MEASURED USING 50Ω OSCILLOSCOPE INPUT THROUGH NETWORK SHOWN IN FIGURE 1 AMPLITUDE (200mv/div) 225 SUPPLY CURRENT (mA) OUTPUT WAVEFORM AT 125MHz (LVCMOS OUTPUT) 50 25 0 -40 -15 10 35 60 85 1ns/div 1ns/div PHASE NOISE AT 125MHz CLOCK FREQUENCY PHASE NOISE AT 212.5MHz CLOCK FREQUENCY (26.5625MHz CRYSTAL) AMBIENT TEMPERATURE (°C) -100 -110 -120 -130 -140 -150 -90 -100 -110 -120 -130 -140 -150 -160 100 1000 10,000 100,000 -100 -110 -120 -130 -140 -160 0.1 OFFSET FREQUENCY (kHz) 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) 0.1 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) NOISE SPUR AMPLITUDE vs. NOISE FREQUENCY 0 fC = 156.25MHz NOISE AMPLITUDE = 40mVP-P -10 -20 MAX3624A toc07 10 SPUR AMPLITUDE (dBc) 1 -90 -150 -160 0.1 -80 MAX3624A toc06 MAX3624A toc05 -90 -80 NOISE POWER DENSITY (dBc/Hz) MAX3624A toc04 NOISE POWER DENSITY (dBc/Hz) -80 NOISE POWER DENSITY (dBc/Hz) PHASE NOISE AT 312.5MHz CLOCK FREQUENCY -30 -40 -50 -60 -70 -80 -90 10 100 1000 10,000 NOISE FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX3624A Typical Operating Characteristics (Typical values are at VCC = +3.3V, TA = +25°C, crystal frequency = 25MHz.) Low-Jitter, Precision Clock Generator with Four Outputs MAX3624A Pin Description 6 PIN NAME 1 VCCO_B FUNCTION 2, 19, 24 GND 3 QB0_OE 4, 5 SELB1, SELB0 6 QAC_OE 7 MR 8 GNDO_A 9 QA_C 10 VDDO_A Power Supply for QA_C Clock Output. Connect to +3.3V. 11 VCCO_A Power Supply for QA Clock Output. Connect to +3.3V. 12 QA Noninverting Clock Output, LVPECL 13 QA Inverting Clock Output, LVPECL 14 BYPASS LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high for normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal 75k pullup to VCC. 15, 16 FB_SEL1, FB_SEL0 LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal 75k pulldown to GND. 17 VCCA Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VCC through 10.5 as shown in Figure 2 (requires VCC = +3.3V ±5%). 18 VCC Core Power Supply. Connect to +3.3V. 20 QA_OE LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high to enable the LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k pullup to VCC. 21, 22 SELA0, SELA1 LVCMOS/LVTTL Input. Controls NA divider setting. See Table 2 for more information. Has 50k input impedance. 23 QB1_OE 25 X_OUT 26 X_IN 27 REF_IN LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling. 28 IN_SEL LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN. Has internal 75k pullup to VCC. 29 QB1 LVPECL, Inverting Clock Output 30 QB1 LVPECL, Noninverting Clock Output 31 QB0 LVPECL, Inverting Clock Output 32 QB0 LVPECL, Noninverting Clock Output — EP Power Supply for QB0 and QB1 Clock Outputs. Connect to +3.3V. Supply Ground LVCMOS/LVTTL Input. Enables/disables QB0 clock output. Connect pin high to enable LVPECL clock output QB0. Connect low to set QB0 to a logic 0. Has internal 50k input impedance. LVCMOS/LVTTL Input. Controls NB divider setting. Has 50k input impedance. See Table 2 for more information. LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C. Connect low to set QA_C to a high-impedance state. Has internal 75k pullup to VCC. LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal 75k pulldown to GND. Not required for normal operation. Ground for QA_C Output. Connect to supply ground. LVCMOS Clock Output LVCMOS/LVTTL Input. Enables/disables QB1 clock output. Connect pin high to enable LVPECL clock output QB1. Connect low to set QB1 to a logic 0. Has internal 50k input impedance. Crystal Oscillator Output Crystal Oscillator Input Exposed Pad. Connect to supply ground for proper electrical and thermal performance. _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Four Outputs The MAX3624A is a low-jitter clock generator designed to operate at Ethernet, Fibre Channel, and SONET/SDH frequencies. It consists of an on-chip crystal oscillator, PLL, programmable dividers, LVCMOS output buffer, and LVPECL output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. Crystal Oscillator An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. Crystal frequency is 19.375MHz to 27MHz. REF_IN Buffer An LVCMOS-compatible clock source can be connected to REF_IN to serve as the reference clock. The LVCMOS REF_IN buffer is internally biased to allow AC- or DC-coupling. It is designed to operate up to 320MHz. PLL The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) with a 620MHz to 648MHz operating range. The VCO output is connected to the PFD input through a feedback divider. See Table 3 for divider values. The PFD compares the reference frequency to the divided-down VCO output (fVCO/M) and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO output clock is sent to the output dividers. To minimize noiseinduced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies. LVPECL Drivers The high-frequency outputs—QA, QB0, and QB1—are differential PECL buffers designed to drive transmission lines terminated with 50Ω to VCC - 2.0V. The maximum operating frequency is specified up to 320MHz. Each output can be individually disabled, if not used. The outputs go to a logic 0 when disabled. LVCMOS Driver QA_C, the LVCMOS output, is designed to drive a single-ended high-impedance load. The maximum operating frequency is specified up to 160MHz. This output can be disabled by the QAC_OE pin if not used and goes to a high impedance when disabled. Reset Logic/POR During power-on, the power-on reset (POR) signal is generated to synchronize all dividers. An external master reset (MR) signal is not required. Applications Information Power-Supply Filtering The MAX3624A is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. In addition to excellent on-chip power-supply noise rejection, the MAX3624A provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 2 illustrates the recommended power-supply filter network for V CCA . The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V ±5%. Decoupling capacitors should be used on all other supply pins for best performance. +3.3V ±5% VCC 0.1μF Output Dividers The output divider is programmable to allow a range of output frequencies. See Table 2 for the divider input settings. The output dividers are automatically set to divide by 1 when the MAX3624A is in bypass mode (BYPASS = 0). 10.5Ω VCCA 0.1μF 10μF Figure 2. Analog Supply Filtering _______________________________________________________________________________________ 7 MAX3624A Detailed Description MAX3624A Low-Jitter, Precision Clock Generator with Four Outputs Table 1. Output Frequency Determination XO OR CMOS INPUT FREQUENCY (MHz) 25 25.78125 26.04166 26.5625 19.44 38.88 (CMOS input) FEEDBACK DIVIDER, M 25 25 24 24 32 16 VCO FREQUENCY (MHz) 625 644.53125 625 637.5 622.08 622.08 Output Divider Configuration Table 2 shows the input settings required to set the output dividers. Leakage in the open case must be less than 1µA. Note that when the MAX3624A is in bypass mode (BYPASS set low), the output dividers are automatically set to divide by 1. OUTPUT DIVIDER, NA AND NB OUTPUT FREQUENCY (MHz) ÷2 312.5 ÷4 156.25 ÷5 125 ÷8 78.125 ÷10 62.5 ÷4 161.132812 ÷2 312.5 ÷4 156.25 ÷5 125 ÷8 78.125 ÷10 62.5 ÷2 318.75 ÷3 212.5 ÷4 159.375 ÷6 106.25 ÷12 53.125 ÷2 311.04 ÷4 155.52 ÷8 77.76 ÷2 311.04 ÷4 155.52 ÷8 77.76 APPLICATIONS Ethernet 10Gbps Ethernet Ethernet Fibre Channel SONET/SDH SONET/SDH Table 2. Output Divider Configuration INPUT NA/NB DIVIDER SELA1/SELB1 SELA0/SELB0 0 0 ÷2* 0 1 ÷3* 1 0 ÷4 1 1 ÷5 1 Open ÷6 Open 1 ÷8 0 Open ÷10 Open 0 ÷12 Open Open ÷1* *Maximum guaranteed output frequency is 160MHz for CMOS and 320MHz for LVPECL output. 8 _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Four Outputs Crystal Selection The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 4 for recommended crystal specifications. See Figure 4 for external capacitance connection. Table 3. PLL Divider Configuration Chart INPUT M DIVIDER FB_SEL1 FB_SEL0 0 0 ÷25 0 1 ÷24 1 0 ÷32 1 1 ÷16 Crystal Input Layout and Frequency Stability The crystal, trace, and two external capacitors should be placed on the board as close as possible to the MAX3624A’s X_IN and X_OUT pins to reduce crosstalk of active signals into the oscillator. The layout shown in Figure 3 gives approximately 3pF of trace plus footprint capacitors per side of the crystal (Y1). The dielectric material is FR4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C22 = 27pF and C23 = 33pF, the measured output frequency accuracy is -14ppm at +25°C ambient temperature. Table 4. Crystal Selection Parameters PARAMETER Crystal Oscillation Frequency SYMBOL MIN f OSC 19.375 TYP Shunt Capacitance CO 2.0 Load Capacitance CL 18 Equivalent Series Resistance (ESR) RS MAX UNITS 27 MHz 7.0 pF pF Maximum Crystal Drive Level 50 300 μW 27pF X_IN CRYSTAL (CL = 18pF) X_OUT 33pF Figure 4. Crystal, Capacitors Connection Figure 3. Crystal Layout _______________________________________________________________________________________ 9 MAX3624A PLL Divider Configuration Table 3 shows the input settings required to set PLL feedback divider. MAX3624A Low-Jitter, Precision Clock Generator with Four Outputs Interfacing with LVPECL Outputs Interface Models The equivalent LVPECL output circuit is given in Figure 8. These outputs are designed to drive a pair of 50Ω transmission lines terminated with 50Ω to VTT = VCC 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as shown in Figure 5 and Figure 6. Unused outputs should be disabled and may be left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN01.0: Introduction to LVDS, PECL, and CML. Figure 7, Figure 8, and Figure 9 show examples of interface models. VCC VB = 1.4V VCC VB 14.5kΩ VB REF_IN +3.3V 130Ω MAX3624A Qx Z0 = 50Ω Qx Z0 = 50Ω 130Ω ESD STRUCTURES HIGH IMPEDANCE Figure 7. Simplified REF_IN Pin Circuit Schematic 82Ω 82Ω VCC Figure 5. Thevenin Equivalent of Standard PECL Termination 0.1μF Z0 = 50Ω Qx 100Ω MAX3624A 0.1μF Qx HIGH IMPEDANCE Qx Z0 = 50Ω Qx 150Ω 150Ω NOTE: AC-COUPLING IS OPTIONAL. ESD STRUCTURES Figure 6. AC-Coupled PECL Termination Figure 8. Simplified LVPECL Output Circuit Schematic 10 ______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Four Outputs The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is also electrical ground on the MAX3624A and must be soldered to the circuit board ground for proper electrical performance. DISABLE 10Ω IN QA_C Pin Configuration SELB1 4 SELB0 5 QAC_OE 6 • An uninterrupted ground plane should be positioned beneath the clock I/Os. • Ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3624A and the receive devices. • Supply decoupling capacitors should be placed close to the MAX3624A supply pins. • Maintain 100Ω differential (or 50Ω single-ended) transmission line impedance out of the MAX3624A. • Use good high-frequency layout techniques and a multilayer board with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3624A Evaluation Kit for more information. MR 7 GNDO_A 8 QB0 QB1 QB1 IN_SEL REF_IN X_IN X_OUT 26 25 + MAX3624A *EP 9 10 11 12 13 14 15 16 FB_SEL0 Layout Considerations The inputs and outputs are critical paths for the MAX3624A, and care should be taken to minimize discontinuities on these transmission lines. Here are some suggestions for maximizing the MAX3624A’s performance: 27 BYPASS 3 28 FB_SEL1 QB0_OE Figure 9. Simplified LVCMOS Output Circuit Schematic 29 QA 2 30 QA 1 GND 31 VCCO_A VCCO_B 32 VDDO_A ESD STRUCTURES QA_C TOP VIEW QB0 10Ω 24 GND 23 QB1_OE 22 SELA1 21 SELA0 20 QA_OE 19 GND 18 VCC 17 VCCA THIN QFN (5mm × 5mm) *EXPOSED PAD CONNECTED TO GROUND. Chip Information TRANSISTOR COUNT: 10,780 PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX3624A Exposed-Pad Package VDDO_A MAX3624A Low-Jitter, Precision Clock Generator with Four Outputs Typical Application Circuit +3.3V ±5% 0.1μF 10.5Ω VCC 10μF 0.1μF VCCO_A VCCO_B 0.01μF VDDO_A 0.1μF 36Ω Z0 = 50Ω QA_C VCCA 0.1μF 0.1μF ASIC 125MHz MR REF_IN IN_SEL QA Z0 = 50Ω QA Z0 = 50Ω ASIC 125MHz QAC_OE 50Ω 50Ω QA_OE QB0_OE VCC (VCC - 2V) QB1_OE MAX3624A BYPASS QB0 Z0 = 50Ω QB0 Z0 = 50Ω ASIC 312.5MHz SELA1 50Ω SELA0 50Ω SELB1 (VCC - 2V) SELB0 FB_SEL1 QB1 Z0 = 50Ω FB_SEL0 QB1 Z0 = 50Ω X_OUT X_IN GND GNDO_A 312.5MHz 25MHz (CL = 18pF) 33pF ASIC 50Ω 50Ω (VCC - 2V) 27pF Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN-EP T3255+3 21-0140 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.