Si4712/Si4713-B30 FM Radio Transmitter with Receive Power Scan

Si4712/13-B30
F M R A DI O T R A N S M I T T E R W I T H R E C E I V E P O W E R S C A N
Features










Integrated receive power
measurement
Worldwide FM band support
(76–108 MHz)
Requires only two external
components
Frequency synthesizer with
integrated VCO
Digital stereo modulator
Programmable pre-emphasis
Analog/digital audio interface
Audio silence detector
Programmable reference clock








RDS/RBDS encoder (Si4713 only)
PCB loop and stub antenna
support with self-calibrated
capacitor tuning
Programmable transmit level
Audio dynamic range control
Advanced modulation control
2.7 to 5.5 V supply voltage
Integrated LDO regulator
3 x 3 x 0.55 mm 20-pin QFN
Pb-free and RoHS Compliant
Designed for compatibility with
cellular operation
Ordering Information:
See page 34.
Pin Assignments
Applications
Si4712/13-B30

Wireless speakers/microphone
 Satellite digital audio radios
 Personal computers/notebooks
The Si4712/13-B30 integrates the complete transmit functions for
standards-compliant unlicensed FM broadcast stereo transmission. The
chip also allows integrated receive power scanning to identify low signal
power FM channels. Users must comply with local regulations on radio
frequency (RF) transmission.
NC
1
20 19 18 17 16
NC 2
15 RIN
RFGND 3
14 DFS
GND
PAD
TXO 4
13 DIN
PEAK
DETECT
Rev. 1.1 2/08
RCLK
VIO
SDIO
10 11 VDD
DFS
DAC
ADC
LIN
DAC
ADC
RIN
Note: To ensure proper operation and
performance, follow the guidelines in “AN383: Universal
Antenna Selection and Layout
Guidelines.” Silicon Laboratories
will evaluate schematics and layouts for qualified customers.
GPO
RDS (Si4713)
SDIO
GPO3/
DCLK
GPO2/
INT
GPO1
SEN
CONTROL
INTERFACE
SCLK
VIO
RCLK
AFC
9
Patents pending
TXO
RFGND
8
DIN
RST
L1
120 nH
7
DIGITAL
AUDIO
DSP
Tx
Ant
6
SCLK
Si4712/13
12 GND
SEN
RST 5
Functional Block Diagram
LIN
NC
Description
GPO3/DCLK
(Top View)
GPO2/INT
Cellular handsets/hands-free
 MP3 players
 Portable media players
GPO1

VDD 2.7–5.5 V
LDO
GND C1
22 nF
Copyright © 2008 by Silicon Laboratories
Si4712/13-B30
Si4712/13-B30
2
Rev. 1.1
Si4712/13-B30
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1. Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Test Circuit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Analog Audio Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Digital Audio Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3. Typical Application Schematic Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Universal AM/FM RX/FM TX Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1. Universal AM/FM RX/FM TX Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2. FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3. Receive Power Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5. Line Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6. Audio Dynamic Range Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7. Audio Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8. Pre-emphasis and De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9. RDS/RBDS Processor (Si4713 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.11. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.12. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.13. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.14. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.15. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Pin Descriptions: Si4712/13-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.1. Si4712 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2. Si4713 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10. Package Outline: Si4712/13-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11. PCB Land Pattern: Si4712/13-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
12. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Rev. 1.1
3
Si4712/13-B30
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Voltage
VDD
2.7
—
5.5
V
Interface Supply Voltage
VIO
1.5
—
3.6
V
Power Supply Powerup Rise Time
VDDRISE
10
—
—
µs
Interface Supply Powerup Rise
Time
VIORISE
10
—
—
µs
TA
–20
25
85
C
Ambient Temperature
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Supply Voltage
VDD
–0.5 to 5.8
V
Interface Supply Voltage
VIO
–0.5 to 3.9
V
Input Current3
IIN
10
mA
3
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
C
Storage Temperature
TSTG
–55 to 150
C
0.4
VPK
Input Voltage
RF Input Level4
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. The Si4712/13 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, DIN, GPO1, GPO2/INT, and GPO3.
4. At RF input pin, TXO.
4
Rev. 1.1
Si4712/13-B30
Table 3. DC Characteristics
Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Transmitter from Line Input
TX Supply Current
ITX
—
18.8
22.8
mA
TX Interface Supply Current
IIO
—
320
600
µA
FM Transmitter from Digital Audio Input
TX Supply Current
IDTX
DCLK = 3.072 MHz
—
18.3
—
mA
TX Interface Supply Current
IDIO
DCLK = 3.072 MHz
—
320
—
µA
FM Transmitter in Receive Power Scan Mode
RX Supply Current
IRX
—
16.8
—
mA
RX Interface Supply Current
IIO
—
320
—
µA
Supplies and Interface
VDD Powerdown Current
IDD
Powerdown mode
—
10
20
µA
VIO Interface Powerdown Current
IIO
SCLK, RCLK inactive
Powerdown mode
—
3
10
µA
High Level Input Voltage1
VIH
0.7 x VIO
—
VIO + 0.3
V
1
VIL
–0.3
—
0.3 x VIO
V
High Level Input Current1
IIH
VIN = VIO = 3.6 V
–10
—
10
µA
1
IIL
VIN = 0 V, VIO = 3.6 V
–10
—
10
µA
High Level Output Voltage2
VOH
IOUT = 500 µA
0.8 x VIO
—
—
V
2
VOL
IOUT = –500 µA
—
—
0.2 x VIO
V
Low Level Input Voltage
Low Level Input Current
Low Level Output Voltage
Notes:
1. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, DIN, GPO1, GPO2/INT, and GPO3.
2. For output pins SDIO, GPO1, GPO2/INT, and GPO3.
Rev. 1.1
5
Si4712/13-B30
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST
tSRST
100
—
—
µs
GPO1, GPO2/INT Hold from RST
tHRST
30
—
—
ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tSRST
RST
70%
GPO1
70%
GPO2/
INT
tHRST
30%
30%
70%
30%
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.1
Si4712/13-B30
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO Hold (START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK Hold4,5
tHD:DAT
0
—
900
ns
SCLK input to SDIO Setup (STOP)
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
SDIO Input, SCLK Rise/Fall Time
Cb
20 + 0.1 -----------1 pF
tf:IN
tr:IN
Cb
20 + 0.1 -----------1 pF
—
ns
250
—
ns
300
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
Notes:
1. When VIO = 0 V, SCLK and SDIO are low-impedance. 2-wire control interface is I2C compatible.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4712/13 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
Rev. 1.1
7
Si4712/13-B30
SCLK
70%
SDIO
70%
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
30%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.1
STOP
Si4712/13-B30
Table 6. 3-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLKHold
tHSDIO
10
—
—
ns
SEN Input to SCLKHold
tHSEN
10
—
—
ns
SCLKto SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLKto SDIO Output High Z
tCDZ
Read
2
—
25
ns
—
—
10
ns
SDIO Input, SEN to SCLKSetup
tR
tF
SCLK, SEN, SDIO, Rise/Fall time
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
tR
tF
tHSDIO
tS
SEN
70%
SDIO
70%
tHIGH
tLOW
tHSEN
tS
30%
A7
30%
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
SEN
70%
30%
tHSDIO
tS
tCDV
tHSEN
tCDZ
tS
30%
70%
SDIO
A7
30%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.1
9
Si4712/13-B30
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
15
—
—
ns
SDIO Input to SCLKHold
tHSDIO
10
—
—
ns
SEN Input to SCLKHold
tHSEN
5
—
—
ns
SCLKto SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLKto SDIO Output High Z
tCDZ
Read
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall time
tR, tF
—
—
10
ns
SDIO Input, SEN to SCLKSetup
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
tR
tHIGH
SEN
70%
SDIO
70%
tS
tLOW
tF
tHSDIO
tHSEN
tS
30%
C7
C6–C1
C0
D7
D6–D1
D0
30%
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
SCLK
70%
30%
tCDV
tS
SEN
70%
tHSEN
tHSDIO
tS
30%
tCDZ
SDIO
70%
C7
C6–C1
C0
D7
D6–D1
D0
30%
Control Byte In
Bus
Turnaround
16 Data Bytes Out
(SDIO or GPO1)
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.1
Si4712/13-B30
Table 8. Digital Audio Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DCLK pulse width high
tDCH
10
—
—
ns
DCLK pulse width low
tDCL
10
—
—
ns
DFS set-up time to DCLK rising edge
tSU:DFS
5
—
—
ns
DFS hold time from DCLK rising edge
tHD:DFS
5
—
—
ns
DIN set-up time from DCLK rising edge
tSU:DIN
5
—
—
ns
DIN hold time from DCLK rising edge
tHD:DIN
5
—
—
ns
tR
tF
—
—
10
ns
1.0
—
40.0
MHz
DCLK, DFS, DIN, Rise/Fall time
DCLK Tx Frequency1,2
Notes:
1. Guaranteed by characterization.
2. The DCLK frequency may be set below the minimum specification if DIGITAL_INPUT_SAMPLE_RATE is first set to 0
(disable).
DCLK
tR
DFS
tHD:DFS
tF
tSU:DFS
tSU:DIN
DIN
tHD:DIN
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.1
11
Si4712/13-B30
Table 9. FM Transmitter Characteristics1
(Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.)
Parameter
Symbol
Transmit Frequency Range2
Test Condition
fRF
Transmit Frequency Accuracy and
Stability2,3
Min
Typ
Max
Unit
76
—
108
MHz
–3.5
—
3.5
kHz
Transmit Voltage Accuracy2
VRF = 103–117 dBµV
–2.5
—
2.5
dB
Transmit Voltage Accuracy
VRF = 102, 118 dBµV
–2.5
—
2.5
dB
–0.075
—
–0.025
dB/ºC
Transmit Voltage Temperature Coefficient2
Transmit Channel Edge Power
> ±100 kHz,
pre-emphasis off
—
—
–20
dBc
Transmit Adjacent Channel Power
> ±200 kHz,
pre-emphasis off
—
–30
–26
dBc
Transmit Alternate Channel Power
> ±400 kHz,
pre-emphasis off
—
–30
–26
dBc
In-band (76–108 MHz)
—
—
–30
dBc
CTUNE
—
53
—
pF
CTUNE
—
5
—
pF
TX_PREMPHASIS = 75 µs
70
75
80
µs
TX_PREMPHASIS = 50 µs
45
50
54
µs
Audio SNR Mono2
f = 22.5 kHz, Mono,
limiter off
58
63
—
dB
Audio SNR Stereo
f = 22.5 kHz,
fpilot = 6.75 kHz, Stereo,
limiter off
53
58
—
dB
Audio THD Mono
f = 75 kHz, Mono,
limiter off
—
0.1
0.5
%
f = 22.5 kHz,
fpilot = 6.75 kHz, Stereo,
limiter off
—
0.1
0.5
%
Transmit Emissions
Output Capacitance Max
2
Output Capacitance Min2
Pre-emphasis Time
Audio THD Stereo2
Constant2
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 9 on page 15.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.
12
Rev. 1.1
Si4712/13-B30
Table 9. FM Transmitter Characteristics1 (Continued)
(Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
left channel only
30
35
—
dB
40
50
—
dB
—
—
110
ms
—
—
0.636
VPK
Mono, ±1.5 dB,
f = 75 kHz, 0, 50, 75 µs
pre-emphasis, limiter off
30
—
15 k
Hz
High Pass Corner Frequency2
Mono, –3 dB, f = 75 kHz,
0, 50, 75 µs pre-emphasis,
limiter off
5
—
30
Hz
Low Pass Corner Frequency2
Mono, –3 dB, f = 75 kHz,
0, 50, 75 µs pre-emphasis,
limiter off
15 k
—
16 k
Hz
Mono
–1
—
1
dB
Pilot Modulation Rate Accuracy2
f = 68.25 kHz,
fpilot = 6.75 kHz, Stereo
–10
—
10
%
Audio Modulation Rate Accuracy2
f = 68.25 kHz,
fpilot = 6.75 kHz, Stereo
–10
—
10
%
LIATTEN[1:0] = 11
50
60
—
k
—
10
—
pF
—
54
—
dBuV
Audio Stereo Separation2
Sub Carrier Rejection Ratio
SCR
Powerup Settling Time2
Input Signal Level2
Frequency
Flatness2
Audio Imbalance
Input Resistance2
VAI
Input Capacitance2
Received Noise Level Accuracy
(Si4712/13 Only)2
60 dBµV input, TA = 25 ºC
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 9 on page 15.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.
Rev. 1.1
13
Si4712/13-B30
Table 10. FM Receive Power Scan Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz)
Parameter
Symbol
Test Condition
Tune and Signal Strength Measurement Time
per Channel
Min
Typ
Max
Unit
—
—
80
ms
Notes:
1. Settling time for ac coupling capacitors on the audio input pins after Receive to Transmit transition can take a few
hundred milliseconds. The actual settling time depends on the values of the ac-coupling capacitors. Using digital audio
input mode avoids this settling time.
2. Guaranteed by characterization.
Table 11. Reference Clock Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz)
Supported Parameter
Symbol
Test Condition
RCLK Frequency Range1,2
Frequency Tolerance
Min
Typ
31.130 32.768
1
–50
—
Max
Unit
40,000
kHz
50
ppm
Notes:
1. Guaranteed by characterization.
2. The RCLK frequency divided by an integer number (the prescaler value) must fall in the range of 31,130 to 34,406 Hz.
Therefore, the range of RCLK frequencies is not continuous below frequencies of 311.3 kHz.
14
Rev. 1.1
Si4712/13-B30
2. Test Circuit
2.1. Test Circuit Schematic
C2
VIO
1
2
L1
120 nH
NC
3
RFGND
4
TXO
5
RST
RIN
C3
RIN
U1
Si4712/13
15
0.47 µF
14
DFS
13
DIN
12
GND
11
VDD
VBATTERY
2.7 to 5.5 V
C1
SEN
SCLK
SDIO
RCLK
VIO
VTXOUT
50 
C4
NC
LIN
R1
22 nF
6
7
8
9
10
2 pF
20
NC
19
GPO1
18
GPO2/INT
17
GPO3/DCLK
16
LIN
0.47 µF
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4712/13 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
Figure 9. Test Circuit Schematic
2.2. Test Circuit Bill of Materials
Table 12. Si4712/13 Test Circuit Bill of Materials
Component(s)
Value/Description
Supplier(s)
C1
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
Murata
C2, C3
AC Coupling Capacitor, 0.47 µF
Murata
C4
2 pF, ±.05 pF, 06035JZR0AB
AVX
L1
120 nH inductor, Qmin = 30
Murata
R1
49.9 , 5%
Murata
U1
Si4712/13 FM Radio Transmitter
Silicon Laboratories
Rev. 1.1
15
Si4712/13-B30
3. Typical Application Schematics
3.1. Analog Audio Inputs
C2
VIO
TX Antenna
1
NC
2
NC
3
RFGND
4
TXO
5
RST
20
NC
19
GPO1
18
GPO2/INT
17
GPO3/DCLK
16
LIN
0.47 µF
U1
Si4712/13
L1
120 nH
RIN
C3
RIN
DFS
DIN
GND
VDD
15
14
13
12
11
0.47 µF
SEN
SCLK
SDIO
RCLK
VIO
C1
22 nF
VBATTERY
2.7 to 5.5 V
6
7
8
9
10
RST
LIN
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4712/13 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
Figure 10. Analog Audio Inputs (LIN, RIN)
16
Rev. 1.1
Si4712/13-B30
3.2. Digital Audio Inputs
1
NC
2
NC
3
RFGND
4
TXO
5
RST
TX Antenna
20
NC
19
GPO1
18
GPO2/INT
17
GPO3/DCLK
16
LIN
VIO
U1
Si4712/13
R1
DCLK
DFS
R2
DIN
15
RIN
14
DFS
13
DIN
12
GND
11
VDD
L1
120 nH
R3
22 nF
VBATTERY
2.7 to 5.5 V
6
7
8
9
10
SEN
SCLK
SDIO
RCLK
VIO
C1
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4712/13 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: Si47xx 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
Figure 11. Digital Audio Inputs (DIN, DFS, DCLK)
3.3. Typical Application Schematic Bill of Materials
Table 13. Si4712/13 Bill of Materials
Component(s)
Value/Description
Supplier(s)
C1
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
Murata
C2, C3
AC Coupling Capacitor, 0.47 µF
Murata
L1
120 nH inductor, Qmin = 30
Murata
R1, R2
2 k Resistor
Any
R3
600  Resistor
Any
U1
Si4712/13 FM Radio Transmitter
Silicon Laboratories
Rev. 1.1
17
Si4712/13-B30
4. Universal AM/FM RX/FM TX Application Schematic
Figure 12 shows an application schematic that supports the Si47xx family of 3 mm x 3 mm QFN products,
including the Si4702/3/4/5 FM receivers, Si471x FM transmitters, Si472x FM transceivers, and Si473x AM/FM
receivers.
R2
FB1
2.5 k @ 100 MHz
Right
Audio
Left
Audio
T5
U2
Headphone Amplifier
FB2
2.5 k @ 100 MHz
S1
Si4702/03: Populate R12, R13, R21, C14, and C15
Si4704/05/1x/2x/3x Analog: Populate C7, C8, C14
and C15 as shown
Si4704/05/1x/2x/3x Digital: Populate R16, R17,
R18, R19, and R20 as shown
J1 HP Jack
R16
2 k
C4
1 nF
LHEADPHONE
270 nH
VBATTERY
2.7 to 5.5 V
System Component
GPIO3
GPIO2
GPIO1
R13
0
C7/R17
0.39 uF/ 2 k
LIN
System Component
L1
10 nH
D4
LSHORT
120 nH
System Component
System Component
AM Ferrite Antenna
C17/R21
3.3pF/0 
1
2
RIN
NC
GPO1
GPO2/IRQ
GPO3/DCLK
LIN/DFS
R14
0
D3
20
19
18
17
16
FM Embedded RX/TX Antenna
NC
FMI
3 RFGND
4 TXO/AMI
5 RST
R12
0
GND/RIN/DOUT
U1
Si47xx
LOUT/DFS
15
14
13
ROUT/DIN
12
GND
VDD 11
C15/R20
C16
470 nF
VBATTERY 0.39 uF/ 0 
2.7 to 5.5 V
System Components
22 nF
6
7
8
9
10
LFERRITE
180–
600 uH
SEN
SCLK
SDIO
RCLK
VIO
C1
D5
C8/R18
0.39 uF/ 600 
C14/R19
0.39 uF/ 0 
RST
SEN
SCLK
SDIO
RCLK
VIO
Figure 12. Universal AM/FM RX/FM TX Application Schematic
Following the schematic and layout recommendations detailed in “AN383: Universal Antenna Selection and Layout
Guidelines” will result in optimal performance with the minimal application schematic shown in Figure 12. “Universal
AM/FM RX/FM TX Application Schematic”. System components are those that are likely to be present for any tuner
or transmitter design.
18
Rev. 1.1
Si4712/13-B30
4.1. Universal AM/FM RX/FM TX Bill of Materials
The bill of materials for the expanded application schematic shown in Figure 12 is provided in Table 14. Refer to
the individual device layout guides and antenna interface guides for a discussion of the purpose of each
component.
Table 14. Universal AM/FM RX/FM TX Bill of Materials
Designator
Description
C1
Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
U1
Silicon Laboratories Si47xx, 3 mm x 3 mm, 20 pin, QFN
R12, R13, R19, 0  jumper, 0402
R20, R21
C16
Note
R12, R13, and R21 for
Si4702/03 Only
AM antenna ac coupling capacitor, 470 nF, 20%, Z5U/X7R
AM Ferrite Antenna
AM Ferrite loop stick, 180–600 µH
AM Ferrite Antenna
Ferrite bead, 2.5 k @ 100 MHZ, 0603, Murata BLM18BD252SN1D
Headphone Antenna
LHEADPHONE Headphone antenna matching inductor, 270 nH, 0603, Q>15, Murata
LQW18ANR27J00D
Headphone Antenna
LFERRITE
FB1,FB2
LSHORT
Embedded antenna matching inductor, 120 nH, 0603, Q>30, Murata
LQW18ANR12J00D
Embedded Antenna
R14
Embedded antenna jumper, 2.2 , 0402
Optional
C2
Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
Optional
C3
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402
Optional
C5, C6
Headphone amp output shunt capacitor, 100 pF, 10%, Z5U/X7R, 0402 Optional
R7-R11
Current limiting resistor, 20 –2 k, 0402
Optional
Crystal load capacitor, 22 pF, 5%, COG
Optional
Crystal, Epson FC-135
Optional
C7, C8
Si47xx input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402
System Component
D1-D5
ESD Diode, SOT23-3, California Micro Devices CM1214-01ST
System Component
C11
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402
Headphone Amplifier
C4
Headphone antenna ac coupling capacitor, 1 nF, 10%, Z5U/X7R, 0402 Headphone Antenna
C12, C13
X1
C9, C10
Headphone amp output ac coupling capacitor, 125 uF, X7R, 0805
C14, C15
Headphone amp input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402 Headphone Amplifier
R1,R2,R3,R4 Headphone amp feedback/gain resistor, 20 k, 0402
R5, R6
U2
R16, R17
R18
L1
C17
Headphone Amplifier
Headphone Amplifier
Headphone amp bleed resistor, 100 k, 0402
Headphone Amplifier
Headphone amplifier, National Semiconductor, LM4910MA
Headphone Amplifier
Current limiting resistor, 2 k0402
System Component
Current limiting resistor, 600 , 0402
System Component
VCO filter inductor, 10 nH, 0603, Q30, Murata, LQW18ANR01J00D
Optional
VCO filter capacitor, 3.3 pF, 0402, COG, Venkel,
C0402COG2503R3JN
Optional
Rev. 1.1
19
Si4712/13-B30
5. Functional Description
5.1. Overview
Si4712/13
PEAK
DETECT
DIN
DIGITAL
AUDIO
DFS
DAC
ADC
LIN
DAC
ADC
RIN
DSP
SEN
VIO
RCLK
GPO
RDS (Si4713)
SCLK
CONTROL
INTERFACE
AFC
VDD 2.7–5.5 V
LDO
GND C1
22 nF
GPO3/
DCLK
GPO2/
INT
GPO1
RFGND
RST
L1
120 nH
TXO
SDIO
Tx
Ant
Figure 13. Functional Block Diagram
The Si4712/13 is the first 100% CMOS FM radio
transmitter with integrated receive functionality to
measure received signal strength. The device leverages
Silicon Labs’ highly successful and proven Si4700/01
FM receiver patent family and offers unmatched
integration and performance, allowing FM transmit to be
added to any portable device with a single chip. The
Si4712/13 offers industry-leading size, performance,
low power consumption, flexibility, and ease of use.
onboard DSP provides modulation adjustment and
audio dynamic range control for optimum sound quality.
The Si4712/13’s digital integration reduces the required
external components of traditional offerings, resulting in
a solution requiring only an external inductor and
bypass capacitor, and PCB space of approximately
15 mm2. This increases the device reliability and
simplifies the design and manufacturing for companies
adopting this technology.
The transmit output (TXO) connects directly to the
transmit antenna with only one external inductor to
provide harmonic filtering. The output is programmable
over a 10 dB voltage range in 1 dB steps. The TXO
output pin can also be configured for loop antenna
support. Users are responsible for complying with local
regulations on RF transmission (FCC, ETSI, ARIB,
etc.).
The Si4712/13’s integrated receive power scan function
shares the same antenna as the transmitter allowing for
a compact printed circuit board design. The device
operates in half duplex mode, meaning the transmitter
and receiver do not operate at the same time.
The Si4712/13 performs FM modulation in the digital
domain to achieve high fidelity, optimal performance
versus power consumption, and flexibility of design. The
20
The Si4713 supports the European Radio Data System
(RDS) and the US Radio Broadcast Data System
(RBDS) including all the symbol encoding, block
synchronization, and error correction functions. Using
this feature, the Si4713 enables data such as artist
name and song title to be transmitted to an RDS/RBDS
receiver.
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I2S and left-justified modes. The interface has
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and a digital bit
synchronization input clock (DCLK). The Si4712/13
supports a number of industry-standard sampling rates
Rev. 1.1
Si4712/13-B30
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
The Si4712/13 includes a low-noise stereo line input
(LIN/RIN) with programmable attenuation. To ensure
optimal audio performance, the Si4712/13 has a
transmit line input property that allows the user to
specify the peak amplitude of the analog input required
to reach maximum deviation level. The deviation levels
of the audio, pilot, and RDS/RBDS signals can be
independently programmed to customize FM transmitter
designs. The Si4712/13 has a programmable low audio
level and high audio level indicators that allows the user
to selectively enable and disable the carrier based on
the presence of audio content. In addition, the device
provides an overmodulation indicator to allow the user
to dynamically set the maximum deviation level. The
Si4712/13 has a programmable audio dynamic range
control that can be used to reduce the dynamic range of
the audio input signal and increase the volume at the
receiver. These features can dramatically improve the
end user’s listening experience.
The Si4712/13 is reset by applying a logic low on the
RST pin. This causes all register values to be reset to
their default values. The digital input/output interface
supply (VIO) provides voltage to the RST, SEN, SDIO,
RCLK, DIN, DFS, and DCLK pins and can be connected
to the audio baseband processor's supply voltage to
save power and remove the need for voltage level
translators. RCLK is not required for register operation.
The Si4712/13 reference clock is programmable,
supporting many RCLK inputs as shown in Table 9.
The S4712/13 are part of a family of broadcast audio
solutions offered in standard, 3 x 3 mm 20-pin QFN
packages. All solutions are layout compatible, allowing
a single PCB to accommodate various feature offerings.
The Si4712/13 includes line inputs to the on-chip
analog-to-digital converters (ADC), a programmable
reference clock input, and a configurable digital audio
interface. The chip supports I2C-compliant 2-wire, 8-bit
SPI, and a 3-wire control interface.
5.2. FM Transmitter
The transmitter (TX) integrates a stereo audio ADC to
convert analog audio signals to high fidelity digital
signals. Alternatively, digital audio signals can be
applied to the Si4712/13 directly to reduce power
consumption by eliminating the need to convert audio
baseband signals to analog and back again to digital.
Digital signal processing is used to perform the stereo
MPX encoding and FM modulation to a low digital IF.
Transmit baseband filters suppress out-of-channel
noise and images from the digital low-IF signal. A
quadrature single-sideband mixer up-converts the
digital IF signal to RF, and internal RF filters suppress
noise and harmonics to support the harmonic emission
requirements of cellular phones, GPS, WLAN, and other
wireless standards.
The TXO output has over 10 dB of output level control,
programmable in approximately 1 dB steps. This large
output range enables a variety of antennas to be used
for transmit, such as a monopole stub antenna or a loop
antenna. The 1 dB step size provides fine adjustment of
the output voltage.
The TXO output requires only one external 120 nH
inductor. The inductor is used to resonate the antenna
and is automatically calibrated within the integrated
circuit to provide the optimum output level and
frequency response for supported transmit frequencies.
Users are responsible for adjusting their system’s
radiated power levels to comply with local regulations
on RF transmission (FCC, ETSI, ARIB, etc.).
5.3. Receive Power Scan
The Si4712/13 is the industry’s first FM transmitter with
integrated receive functionality to measure received
signal strength. This has been designed to specifically
handle various antenna lengths including integrated
PCB antennas, wire antennas, and loop antennas,
allowing it to share the same antenna as the transmitter.
The receive function reuses the on-chip varactor from
the transmitter to optimize the receive signal power
applied to the front-end amplifier. Auto-calibration of the
varactor occurs with each tune command for consistent
performance across the FM band.
Rev. 1.1
21
Si4712/13-B30
5.3.1. Stereo Encoder
The MPX message signal can be expressed as follows:
Figure 14 shows an example modulation level
breakdown for the various components of a typical MPX
signal.
m(t) = C0[L(t) + R(t)] + C1 cos(219 kHz)
The total modulation level for the MPX signal shown in
Figure 14, assuming no correlation, is equal to the
arithmetic sum of each of the subchannel levels
resulting in 102.67 percent modulation or a peak
frequency deviation of 77.0025 kHz (an instantaneous
frequency deviation of 75 kHz corresponds to 100
percent modulation). Frequency deviation is related to
the amplitude of the MPX signal by a gain constant,
KVCO, as given by the following equation:
f = K VCO A m
where f is the frequency deviation; KVCO is the
voltage-to-frequency gain constant, and Am is the
amplitude of the MPX message signal. For a fixed
KVCO, the amplitude of all the subchannel signals within
the MPX message signal must be scaled to give the
appropriate total frequency deviation.
MPX Encoder
RDS(t)
C2
57 kHz
L(t)
C0
Frequency
Tripler
38 kHz
Frequency
Doubler
m(t)
C1
19 kHz
R(t)
C0
Figure 14. MPX Encoder
Figure 14 shows a conceptual block diagram of an MPX
encoder used to generate the MPX signal. L(t) and R(t)
denote the time domain waveforms from the left and
right audio channels, and RDS(t) denotes the time
domain waveform of the RDS/RBDS signal.
22
+ C0[L(t) – R(t)] cos(238 kHz)
+ C2RDS(t) cos(257 kHz)
where C0, C1, and C2 are gains used to scale the
amplitudes of the audio signals (L(t) ± R(t)), the 19 kHz
pilot tone, and the RDS subcarrier respectively, to
generate the appropriate modulation level. To achieve
the
modulation
levels
of
Figure 14
with
KVCO = 75 kHz/V, C0 would be set to 0.45; C1 would be
set to 0.1, and C2 would be set to 0.0267 giving a peak
audio frequency deviation of 0.9 x 75 kHz = 67.5 kHz, a
peak
pilot
frequency
deviation
of
0.1 x 75 kHz = 7.5 kHz, and a peak RDS frequency
deviation of 0.0267 x 75 kHz = 2.0025 kHz for a total
peak frequency deviation of 77.0025 kHz.
In the Si4712/13, the peak audio, pilot, and RDS
frequency deviations can be programmed directly with
the Transmit Audio, Pilot, and RDS Deviation
commands with an accuracy of 10 Hz. For the example
in Figure 14, the Transmit Audio Deviation is
programmed with the value 6750, the Transmit Pilot
Deviation with 750, and the Transmit RDS Deviation
with 200, generating peak audio frequency deviations of
67.5 kHz, peak pilot deviations of 7.5 kHz, and peak
RDS deviations of 2.0 kHz for a total peak frequency
deviation of 77 kHz. The total peak transmit frequency
deviation of the Si4712/13 can range from 0 to 100 kHz
and is equal to the arithmetic sum of the Transmit
Audio, Pilot, and RDS deviations. Users must comply
with local regulations on radio frequency transmissions.
Each of the individual deviations (transmit audio, pilot,
and RDS) can be independently programmed; however,
the total peak frequency deviation cannot exceed
100 kHz.
The Si4712/13 provides an overmodulation indicator to
allow the user to dynamically set the maximum
deviation level. If the instantaneous frequency exceeds
the
deviation
level
specified
by
the
TX_AUDIO_DEVIATION property, the SQINT interrupt
bit (and optional interrupt) will be set.
Rev. 1.1
Si4712/13-B30
5.4. Digital Audio Interface
5.4.2. Audio Sample Rates
The digital audio interface operates in slave mode and
supports 3 different audio data formats:
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs and ADCs on
the audio baseband processor. The sampling rate is
selected using the DIGITAL_INPUT_SAMPLE_RATE
property.
1. I2S
2. Left-Justified
3. DSP Mode
5.4.1. Audio Data Formats
In I2S mode, the MSB is captured on the second rising
edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is low, and the Right Channel is transferred when the
DFS is high.
In Left-Justified mode, the MSB is captured on the first
rising edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is high, and the Right Channel is transferred when the
DFS is low.
The device supports DCLK frequencies above 1 MHz.
After powerup the DIGITAL_INPUT_SAMPLE_RATE
property defaults to 0 (disabled). After DCLK is
supplied,
the
DIGITAL_INPUT_SAMPLE_RATE
property should be set to the desired audio sample rate
such
as
32,
40,
44.1,
or
48 kHz.
The
DIGITAL_INPUT_SAMPLE_RATE property must be set
to 0 before DCLK is removed or the DCLK frequency
drops below 1 MHz. A device reset is required if this
requirement is not followed.
In DSP mode, the DFS becomes a pulse with a width of
1 DCLK period. The Left Channel is transferred first,
followed right away by the Right Channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
Rev. 1.1
23
Si4712/13-B30
(IFALL = 1)
INVERTED
DCLK
(IFALL = 0)
DCLK
I2S
(IMODE = 0000)
LEFT CHANNEL
DFS
RIGHT CHANNEL
1 DCLK
1 DCLK
1
DIN/DOUT
2
n-2
3
n-1
MSB
n
1
LSB
MSB
2
n-2
3
n-1
n
LSB
Figure 15. I2S Digital Audio Format
(IFALL = 1)
INVERTED
DCLK
(IFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
Left-Justified
(IMODE = 0110)
DIN/DOUT
1
2
3
n-2
n-1
MSB
n
1
LSB
MSB
2
n-1
n-2
3
n
LSB
Figure 16. Left-Justified Digital Audio Format
(IFALL = 0)
DCLK
DFS
RIGHT CHANNEL
LEFT CHANNEL
(IMODE = 1100)
DIN/DOUT
(MSB at 1st rising edge)
1
2
3
n-2
n-1
MSB
DIN/DOUT
(MSB at 2nd rising edge)
1
LSB
MSB
n-1
n
1
LSB
MSB
2
3
1
2
3
n-2
MSB
Rev. 1.1
n-1
n
LSB
RIGHT CHANNEL
2
Figure 17. DSP Digital Audio Format
24
n-2
LEFT CHANNEL
1 DCLK
(IMODE = 1000)
n
3
n-2
n-1
n
LSB
Si4712/13-B30
5.5. Line Input
The Si4712/13 provides left and right channel line inputs
(LIN and RIN). The inputs are high-impedance and lowcapacitance, suited to receiving line level signals from
external audio baseband processors. Both line inputs
are low-noise inputs with programmable attenuation.
Passive and active anti-aliasing filters are incorporated
to prevent high frequencies from aliasing into the audio
band and degrading performance.
To ensure optimal audio performance, the Si4712/13
has a TX_LINE_INPUT_LEVEL property that allows the
user to specify the peak amplitude of the analog input
(LILEVEL[9:0]) required to reach the maximum
deviation level programmed in the audio deviation
property, TX_AUDIO_DEVIATION. A corresponding line
input attenuation code, LIATTEN[1:0], is also selected
by the expected peak amplitude level. Table 15 shows
the line attenuation codes.
Table 15. Line Attenuation Codes
LIATTEN[1:0]
Peak Input
Voltage [mV]
RIN/LIN Input
Resistance [k]
00
190
396
01
301
100
10
416
74
11
636
60
The line attenuation code is chosen by picking the
lowest Peak Input Voltage in Table 15 that is just above
the expected peak input voltage coming from the audio
baseband processor. For example, if the expected peak
input voltage from the audio baseband processor is
400 mV, the user chooses LIATTEN[1:0] = 10 since the
Peak Input Voltage of 416 mV associated with
LIATTEN[1:0] = 10 is just greater than the expected
peak input voltage of 400 mV. The user also enters
400 mV into the LILEVEL[9:0] to associate this input
level to the maximum frequency deviation level
programmed into the audio deviation property. Note that
selecting a particular value of LIATTEN[1:0] changes
the input resistance of the LIN and RIN pins. This
feature is used for cases where the expected peak input
level exceeds the maximum input level of the LIN and
RIN pins.
The maximum analog input level is 636 mVpK. If the
analog input level from the audio baseband processor
exceeds this voltage, series resistors must be inserted
in front of the LIN and RIN pins to attenuate the voltage
such that it is within the allowable operating range. For
example, if the audio baseband's expected peak
amplitude is 900 mV and the VIO supply voltage is 1.8 V,
the designer can use 30 k series resistors in front of
the LIN and RIN pins and select LIATTEN[1:0] = 11. The
resulting expected peak input voltage at the LIN/RIN
pins is 600 mV, since this is just a voltage divider
between the LIN/RIN input resistance (see Table 15,
60 k for this example) and the external resistor. Note
that the Peak Input Voltage corresponding to the chosen
LIATTEN[1:0] code still needs to satisfy the condition of
being just greater than the attenuated voltage. In this
example, a line attenuation code of LIATTEN[1:0] = 11
has a Peak Input Voltage of 636 mV, which is just
greater than the expected peak attenuated voltage of
600 mV. Also, the expected peak attenuated voltage is
entered into the LILEVEL[9:0] parameter. Again, in this
example, 600 mV is entered into LILVEVEL[9:0]. This
example shows one possible solution, but many other
solutions exist. The optimal solution is to apply the
largest possible voltage to the LIN and RIN pins for
signal-to-noise considerations; however, practical
resistor values may limit the choices.
Note that the TX_LINE_INPUT_LEVEL parameter will
affect the high-pass filter characteristics of the accoupling capacitors and the resistance of the audio
inputs.
The Si4712/13 has a programmable low audio level and
high audio level indicators that allows the user to
selectively enable and disable the carrier based on the
presence of audio content. The TX_ASQ_LEVEL_LOW
and TX_ASQ_LEVEL_HIGH parameters set the low
level and high level thresholds in dBFS, respectively.
The time required for the audio level to be below the low
threshold is set with the TX_ASQ_DURATION_LOW
parameter, and similarly, the time required for the audio
level to be above the high threshold is set with the
TX_ASQ_DURATION_HIGH parameter.
Rev. 1.1
25
Si4712/13-B30
5.6. Audio Dynamic Range Control
The Si4712/13 includes digital audio dynamic range
control with programmable gain, threshold, attack rate,
and release rate. The total dynamic range reduction is
set by the gain value and the audio output compression
above
the
threshold
is
equal
to
Threshold/(Gain + Threshold) in dB. The gain specified
cannot be larger than the absolute value of the
threshold. This feature can also be disabled if audio
compression is not desired.
The audio dynamic range control can be used to reduce
the dynamic range of the audio signal, which improves
the listening experience on the FM receiver. Audio
dynamic range reduction increases the transmit volume
by decreasing the peak amplitudes of audio signals and
increasing the root mean square content of the audio
signal. In other words, it amplifies signals below a
threshold by a fixed gain and compresses audio signals
above
a
threshold
by
the
ratio
of
Threshold/(Gain + Threshold). Figure 18 shows an
example transfer function of an audio dynamic range
controller with the threshold set at –40 dBFS and a
Gain = 20 dB relative to an uncompressed transfer
function.
Input [dBFS]
–90
–80
–70
–60
–50
–40
–30
–20
Compression
2:1 dB
Threshold
= –40 dB
0
–30
M=1
Gain
= 20 dB
Output [dBFS]
–50
Audio
Input
Audio
Output
Attack
time
–60
Figure 19. Time Domain Characteristics of the
Audio Dynamic Range Controller
The limiter performs as a peak detector with an attack
rate set to one audio sample, resulting in an almost
immediate attenuation of the input peak. The recover
rate is programmable to the customer’s preference, and
is set by default to 5 ms. This is the recommended
setting to avoid audible pumping or popping. Refer to
“AN332: Universal Programming Guide.”
–70
–80
–90
Figure 18. Audio Dynamic Range Transfer
Function
For input signals below the threshold of –40 dBFS, the
output signal is amplified or gained up by 20 dB relative
to an uncompressed signal. Audio inputs above the
threshold are compressed by a 2 to 1 dB ratio, meaning
that every 2 dB increase in audio input level above the
threshold results in an audio output increase of 1 dB. In
this example, the input dynamic range of 90 dB is
reduced to an output dynamic range of 70 dB.
26
Release
time
The 4712/13 also includes a digital audio limiter. The
audio limiter prevents over-modulation of the FM
transmit output by dynamically attenuating peaks in the
audio input signal that exceed a programmable
threshold. The limiter threshold is set to the
programmed audio deviation + ten percent. The
threshold ensures that the output signal audio deviation
does not exceed the programmed levels, avoiding
audible artifacts or distortion in the target FM receiver,
and complying with FCC or ETSI regulatory standards.
–10
–40
Threshold
5.7. Audio Limiter
–20
No
Compression
M=1
–10
Figure 19 shows the time domain characteristics of the
audio dynamic range controller. The attack rate sets the
speed with which the audio dynamic range controller
responds to changes in the input level, and the release
rate sets the speed with which the audio dynamic range
controller returns to no compression once the audio
input level drops below the threshold.
Rev. 1.1
Si4712/13-B30
5.8. Pre-emphasis and De-emphasis
5.10. Tuning
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. All FM receivers
incorporate a de-emphasis filter that attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The preemphasis time constant is programmable to 50 or 75 µs
and is set by using the TX_PREEMPHASIS property.
The frequency synthesizer uses Silicon Laboratories’
proven technology including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to upconvert the
low intermediate frequency to RF. The VCO frequency
is locked to the reference clock and adjusted with an
automatic frequency control (AFC) servo loop during
transmission.
5.9. RDS/RBDS Processor (Si4713 Only)
The Si4713 implements an RDS/RBDS* processor for
symbol encoding, block synchronization, and error
correction. Digital data can be transmitted with the
Si4713 RDS/RBDS encoding feature.
RDS transmission is supported with three different
modes. The first mode is the simplest mode and
requires no additional user support except for preloading the desired RDS PI and PTY codes and up to
12 8-byte PS character strings. The Si4713 will transmit
the PI code and rotate through the transmission of the
PS character strings with no further control required
from outside the device. The second mode allows for
more complicated transmissions. The PI and PTY
codes are written to the device as in mode 1. The
remaining blocks (B, C, and D) are written to a 252 byte
buffer. This buffer can hold 42 sets of BCD blocks. The
Si4713 creates RDS groups by creating block A from
the PI code, concatenating blocks BCD from the buffer,
and rotating through the buffer. The BCD buffer is
circular; so, the pattern is repeated until the buffer is
changed. Finally, the third mode allows the outside
controller to burst data into the BCD buffer, which
emulates a FIFO. The data does not repeat, but, when
the buffer is nearly empty, the Si4713 signals the
outside device to initiate another data burst. This mode
permits the outside device to use any RDS functionality
(including open data applications) that it wants.
The tuning frequency can be directly programmed with
commands. For example, to tune to 98.1 MHz, the user
writes the TX_TUNE_FREQ command with an
argument = 9810.
The Si4712/13 supports channel spacing of 50, 100, or
200 kHz.
5.11. Reference Clock
The Si4712/13 reference clock is programmable,
supporting RCLK frequencies from 31.130 kHz to
40 MHz. The RCLK frequency divided by an integer
number (the prescaler value) must fall in the range of
31,130 to 34,406 Hz. Therefore, the range of RCLK
frequencies is not continuous below frequencies of
311.3 kHz. The default RCLK frequency is 32.768 kHz.
Please refer to “AN332: Universal Programming Guide”
for using other RCLK frequencies.
5.12. Control Interface
A serial port slave interface is provided; this allows an
external controller to send commands to the Si4712/13
and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, SPI
mode, or 3-wire mode. The Si4712/13 selects the bus
mode by sampling the state of the GPO1 and
GPO2/INT pins on the rising edge of RST. The GPO1
pin includes an internal pull-up resistor that is
connected while RST is low, and the GPO2/INT pin
includes an internal pull-down resistor that is connected
while RST is low. Therefore, it is only necessary for the
user to actively drive pins that differ from these states.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
Rev. 1.1
27
Si4712/13-B30
Table 16. Bus Mode Select on Rising Edge of
RST
Bus Mode
GPO1
GPO2/INT
2-Wire
1
0
SPI
1
1 (must drive)
3-Wire
0 (must drive)
0
After the rising edge of RST, the pins, GPO1 and
GPO2/INT, are used as general-purpose output (O) pins
as described in Section “5.13. GPO Outputs”. In any
bus mode, commands may only be sent after VIO and
VDD supplies are applied.
5.12.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address followed by a read/write bit (read = 1,
write = 0). The Si4712/13 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4712/13 responds to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the seven-bit device
address is 0010001. When SEN = 1, the address is
1100011.
For write operations, the user then sends an eight bit
data byte on SDIO, which is captured by the device on
rising edges of SCLK. The Si4712/13 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to
eight data bytes in a single two-wire transaction. The
first byte is a command, and the next seven bytes are
arguments.
For read operations, after the Si4712/13 has
acknowledged the control byte, it drives an eight-bit
data byte on SDIO, changing the state of SDIO on the
falling edge of SCLK. The user acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. If a data byte is not
acknowledged, the transaction ends. The user may
read up to 16 data bytes in a single two-wire
28
transaction. These bytes contain the response data
from the Si4712/13.
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to
Table 5,
“2-Wire
Control
Interface
Characteristics1,2,3,” on page 7, Figure 2, “2-Wire
Control Interface Read and Write Timing Parameters,”
on page 8, and Figure 3, “2-Wire Control Interface Read
and Write Timing Diagram,” on page 8.
5.12.2. SPI Control Interface Mode
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. For reads, the user can choose to
receive data from the device on either SDIO or GPO1. A
transaction begins when the user drives SEN low. The
user then pulses SCLK eight times while driving an 8-bit
control byte (MSB first) serially on SDIO. The device
captures the data on rising edges of SCLK. The control
byte must have one of these values:
0x48 = write eight command/argument bytes (user
drives write data on SDIO)
0x80 = read status byte (device drives read data on
SDIO)
0xA0 = read status byte (device drives read data on
GPO1)
0xC0 = read 16 response bytes (device drives read data
on SDIO)
0xE0 = read 16 response bytes (device drives read data
on GPO1)
When writing a command, after the control byte has
been written, the user must drive exactly eight data
bytes (a command byte and seven argument bytes) on
SDIO. The data will be captured by the device on the
rising edges of SCLK. After all eight data bytes have
been written, the user raises SEN after the last falling
edge of SCLK to end the transaction.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high). In SPI
mode, this is done by sending control byte 0x80 or
0xA0, followed by reading a single byte on SDIO or
GPO1. The Si4712/13 changes the state of SDIO or
GPO1 after the falling edges of SCLK. Data should be
captured by the user on the rising edges of SCLK. After
the status byte has been read, the user raises SEN after
the last falling edge of SCLK to end the transaction.
When reading a response, the user must read exactly
16 data bytes after sending the control byte. It is
Rev. 1.1
Si4712/13-B30
recommended that the user keep SEN low until all bytes
have transferred. However, it will not disrupt the
protocol if SEN temporarily goes high at any time, as
long as the user does not change the state of SCLK
while SEN is high. After 16 bytes have been read, the
user raises SEN after the last falling edge of SCLK to
end the transaction.
At the end of any SPI transaction, the user must drive
SEN high after the final falling edge of SCLK. At any
time during a transaction, if SEN is sampled high by the
device on a rising edge of SCLK, the transaction will be
aborted. When SEN is high, SCLK may toggle without
affecting the device.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 10.
5.12.3. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
3-wire bus mode uses the SCLK, SDIO and SEN pins.
A transaction begins when the system controller drives
SEN low. Next, the system controller drives a 9-bit
control word on SDIO, which is captured by the device
on rising edges of SCLK. The control word is comprised
of a three bit chip address (A7:A5 = 101b), a read/write
bit (write = 0, read = 1), the chip address (A4 = 0), and a
four bit register address (A3:A0).
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turnaround. Next,
the Si4712/13 drives the 16-bit read data word serially
on SDIO, changing the state of SDIO on each rising
edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9, Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
5.13. GPO Outputs
The Si4712/13 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-Z. The GPO pins
are multiplexed with the bus mode pins or DCLK
depending on the application schematic of the
transmitter. GPO2/INT can be configured to provide
interrupts.
5.14. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset and place it in powerdown mode.
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
and keep the bus active. For more information
concerning Reset, Powerup, Powerdown, and
Initialization, refer to “AN332: Universal Programming
Guide.”
5.15. Programming with Commands
To ease development time and offer maximum
customization, the Si4712/13 provides a simple yet
powerful software interface to program the transmitter.
The device is programmed using commands,
arguments, properties, and responses.
To perform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control actions, such
as powering up the device, shutting down the device, or
tuning to a station. Arguments are specific to a given
command and are used to modify the command. For
example, after the TX_TUNE_FREQ command,
arguments are required to set the tune frequency. A
complete list of commands is available in Table 17,
“Si471x Command Summary,” on page 30.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties
are
TX_PREEMPHASIS
and
GPO_CONFIGURE. A complete list of properties is
available in Table 18, “Si471x Property Summary,” on
page 31.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. At a minimum, all commands provide a one-byte
status update indicating interrupt and clear-to-send
status information. For a detailed description of using
the commands and properties of the Si4712/13, see
“AN332: Universal Programming Guide.”
Rev. 1.1
29
Si4712/13-B30
6. Commands and Properties
Table 17. Si471x Command Summary
30
Cmd
Name
0x01
POWER_UP
Description
Power up device and mode selection. Modes include FM transmit
and analog/digital audio interface configuration.
0x10
GET_REV
0x11
POWER_DOWN
Returns revision information on the device.
Power down device.
0x12
SET_PROPERTY
Sets the value of a property.
0x13
GET_PROPERTY
Retrieves a property’s value.
0x14
GET_INT_STATUS
Read interrupt status bits.
0x15
PATCH_ARGS
Reserved command used for patch file downloads.
0x16
PATCH_DATA
Reserved command used for patch file downloads.
0x30
TX_TUNE_FREQ
Tunes to given transmit frequency.
0x31
TX_TUNE_POWER
Sets the output power level and tunes the antenna capacitor
0x32
TX_TUNE_MEASURE
Measure the received noise level at the specified frequency.
0x33
TX_TUNE_STATUS
0x34
TX_ASQ_STATUS
0x35
TX_RDS_BUFF
0x36
TX_RDS_PS
0x80
GPO_CTL
Configures GPO3 as output or Hi-Z.
0x81
GPO_SET
Sets GPO3 output level (low or high).
Queries the status of a previously sent TX Tune Freq, TX Tune
Power, or TX Tune Measure command.
Queries the TX status and input audio signal metrics.
Si4713 Only. Queries the status of the RDS Group Buffer and loads
new data into buffer.
Si4713 Only. Set up default PS strings.
Rev. 1.1
Si4712/13-B30
Table 18. Si471x Property Summary
Prop
Name
0x0001
GPO_IEN
0x0101
DIGITAL_INPUT _FORMAT
Description
Default
Enables interrupt sources.
0x0000
Configures the digital input format.
0x0000
0x0103 DIGITAL_INPUT _SAMPLE_RATE
Configures the digital input sample rate in 10 Hz steps.
Default is 0.
0x0000
0x0201
REFCLK_FREQ
Sets frequency of the reference clock in Hz. The range is
31130 to 34406 Hz, or 0 to disable the AFC. Default is
32768 Hz.
0x8000
0x0202
REFCLK_PRESCALE
Sets the prescaler value for the reference clock.
0x0001
0x2100
TX_COMPONENT_ENABLE
Enable transmit multiplex signal components.
Default has pilot and L-R enabled.
0x0003
0x2101
TX_AUDIO_DEVIATION
Configures audio frequency deviation level. Units are in
10 Hz increments. Default is 6285 (68.25 kHz).
0x1AA9
0x2102
TX_PILOT_DEVIATION
Configures pilot tone frequency deviation level. Units are
0x02A3
in 10 Hz increments. Default is 675 (6.75 kHz)
0x2103
TX_RDS_DEVIATION
Si4713 Only. Configures the RDS/RBDS frequency
deviation level. Units are in 10 Hz increments. Default is
2 kHz.
0x00C8
0x2104
TX_LINE_INPUT_LEVEL
Configures maximum analog line input level to the
LIN/RIN pins to reach the maximum deviation level programmed into the audio deviation property TX Audio
Deviation. Default is 636 mVPK.
0x327C
0x2105
TX_LINE_INPUT_MUTE
Sets line input mute. L and R inputs may be independently muted. Default is not muted.
0x0000
0x2106
TX_PREEMPHASIS
Configures pre-emphasis time constant.
Default is 0 (75 µS).
0x0000
0x2107
TX_PILOT_FREQUENCY
Configures the frequency of the stereo pilot. Default is
19000 Hz.
0x4A38
0x2200
TX_ACOMP_ENABLE
Enables audio dynamic range control.
Default is 0 (disabled).
0x0002
0x2201
TX_ACOMP_THRESHOLD
Sets the threshold level for audio dynamic range control.
Default is –40 dB.
0xFFD8
0x2202
TX_ACOMP_ATTACK_TIME
Sets the attack time for audio dynamic range control.
Default is 0 (0.5 ms).
0x0000
0x2203
TX_ACOMP_RELEASE_TIME
Sets the release time for audio dynamic range control.
Default is 4 (1000 ms).
0x0004
0x2204
TX_ACOMP_GAIN
Sets the gain for audio dynamic range control.
Default is 15 dB.
0x000F
0x2205
TX_LIMITER_RELEASE_TIME
Sets the limiter release time. Default is 102 (5.01 ms)
0x0066
Configures measurements related to signal quality metrics. Default is none selected.
0x0000
Configures low audio input level detection threshold.
This threshold can be used to detect silence on the
incoming audio.
0x0000
0x2300
TX_ASQ_INTERRUPT_SOURCE
0x2301
TX_ASQ_LEVEL_LOW
Rev. 1.1
31
Si4712/13-B30
Table 18. Si471x Property Summary (Continued)
Prop
Name
Description
Default
0x2302
TX_ASQ_DURATION_LOW
Configures the duration which the input audio level must
be below the low threshold in order to detect a low audio
condition.
0x0000
0x2303
TX_ASQ_LEVEL_HIGH
Configures high audio input level detection threshold.
This threshold can be used to detect activity on the
incoming audio.
0x0000
0x2304
TX_ASQ_DURATION_HIGH
Configures the duration which the input audio level must
be above the high threshold in order to detect a high
audio condition.
0x0000
0x2C00
TX_RDS_INTERRUPT_SOURCE
Si4713 Only. Configure RDS interrupt sources. Default
is none selected.
0x0000
0x2C01
TX_RDS_PI
Si4713 Only. Sets transmit RDS program identifier.
0x40A7
0x2C02
TX_RDS_PS_MIX
Si4713 Only. Configures mix of RDS PS Group with
RDS Group Buffer.
0x0003
0x2C03
TX_RDS_PS_MISC
Si4713 Only. Miscellaneous bits to transmit along with
RDS_PS Groups.
0x1008
0x2C04
TX_RDS_PS_REPEAT_COUNT
Si4713 Only. Number of times to repeat transmission of
a PS message before transmitting the next PS message.
0x0003
0x2C05 TX_RDS_PS_MESSAGE_COUNT Si4713 Only. Number of PS messages in use.
0x2C06
TX_RDS_PS_AF
Si4713 Only. RDS Program Service Alternate Frequency. This provides the ability to inform the receiver of
a single alternate frequency using AF Method A coding
and is transmitted along with the RDS_PS Groups.
0x2C07
TX_RDS_FIFO_SIZE
Si4713 Only. Number of blocks reserved for the FIFO.
Note that the value written must be one larger than the
desired FIFO size.
32
Rev. 1.1
0x0001
0xE0E0
0x0000
Si4712/13-B30
NC
1
LIN
GPO3/DCLK
GPO2/INT
GPO1
NC
7. Pin Descriptions: Si4712/13-GM
20 19 18 17 16
NC 2
15 RIN
RFGND 3
14 DFS
GND
PAD
TXO 4
13 DIN
7
8
9
SDIO
RCLK
10 11 VDD
VIO
6
SCLK
12 GND
SEN
RST 5
Pin Number(s)
Name
Description
1, 2, 20
NC
3
RFGND
4
TXO
FM transmit output connection to transmit antenna.
5
RST
Device reset (active low) input.
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
External reference oscillator input.
10
VIO
I/O supply voltage.
11
VDD
Supply voltage. May be connected directly to battery.
13
DIN
Digital input data.
14
DFS
Digital frame synchronization input.
15
RIN
Right audio line input.
16
LIN
Left audio line input.
17
GPO3/DCLK
18
GPO2/INT
19
GPO1
General purpose output.
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
No connect. Leave floating.
RF ground. Connect to ground plane on PCB.
General purpose output/digital bit synchronous clock input.
General purpose output/interrupt request.
Rev. 1.1
33
Si4712/13-B30
8. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4712-B30-GM
Portable broadcast FM transmitter with receive power
scan
QFN
Pb-free
–20 to 85 °C
Si4713-B30-GM
Portable broadcast FM transmitter with receive power
scan and RDS/RBDS encoder
QFN
Pb-free
–20 to 85 °C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
34
Rev. 1.1
Si4712/13-B30
9. Package Markings (Top Marks)
9.1. Si4712 Top Mark
Figure 20. Si4712 Top Mark
9.2. Si4713 Top Mark
Figure 21. Si4713 Top Mark
9.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
12 = Si4712
13 = Si4713
Firmware Revision
30 = Firmware Revision 30
R = Die Revision
B = Revision B Die
TTT = Internal Code
Internal tracking code.
Line 2 Marking:
Line 3 Marking:
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date.
Rev. 1.1
35
Si4712/13-B30
10. Package Outline: Si4712/13-GM
Figure 22 illustrates the package details for the Si4712/13. Table 19 lists the values for the dimensions shown in
the illustration.
Figure 22. 20-Pin Quad Flat No-Lead (QFN)
Table 19. Package Dimensions
Symbol
Millimeters
Symbol
Min
Nom
Max
A
0.50
0.55
0.60
f
A1
0.00
0.02
0.05
L
0.35
0.40
0.45
b
0.20
0.25
0.30
L1
0.00
—
0.10
c
0.27
0.32
0.37
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
D
D2
1.65
1.70
1.75
0.50 BSC
E
E2
Min
3.00 BSC
e
3.00 BSC
1.65
1.70
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
36
Millimeters
Rev. 1.1
Nom
Max
2.53 BSC
Si4712/13-B30
11. PCB Land Pattern: Si4712/13-GM
Figure 23 illustrates the PCB land pattern details for the Si4712/13-GM. Table 20 lists the values for the dimensions
shown in the illustration.
Figure 23. PCB Land Pattern
Rev. 1.1
37
Si4712/13-B30
Table 20. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
2.71 REF
1.60
1.80
Min
Max
GE
2.10
—
W
—
0.34
—
e
0.50 BSC
X
E
2.71 REF
Y
E2
f
GD
1.60
1.80
2.53 BSC
2.10
Millimeters
0.28
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.
3. This land pattern design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.
Note: Solder Mask Design
1. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 mm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component standoff.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for small body components.
38
Rev. 1.1
Si4712/13-B30
12. Additional Reference Resources







Si47xx Evaluation Board User’s Guide
AN307: Si4712/13/20/21 Receive Power Scan
AN309: Si4710/11/12/13 Evaluation Board QuickStart Guide
AN332: Universal Programming Guide
AN383: Universal Antenna Selection and Layout
Guidelines
AN388: Universal Evaluation Board Test Procedure
Si4710/11/12/13 Customer Support Site:
http://www.mysilabs.com
This site contains all application notes, evaluation
board schematics and layouts, and evaluation
software. NDA is required for access. To request
access, send mysilabs user name and request for
access to [email protected].
Rev. 1.1
39
Si4712/13-B30
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 0.9






Updated Table 3 on page 5.
Updated Table 8 on page 11.
Updated Table 9 on page 12.
Updated Table 17 on page 30.
Updated Table 18 on page 31.
Added "9. Package Markings (Top Marks)" on page
35.
Revision 0.9 to Revision 1.0






Updated Table 3 on page 5.
Updated production test conditions in Table 9 on
page 12.
Updated Table 10 on page 14.
Corrected title in Figure 19 on page 26.
Corrected typo in "5.4.2. Audio Sample Rates" on
page 23.
Updated references to new application notes
throughout document.
Revision 1.0 to Revision 1.1

40
Updated Table 3 on page 5.
Rev. 1.1
Si4712/13-B30
NOTES:
Rev. 1.1
41
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