AN930: EFR32 2.4 GHz Matching Guide

AN930: EFR32 2.4 GHz Matching Guide
This document describes the matching techniques applied to the
EFR32 Wireless Gecko Portfolio in the 2.4 GHz band. A separate, upcoming application note will describe the matching procedure in the sub-GHz bands. In addition, application note, "AN928:
EFR32 Layout Design Guide", describes the pcb layout hints required for proper 2.4 GHz operation and application note,
"AN933: EFR32 2.4 GHz Minimal BOM", describes the method to
minimize the BOM of the design. This application note presents a
thorough derivation of a number of matching topologies. For the
reader simply looking for recommended values and topologies,
skip to sections 3.5 and 4.
KEY POINTS
• Description of the applied 2.4 GHz
matching networks and techniques for the
EFR32 device
• Detailed discussion of the design steps
and design examples are presented.
• Three different EFR32 versions: 7x7mm 48
pin dual band version, 7x7mm 48 pin
2.4GHz version, and 5x5mm 32pin 2.4GHz
version.
• Measured TX spectrum and RX sensitivity
results are presented
Two 2.4 GHz matching types are detailed in this application note:
• 2-element discrete LC match up to 10 dBm power levels
• 4-element discrete LCLC match for higher power levels
The EFR32 devices include chip variants that provide 2.4 GHzonly operation, sub-GHz-only operation, or dual-band (2.4 GHz
and sub-GHz) operation. Also, the EFR32 chips are available
with a 7x7mm 48pin package and with a 5x5mm 32pin package.
The above matches are tested with three EFR32 variants: 7x7
mm, 48-pin 2.4 GHz; 5x5 mm, 32-pin 2.4 GHz and 7x7 mm, 48pin dual band. As an example, the 7x7 mm, 48-pin 2.4 GHz-only
version's package pin out is shown in the figure below. The 2.4
GHz RF pins are highlighted with the red square in the figure.
Figure .1. EFR32 2.4 GHz RF Pins
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AN930: EFR32 2.4 GHz Matching Guide
EFR RF Architecture Overview
1. EFR RF Architecture Overview
The EFR (Dumbo) chip has separate sub-GHz and 2.4 GHz RF frontends. The sub-GHz part is not detailed here. The 2.4 GHz RF
frontend architecture of the EFR (Dumbo) chip is shown in the figure below.
The 2.4 GHz frontend has a unified, single-ended TX and RX pin (RFIO_P), so the TX and RX path are tied together internally. The
RFIO_N TX pin has to be grounded right at the pin. It should be a good RF ground with many parallel GND vias.
Radio Transciever
2G4RF_IOP
2G4RF_ION
BALUN
PA
I
Q
PGA
Frequency
Synthesizer
BUFC
LNA
RAC
RF Frontend
FRC
RFSENSE
CRC
DEMOD
IFADC
AGC
MOD
Figure 1.1. 2.4 GHz Frontend Configuration
The on-chip part of the frontend comprises a variable (from 0 dBm up to 20 dBm) power class AB differential PA, a variable PA tuning
cap, a differential LNA, an LNA/low power PA match + protection circuit, and an integrated balun. The high power PA is biased through
the PAVDD pin. Externally, a single-ended matching network and harmonic filtering is required.
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Optimum Termination Impedance for the PA
2. Optimum Termination Impedance for the PA
The first step of the matching design procedure is to determine the optimum termination impedance at the PA. The realized matching
network should present this impedance for the PA at the 2G4RF_IOP pin if 50 Ω termination is applied at the antenna port. The optimum impedance depends on the power level and the package version. Fortunately, they are quite close to each other so one match is
a good compromise for all versions and power levels. The optimum impedances are determined empirically by load pull methods. Figure 2.1.a shows the 2.4 GHz load-pull curves measured at the TX pin of the 7x7 mm, 48-pin 2.4 GHz single band EFR version with 20
dBm power setting. The optimum impedance point here is ~23.7+j7.1 Ω. Fortunately, this is quite constant with frequency. For example,
in the middle of the 2.4 GHz band (2.45 GHz), it is only very slightly off: ~24.1+j7.2 Ω. Figure 2.1.b shows the measured 20 dBm, 2.4
GHz load pull data for the 7x7 mm, 48-pin dual band EFR version at the TX pin. Here the optimum impedance is approximately
23+j11.5 Ω. At 2.45 GHz, the optimum is slightly lower: ~21+j10.4 Ω. Figure 2.1.c shows the measured 20 dBm, 2.4 GHz load-pull data
for the 5x5 mm, 32-pin single band EFR version at the TX pin. The optimum impedance here is approximately 20+j14 Ω.
Figure 2.1. Load-pull Curves and Optimum Termination Impedances at the 2G4RF_IOP Pin of the Different EFR32 Package
Versions: a) 7x7 mm Dual Band, b) 7x7 mm Single Band, c) 5x5 mm Single Band, d) Optimum TX Impedances of the Three
Package Versions
The 2.4 GHz, 20 dBm level optimum termination impedances for the three EFR versions are shown together in Fig 2.1.d. As only one
matching will be used for all variations, a compromise must be found. Fortunately, the three optimum impedances are close to each
other so if a compromise is used, which is 23+j11.5 Ω, the power degradation is less than 0.3 dB. According to this, the selected target
impedance for further PA matching design is 23+j11.5 Ω.The optimum impedance does not depend too much on the power level. At 10
dBm power level the optimum termination is ~20+j10.6 Ω for the 7x7 mm dual band EFR version. This is used as a target for the 10
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Optimum Termination Impedance for the PA
dBm 2-element matching network design. The proper impedance at the single-ended output pin (2G4RF_IOP) also depends on the
grounding of the other (2G4RF_ION) TX pin. To keep its effect negligible, this pin should be massively connected to the next ground
layer beneath by many vias, as shown by the blue dashed ellipse in the figure below. More detailed information about the proper layout
design can be found in the application note, "AN928: EFR32 Layout Design Guide".
Figure 2.2. Element Match PCB Layout with Good 2G4RF_ION Grounding
In real radio links, the TX power and the receiver sensitivity together (i.e., the link budget) determines the range. So with the applied TX
termination impedance, the impedance match in RX mode should be acceptable as well.
In RX mode, the optimum termination impedance would be 50 Ω. Using 23+j11.5 Ω instead, the reflection coefficient is:
Gamma =
Z term − Z 0
Z term + Z 0
=
23 + j11.5 − 50
= 0.4e j148
23 + j11.5 + 50
This corresponds to an S11 of -8 dB. Knowing the Gamma, the extra insertion loss caused by this can be calculated easily:
I L dB = − 10log (1 − | Gamma | 2) = 0.75dB
By decreasing the reactance and increasing the real part of the impedance, the extra insertion loss in RX mode can be decreased
slightly. Unfortunately, from the load pull curves one can see that only limited impedance variation is allowed to avoid a significant power decrease. So, on one hand we lose some TX power as the impedance is slightly away from the load-pull optimum, but on other
hand, we win some RX sensitivity as the reflection loss is lower in RX mode. By maintaining nearly the same overall link budget one
can play slightly with the matching impedance, if due to other reasons (e.g. harmonic suppression) the optimum TX impedance of
23+j11.5 Ω cannot be kept. This method will be used in section 3. Detailed Matching Procedure for the Lumped Element Match with the
discrete 4-element match.
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Detailed Matching Procedure for the Lumped Element Match
3. Detailed Matching Procedure for the Lumped Element Match
With the conditions described in section 2. Optimum Termination Impedance for the PA, the optimum termination impedance at the
2G4RF_IOP pin should be: Zload_opt = F 23 + j11.5Ω.
3.1 Matching Procedure without Parasitic and Loss
The second step of the matching design procedure is to generate the lumped element skeleton of the match with ideal loss free elements and pcb parasitics. The matching circuit should show the Zload_opt = ~23+j11.5 Ω impedance at the input while it is terminated
by 50 Ω at its output. If it shows the Zload_opt impedance at the input, then it has to be matched to a generator which has the conjugate of the Zload_opt impedance. One can apply the general lumped, two reactive element matching technique (see the 6. References
section, item 1. ) to create the skeleton of the simplest 2-element match. In theory, two possible solutions exist: a low pass and a high
pass. These procedures are shown in Figure 3.1 Basic 2-element Matching Techniques with Ideal Lumped Elements on page 4 a
and b. As the circuit should filter the harmonics as well, only the low pass solution shown in the first column of Figure 3.1 Basic 2element Matching Techniques with Ideal Lumped Elements on page 4 is applied further. The ideal (parasitic and loss free) 2-element low pass match (Figure 3.1.a) is comprised of a series 2.3 nH inductor followed by 1.4 pF parallel capacitor.
Figure 3.1. Basic 2-element Matching Techniques with Ideal Lumped Elements
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Detailed Matching Procedure for the Lumped Element Match
A 4-element match can be designed in two ways: using the 2- element match with an additional 2-element filter section or using a 4element matching + filter combo. In the latter case, all the four elements take part in the impedance match as well and thus, it is less
sensitive to the element spreading. Additionally, the (reactive) elements realize less phase shift so the impedance locus varies closer to
the smith chart center, which means a lower Q route. As a result, the loss of the elements has lower influence. Unfortunately, due to
having more stages, the overall insertion loss can be higher with four elements. A possible 4-element design with ideal elements is
shown in the figure below.
Figure 3.2. Basic 4-element Matching Technique with Ideal Lumped Elements
Unfortunately, in pcb designs, the parasitics and losses of the pcb and SMD elements have to be taken into account.
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Detailed Matching Procedure for the Lumped Element Match
3.2 Matching Procedure with SMD Parasitics and Losses
As a third step, the parasitics of the discretes should be taken into account in the design. For the Silicon Laboratories reference designs
0402, size SMD elements are used. With 0201 elements, one can expect lower losses and parasitics and thus better performance, but
their handling is more difficult. The most critical elements in the matching networks are the inductors due to their much higher cost and
lower Q compared to the SMD capacitors.
There are three basic SMD inductor types: the wirewound, the film-based, and the multilayer type. A good description about SMD inductors can be found in the 6. References section, item 2., at the end of this document. The wirewound inductor has the best Q, while
the multilayer type has the worst. The good Q (i.e., the low loss) is important to achieve low insertion loss in low pass structures, where
the inductor is the series element. Unfortunately, the price of the wirewound inductor is the highest, it is typically several cents, while the
multilayer is the cheapest one, typically much less than a cent in high volume. The film type inductors are in the middle, i.e., they are a
good compromise at 2.4 GHz both from price and Q point of view.
The SMD parasitics are investigated on the 2-element match applying a film type inductor. A simplified equivalent circuit of the used
Murata SMD capacitance (1.4 pF) and film inductance (2.3 nH) is shown in Figure 3.3 Equivalent Circuits of Real SMDs at the Fundamental Frequency on page 6. Up to higher harmonics, these SMDs have several secondary resonances, which are not covered by
this simplified equivalent circuit, so they are accurate at the fundamental frequency only. For higher harmonic simulations, the measured S-parameters given by the SMD manufacturer are used as the real equivalent circuits are very complicated. Using these SMD
models, the impedance is slightly different from 50 Ω at the termination side of the match (Figure 3.4 2-element Matching Mistuning with
Real SMD Elements on page 6). To shift it back it to the center (i.e., to the 50 Ω), a slight decrease of the parallel capacitor to 1.2 pF
value is required (Figure 3.5 Tuned 2-element Match with Real SMD Elements on page 7).
Figure 3.3. Equivalent Circuits of Real SMDs at the Fundamental Frequency
Figure 3.4. 2-element Matching Mistuning with Real SMD Elements
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.5. Tuned 2-element Match with Real SMD Elements
3.3 Rough Estimation of PCB Parasitics
In addition to the discrete parasitics, the following pcb trace parasitics also have significant effects:
• Series inductances
• Parallel capacitances
• Losses
Accounting for these effects is the fourth step of the matching design. These trace parasitics usually enforce the further decrease of the
values of the discrete low pass prototype (series inductance and parallel capacitance) matching elements. There are three ways to simulate the pcb parasitics: lumped element, distributed element, and EM-based approach. As the trace lengths in the match are usually
shorter than 1 mm, i.e., much lower than the wavelength at 2.4 GHz, even the simple distributed element method gives good accuracy.
The most accurate is the EM-based method, but that usually requires expertise and expensive CAD tools.
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Detailed Matching Procedure for the Lumped Element Match
3.3.1 Reference Plane Considerations for the EFR IC Pins and the SMDS
The figure below shows the reference plane positions used in the simulations for the EFR IC 2G4RF_IOP pin and for the discrete SMD
pins. As the IC pin covers the whole pad area, the reference plane falls to the geometrical middle of the pcb pad as well, i.e., the series
parasitics (either an inductance or a transmission line) are averaged. With the discrete SMD elements, the reference plane is put to the
ends of the SMD soldering pin as the S-parameters given by the vendor are calibrated to these planes as well.
Figure 3.6. Reference Planes with Real SMD Elements
Figure 3.7 Estimation of PCB Layout Parasitics on page 9 shows the 5x5 mm single band top layer RF part layout with estimated
series parasitic inductor and parallel capacitor values. The series pcb parasitics are calculated here using the reference plane definitions of Figure 3.6 Reference Planes with Real SMD Elements on page 8. For example, the parasitic inductance of the EFR soldering
pad are taken into account with half of the physical length. Also, in case of the series SMDs, the non-overlapping sections of the soldering pads are taken into account as additional series parasitics. Here, a section is 0.25 mm long between the SMD reference plane and
trace side pad edge. The traces between the soldering pads are represented with full parasitic inductance. The parallel parasitic cap
values are calculated to the whole printed area including the soldering pads. Here, estimation both for the area cap and the fringing field
caps (down to the grounding layer beneath and to the side ground metal on the same layer) are required. The easiest way to make that
estimation is to use a grounded coplanar calculator, which computes the unit parallel capacitance and series inductance parasitics as
well. Numerous calculators can be found on the internet. An example of this type of calculator is given in the 6. References section,
item 3., at the end of this document.
In Figure 3.7 Estimation of PCB Layout Parasitics on page 9, the dimensions including the gap size to side ground of all route sections in the match are detailed. From this and from the pcb parameters (thickness 0.325 mm, epsilon 4.3, tangd = 0.02, metal thickness
= 17 um, etc.) one can calculate the parasitics. They are shown in the figure as well (here the pcb loss is neglected as it is significantly
lower than the SMD losses).
The 2-element matching circuit with pcb parasitics is shown in Figure 3.8 2-element Lumped Element Match with Discrete Models of the
PCB Layout Parasitics on page 9. Here in place of the second inductor (L1) a 0 Ω is used with 0.1 nH parasitic inductance. The
second matching cap (C1) is not fitted.
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.7. Estimation of PCB Layout Parasitics
Figure 3.8. 2-element Lumped Element Match with Discrete Models of the PCB Layout Parasitics
This section describes the matching network structure on the smith chart step-by-step. Here the equivalent circuits of the SMDs given in
Figure 3.3 Equivalent Circuits of Real SMDs at the Fundamental Frequency on page 6 are used. Figure 3.9 2-element Matching Mistuning due to PCB and SMD Parasitics on page 10 shows the locust. Here, due to the pcb and SMD parasitics, the output impedance
(denoted by Zin in the figure) is not matched to 50 Ω. For a good match, both the L0 and the C0 should be decreased. Figure 3.10 2element Match both with SMD and PCB Layout Parasitics Tuned to the 20 dBm Power Level Optimum Impedance (23+j11.5 Ω) on
page 10 shows the modified match with an L0 of 1.8 nH and a C0 of 1.1 pF. Unfortunately, the harmonic suppression of the 2-element match is not enough at 20 dBm power level, so it is used up to 10 dBm. However, at 10 dBm power level the optimum load-pull
termination impedance is slightly lower, around 20+j10 Ω, and thus, slight modifications in the matching element values are required.
Figure 3.11 2-element Match both with SMD and PCB Layout Parasitics Tuned for the 10 dBm Power Level Optimum (20+j10 Ω) on
page 11 shows the modified match (with L0=1.7 nH, C0=1.2 pF) to this new impedance.
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.9. 2-element Matching Mistuning due to PCB and SMD Parasitics
Figure 3.10. 2-element Match both with SMD and PCB Layout Parasitics Tuned to the 20 dBm Power Level Optimum Impedance (23+j11.5 Ω)
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.11. 2-element Match both with SMD and PCB Layout Parasitics Tuned for the 10 dBm Power Level Optimum (20+j10
Ω)
3.4 EM Simulations
As mentioned previously, the best accuracy can be achieved by EM simulations. However, this step can be skipped if one does not
have the proper CAD tool for it. The EM simulated results shown here are created by the Axiem 3D planar simulator of AWR Corporation.
Figure 3.12 EM Simulated Layout for the Discrete Lumped Element Matches on page 12 shows the simulated layout. This layout is
used both for the 2-element and 4-element match. Here the 2G4RF_IOP pin of the EFR32 chip is connected to Port 2. The L0 inductor
is connected between Port 3 and 4, the C0 capacitor between Port 5 and 6, the L1 inductor between Port 7 and 8 and the C1 capacitor
between Port 9 and 10. For the 2-element match, a 0 Ω is connected to the place of L1 and the C1 and is not fitted.
Figure 3.13.a shows the EM simulated impedance of the 2 -element match at the EFR TX pin (Port 2) together with the targeted 10
dBm power impedance (~20+j10 Ω). They are quite close. Here an L0 series inductance of 1.9 nH and a C0 parallel capacitance of 1.5
pF is used as shown in Table 3.1 Final SMD Values for the 2-element Match on page 11.
Table 3.1. Final SMD Values for the 2-element Match
Two-element Matching Network
Schematic Reference Designator
Component Value
Tolerance
Part Number
Manufacturer
LH0
1.9 nH
±0.05 nH
LQP15MN1N9W02
Murata
CH0
1.5 pF
±0.1 pF
GRM1555C1H1R5BA01D
Murata
Figure 3.13.b shows the simulated transfer characteristic from the TX pin to the 50 Ω output port. As expected, the 2nd harmonic suppression is enough up to ~10 dBm fundamental power only.
Figure 3.14 EM Simulation Results of the 4-element SMD Match on page 13 shows the EM simulated results of the 4-element match,
with the SMD elements given in Table 3.2 Final SMD Values for the 4-element Match on page 13. The 4-element match harmonic
suppression is properly high for the 20 dBm power level, but unnecessarily high for the 10 dBm or lower power levels, so to save cost, it
is not recommended for low power levels.
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.12. EM Simulated Layout for the Discrete Lumped Element Matches
Figure 3.13. EM Simulation Results of the 2-element SMD Match
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.14. EM Simulation Results of the 4-element SMD Match
Table 3.2. Final SMD Values for the 4-element Match
Four-element matching network
Schematic reference designator
Component value
Tolerance
Part Number
Manufacturer
LH0
1.8 nH
±0.1 nH
LQP15MN1N8B02
Murata
LH1
3.0 nH
±0.1 nH
LQP15MN3N0B02
Murata
CH0
2.0 pF
±0.1 pF
GRM1555C1H2R0BA01D
Murata
CH1
1.0 pF
±0.1 pF
GRM1555C1H1R0BA01D
Murata
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Detailed Matching Procedure for the Lumped Element Match
3.5 Bench Tuning and Measured Results
The final (5th) step of the matching design is bench tuning with real measurements. Figure 3.15 Impedance and Transfer Characteristic
Measurement of the Matches on page 14 shows the impedance and transfer characteristic measurement setup. Port 1 of the VNA is
connected to the soldering pad of the 2G4RF_IOP pin through a pigtail (the EFR32 chip is removed here as only the matching network
is measured). The reference plane of the S-parameter measurements are shifted to the TX pin. Port 2 is connected to the matching 50
Ω output through an UFL connector.
Figure 3.16 Measured S11 and S21 (Transfer) Characteristic of the 2-element SMD Match on page 15 shows the measured impedance and transfer characteristic of the 2-element match with the SMD elements of Table 3.1 Final SMD Values for the 2-element
Match on page 11. As shown, the real part is very close to the targeted 20 Ω but the reactance is slightly higher (14 Ω instead of the
targeted 10 Ω). This slight deviation causes a negligible (> 0.1 dB) power drop according to the load pull curves of Figure 2.1 Load-pull
Curves and Optimum Termination Impedances at the 2G4RF_IOP Pin of the Different EFR32 Package Versions: a) 7x7 mm Dual
Band, b) 7x7 mm Single Band, c) 5x5 mm Single Band, d) Optimum TX Impedances of the Three Package Versions on page 2, so the
2-element match is not tuned further.
Regarding the 2nd harmonic suppression, it is only 13.7 dB, so the 2-element match is only proper for the lower (< -10 dBm) power
states as expected..
The measured characteristic of the 4-element match applying the elements of Table 3.2 Final SMD Values for the 4-element Match on
page 13 is shown in Figure 3.17 Measured S11 and S21 (Transfer) Characteristic of the 4-element SMD Match on page 16. In Figure
3.16.a, the real impedance is quite close to the targeted 23 Ω, while the imaginary part is lower (~3 Ω instead of ~11.5 Ω).
Figure 3.15. Impedance and Transfer Characteristic Measurement of the Matches
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.16. Measured S11 and S21 (Transfer) Characteristic of the 2-element SMD Match
According to the load-pull figures (Figure 2.1 Load-pull Curves and Optimum Termination Impedances at the 2G4RF_IOP Pin of the
Different EFR32 Package Versions: a) 7x7 mm Dual Band, b) 7x7 mm Single Band, c) 5x5 mm Single Band, d) Optimum TX Impedances of the Three Package Versions on page 2), this reactance deviation causes a ~0.2…0.4 dB power drop depending on the EFR32
package version. However, in RX mode this lower match reactance can be advantageous due to the lower mismatch loss to the
2G4RF_IOP pin as already detailed at the end of section 2. Optimum Termination Impedance for the PA. Let’s calculate the situation
here: the 4-element match measured impedance of ~25+j3 Ω results in a Gamma of 0.34exp(j170) at the 2G4RF_IOP pin in RX mode.
The mismatch loss caused by this Gamma is ~0.5 dB. With the targeted Zload_opt=23+j11.5 Ω matching impedance it would be ~0.75
dB i.e. ~0.25 dB higher. So, with the 25+j3 Ω impedance, ~0.2…0.4 dB power will be lost on the TX side, but ~0.25 dB sensitivity will be
gained on the RX side. This yields nearly the same overall link budget. As the transfer impedance is also quite good (it has low insertion
loss and high second- and third-harmonic suppression), the designed 4-element discrete match is a good compromise.
The measured 2-element and 4-element spectrum plots in the middle of the band (2.45 GHz) with the 7x7 mm dual band EFR32 version are shown in Figure 3.18 Measured Spectrum Plots of the Dual Band 7x7 mm EFR32 with a) 2-element Match in 10 dBm Power
State b) 4-element Match in 20 dBm Power State on page 16. The 2-element match is tested with 10 dBm power setting while the 4element match is tested with 20 dBm power setting.
In the 20 dBm power setting (Figure 3.18.b), the achieved fundamental power is ~19 dBm at 2.45 GHz. Large volume measurements
shows approx. ±1 dB variation of the output power. The average is typically ~19.5 dBm with 134 mA total IC current. It has to emphasize that the loss of the applied UFL connector at the matching output is higher compared to an SMA connector. With an SMA connector applied the output power level is approximately 0.3 dB higher, i.e., close to 19.8 dBm. And if the output is directly connected to the
terminating antenna, then the delivered power is approximately 20 dBm.
With the 2-element match, the IC consumes ~40 mA current at ~10 dBm power level. Here and up to 13 dBm power levels, Silicon
Laboratories proposes to supply the PA from the internal dc-dc converter. The generated supply voltage by the dc-dc converter is 1.8 V.
The allowed harmonic level by the US FCC is -41.2 dBm EIRP (or 500 uV/m electric field strength at 3 m distance), while it is -27.8
dBm EIRP by the EU ETSI regulation. As shown in the figures, the 2nd harmonic with the 2-element match has approximately 3 dB
margin to the more strict FCC limit at 10 dBm power level. With the 4-element match the margin is much larger even at the highest, 20
dBm power level.
It should be noted that, in the spectrum measurements, the Spectrum Analyzer is used as a wide band 50 Ω termination. With a real
antenna, the termination at the harmonics can differ significantly from the 50 Ω and as well as the delivered power to the antenna.
Moreover, the harmonic termination impedance at the matching output depends on the transmission line properties between the matching and the antenna. In addition, the radiation gain of the antenna can also differ at the different harmonic frequencies. Due to these
facts, the radiated harmonic power levels can be very different from the conducted measurement results and may violate the radiation
standards. This behavior is most critical at the 2nd harmonic frequency as that is the strongest spurious spectral component.
Silicon Laboratories will determine (in the next version of this application note) the critical termination impedance regions at the 2nd
harmonic frequency, where significant increase of the harmonic power can occur. The impedance of the antenna together with the connecting transmission line section should avoid these impedance regions at the 2nd harmonic. Measured 20 dBm 4-element spectrum
plots at 2.45 GHz with the 7x7 mm and 5x5 mm 2.4 GHz single band EFR32 versions are shown in Figure 3.19 Measured Spectrum
Plots of the Single Band EFR32 with 4-element Match with 20dBm Power State a) 7x7mm Package Version b) 5x5mm Package Version on page 17. The different package versions have no significant effect on the output spectrum using the same 4-element match.
This is the case with the 2-element match as well. Band edge (2.4 GHz and 2.48 GHz) spectrum variations are detailed in the
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Appendix. The largest fundamental power variation across the band is typically less than 0.5 dB and the harmonics also much lower
than the allowed limits independently of the package version.
Figure 3.17. Measured S11 and S21 (Transfer) Characteristic of the 4-element SMD Match
Figure 3.18. Measured Spectrum Plots of the Dual Band 7x7 mm EFR32 with a) 2-element Match in 10 dBm Power State b) 4element Match in 20 dBm Power State
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Detailed Matching Procedure for the Lumped Element Match
Figure 3.19. Measured Spectrum Plots of the Single Band EFR32 with 4-element Match with 20dBm Power State a) 7x7mm
Package Version b) 5x5mm Package Version
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Sensitivity Measurements
4. Sensitivity Measurements
The sensitivity of the different matches are compared in Table 4.1 Measured Sensitivities of the Different Matching Types and EFR32
Package Versions using Standard 20 byte ZigBee Packages on page 18. Here, 20 byte long standard 802.15.4 packages are used
and 1 % PER sensitivity is shown. The frequency is 2.405 GHz (i.e., the first Zigbee channel). As no large quantities are measured here
yet, these measurements are indicative ones. The applied setup is the WSTK motherboard and the Dev4150 type development boards
with different match types.
Table 4.1. Measured Sensitivities of the Different Matching Types and EFR32 Package Versions using Standard 20 byte ZigBee Packages
Matching Type
Sensitivity [dBm]
7x7 mm Dual Band 4-element
–97.9
7x7 mm Dual Band 2-element
–98.5
7x7 mm 2.4 GHz Single Band 4-element
TBD
7x7mm 2.4 GHz Single Band 2-element
–98
5x5 mm 2.4 GHz Single Band 4-element
–97.5
5x5 mm 2.4 GHz Single Band 2-element
–98
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Conclusions
5. Conclusions
1. The 2-element an 4-element matches work well with all the investigated EFR32 package versions. The TX power variation is less
than ~0.5 dB. The harmonics are below the FCC and ETSI limits
Note: The the 2-element match is devoted only up to 10 dBm operation.
2. All matches with all EFR32 package versions have less than ~0.5 dB power variation across the whole 2.4 GHz band.
3. Typical total IC current consumption is ~40 mA at 10 dBm and ~135 mA at 20 dBm power level. Silicon Laboratories recommends
up to 13 dBm power level to supply the PA from the internal dc-dc converter. The current does not vary too much with the different
packages.
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References
6. References
1. Christian Gentili: Microwave Amplifiers and Oscillators, McGraw-Hill, 1987, ISBN0-07-022995-3
2. MuRata: http://www.murata.com/products/inductor/chip/feature/rf
3. http://wcalc.so+urceforge.net/cgi-bin/coplanar.cgi(Copyright © 2001-2009 Dan McMahill.CGIC, copyright 1996, 1997, 1998, 1999,
2000 by Thomas Boutell and Boutell.Com, Inc.. Permission is granted to use CGIC in any application, commercial or noncommercial, at no cost.)
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Appendix 1.
Figure 1.1. 4-element Match 7x7 mm Dual Band Spectrum Variations across the 2.4 GHz Band
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Figure 1.2. 4-element Match 7x7 mm Single Band Spectrum Variations across the 2.4 GHz Band
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Figure 1.3. 4-element Match 7x7 mm Single Band Spectrum Variations across the 2.4 GHz Band
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Figure 1.4. 4-element Match 5x5 mm Single Band Spectrum variations across the 2.4 GHz Band
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