TS10 EMBER® EM35 X NCP HOST (STM32) MODULE TECHNICAL SPECIFICATION When combined with an Ember EM35x NCP Breakout Board, the Ember STM32 NCP Host Module offers a complete ZigBee wireless solution for development and deployment of a low-data-rate, low-power ZigBee application. The STM32 microprocessor is part of the two-layer (FR4-based) host module that connects to the EM35x NCP Breakout Board through the board-to-board connectors. This document provides the technical specification for the STM32 EM35x NCP Host Module. It describes the boardlevel interfaces as well as the key performance parameters. In addition, it provides the necessary information for developer to validate their application designs using the STM32 EM35x NCP Host Module. New in This Revision Document renumbering. Contents 1 STM32 Host Module Features ......................................................................................................................... 2 2 Components ................................................................................................................................................... 3 3 2.1 STM32 Microcontroller ............................................................................................................................. 4 2.2 EM35x NCP Breakout Board interface connector (J1-J2) .......................................................................... 4 2.3 JTAG Programming and Debug Connector (J3)........................................................................................ 6 2.4 Unused STM32 GPIO (TP0-TP10) ........................................................................................................... 7 STM32 NCP Host Module Schematic .............................................................................................................. 7 Rev 0.4 Copyright © 2013 by Silicon Laboratories TS10 TS10 1 STM32 Host Module Features The STM32 EM35x NCP Host Module offers: • ® ARM Cortex™-M3 based microprocessor (STM32F103RET6) 512 kB FLASH, 64 kB RAM • • • • • • • • Host UART1 for use with STM32 serial bootloader and application serial UART Host UART2 for EZSP UART interface to EM35x NCP Host SPI1 for EZSP SPI interface to EM35x NCP 16 additional Host GPIO routed to mating connector for application use on EM35x NCP Breakout Board All unused Host GPIO routed to test points 14-pin, 0.1” pitch, dual-row, JTAG programming and debug header (could be used with a JTAG programmer such as SEGGER’s JLINK.) 16-pin, 0.1” pitch, single-row along with a 20-pin 0.1” pitch, single-row, board-to-board connector for mating to the EM35x NCP Breakout Board Spare Host IO routed to test points for application use Table 1 lists the DC electrical characteristics of the STM32 EM35x NCP Host Module. Table 1. DC Electrical Characteristics Parameter Min. VDD supply 2.0 Current Draw (active) Operating temperature Typ. Max. Unit 3.6 V 45 0 mA + 55 For more information on the STM32F103RET6, refer to the STM32 data sheet (download from http://www.st.com/internet/mcu/product/164485.jsp). 2 Rev. 0.4 C TS10 2 Components Figure 1 illustrates the components on layer 1 (top side), while Figure 2 illustrates the components on layer 2 (bottom side). Spare GPIO Routed to Test Points (TP0-TP10) Pair of 0.1" Interface Connectors (J1-J2) STM32F103RET6 Micro (U1) 14-pin 0.1" JTAG Connector (J3) Figure 1. Assembly Print for Layer 1 Serial Number Label Pair of 0.1" Interface Connectors (J1-J2) Figure 2. Assembly Print for Layer 2 Rev. 0.4 3 TS10 2.1 STM32 Microcontroller The STM32 NCP Host Module contains the STM32F103RET6 microcontroller from ST Microelectronics. This microcontroller is based on the Cortex-M3 core from ARM. This version of the STM32 contains 512 kB of FLASH and 64 kB of SRAM. Two USARTs are exposed to the board-to-board connector for STM32 system bootloading (STM32 USART1) and EZSP UART (STM32 USART2) to the EM35x NCP. Two SPI ports are also routed to the board-to-board connector for EZSP SPI interface to the EM35x NCP (STM32 SPI1) and external DataFlash (STM32 SPI2). Various other IOs are exposed to the board-to-board connector, including timers and interrupts. For more information on the STM32F103RET6, refer to the STM32 datasheet (download from http://www.st.com/internet/mcu/product/164485.jsp). 2.2 EM35x NCP Breakout Board interface connector (J1-J2) Two single-row, 0.1” pitch, connectors make up the STM32 NCP host module interface to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to 16 Host GPIO for application purposes, along with 2 USART ports and 1 SPI port dedicated to EZSP and debug use. These 16 Host GPIO are listed in Table 2; the connector is illustrated in Figure 3. Interface connector dimensions are shown in Figure 4. Table 2. Host GPIO Functions 4 Host GPIO STM32 I/O Primary GPIO Function HGPIO0 PB8 Application LED (LED0) HGPIO1 PB9 Application LED (LED1) HGPIO2 PB10 Application Button (BUTTON0) HGPIO3 PB11 Application Button (BUTTON1) HGPIO4 PC6 Application Speaker (PIEZO) HGPIO5 PC7 Spare GPIO HGPIO6 PC8 Spare GPIO HGPIO7 PA8 Temperature Sensor Enable (TEMP_ENABLE) HGPIO8 PC0 Temperature Sensor ADC (TEMP_SENSOR) HGPIO9 PC1 Spare GPIO HGPIO10 PB6 Spare GPIO HGPIO11 PB7 DataFlash Shutdown (DF_nSD) HGPIO12 PB12 DataFlash SPI Chip Select (DF_nCS) HGPIO13 PB13 DataFlash SPI Clock (DF_SCK) HGPIO14 PB15 DataFlash SPI Serial In (DF_SI) HGPIO15 PB14 DataFlash SPI Serial Out (DF_SO) Rev. 0.4 TS10 J2 J1 VDD_3V 17 EZSP_nRTS2 18 1 PB6 EZSP_nCTS2 19 2 PB7 EZSP_RXD2 20 3 LED0 EZSP_TXD2 21 4 LED1 TEMP_ENABLE 22 5 nRESET PC8 23 6 TEMP_SENSOR PC7 24 7 PC1 PIEZO 25 SER_nCTS1 DF_SO 26 SER_nRTS1 DF_SI 27 DF_SCK 28 8 9 10 SER_TXD1 11 SER_RXD1 DF_nCS 29 12 nSS BUTTON1 30 13 SCK BUTTON0 31 14 MISO BTL 32 15 MOSI NCP_nRESET 33 16 nHOST_INT nWAKE 34 N/C 35 GND 36 Figure 3. Board-to-Board Connector for the STM32 NCP Host Module Figure 4. Board-to-Board Connector Dimensions for the STM32 NCP Host Module Table 3 describes the pinout and signal names at J1 and J2. For more information on the functions of the STM32 GPIO, refer to the STM32 datasheet (download from http://www.st.com/internet/mcu/product/164485.jsp). Rev. 0.4 5 TS10 Table 3. Pinout and signal names of the interface connectors 2 2 Pin # Signal name Direction Connector Description 1 PB6 I/O J1 Spare STM32 GPIO (HGPIO10) 2 PB7 I/O J1 Spare STM32 GPIO (HGPIO11) 3 LED0 I/O J1 STM32 PB8 (HGPIO0) 4 LED1 I/O J1 STM32 PB9 (HGPIO1) 5 nRESET I/O J1 STM32 Reset 6 TEMP_SENSOR I/O J1 STM32 PC0 (HGPIO8) 7 PC1 I/O J1 Spare STM32 GPIO (HGPIO9) 8 SER_nCTS1 I/O J1 STM32 PA11 9 SER_nRTS1 I/O J1 STM32 PA12 10 SER_TXD1 I/O J1 STM32 PA9 11 SER_RXD1 I/O J1 STM32 PA10 12 nSS I/O J1 STM32 PA4 13 SCK I/O J1 STM32 PA5 14 MISO I/O J1 STM32 PA6 15 MOSI I/O J1 STM32 PA7 16 nHOST_INT I/O J1 STM32 PC4 17 VDD_3V Power J2 3V Source Pin 18 EZSP_nRTS2 I/O J2 STM32 PA1 19 EZSP_nCTS2 I/O J2 STM32 PA0-WKUP 20 EZSP_RXD2 I/O J2 STM32 PA3 21 EZSP_TXD2 I/O J2 STM32 PA2 22 TEMP_ENABLE I/O J2 STM32 PA8 (HGPIO7) 23 PC8 I/O J2 Spare STM32 GPIO (HGPIO6) 24 PC7 I/O J2 Spare STM32 GPIO (HGPIO5) 25 PIEZO I/O J2 STM32 PC6 (HGPIO4) 26 DF_SO I/O J2 STM32 PB14 (HGPIO15) 27 DF_SI I/O J2 STM32 PB15 (HGPIO14) 28 DF_SCK I/O J2 STM32 PB13 (HGPIO13) 29 DF_nCS I/O J2 STM32 PB12 (HGPIO12) 30 BUTTON1 I/O J2 STM32 PB11 (HGPIO3) 31 BUTTON0 I/O J2 STM32 PB10 (HGPIO2) 32 BTL I J2 Inverted and routed to STM32 BOOT0 33 NCP_nRESET I/O J2 STM32 PB0 34 nWAKE I/O J2 STM32PC5 35 NC N/A J2 Not connected 36 GND Power J2 Ground connection with respect to the STM32 2.3 JTAG Programming and Debug Connector (J3) The STM32 NCP Host module includes a 14-pin 0.1” dual-row header for JTAG programming and debug access. Figure 5 shows the pinout of this header. Note that the EM35x NCP Kit does not ship with a programmer that interfaces to this header. Third-party programmers may connect to this header. For example, the J-Link ARM 14- 6 Rev. 0.4 TS10 VDD_3V nJTRST JTDI JTMS-SWDIO JCLK-SWCLK JTDO J3 VDD_3V pin Adapter from SEGGER (http://www.segger.com/cms/jlink-adapters.html#14pinAdapter) may be connected directly to this header. GND GND GND GND GND 2 GND 1 14 nRESET 13 Figure 5. JTAG Connector Pinout (J3) 2.4 Unused STM32 GPIO (TP0-TP10) The STM32 NCP Host module routes all GPIO not routed to the mating connectors to test points TP0 through TP10. This allows the developer to utilize all STM32 GPIO for their application, if required. Table 4 lists these test points. Table 4. STM32 Unused GPIO Routed to Test Points Test Point Signal name Test Point Signal name TP0 VBAT TP6 PC9 TP1 PB1 TP7 PC10 TP2 PB2_BOOT1 TP8 PC11 TP3 PB5 TP9 PC12 TP4 PC2 TP10 PD2 TP5 PC3 3 STM32 NCP Host Module Schematic The STM32 NCP Host Module schematic is included at the end of this document. Rev. 0.4 7 4 3 2 1 B B EM35x NCP Host Module (STM32) Sheet 1 2 3 Details COVER SHEET STM32 MICRO, INTERFACE CONNECTORS REVISION NOTES A A Silicon Labs, 25 Thomson Place, Boston, MA 02110 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE REV A0 SCH0820 EM35X NCP HOST MODULE (STM32) COVER SHEET The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 3 2 DATE: SHEET: 19-09-2010_21:15 1 1 of 3 4 2 3 STM32 EZSP Host Micro EM35x EZSP Breakout Board Interface Connectors TEMP_ENABLE PC9 PC8 PC7 PIEZO DF_SI DF_SO DF_SCK DF_nCS SER_TXD1 SER_RXD1 SER_nCTS1 SER_nRTS1 JTMS-SWDIO J1 HEADER-16 Datasheet PB6 PB7 LED0 LED1 nRESET TEMP_SENSOR PC1 SER_nCTS1 SER_nRTS1 SER_TXD1 SER_RXD1 nSS SCK MISO MOSI nHOST_INT R3 DNI R2 10K VDD_1 VSS_1 PB11 PB10 PB2 PB1 PB0 PC5 PC4 PA7 PA6 PA5 PA4 VDD_4 VSS_4 PA3 R5 DNI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BUTTON1 BUTTON0 PB2_BOOT1 PB1 NCP_nRESET nWAKE nHOST_INT MOSI MISO SCK nSS R4 0_Ohm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R6 10K J2 HEADER-20 Datasheet VDD_3V PCB1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 710-0820-000 EZSP_nRTS2 EZSP_nCTS2 EZSP_RXD2 EZSP_TXD2 TEMP_ENABLE PC8 PC7 PIEZO DF_SO DF_SI DF_SCK DF_nCS BUTTON1 BUTTON0 BTL NCP_nRESET nWAKE J3 S-HEADER-14 EZSP_TXD2 EZSP_nRTS2 EZSP_nCTS2 PC3 PC2 PC1 TEMP_SENSOR nRESET OSC_OUT OSC_IN Y2 8MHZ 1 2 TP0 VBAT TP1 PB1 TP6 PC9 nJTRST TP2 PB2_BOOT1 TP7 PC10 JTDI TP3 PB5 TP8 PC11 JTMS-SWDIO TP4 PC2 TP9 PC12 JCLK-SWCLK TP5 PC3 TP10 PD2 VDD_3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OSC32_IN OSC32_OUT 1 FID1 Test Points - Unused IO Datasheet Datasheet B NC JTAG Connector Datasheet Fiducials EZSP_RXD2 VBAT PC13 Y1 ABS07-32.768KHZ-T SN1 130-0820-000 J1p35 - NC, can be used later as needed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD_3V U1 STM32F103RET6 Datasheet VDD_3V VDD_3V VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD_3V PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 VBAT PC13_TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 B 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 JCLK-SWCLK JTDI PC10 PC11 PC12 PD2 JTDO nJTRST PB5 PB6 PB7 BOOT0 LED0 LED1 PCB Information X1 HOST_INTERFACE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD_3V 1 JTDO nRESET 2 C4 C5 C6 C7 18PF 18PF 18PF 18PF A A Bootload Signal Inverter Power Supply Decoupling VDD_3V U2 74AUP1G04GW,125 NOTE: Place as close to noted U1 pins as possible VDD_3V VDD_3V R1 10K VDD_3V VDD_3V BTL C2 C1 C10 C9 C3 C11 C8 1UF 10NF 100NF 100NF 100NF 4.7UF 100NF Datasheet NC 1 VDD_3V 2 3 NC VDD_3V VCC Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com 5 A GND DWG Y 4 BOOT0 TITLE PAGE U1p12,13 (VDDA) U1p18,19 (VDD_4) U1p31,32 (VDD_1) U1p63,64 (VDD_3) The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation U1p47,48 (VDD_2) SIZE B 4 REV A0 SCH0820 EM35X NCP HOST MODULE (STM32) STM32 MICRO, INTERFACE CONNECTORS 3 2 DATE: SHEET: 19-09-2010_21:15 1 2 of 3 2 B 1 SCHEMATIC NOTES: PCB LAYOUT NOTES: -- Version P0 -*Released: 2010-06-11 *Initial version released, Version P0 (initial draft) -- Version P0 -*Released: 2010-06-11 *Initial version released, Version P0 (initial draft) -- Version P1 -*Released: 2010-08-03 *Changes from P0 to P1: 1) Swapped UART1 with UART2 on X1 (J1, J2). 2) Changed R2 from 0 ohm to 10k ohm. 3) Changed R6 from DNI to 10k ohm. 4) Changed U1.27 net connection from BTL to PB1. 5) Change TP1 to TP0 for VBAT net. 6) Added TP1 for PB1 net. 7) Added inverter IC U2 for inverting BTL net for connection to BOOT0 net. -- Version P1 -*Released: 2010-08-03 *Changes from P0 to P1: 1) Added Inverter IC U2. 2) Re-routed UART1 and UART2 nets. 3) Added missing test points from P0 version. -- Version A0 -*Released: 2010-09-20 *Changes from P1 to A0: *Production version release 1) All schematic notes reflected in layout. -- Version A0 -*Released: 2010-09-20 *Production version release *Changes from P1 to A0: 1) Removed DS1 and R1 for lowest current capability. 2) Renamed UART1 nets to SER_TXD1, etc. 3) Renamed UART2 nets to EZSP_TXD1, etc. 4) Added 10k pull-up R7 to U2 BTL net. 5) Updated title from EZSP to NCP. 6) Corrected DF_SO/_SI error at X1 J2p26/27 (reversed). 7) Removed Packet Trace Port connector footprint J4. 8) Replaced J3 with 14-pin 0.1" JTAG connector. B A A Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE REV A0 SCH0820 EM35X NCP HOST MODULE (STM32) REVISION NOTES The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE A 2 DATE: SHEET: 19-09-2010_21:15 1 3 of 3 TS10 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page for ZigBee products: www.silabs.com/zigbee-support and register to submit a technical support request Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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