Data Sheet

DF
N1
01
0B
-6
PMDXB950UPE
20 V, dual P-channel Trench MOSFET
30 June 2015
Product data sheet
1. General description
Dual P-channel enhancement mode Field-Effect Transistor (FET) in a leadless ultra small
DFN1010B-6 (SOT1216) Surface-Mounted Device (SMD) plastic package using Trench
MOSFET technology.
2. Features and benefits
•
•
•
•
•
Trench MOSFET technology
Leadless ultra small and ultra thin SMD plastic package: 1.1 × 1.0 × 0.37 mm
Exposed drain pad for excellent thermal conduction
ElectroStatic Discharge (ESD) protection > 1 kV HBM
Drain-source on-state resistance RDSon = 1.02 Ω
3. Applications
•
•
•
•
Relay driver
High-speed line driver
High-side load switch
Switching circuits
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj = 25 °C
-
-
-20
V
VGS
gate-source voltage
-8
-
8
V
ID
drain current
-
-
-500
mA
-
1.02
1.4
Ω
Per transistor
VGS = -4.5 V; Tamb = 25 °C
[1]
Static characteristics (per transistor)
RDSon
drain-source on-state
resistance
[1]
VGS = -4.5 V; ID = -500 mA; Tj = 25 °C
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for
2
drain 1 cm .
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PMDXB950UPE
NXP Semiconductors
20 V, dual P-channel Trench MOSFET
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
S1
Simplified outline
Graphic symbol
source TR1
D1
1
2
G1
gate TR1
3
D2
drain TR2
4
S2
source TR2
5
G2
gate TR2
6
D1
drain TR1
Transparent top view
7
D1
drain TR1
DFN1010B-6 (SOT1216)
8
D2
drain TR2
7
2
3
G1
5
8
D2
6
G2
4
S1
S2
017aaa260
6. Ordering information
Table 3.
Ordering information
Type number
Package
PMDXB950UPE
Name
Description
Version
DFN1010B-6
DFN1010B-6: plastic thermal enhanced ultra thin small outline
package; no leads; 6 terminals
SOT1216
7. Marking
Table 4.
Marking codes
Type number
Marking code
PMDXB950UPE
10 10 00
MARKING CODE
(EXAMPLE)
READING
DIRECTION
MARK-FREE AREA
PIN 1
INDICATION MARK
READING EXAMPLE:
YEAR DATE
CODE
11
01
10
Fig. 1.
aaa-007665
DFN1010B-6 (SOT1216) binary marking code description
PMDXB950UPE
Product data sheet
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20 V, dual P-channel Trench MOSFET
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj = 25 °C
-
-20
V
VGS
gate-source voltage
-8
8
V
ID
drain current
Per transistor
VGS = -4.5 V; Tamb = 25 °C
[1]
-
-500
mA
VGS = -4.5 V; Tamb = 100 °C
[1]
-
-300
mA
-
-2
A
[2]
-
265
mW
[1]
-
380
mW
-
4025
mW
-
-350
mA
IDM
peak drain current
Tamb = 25 °C; single pulse; tp ≤ 10 µs
Ptot
total power dissipation
Tamb = 25 °C
Tsp = 25 °C
Source-drain diode
IS
source current
Tamb = 25 °C
[1]
Per device
Tj
junction temperature
-55
150
°C
Tamb
ambient temperature
-55
150
°C
Tstg
storage temperature
-65
150
°C
PMDXB950UPE
Product data sheet
[1]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for
[2]
drain 1 cm .
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
2
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NXP Semiconductors
20 V, dual P-channel Trench MOSFET
017aaa123
120
017aaa124
120
Pder
(%)
Ider
(%)
80
80
40
40
0
- 75
Fig. 2.
- 25
25
75
125
Tj (°C)
0
- 75
175
Normalized total power dissipation as a
function of junction temperature
Fig. 3.
- 25
25
75
125
Tj (°C)
175
Normalized continuous drain current as a
function of junction temperature
aaa-006901
-10
ID
(A)
Limit RDSon = VDS/ID
tp =
10 µs
-1
100 µs
1 ms
-10-1
DC; Tsp = 25 °C
10 ms
DC; Tamb = 25 °C;
drain mounting pad 1 cm2
-10-2
-10-1
-1
100 ms
-10
-102
VDS (V)
IDM = single pulse
Fig. 4.
Safe operating area; junction to ambient; continuous and peak drain currents as a function of drainsource voltage
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
thermal resistance
from junction to
ambient
in free air
Min
Typ
Max
Unit
[1]
-
410
475
K/W
[2]
-
285
330
K/W
Per transistor
Rth(j-a)
PMDXB950UPE
Product data sheet
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20 V, dual P-channel Trench MOSFET
Symbol
Parameter
Rth(j-sp)
thermal resistance
from junction to solder
point
[1]
[2]
Conditions
Min
Typ
Max
Unit
-
27
31
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
2
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm .
aaa-006902
103
duty cycle = 1
Zth(j-a)
(K/W)
0.75
0.5
102
0.25
0.33
0.2
0.1
0.05
0
0.02
0.01
10
10-3
10-2
10-1
1
10
102
tp (s)
103
FR4 PCB, standard footprint
Fig. 5.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-006903
103
Zth(j-a)
(K/W)
duty cycle = 1
0.75
0.5
102
0.25
0.33
0.2
0.1
0.05
0
10
10-3
0.02
0.01
10-2
10-1
FR4 PCB, mounting pad for drain 1 cm
Fig. 6.
1
10
102
tp (s)
103
2
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PMDXB950UPE
Product data sheet
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20 V, dual P-channel Trench MOSFET
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics (per transistor)
V(BR)DSS
drain-source
breakdown voltage
ID = -250 µA; VGS = 0 V; Tj = 25 °C
-20
-
-
V
VGSth
gate-source threshold
voltage
ID = -250 µA; VDS = VGS; Tj = 25 °C
-0.45
-0.7
-0.95
V
IDSS
drain leakage current
VDS = -20 V; VGS = 0 V; Tj = 25 °C
-
-
-1
µA
VDS = -20 V; VGS = 0 V; Tj = 150 °C
-
-
-10
µA
VGS = 8 V; VDS = 0 V; Tj = 25 °C
-
-
10
µA
VGS = -8 V; VDS = 0 V; Tj = 25 °C
-
-
-10
µA
VGS = 4.5 V; VDS = 0 V; Tj = 25 °C
-
-
1
µA
VGS = -4.5 V; VDS = 0 V; Tj = 25 °C
-
-
-1
µA
VGS = -4.5 V; ID = -500 mA; Tj = 25 °C
-
1.02
1.4
Ω
VGS = -4.5 V; ID = -500 mA; Tj = 150 °C
-
1.54
2.1
Ω
VGS = -2.5 V; ID = -200 mA; Tj = 25 °C
-
1.27
2.2
Ω
VGS = -1.8 V; ID = -40 mA; Tj = 25 °C
-
1.7
3.3
Ω
VGS = -1.5 V; ID = -10 mA; Tj = 25 °C
-
2.3
5
Ω
VGS = -1.2 V; ID = -1 mA; Tj = 25 °C
-
3.5
-
Ω
VDS = -10 V; ID = -500 mA; Tj = 25 °C
-
480
-
mS
IGSS
RDSon
gfs
gate leakage current
drain-source on-state
resistance
forward
transconductance
Dynamic characteristics (per transistor)
QG(tot)
total gate charge
VDS = -10 V; ID = -450 mA;
-
1.19
2.1
nC
QGS
gate-source charge
VGS = -4.5 V; Tj = 25 °C
-
0.17
-
nC
QGD
gate-drain charge
-
0.1
-
nC
Ciss
input capacitance
VDS = -10 V; f = 1 MHz; VGS = 0 V;
-
43
-
pF
Coss
output capacitance
Tj = 25 °C
-
14
-
pF
Crss
reverse transfer
capacitance
-
8
-
pF
td(on)
turn-on delay time
VDS = -10 V; ID = -0.45 A; RL = 22 Ω;
-
2.3
-
ns
tr
rise time
VGS = -4.5 V; RG(ext) = 6 Ω; Tj = 25 °C
-
5
-
ns
td(off)
turn-off delay time
-
13.5
-
ns
tf
fall time
-
6
-
ns
-
-0.7
-1.2
V
Source-drain diode (per transistor)
VSD
source-drain voltage
PMDXB950UPE
Product data sheet
IS = -115 mA; VGS = 0 V; Tj = 25 °C
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NXP Semiconductors
20 V, dual P-channel Trench MOSFET
aaa-006904
-2.0
VGS = -4.5 V
ID
(A)
aaa-006905
-10-2
ID
(A)
-3.5 V
-1.5
-10-3
-3 V
min
-1.0
-2.5 V
-10-4
-0.5
-1.8 V
-10-5
typ
max
-1.2 V
0.0
Fig. 7.
0
-1
-2
-3
VDS (V)
-10-6
0.0
-4
-0.5
-1.0
VGS (V)
-1.5
Tj = 25 °C
Tj = 25 °C; VDS = -5 V
Output characteristics: drain current as a
Fig. 8.
function of drain-source voltage; typical values
Sub-threshold drain current as a function of
gate-source voltage
aaa-006906
2.0
RDSon
(Ω)
-1.8 V
-2.2 V
aaa-006907
5
RDSon
(Ω)
-2.5 V
4
1.5
-3 V
3
-3.5 V
1.0
VGS = -4.5 V
2
0.5
0.0
0.0
1
-0.5
-1.0
-1.5
ID (V)
0
-2.0
Tj = 25 °C
Fig. 9.
Product data sheet
Tj = 25 °C
0
-1
-2
-3
-4
VGS (V)
-5
ID = -0.5 A
Drain-source on-state resistance as a function
of drain current; typical values
PMDXB950UPE
Tj = 150 °C
Fig. 10. Drain-source on-state resistance as a function
of gate-source voltage; typical values
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NXP Semiconductors
20 V, dual P-channel Trench MOSFET
aaa-006908
-1.00
aaa-006909
1.50
ID
(A)
a
Tj = 25 °C
-0.75
Tj = 150 °C
1.25
-0.50
1.00
-0.25
0.75
0.00
0
-1
-2
-3
VGS (V)
0.50
-60
-4
VDS > ID × RDSon
Fig. 11. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
60
120
Tj (°C)
180
Fig. 12. Normalized drain-source on-state resistance
as a function of junction temperature; typical
values
aaa-006910
-1.5
0
aaa-006911
102
Ciss
VGS(th)
(V)
C
(pF)
-1.0
Coss
max
10
typ
Crss
-0.5
min
0.0
-60
0
60
120
Tj (°C)
1
-10-1
180
ID = -0.25 mA; VDS = VGS
Product data sheet
-10
VDS (V)
-102
f = 1 MHz; VGS = 0 V
Fig. 13. Gate-source threshold voltage as a function of
junction temperature
PMDXB950UPE
-1
Fig. 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
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NXP Semiconductors
20 V, dual P-channel Trench MOSFET
aaa-016469
-5
VDS
VGS
(V)
ID
-4
VGS(pl)
-3
VGS(th)
VGS
-2
QGS1
QGS2
QGS
-1
QGD
QG(tot)
017aaa137
0
0
0.2
0.4
QG (nC)
Fig. 16. MOSFET transistor: Gate charge waveform
definitions
0.6
ID = -0.5 A; VDS = -10 V; Tamb = 25 °C
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
aaa-006913
-2.0
IS
(A)
-1.5
-1.0
Tj = 150 °C
-0.5
0.0
0.0
-0.5
Tj = 25 °C
-1.0
-1.5
VSD (V)
-2.0
VGS = 0 V
Fig. 17. Source current as a function of source-drain voltage; typical values
11. Test information
P
t2
duty cycle δ =
t1
t2
t1
t
006aaa812
Fig. 18. Duty cycle definition
PMDXB950UPE
Product data sheet
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20 V, dual P-channel Trench MOSFET
12. Package outline
0.35
0.35
0.15
0.23
1
2
0.125
0.205
0.22
0.30
0.95
1.05
6
0.04
max
3
0.34
0.40
Dimensions in mm
5
4
0.32
0.40
0.275 0.275
1.05
1.15
13-03-05
Fig. 19. Package outline DFN1010B-6 (SOT1216)
PMDXB950UPE
Product data sheet
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20 V, dual P-channel Trench MOSFET
13. Soldering
Footprint information for reflow soldering of DFN1010B-6 package
SOT1216
0.9
0.35
0.35
0.15 0.2 (6x) 0.15
1.3
1.2
0.35
0.25
0.5
0.6
0.35
0.25
1.1
0.3 (6x)
1
1.35
solder land
solder land plus solder paste
occupied area
solder resist
Dimensions in mm
Issue date
13-03-06
14-07-28
sot1216_fr
Fig. 20. Reflow soldering footprint for DFN1010B-6 (SOT1216)
PMDXB950UPE
Product data sheet
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20 V, dual P-channel Trench MOSFET
14. Revision history
Table 8.
Revision history
Data sheet ID
Release date
Data sheet status
Change notice
Supersedes
PMDXB950UPE v.2
20150630
Product data sheet
-
PMDXB950UPE v.1
Modification:
•
PMDXB950UPE v.1
20130910
-
-
PMDXB950UPE
Product data sheet
Change of binary marking code position.
Product data sheet
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20 V, dual P-channel Trench MOSFET
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or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Right to make changes — NXP Semiconductors reserves the right to
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limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Please consult the most recently issued document before initiating or
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PMDXB950UPE
Product data sheet
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the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
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automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip,
HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE,
MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP
Semiconductors N.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PMDXB950UPE
Product data sheet
All information provided in this document is subject to legal disclaimers.
30 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved
14 / 15
PMDXB950UPE
NXP Semiconductors
20 V, dual P-channel Trench MOSFET
16. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 2
8
Limiting values .......................................................3
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 6
11
Test information ..................................................... 9
12
Package outline ................................................... 10
13
Soldering .............................................................. 11
14
Revision history ................................................... 12
15
15.1
15.2
15.3
15.4
Legal information .................................................13
Data sheet status ............................................... 13
Definitions ...........................................................13
Disclaimers .........................................................13
Trademarks ........................................................ 14
© NXP Semiconductors N.V. 2015. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 30 June 2015
PMDXB950UPE
Product data sheet
All information provided in this document is subject to legal disclaimers.
30 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved
15 / 15