dm00245237

UM1977
User manual
STEVAL-IME013V1 evaluation board based on the STHV800
ultrasound pulser
Introduction
The STEVAL-IME013V1 is an evaluation board designed around the STHV800 ultrasound pulser IC, a
state of the art device for ultrasound imaging applications. The system can drive eight transducers as 8channel transmitters and display the output waveforms directly on an oscilloscope by connecting the
scope probe on the relative BNCs. Four preset waveforms are available to test the HV pulser under
different conditions. It is also possible to change these preset waveforms via a PC GUI (see STSWIME011 on www.st.com ).
Figure 1: STEVAL-IME013V1 evaluation board
December 2015
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www.st.com
Contents
UM1977
Contents
1
Board features ................................................................................. 3
2
Getting starting ................................................................................ 4
3
Hardware layout and configuration ................................................ 5
4
3.1
Power supply..................................................................................... 5
3.2
MCU .................................................................................................. 6
3.3
Stored patterns.................................................................................. 8
3.4
STHV800 stage ............................................................................... 17
3.5
Operating supply conditions ............................................................ 18
Connectors .................................................................................... 19
4.1
Power supply................................................................................... 19
4.2
Power-up sequence ........................................................................ 20
4.3
MCU ................................................................................................ 20
5
Schematic ...................................................................................... 22
6
Revision history ............................................................................ 23
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1
Board features
Board features










Suitable for ultrasound imaging applications
8 monolithic channels, 3 level high voltage pulser
Integrated T/R switch
On-board equivalent piezoelectric load implemented through an R/C equivalent
network
USB interface is available to upload customized output waveforms
Built in microcontroller Flash memory available for storing customized waveforms
High voltage screw connectors to power the STHV800
Automatic lockout overvoltage protection
7 LEDs to check EVAL BOARD status and proper operation
Human machine interface to select, start and stop the stored output waveforms
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Getting starting
2
UM1977
Getting starting
The STEVAL-IME013V1 is shipped by STMicroelectronics ready to use. The user only has
to:
1.
2.
3.
4.
5.
6.
7.
8.
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Plug the right power supply to the board (see Section 2: "Board features" for further
details)
Connect the BNC to the oscilloscope to visualize the generated waveforms once you
start the program
Check that the LED PROGRAM 1 (L1) turns on
Select the waveform with the program button. The corresponding program LED (L1L4) turns on
Press the start button to run the selected program, the start LED L5 turns on. After
program ends, the microcontroller returns to the idle state (LED L5 is off)
If a continuous wave program is selected, only the stop can halt program execution.
The microcontroller returns to the idle state and the STOP LED (L5) turns off
To run the same program again, restart from step 5. To run another program, restart
from step 4
Overvoltage protection will suspend pattern generation and the red LED L6 switch on
if the HV supply exceeds 90 V. Pattern generation will restart after the HV supply
voltage drops back into the allowed range.
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3
Hardware layout and configuration
Hardware layout and configuration
The STEVAL-IME013V1 evaluation board is designed around the STHV800. The hardware
block diagram ( Figure 2 ) illustrates the main connection between STHV800 and the
STM32F4. Figure 3: "STEVAL-IME013V1 board layout" can help you to locate connectors,
LEDs and features on the board.
Figure 2: Hardware block diagram
Figure 3: STEVAL-IME013V1 board layout
3.1
Power supply
The low voltage block of the STEVAL-IME013V1 board is designed to be powered:


during programming and when the board is connected to the PC:

5 V DC through USB Mini B connector to supply the STM32F4
during pattern generation and when high voltage is powered on:

5 V DC connected to VDD to supply STM32F4 and STHV800 through an LDO

-5 V DC connected to VSS to supply STHV800 through an LDO
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Hardware layout and configuration
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the USB link must be removed when high voltage is connected to the board
The high voltage block of the STEVAL-IME013V1 is designed to be powered by:








VDD: Positive supply voltage, 5 V (2 - VDD conn.)
GND: Ground (1 – VDD conn. And 2 – VSS conn.)
VSS: Negative supply voltage -5 V (1 - VSS conn.)
HVM: TX high voltage negative supply
HVM_CW: Continuous high voltage negative supply
GND: Ground
HVP_CW: Continuous high voltage positive supply
HVP: TX High voltage positive supply
Figure 4: STEVAL-IME013V1 board connections
3.2
MCU
The STM32F427 is fully dedicated to generate the bitstream on its GPIO pins to drive the
pulser output channels. It is pre-programmed as a DFU (device firmware upgrade) device
to upgrade internal FLASH memory. The STM32F427 manages all the DFU operations,
such as the authentication of product identifier, vendor identifier and Firmware version.
The MCU drives the pulser channels through the use of different General Purpose I/O
(GPIO) pins. You can simulataneously drive 1 to 16 different pins by simply writing a 16-bit
word in the GPIO Output Data Register (ODR). The board can be connected to a PC
through via USB and the required pattern can be transmitted as a sequence of states for
each pulser channel and of durations for each state. Here, all the durations are expressed
in units of MCU system clock cycles. Once the information is received, the channel states
are converted into 16-bit words for the GPIO peripheral and they are stored in the
embedded Flash, together with the timing information.
Once programmed, the PC connection is no longer required as the board can act as a
stand-alone device. Different patterns can be stored selected for use at run-time.
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Hardware layout and configuration
The same MCU can perform two different solutions to ensure real-time execution.
The first solution involves the use of the STM32 Direct Memory Access (DMA) peripheral.
The DMA is able to transfer data from memory to any peripheral register, GPIO included,
without taking into account the MCU core. To trigger the DMA transfer, a general purpose
TIMER is used. The timer works at the system clock frequency, basically acting as a
counter, and the reload value (the value at which the counter returns to zero) is stored in
the Auto Reload Register (ARR).
The timer triggers two different DMA channels in two different moments:
1.
2.
the first channel is triggered at each reload event
the second is triggered at a constant time after reload.
Once the first trigger is received, the first channel transfers the new GPIO word into the
ODR. At the second trigger, the second channel transfers the new duration information into
the ARR. The timer preload feature is enabled, so that the new ARR value is effective only
at the next reload. Since the time needed by the first DMA channel to update the ODR is a
constant, considering the reload trigger as the starting point, the time that elapses between
two different GPIO updates is simply given by the ARR value.
The Circular buffer feature of the DMA can be enabled to allow the automatic regeneration
of the same pattern at each end.
This solution has the advantage of being fully managed by hardware and the MCU core
remains free to handle user tasks. The main drawback is that each timing value between
two subsequent states cannot be lower than a minimum value in order to guarantee
enough time for both the two DMA channels to perform their transfers.
Figure 5: Solution 1
The second solution is designed to overcome the minimum duration requirement of the
DMA solution and involves the MCU core directly.
During run-time, the core generates the binary assembly code it needs to load and store
each word in the ODR. Unnecessary instructions like control loops are avoided, so the
code is simply a succession of simple load/store instructions. To adapt the timing to the
pattern needs, dummy instructions are inserted in the assembly code.
To avoid wasting time to load each word from memory, the word is inserted as a literal in
the assembly instruction itself. This means that a 32-bit instruction is needed instead of a
16-bit equivalent. In order to avoid any latency due to the instruction fetch from Flash, the
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code is executed from the embedded RAM. Moreover, the RAM is configured to be
accessed by the core through a different bus from the bus used to access the ODR.
These solutions render it possible to achieve a minimum two system clock cycle time
before two updates and still maintain a one system clock cycle resolution. For instance, if
you consider a STM32F4 clocked at 168 MHz, the minimum timing you can achieve is 12
ns and you can set the duration of each state with a resolution of 6 ns.
For a repetitive pattern, a branch instruction is added at the end of the routine to restart the
pattern generation. In this case, the clock cycles needed for the branch instruction must be
considered for the last state.
The main drawback of this solution is that the MCU core is 100% occupied by the pattern
generation, even if it can be still called by peripheral interrupts to stop the pattern
generation to perform other tasks.
Figure 6: Solution 2
3.3
Stored patterns
STEVAL-IME013V1 can store four patterns in the MCU Flash memory in order to show the
achievable performance at the pulser outputs. Four selectable patterns are already stored
in the STM32 Flash memory as the default, ready-to-use set. A detailed description of the
programs settings is listed below.
Program 1, CW=0
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Hardware layout and configuration
Table 1: Program 1
PW 5 pulses - HV=±60 V; Load: 270 pF//100 Ω
Mode
Freq. (MHz)
No of pulses
Initial pulse
H-Bridge
PRF
Ch 1
PW
2.5
5
Negative
TX
150 µs
Ch 2
PW
2.5
5
Positive
TX
150 µs
Ch 3
PW
5
5
Negative
TX
150 µs
Ch 4
PW
5
5
Positive
TX
150 µs
Ch 5
PW
2.5
5
Negative
TX
150 µs
Ch 6
PW
2.5
5
Positive
TX
150 µs
Ch 7
PW
5
5
Negative
TX
150 µs
Ch 8
PW
5
5
Positive
TX
150 µs


XDCR_1, XDCR_2, XDCR_5, XDCR_6: Pulse Wave mode, TX switching, 5 pulses,
time-period TP=400 ns and PRF=150 µs
XDCR_3, XDCR_4, XDCR_7, XDCR_8: Pulse Wave mode, TX switching, 5 pulses,
time-period TP=200 ns and PRF=150 µs
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Figure 7: Acquisition by program 1
Program 2 CW=0


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XDCR_1, XDCR_2, XDCR_5, XDCR_6: Pulse Wave mode, TX switching, 5 pulses,
time-period TP=200 ns and PRF=150 µs
XDCR_3, XDCR_4, XDCR_7, XDCR_8: Pulse Wave mode, TX switching, 5 pulses,
time-period TP=100 ns and PRF=150 µs
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Hardware layout and configuration
Table 2: Program 2
PW 5 pulses - HV=±60 V; Load: 270 pF//100 Ω
Mode
Freq. (MHz)
No. of pulses
Initial pulse
H-Bridge
PRF
Ch 1
PW
5
5
Negative
TX
150 µs
Ch 2
PW
5
5
Positive
TX
150 µs
Ch 3
PW
10
5
Negative
TX
150 µs
Ch 4
PW
10
5
Positive
TX
150 µs
Ch 5
PW
5
5
Negative
TX
150 µs
Ch 6
PW
5
5
Positive
TX
150 µs
Ch 7
PW
10
5
Negative
TX
150 µs
Ch 8
PW
10
5
Positive
TX
150 µs
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Figure 8: Acquisition by program 2
Program 3


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XDCR_1, XDCR_2, XDCR_5, XDCR_6: Continuous Wave mode, TX-CW switching,
time-period TP=400 ns
XDCR_3, XDCR_4, XDCR_7, XDCR_8: Continuous Wave mode, TX-CW switching,
time-period TP=200 ns
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Hardware layout and configuration
Table 3: Program 3
Continuous Wave – HV_CW=±10V; Load: 270 pF//100 Ω
Mode
Freq. (MHz)
No. of pulses
Initial pulse
H-Bridge
Ch 1
CW
2.5
Continuous wave
Positive
TX-CW
Ch 2
CW
2.5
Continuous wave
Negative
TX-CW
Ch 3
CW
5
Continuous wave
Positive
TX-CW
Ch 4
CW
5
Continuous wave
Negative
TX-CW
Ch 5
CW
2.5
Continuous wave
Positive
TX-CW
Ch 6
CW
2.5
Continuous wave
Negative
TX-CW
Ch 7
CW
5
Continuous wave
Positive
TX-CW
Ch 8
CW
5
Continuous wave
Negative
TX-CW
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Hardware layout and configuration
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Figure 9: Acquisition by program 3
Program 4 CW=0


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XDCR_1, XDCR_2, XDCR_5, XDCR_6: Pulse Wave mode, TX0 switching, 1.5
pulses, time-period TP=400ns and consequently TX1 switching, 5 pulses, timeperiod=200 ns and PRF=150 µs
XDCR_3, XDCR_4, XDCR_7, XDCR_8: Pulse Wave mode, TX0 switching, 1.5
pulses, time-period TP=200ns and consequently TX1 switching, 5 pulses, timeperiod=200 ns and PRF=150 µs.
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Hardware layout and configuration
Table 4: Program 4
PW - HV=±60 V; Load: 270 pF//100 Ω
Mode
Freq. (MHz)
No. of pulses
Initial pulse
H-Bridge
PRF
Ch 1
PW
2.5 - 5
3 half pulse then 4 pulse
Positive
TX
150 µs
Ch 2
PW
2.5 - 5
3 half pulse then 4 pulse
Negative
TX
150 µs
Ch 3
PW
5
3 half pulse then 4 pulse
Positive
TX
150 µs
Ch 4
PW
5
3 half pulse then 4 pulse
Negative
TX
150 µs
Ch 5
PW
2.5 - 5
3 half pulse then 4 pulse
Positive
TX
150 µs
Ch 6
PW
2.5 - 5
3 half pulse then 4 pulse
Negative
TX
150 µs
Ch 7
PW
5
3 half pulse then 4 pulse
Positive
TX
150 µs
Ch 8
PW
5
3 half pulse then 4 pulse
Negative
TX
150 µs
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Hardware layout and configuration
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Figure 10: Acquisition by Program 4
The board can be connected to a PC via USB cable and patterns can be edited through a
user inetrface.
Remove the USB link when the high voltage is connected to the board.
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3.4
Hardware layout and configuration
STHV800 stage
The STHV800 high-voltage, high-speed pulser generator features eight independent
channels. It is designed for medical ultrasound applications, but can also be used for other
piezoelectric, capacitive or MEMS transducers. The device contains a controller logic
interface circuit, level translators, MOSFET gate drivers, noise blocking diodes and highpower P-channel and N-channel MOSFETs as output stages for each channel. It also
includes clamping-to-ground circuitry, anti-leakage, an anti-memory effect block, a thermal
sensor and a HV receiver switch (HVR_SW) that ensures strong decoupling during the
transmission phase. The STHV800 also features self-biasing and thermal shutdown blocks.
Figure 11: STHV800 single channel block diagram
Each channel can support up to three active output levels with one half-bridge. Each
channel consists of two supplied output stages for pulsed wave (PW) and continuous wave
(CW) operations. The PW output stage is able to provide up to ±2 A peak output current
while, to reduce power dissipation and jitter during continuous wave mode, the fully
optimized CW output stage delivers up to ±0.3 A.
For further information, please refer to the STHV800 datasheet.
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Hardware layout and configuration
3.5
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Operating supply conditions
Table 5: DC working supply conditions
Operating supply voltage
Symbol
Parameter
Min.
Typ.
Max.
Value
VDD
Positive supply voltage
5
6
10
V
VSS
Negative supply voltage
-5
6
-10
V
HVP
TX high voltage positive supply
95
V
HVM
TX high voltage negative supply
HVP_CW
CW high voltage positive supply
HVM_CW
CW high voltage negative supply
-95
V
95
-95
V
V
While HVM / HVM_CW and HVP / HVP_CW are fully independent on the board,
the relationships HVM_CW ≥ HVM and HVP_CW ≤ HVP must be respected
during operation.
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Connectors
4
Connectors
4.1
Power supply
The STEVAL-IME013V1 board must be powered through the screw connectors shown in
following figures.
Figure 12: Power supply connector VDD (+5 V - GND)
Figure 13: Power supply connector VSS (GND - -5 V)
Figure 14: Power supply connector HVP – HVP_CW and HVM – HVM_CW
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Connectors
4.2
UM1977
Power-up sequence
1
VDD
2
VSS
The only recommendation for powering up the board is for low voltages as shown in above.
Other voltages are fully power-up/power-down free, so there is no recommended sequence
to follow.
4.3
MCU
Figure 15: USB mini-B connector (CN1)
Table 6: USB mini B connector pin out
PIN number
Description
1
VBUS (power)
2
DM (STM32 PA11)
3
DP (STM32 PA12)
4
N.C.
5
Ground
Figure 16: JTAG connector
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Connectors
Figure 17: Boot connector
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L1
L2
L3
RL2
56
L2
L4
RL3
56
L3
L5
5
4
UF1
DVDD
BA T20J
D2
L6
RL6
56
L6
USBDM
USBDP
+5V
DVDD
RF4
107k
RF3
62k
RF2
62k
RF1
107k
8M H z
1M
Cosc1
22pF
22pF
C osc 2
X1
V D D1
VDD2
VDD3
VDD 4
VDD5
VDDA
VREF+
O S C_IN
OSC_OUT
NRST
BOO T
VSSA
VSS3
VSS1
NC
VREFV S S2
VSS4
VSS5
100nF
100nF
100nF
100nF
100nF
SPI3_MISO
SPI2_MISO
SPI1_MISO
CB4
CB3
CB2
100nF
CB11
AVSS
CB8
CB7
AN_SUPPLY
OSC_IN
AV SS
C F6
10F
C F5
10F
Rosc
OSC_OUT
1 0n F
CC2
1 0n F
CC1
USBUF01W 6
1
D4 VDD D1
3
D3 GND D2
RL5
56
L5
36
24
1
USB_PW R
CF4
10 F
-5V
LT3032
SHD
INP OUTP
10,12
3
SHD BYPP
2
ADJP
8
AD J N
CF3 4,5
11
GND BYPN
10 F
INN O UTN
RL4
56
L4
GND
1734035-1
Shell
ID
D+
D-
VBUS
USB
REG2
50
75
DVDD
100
28
BOOT0
11
22
21
R1_F2 R2_F2_F4
12
OSC_IN
0
0
OSC_OUT 13
14
NR S T
94
19
99
49
R1_F1_F4
C1_F2_F4
73
R2_F1 R3_F1
20
2_F
4
C
2_F
0
0
0
74
27
10
2.2F
2 . 2F
RL1
56
L1
-5V
R18 330
LVLV+
VSS
LV+
LV-
VDD
14
6,9
5
2
D1
BAT20J
1
7
+5V
ADC_IN0
ADC_IN1
ADC_IN2
C F1
10F
SPI_CLK
CF2
10F
SPI_JTAG_1
CB1
100nF
SPI_CLK
SPI1_MISO
AVD D
SPI3
SPI2
SPI1
100nF
CB5
STM32F427
U1
VBAT
PC0
PC 1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC 1 1
P C 12
PC13
P C 14
PC15
RTHSD
10k
T HSD
RSHD
33 0
SHD
CW
6
15 PC0
16 PC1
17 PC2
18 P C3
33 P C 4
34 PC5
63 PC6
64 PC7
65 PC8
66 PC9
78P C 10
79PC11
80PC12
7 PC13
8 PC14
9 PC15
CW
PC10
PC11
100nF
CB6
DVDD
SPI_CLK
SPI2_MISO
AVDD
L5
L6
DVDD
USBDP
USBDM
JTMS
JTCK
JTDI
23
24
25
26
29
30
31
32
67
68
69
70
71
72
76
77
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PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
JTDO
SPI_CLK
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
JRST
SPI3_MISO
97
98
1
2
3
4
5
38
39
40
41
42
43
44
45
46
SPI_JTAG_2
35
36
37
89
90
91
92
93
95
96
47
48
51
52
53
54
PC7
PC6
PC0
PC1
PC2
PC3
PC4
PC5
PC1 0
PC11
PC12
PC 1 3
PC14
PC15
PC9
PC8
AVDD
55 %
POT1
AVSS
100nF
CP1
STR
100nF
CP2
P2
PRG
100nF
CP3
P3
STP
RAD4
2.7k
CAD2
100nF
RAD3
100k
HVP_CW
RP3
10k
ADC_IN2
ZAD2
100nF
CP4
RE 0
56
RE1
56
RE2
56
RE3
56
R E4
56
RE5
56
RE6
56
RE7
56
RLD
100
RLC
100
USR
100
100nF
CRST
220nF
CB22
220nF
2 2 0nF
CB21
220nF
2 2 0n F
CB20
220nF
2 2 0 nF
CB19
220nF
HVM_CW
10F
CF12
10F
220nF
CB24
220nF
J TA G
CF11
H V+
HV-
H VM
GND_PW R
HV+
HV-
HVP
LVOUT1
HV+
HV-
HVM_CW
GND_PW R
HV+
HV-
HVP_CW
10F
CF8
10F
CF7
100
CB23
HVP_CW
CB17
CB16
CR2
270pF
RR2
XDCR8
XDCR7
XDCR6
XDCR5
GND_PW R
XDCR4
XDCR3
XDCR2
XDCR1
CB15
LVOUT8
GND_PW R
0
R GND
CB14
RST
220nF
CB18
2 2 0nF
CB13
NRST
H VM
HV P
CR1
270pF
RR1
RLH
100
RLG
100
RLF
100
270pF
27 0 pF
2 70pF
27 0p F
RLE
100
CLH
CLG
CLF
CLE
RLB
100
270pF
270pF
RLA
100
CLD
CLC
270pF
HVP
CLB
0
R H VP
HVP_CW
270pF
HVM
CLA
DVDD
P4
RP4
10k
15,20,51,56
52
53
54
55
16
17
18
19
1
2
3
4
11
12
13
14
ADC_IN1
USR_RX
DZ2S033
RP2
10k
ADC _IN0
P1
RP 1
10k
100nF
CAD1
DVDD
GND_PW R
LVOUT_1
LVOUT_2
LVOUT_3
LVOUT_4
L V O UT _ 5
LVOUT_6
LVOUT_7
L V O UT _ 8
XDCR_1
XDCR_2
XD CR_3
XDCR_4
XDCR_5
XDCR_6
XDCR_7
XDCR_8
0
RHVM
HVM_CW
A U X 0 AUX1 AUX2 AUX 3 AUX4 A UX5 A UX6 AU X 7
RAD2
100k
U2
STHV800
ZAD1
DZ2S033
IN1_0
IN1_1
IN 2 _0
IN2_1
IN3_0
IN3_1
IN4_0
IN4_1
IN5_0
IN5_1
IN6_0
IN6_1
IN7_0
IN7_1
IN8_0
IN8_1
CW
THSD
CK
RAD1
2 . 7k
43
44
45
46
47
48
49
50
21
22
23
24
25
26
27
28
41
29
42
AV DD
HVM_CW
PC
THSD
CW
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
33,34,35,36,37
HVP
38 HVP_CW
HVM_CW
HVM
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
GND_PW R
81
82
83
84
85
86
87
88
55
56
57
58
59
60
61
62
40
30
DVDD
VDDP
DGND
AGND
VDDM
39
32
31
22/24
HVP
HVP_CW
5
5,6,7,8,9,57
HVM
10
HVM_CW
REG1 L D 1 1 17
+5V
IN OUT
GND
Schematic
UM1977
Schematic
Figure 18: STEVAL-IME013V1 circuit schematic
NRST
JRST
JTCK
JTDO
JTMS
DVDD
JTDI
L4
L3
L2
L1
P4
P3
P2
P1
AUX7
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
AUX0
GSPG0308151420SG
UM1977
6
Revision history
Revision history
Table 7: Document revision history
Date
Version
Changes
02-Dec-2015
1
Initial release.
DocID028610 Rev 1
23/24
UM1977
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