Data Sheet

Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
FEATURES
PHN210
SYMBOL
• Dual device
• Low threshold voltage
• Fast switching
• Logic level compatible
• Surface mount package
QUICK REFERENCE DATA
d1 d1
VDS = 30 V
d2 d2
ID = 3.4 A
RDS(ON) ≤ 100 mΩ (VGS = 10 V)
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
s1
GENERAL DESCRIPTION
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using ’trench’
technology.
Applications:• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
The PHN210 is supplied in the
SOT96-1 (SO8) surface mounting
package.
s2 g2
g1
PINNING
PIN
SOT96-1
DESCRIPTION
1
source 1
2
gate 1
3
source 2
4
gate 2
5,6
drain 2
7,8
drain 1
pin 1 index
8
7
6
5
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDS
Repetitive peak drain-source
voltage
Continuous drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current per MOSFET1
Tj = 25 ˚C to 150˚C
VDS
VDGR
VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain current per MOSFET (both
MOSFETs conducting)1
Drain current per MOSFET (pulse
peak value)
Total power dissipation (either or
both MOSFETs conducting)1
Storage & operating temperature
RGS = 20 kΩ
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
MIN.
MAX.
UNIT
-
30
V
-
30
30
± 20
3.4
2.8
2.4
1.9
14
V
V
V
A
A
A
A
A
- 65
2
1.3
150
W
W
˚C
1 Surface mounted on FR4 board, t ≤ 10 sec
January 2002
1
Rev 1.100
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
Rth j-a
Surface mounted, FR4 board, t ≤ 10 sec
Rth j-a
Thermal resistance junction
to ambient
Thermal resistance junction
to ambient
Surface mounted, FR4 board
TYP.
MAX.
UNIT
-
62.5
K/W
150
-
K/W
MIN.
MAX.
UNIT
-
13
mJ
-
3.4
A
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS
Non-repetitive avalanche
energy (per MOSFET)
Unclamped inductive load, IAS = 3.4 A;
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
IAS
Non-repetitive avalanche
current (per MOSFET)
ELECTRICAL CHARACTERISTICS
Tj= 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 10 µA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
MIN.
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
2
80
120
4.5
10
0.6
10
2.8
3.2
100
200
170
100
10
100
V
V
V
V
V
mΩ
mΩ
mΩ
S
A
A
nA
µA
nA
IGSS
VGS = 10 V; ID = 2.2 A
VGS = 4.5 V; ID = 1 A
VGS = 10 V; ID = 2.2 A; Tj = 150˚C
Forward transconductance
VDS = 20 V; ID = 2.2 A
On-state drain current
VGS = 10 V; VDS = 1 V;
VGS = 4.5 V; VDS = 5 V
Zero gate voltage drain
VDS = 24 V; VGS = 0 V;
current
VDS = 24 V; VGS = 0 V; Tj = 150˚C
Gate source leakage current VGS = ±20 V; VDS = 0 V
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 2.3 A; VDD = 15 V; VGS = 10 V
-
6
0.7
0.7
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 20 V; RD = 18 Ω;
VGS = 10 V; RG = 6 Ω
Resistive load
-
6
8
21
15
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
2.5
5
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
250
88
54
-
pF
pF
pF
RDS(ON)
gfs
ID(ON)
IDSS
Drain-source on-state
resistance
30
27
1
0.4
2
3.5
2
-
TYP. MAX. UNIT
January 2002
2
Rev 1.100
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
Ta = 25 ˚C
VSD
Continuous source diode
current (per MOSFET)
Pulsed source diode current
(per MOSFET)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS
ISM
120
MIN.
TYP. MAX. UNIT
-
-
2.2
A
-
-
14
A
IF = 1.25 A; VGS = 0 V
-
0.82
1.2
V
IF = 1.25 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
69
55
-
ns
nC
Normalised Power Derating
PD%
110
100
100
PHN210
Peak Pulsed Drain Current, IDM (A)
90
80
tp = 10 us
RDS(on) = VDS/ ID
10
100 us
70
1 ms
60
1
50
10 ms
40
100 ms
30
0.1
10 s
20
10
0.01
0
0
20
40
60
80
100
Tamb / C
120
140
0.1
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ta)
120
1
10
Drain-Source Voltage, VDS (V)
100
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
110
100
100
PHN210
Zth j-a (K/W)
D = 0.5
90
10
80
0.2
0.1
0.05
70
60
0.02
1
P
D
50
tp
D = tp/T
40
0.1
30
single pulse
20
T
10
0.01
1E-06
0
0
20
40
60
80
100
Ambient temperature, Tamb (C)
120
140
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 10 V
January 2002
1E-05
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
3
Rev 1.100
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
Transconductance, gfs (S)
6
Drain Current, ID (A)
10
VGS = 20 V
9
8
10 V
5
5V
Tj = 25 C
4
Tj = 25 C
7
150 C
6
4.2 V
5
3
4V
4
2
3.8 V
3.6 V
3.4 V
3.2 V
3
2
1
1
0
0
0
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6
Drain-Source Voltage, VDS (V)
1.8
0
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
0.5
3.2 V
4V
2
4.2 V
2
3
4
5
6
7
Drain current, ID (A)
8
9
10
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID) ; parameter Tj
Drain-Source On Resistance, RDS(on) (Ohms)
3.6 V 3.8V
1
a
SOT223 30V Trench
Normalised RDS(ON) = f(Tj)
Tj = 25 C
3.4 V
0.4
1.5
0.3
1
0.2
VGS =5 V
10V
0.1
0.5
20V
0
0
1
2
3
4
5
6
Drain Current, ID (A)
7
8
9
0
-50
10
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
0
50
Tj / C
100
150
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
VGS(TO) / V
Drain current, ID (A)
10
4
VDS > ID X RDS(ON)
9
8
7
3
Tj = 25 C
6
max.
150 C
5
typ.
2
4
3
2
min.
1
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
-60 -40 -20
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
January 2002
0
20
40 60
Tj / C
80 100 120 140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
4
Rev 1.100
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
Sub-Threshold Conduction
1E-01
Source-Drain Diode Current, IF (A)
10
9
1E-02
VGS = 0 V
8
7
min
1E-03
typ
6
max
150 C
5
Tj = 25 C
4
1E-04
3
2
1
1E-05
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
1E-06
0
1
2
3
4
Drain-Source Voltage, VSDS (V)
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A)
PHN210
10
Capacitances, Ciss, Coss, Crss (pF)
1000
25 C
Ciss
Tj prior to avalanche =125 C
1
100
VDS
Coss
tp
Crss
ID
0.1
1E-06
10
0.1
1
10
Drain-Source Voltage, VDS (V)
100
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID = 2.3A
Tj = 25 C
VDD = 15 V
0
1
2
3
4
5
6
7
Gate charge, QG (nC)
8
9
10
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
January 2002
5
Rev 1.100
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
4
1
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
A
max.
A1
A2
1.75
0.25
0.10
1.45
1.25
0.010 0.057
0.069
0.004 0.049
A3
bp
c
D (1)
E (2)
e
HE
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.244
0.039 0.028
0.050
0.041
0.228
0.016 0.024
L
Lp
Q
1.05
1.0
0.4
0.7
0.6
v
0.25
0.01
w
0.25
0.01
y
Z (1)
0.1
0.7
0.3
0.028
0.004
0.012
θ
o
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
Fig.16. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
January 2002
6
Rev 1.100
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
DEFINITIONS
DATA SHEET STATUS
DATA SHEET
STATUS2
PRODUCT
STATUS3
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
2 Please consult the most recently issued datasheet before initiating or completing a design.
3 The product status of the device(s) described in this datasheet may have changed since this datasheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
January 2002
7
Rev 1.100
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