PSMN015-100YL N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 14 April 2016 Product data sheet 1. General description Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS technology. This product is designed and qualified for use in a wide range of power supply & motor control equipment. 2. Features and benefits • • • • Advanced TrenchMOS provides low RDSon and low gate charge Logic level gate operation Avalanche rated, 100 % tested LFPAK provides maximum power density in a Power SO8 package 3. Applications • • • • • Synchronous rectification in power supply equipment Chargers & adaptors with Vout < 10 V Fast charge & USB-PD applications Battery powered motor control LED lighting & TV backlight 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 100 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 69 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 195 W VGS = 5 V; ID = 20 A; Tj = 25 °C; Fig. 11 - 12.1 15 mΩ ID = 20 A; VDS = 80 V; VGS = 5 V; - 16 - nC Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Fig. 13; Fig. 14 Scan or click this QR code to view the latest information for this product PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN015-100YL Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Marking Table 4. Marking codes Type number Marking code PSMN015-100YL 15L100 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 100 V VDGR drain-gate voltage RGS = 20 kΩ - 100 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 195 W ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - 69 A VGS = 5 V; Tmb = 100 °C; Fig. 2 - 49 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 274 A -55 175 °C IDM peak drain current Tstg storage temperature PSMN015-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Tj junction temperature Min Max Unit -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 69 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 274 A - 110 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 69 A; Vsup ≤ 100 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [1] [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 03aa16 120 003aai775 80 ID (A) Pder (%) 60 80 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature PSMN015-100YL Product data sheet 0 200 Fig. 2. 0 50 150 Tmb (°C) 200 Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 14 April 2016 100 © NXP Semiconductors N.V. 2016. All rights reserved 3 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 003aai777 103 ID (A) Limit R DSon = VDS / ID 102 tp =10 µ s 100 µ s 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 Fig. 3. 1 102 10 103 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003aai776 103 IAL (A) 102 10 (1) 1 (2) (3) 10-1 10-3 Fig. 4. 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 0.77 K/W PSMN015-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 Zth(j-mb) (K/W) aaa-018259 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 single shot P 10-2 δ= tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 tp T t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration. 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - V gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9; 1.4 1.7 2.1 V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9 - - 2.45 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9 0.5 - - V VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.11 10 µA VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 20 A; Tj = 25 °C; Fig. 11 - 12.1 15 mΩ VGS = 10 V; ID = 20 A; Tj = 25 °C; - 11.6 14.7 mΩ - - 41.4 mΩ - 86.3 - nC ID = 20 A; VDS = 80 V; VGS = 5 V; - 45.8 - nC Fig. 13; Fig. 14 - 11 - nC Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 10 Fig. 11 VGS = 5 V; ID = 20 A; Tj = 175 °C; Fig. 12; Fig. 11 Dynamic characteristics QG(tot) total gate charge ID = 20 A; VDS = 80 V; VGS = 10 V; Fig. 13; Fig. 14 QGS gate-source charge PSMN015-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 5 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 16 - nC Ciss input capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; - 4604 6139 pF Tj = 25 °C; Fig. 15 Coss output capacitance - 269 323 pF Crss reverse transfer capacitance - 156 213 pF td(on) turn-on delay time VDS = 80 V; RL = 4 Ω; VGS = 5 V; - 21 - ns tr rise time RG(ext) = 5 Ω - 32 - ns td(off) turn-off delay time - 85 - ns tf fall time - 59 - ns Source-drain diode VSD source-drain voltage IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.8 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 38 - ns Qr recovered charge VDS = 25 V - 64 - nC ID (A) 003aai779 75 3 10 4.5 60 003aai780 30 R DSon (mΩ) 25 2.8 20 45 15 30 2.6 10 15 5 VGS (V) = 2.4 0 0 1 2 V DS(V) 0 3 Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values PSMN015-100YL Product data sheet 0 2 6 8 10 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 14 April 2016 4 © NXP Semiconductors N.V. 2016. All rights reserved 6 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 003aai782 160 003aah025 3 VGS(th) (V) 2.5 ID (A) max 120 2 typ 1.5 80 min 1 40 Tj = 175 °C 0 Fig. 8. 0 1 0.5 Tj = 25 °C 2 3 VGS (V) 0 -60 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values 003aah026 10-1 Fig. 9. 0 10-2 120 Tj (° C) 180 Gate-source threshold voltage as a function of junction temperature 003aai785 30 R DSon (mΩ ) ID (A) 60 2.8 24 min 10-3 typ 3 max 18 4.5 10-4 12 10-5 6 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage PSMN015-100YL Product data sheet VGS (V) = 10 0 20 40 60 ID (A) 80 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 7 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 003aag818 3 VDS a ID 2.4 VGS(pl) 1.8 VGS(th) VGS 1.2 QGS2 QGS1 0.6 0 -60 0 60 120 Tj (°C) QGS QGD QG(tot) 003aaa508 Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aai787 10 VGS (V) 003aai788 104 C (pF) 8 C iss 6 VDS = 14V VDS = 80V 103 4 2 0 Coss 0 20 40 60 80 100 QG (nC) Fig. 14. Gate-source voltage as a function of gate charge; typical values PSMN015-100YL Product data sheet 102 10-1 C rss 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 8 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 003aai789 80 IS (A) 60 40 20 0 Tj = 25 ° C Tj = 175° C 0 0.3 0.6 0.9 V (V) 1.2 SD Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN015-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 9 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 mm c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN015-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 10 / 13 PSMN015-100YL NXP Semiconductors N-channel 100 V, 15 mΩ logic level MOSFET in LFPAK56 In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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PSMN015-100YL Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 April 2016 PSMN015-100YL Product data sheet All information provided in this document is subject to legal disclaimers. 14 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 13 / 13