Data Sheet

LF
PA
K
33
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33
designed specifically for PoE applications
26 March 2013
Product data sheet
1. General description
New standards and proprietary approaches are enabling the next generation of Powerover-Ethernet (PoE) systems capable of delivering up to 100W to each powered
device (PD). Large screen LCD displays, 3G / 4G / Wi-Fi hot-spots and pan-tilt-zoom
CCTV cameras, for example, are placing increased demands on the power sourcing
equipment (PSE) in terms of “soft-start” procedures, resilience to short-circuits, thermal
management and power density. Part of NXP’s “NextPower Live” MOSFET portfolio,
the PSMN075-100MSE has been designed specifically to compliment the latest PoE
controllers, offering both superior linear mode operation and very low RDS(on) in a costeffective, industry compatible, LFPAK33 package.
2. Features and benefits
•
•
•
•
Enhanced forward biased safe operating area for superior linear mode operation
Low Rdson for low conduction losses
Ultra reliable LFPAK33 package – no glue, no wires, 175°C
Very low IDSS
3. Applications
•
•
•
IEEE802.3at and proprietary solutions - (type 2)
Suitable for PoE applications upto 30W
Use PSMN040-100MSE for higher power requirements
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
100
V
ID
drain current
Tj = 25 °C; VGS = 10 V; Fig. 1
-
-
18
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
-
65
W
VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12
-
57
71
mΩ
VGS = 10 V; ID = 5 A; VDS = 50 V;
-
5.3
-
nC
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD
gate-drain charge
Tj 25 °C; Fig. 14; Fig. 15
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
QG(tot)
total gate charge
VGS = 10 V; ID = 5 A; VDS = 50 V;
-
16.4
-
nC
-
-
25
mJ
Tj = 25 °C; Fig. 14; Fig. 15
Avalanche Ruggedness
EDS(AL)S
non-repetitive drainsource avalanche
energy
VGS = 10 V; Tj(init) = 25 °C; ID = 18 A;
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
G
S
mbb076
1
2
3
4
LFPAK33 (SOT1210)
6. Ordering information
Table 3.
Ordering information
Type number
Package
PSMN075-100MSE
Name
Description
Version
LFPAK33
Plastic single ended surface mounted package (LFPAK33); 4
leads
SOT1210
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN075-100MSE
M75E10
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
100
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
100
V
PSMN075-100MSE
Product data sheet
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
Parameter
Conditions
VGS
gate-source voltage
ID
drain current
Min
Max
Unit
-20
20
V
VGS = 10 V; Tj = 25 °C; Fig. 1
-
18
A
VGS = 10 V; Tmb = 100 °C; Fig. 1
-
13
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
-
74
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
65
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
-
260
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
54
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
74
A
VGS = 10 V; Tj(init) = 25 °C; ID = 18 A;
-
25
mJ
Avalanche Ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
ID
(A)
003aak714
20
03aa16
120
Pder
(%)
16
80
12
8
40
4
0
Fig. 1.
0
25
50
75
100
125
150 175
Tj (°C)
Continuous drain current as a function of
mounting base temperature
PSMN075-100MSE
Product data sheet
0
200
Fig. 2.
0
100
150
Tmb (°C)
200
Normalized total power dissipation as a
function of mounting base temperature
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
IAL
(A)
003aak715
102
10
(1)
(2)
1
10-1
10-3
Fig. 3.
10-2
10-1
1
tAL (ms)
10
Single pulse avalanche rating; avalanche current as a function of avalanche time
ID
(A)
003aak716
102
Limit RDSon = VDS / ID
tp = 10 us
10
100 us
1 ms
DC
1
10 ms
100 ms
10-1
Fig. 4.
1
102
10
VDS (V)
103
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
2.09
2.32
K/W
PSMN075-100MSE
Product data sheet
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak717
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
0.05
P
0.02
δ=
Fig. 5.
T
single shot
tp
10-2
10-6
tp
10-5
10-4
10-3
10-2
10-1
t
T
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
100
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
90
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
2.3
3.3
4
V
1
-
-
V
-
-
4.6
V
VDS = 100 V; VGS = 0 V; Tj = 25 °C
-
0.01
1
µA
VDS = 100 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
10
100
nA
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
10
100
nA
VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12
-
57
71
mΩ
VGS = 10 V; ID = 5 A; Tj = 100 °C;
-
-
128
mΩ
-
-
192
mΩ
-
1.55
-
Ω
Static characteristics
V(BR)DSS
VGS(th)
Fig. 10; Fig. 11
ID = 1 mA; VDS = VGS; Tj = 175 °C;
Fig. 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 10
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
Fig. 13; Fig. 12
VGS = 10 V; ID = 5 A; Tj = 175 °C;
Fig. 13; Fig. 12
RG
gate resistance
PSMN075-100MSE
Product data sheet
f = 10 MHz
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ID = 5 A; VDS = 50 V; VGS = 10 V;
-
16.4
-
nC
-
12.9
-
nC
Dynamic characteristics
QG(tot)
total gate charge
Tj = 25 °C; Fig. 14; Fig. 15
ID = 0 A; VDS = 0 V; VGS = 10 V;
Tj = 25 °C
QGS
gate-source charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
-
3.1
-
nC
QGS(th)
pre-threshold gatesource charge
Tj = 25 °C; Fig. 14; Fig. 15
-
2.1
-
nC
QGS(th-pl)
post-threshold gatesource charge
-
1
-
nC
QGD
gate-drain charge
-
5.3
-
nC
-
4.3
-
V
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj 25 °C; Fig. 14; Fig. 15
VGS(pl)
gate-source plateau
voltage
ID = 5 A; VDS = 50 V; Tj = 25 °C;
input capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
-
773
-
pF
Coss
output capacitance
Tj = 25 °C; Fig. 16
-
66
-
pF
Crss
reverse transfer
capacitance
-
48
-
pF
td(on)
turn-on delay time
VDS = 50 V; RL = 10 Ω; VGS = 10 V;
-
5.5
-
ns
tr
rise time
RG(ext) = 5 Ω; Tj = 25 °C
-
5.8
-
ns
td(off)
turn-off delay time
-
12.4
-
ns
tf
fall time
-
6.2
-
ns
Ciss
Fig. 14; Fig. 15
Source-drain diode
VSD
source-drain voltage
IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
0.89
1.2
V
trr
reverse recovery time
IS = 5 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
35.8
-
ns
recovered charge
VDS = 50 V; Tj = 25 °C
-
50.7
-
nC
Qr
PSMN075-100MSE
Product data sheet
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
ID
(A)
003aak718
20
16
003aak719
200
RDSon
6.5 V
10 V
8V
7V
6V
160
12
VGS = 5.5 V
8
5V
80
4
4.5 V
40
120
44 V
V
0
Fig. 6.
0
0.5
1
1.5
2
2.5
VDS (V)
0
3
Output characteristics; drain current as a
Fig. 7.
function of drain-source voltage; typical values
gfs
(S)
4
8
12
ID
(A)
20
6
15
4
10
2
5
175°C
Fig. 8.
0
2
4
6
8
10
ID (A)
0
12
Forward transconductance as a function of
drain current; typical values
PSMN075-100MSE
Product data sheet
Fig. 9.
0
1
2
3
Tj = 25°C
4
5
6
7
VGS (V)
8
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
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26 March 2013
20
003aak721
25
8
0
16
VGS (V)
Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aak720
10
0
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7 / 13
PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak573
5
VGS(th) (V)
ID
(A)
Max
4
3
10- 5
-30
0
30
60
90
120 150
Tj (°C)
180
10- 6
4.5 V
5V
5.5 V
0
2
4
6
VGS (V)
Fig. 11. Sub-threshold drain current as a function of
gate-source voltage
003aak722
RDSon
max
10- 4
Min
Fig. 10. Gate-source threshold voltage as a function of
junction temperature
160
typ
10- 3
1
0
-60
min
10- 2
Typ
2
003aak574
10- 1
003aaj323
3
6V
a
140
2.4
120
1.8
100
6.5 V
1.2
80
0.6
60
7 V 8 V 10 V
40
0
4
8
12
16
ID (A)
Fig. 12. Drain-source on-state resistance as a function
of drain current; typical values
PSMN075-100MSE
Product data sheet
0
-60
20
0
60
120
Tj (°C)
180
Fig. 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
VDS
VGS
(V)
ID
003aak723
10
8
VGS(pl)
VGS = 20 V
80 V
6
VGS(th)
VGS
4
QGS1
50 V
QGS2
QGS
QGD
QG(tot)
2
003aaa508
0
Fig. 14. Gate charge waveform definitions
0
4
8
12
16
QG (nC)
20
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
003aak724
103
C
(pF)
IS
(A)
Ciss
003aak725
20
16
12
102
Coss
8
Crss
175°C
4
10
10-1
1
10
VDS (V)
0
102
0
0.2
0.4
Tj = 25°C
0.6
0.8
1
VSD (V)
1.2
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain
as a function of drain-source voltage; typical
voltage; typical values
values
PSMN075-100MSE
Product data sheet
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
11. Package outline
Plastic single ended surface mounted package (LFPAK33); 8 leads
E
e1
L
SOT1210
A
A
c1
b1
E1
mounting
base
D1
D
H
1
4
e
b
w
X
A
A1
c
C
θ
Lp
y C
detail X
0
2.5
Dimensions
Unit(1)
mm
5 mm
scale
A
A1
b
b1
c
c1
D(1)
D1
E(1)
E1
e
e1
H
L
Lp
w
y
max 0.90 0.10 0.35 0.35 0.20 0.30 2.70 2.35 3.40 2.45
3.40 0.25 0.50
nom
0.65 0.65
0.20 0.10
3.20 0.13 0.30
min 0.80 0.00 0.25 0.25 0.10 0.20 2.50 1.90 3.20 2.00
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
Outline
version
JEDEC
8°
0°
sot1210_po
References
IEC
θ
JEITA
European
projection
Issue date
11-12-19
12-03-12
SOT1210
Fig. 18. Package outline LFPAK33 (SOT1210)
PSMN075-100MSE
Product data sheet
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Please consult the most recently issued document before initiating or
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The product status of device(s) described in this document may have
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Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
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representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
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with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
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Limited warranty and liability — Information in this document is believed
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or completeness of such information and shall have no liability for the
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PSMN075-100MSE
Product data sheet
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authorized or warranted to be suitable for use in life support, life-critical or
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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representation or warranty that such applications will be suitable for the
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
grant, conveyance or implication of any license under any copyrights, patents
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liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN075-100MSE
Product data sheet
All information provided in this document is subject to legal disclaimers.
26 March 2013
© NXP B.V. 2013. All rights reserved
12 / 13
PSMN075-100MSE
NXP Semiconductors
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 2
8
Limiting values .......................................................2
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 5
11
Package outline ................................................... 10
12
12.1
12.2
12.3
12.4
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
© NXP B.V. 2013. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 March 2013
PSMN075-100MSE
Product data sheet
All information provided in this document is subject to legal disclaimers.
26 March 2013
© NXP B.V. 2013. All rights reserved
13 / 13