PSMN1R0-25YLD N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 19 April 2016 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers high efficiency, low spiking performance usually associated with MOSFETS with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits • • • • • • • • • 100% Avalanche tested at I(AS) = 100 A Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching frequencies Superfast switching with soft-recovery Low spiking and ringing for low EMI designs Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at 25 °C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package; no glue, no wire bonds, qualified to 175 °C Wave solderable; exposed leads for optimal visual solder inspection 3. Applications • • • • • • • On-board DC:DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control Power OR-ing 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 25 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 100 A Scan or click this QR code to view the latest information for this product [1] PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 160 W Tj junction temperature -55 - 175 °C - 0.89 1 mΩ - 1.19 1.43 mΩ - 71.8 - nC - 33.2 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 39.7 - nC ID = 25 A; VDS = 12 V; VGS = 4.5 V; - 8 - nC - 0.9 - Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS = 12 V; VGS = 10 V; Fig. 12; Fig. 13 ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 QGD gate-drain charge Fig. 12; Fig. 13 Source-drain diode S softness factor IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 12 V; Fig. 16 [1] Continuous current is limited by package. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number PSMN1R0-25YLD PSMN1R0-25YLD Product data sheet Package Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 7. Marking Table 4. Marking codes Type number Marking code PSMN1R0-25YLD 1D025L PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 3 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 25 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 160 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 100 A VGS = 10 V; Tmb = 100 °C; Fig. 2 [1] - 100 A - 1226 A IDM peak drain current tp ≤ 10 µs; Fig. 3 Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage 1700 - V - 100 A - 1226 A - 1762 mJ HBM Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C [1] Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 25 A; Vsup ≤ 25 V; RGS = 50 Ω; [2][3] VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 4.34 ms [1] [2] [3] PSMN1R0-25YLD Product data sheet Continuous current is limited by package. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 03na19 120 aaa-022183 200 ID (A) Pder (%) 150 80 100 (1) 40 50 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 25 50 75 100 125 150 175 Tmb (°C) (1) Capped at 100A due to package Continuous drain current as a function of mounting base temperature aaa-022213 104 103 200 VGS ≥ 10 V Normalized total power dissipation as a function of mounting base temperature Fig. 2. ID (A) 0 Limit RDSon = VDS / ID tp = 10 us 102 100 us DC 10 1 ms 10 ms 100 ms 1 10-1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 5 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 4 - 0.68 0.94 K/W Rth(j-a) thermal resistance from junction to ambient Fig. 5 - 50 - K/W Fig. 6 - 125 - K/W Zth(j-mb) (K/W) aaa-022204 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 single shot P 10-2 δ= tp 10-3 10-6 Fig. 4. 10-5 10-4 10-3 10-2 T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration aaa-005751 aaa-005750 Fig. 5. 10-1 tp PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper PSMN1R0-25YLD Product data sheet Fig. 6. PCB layout for thermal resistance junction to ambient minimum footprint; FR4 Board; 2oz copper All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 6 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 25 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 22.5 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C 1.2 1.75 2.2 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 175 °C - -5 - mV/K IDSS drain leakage current VDS = 20 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 20 V; VGS = 0 V; Tj = 125 °C - 29.7 - µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; - 0.89 1 mΩ - - 1.7 mΩ - 1.19 1.43 mΩ - - 2.43 mΩ f = 1 MHz - 1.14 - Ω ID = 25 A; VDS = 12 V; VGS = 10 V; - 71.8 - nC - 33.2 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 39.7 - nC Static characteristics V(BR)DSS IGSS RDSon gate leakage current drain-source on-state resistance Fig. 10 VGS = 10 V; ID = 25 A; Tj = 175 °C; Fig. 10; Fig. 11 VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 4.5 V; ID = 25 A; Tj = 175 °C; Fig. 10; Fig. 11 RG gate resistance Dynamic characteristics QG(tot) total gate charge Fig. 12; Fig. 13 ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 QGS gate-source charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; - 12.9 - nC QGS(th) pre-threshold gatesource charge Fig. 12; Fig. 13 - 7.8 - nC QGS(th-pl) post-threshold gatesource charge - 5.1 - nC QGD gate-drain charge - 8 - nC VGS(pl) gate-source plateau voltage - 2.7 - V PSMN1R0-25YLD Product data sheet ID = 25 A; VDS = 12 V; Fig. 12; Fig. 13 All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 7 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit Ciss input capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; - 5308 - pF Coss output capacitance Tj = 25 °C; Fig. 14 - 1979 - pF Crss reverse transfer capacitance - 342 - pF td(on) turn-on delay time VDS = 12 V; RL = 0.6 Ω; VGS = 4.5 V; - 30.3 - ns tr rise time RG(ext) = 5 Ω - 36 - ns td(off) turn-off delay time - 34 - ns tf fall time - 24.5 - ns Qoss output charge - 36.4 - nC VGS = 0 V; VDS = 12 V; f = 1 MHz; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.79 1.2 V trr reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; - 36.9 - ns Qr recovered charge VDS = 12 V; Fig. 16 - 36.7 - nC ta reverse recovery rise time - 19.2 - ns tb reverse recovery fall time - 17.7 - ns S softness factor - 0.9 - [1] ID (A) includes capacitive recovery aaa-022205 80 VGS =3 V 3.5 V 4.5 V 10 V 64 [1] 2.8 V 16 48 12 32 8 2.6 V 16 0 Fig. 7. aaa-022206 20 RDSon (mΩ) 4 0 0.5 1 1.5 2 VDS (V) 0 2.5 0 2 4 6 8 10 12 14 VGS (V) 16 Tj = 25 °C Tj = 25 °C; ID = A Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values Drain-source on-state resistance as a function of gate-source voltage; typical values PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 8 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology aaa-022297 200 ID (A) aaa-022207 25 RDSon (mΩ) 2.8 V 20 150 15 100 10 50 175°C 0 0 0.5 1 1.5 2 2.5 3 3.5 VGS (V) a 3V 4.5 V 3.5 V 0 4 VDS = 12 V Fig. 9. VGS = 10 V 5 Tj = 25°C 0 16 32 48 64 ID (A) 80 Tj = 25 °C Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 10. Drain-source on-state resistance as a function of drain current; typical values aaa-021697 2 VGS (V) 10 V 1.6 1.2 aaa-022208 10 8 6 VGS = 4.5 V 20 V 0.8 12 V 4 VDS = 5 V 0.4 0 -60 2 -30 0 30 60 90 120 150 Tj (°C) 0 180 Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN1R0-25YLD Product data sheet 0 10 20 30 40 50 60 70 QG (nC) 80 Tj = 25 °C; ID = 25 A Fig. 12. Gate-source voltage as a function of gate charge; typical values All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 9 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology aaa-022209 104 C (pF) VDS ID Ciss Coss 103 VGS(pl) Crss VGS(th) VGS QGS2 QGS1 QGS 102 QGD QG(tot) 003aaa508 10 10-1 Fig. 13. Gate charge waveform definitions 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values IS (A) 003aal160 aaa-022210 103 ID (A) 102 trr ta 0.25 IRM 1 175°C 10-1 tb 0 10 0 0.2 Tj = 25°C 0.4 0.6 0.8 IRM 1 VSD (V) t (s) 1.2 VGS = 0 V Fig. 16. Reverse recovery timing definition Fig. 15. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 10 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) mm A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 11 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. 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PSMN1R0-25YLD Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 12 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 13 / 14 PSMN1R0-25YLD NXP Semiconductors N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 3 8 Limiting values .......................................................4 9 Thermal characteristics .........................................6 10 Characteristics ....................................................... 7 11 Package outline ................................................... 11 12 12.1 12.2 12.3 12.4 Legal information .................................................12 Data sheet status ............................................... 12 Definitions ...........................................................12 Disclaimers .........................................................12 Trademarks ........................................................ 13 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 April 2016 PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 19 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved 14 / 14