Data Sheet

PSMN8R5-100ES
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
11 October 2012
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in a I2PAK package qualified to 175 °C. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
• High efficiency due to low switching and conduction losses
• Suitable for standard level gate drive sources
1.3 Applications
• AC-to-DC power supply equipment
• Motor control
• Server power supplies
• Synchronous rectification
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
100
V
ID
drain current
Tj = 25 °C; VGS = 10 V; Fig. 1
-
-
100
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
-
263
W
VGS = 10 V; ID = 25 A; Tj = 25 °C;
-
6.4
8.5
mΩ
[1]
Static characteristics
RDSon
drain-source on-state
resistance
Fig. 13; Fig. 12
Dynamic characteristics
QGD
gate-drain charge
VGS = 10 V; ID = 25 A; VDS = 50 V;
-
33
-
nC
QG(tot)
total gate charge
Fig. 14; Fig. 15
-
111
-
nC
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
-
-
219
mJ
Avalanche Ruggedness
EDS(AL)S
non-repetitive drainsource avalanche
energy
[1]
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
Continious current limited by package.
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
S
mbb076
1 2 3
I2PAK (SOT226)
3. Ordering information
Table 3.
Ordering information
Type number
Package
PSMN8R5-100ES
Name
Description
Version
I2PAK
plastic single-ended package (I2PAK); TO-262
SOT226
4. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN8R5-100ES
PSMN8R5-100ES
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
100
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
100
V
VGS
gate-source voltage
-20
20
V
ID
drain current
-
100
A
VGS = 10 V; Tmb = 100 °C; Fig. 1
-
75
A
VGS = 10 V; Tj = 25 °C; Fig. 1
[1]
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
-
429
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
263
W
Tstg
storage temperature
-55
175
°C
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
Symbol
Parameter
Tj
Tsld(M)
Conditions
Min
Max
Unit
junction temperature
-55
175
°C
peak soldering temperature
-
260
°C
-
100
A
Source-drain diode
IS
source current
Tmb = 25 °C
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
429
A
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
-
219
mJ
[1]
Avalanche Ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
[1]
Continious current limited by package.
003aak417
160
ID
(A)
03aa16
120
Pder
(%)
120
80
(1)
80
40
40
0
0
50
100
150
Tmb (°C)
(1) Capped at 100A due to package
Fig. 1.
Continuous drain current as a function of
mounting base temperature
PSMN8R5-100ES
Product data sheet
0
200
Fig. 2.
0
100
150
Tmb (°C)
200
Normalized total power dissipation as a
function of mounting base temperature
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3 / 14
PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
003aak418
103
IAL
(A)
102
(1)
10
(2)
1
10-3
Fig. 3.
10-2
10-1
1
tAL (ms)
10
Avalanche rating; avalanche current as a function of avalanche time
003aak419
103
ID
(A)
Limit RDSon = V DS / ID
tp =10 µ s
102
100 µ s
10
DC
1 ms
1
10 ms
100 ms
10-1
10-1
Fig. 4.
1
10
102
103
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
0.49
0.57
K/W
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
003aah108
1
δ = 0.5
Zth(j-mb)
(K/W)
0.2
10-1
0.1
0.05
0.02
10
-2
10
-3
P
single shot
tp
10-6
Fig. 5.
10-5
10-4
10-3
10-2
tp
T
δ=
t
T
10-1
1
tp (s)
Transient thermal impedance from junction to mounting base as a function of pulse duration
7. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
100
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
90
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
2.4
3
4
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 175 °C;
1
-
-
V
-
-
4.5
V
VDS = 100 V; VGS = 0 V; Tj = 25 °C
-
0.02
1
µA
VDS = 100 V; VGS = 0 V; Tj = 100 °C
-
-
20
µA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = 10 V; ID = 25 A; Tj = 175 °C;
-
-
22.6
mΩ
-
-
14.9
mΩ
-
6.4
8.5
mΩ
-
0.71
-
Ω
Static characteristics
V(BR)DSS
VGS(th)
VGSth
Fig. 10; Fig. 11
Fig. 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 10
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
Fig. 12
VGS = 10 V; ID = 25 A; Tj = 100 °C;
Fig. 12
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 13; Fig. 12
RG
gate resistance
PSMN8R5-100ES
Product data sheet
f = 1 MHz
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
total gate charge
ID = 25 A; VDS = 50 V; VGS = 10 V;
-
111
-
nC
QGS
gate-source charge
Fig. 14; Fig. 15
-
24
-
nC
QGS(th)
pre-threshold gatesource charge
-
16
-
nC
QGS(th-pl)
post-threshold gatesource charge
-
8
-
nC
QGD
gate-drain charge
-
33
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 15 A; VDS = 50 V; Fig. 14; Fig. 15
-
4.4
-
V
Ciss
input capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
-
5512
-
pF
-
380
-
pF
-
256
-
pF
Dynamic characteristics
QG(tot)
Tj = 25 °C; Fig. 16; Fig. 17
Coss
output capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
td(on)
turn-on delay time
VDS = 50 V; RL = 2 Ω; VGS = 10 V;
-
20
-
ns
tr
rise time
RG(ext) = 5 Ω
-
35
-
ns
td(off)
turn-off delay time
-
87
-
ns
tf
fall time
-
43
-
ns
Tj = 25 °C; Fig. 16; Fig. 17
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 18
-
0.82
1.2
V
trr
reverse recovery time
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
53
-
ns
Qr
recovered charge
VDS = 50 V
-
124
-
nC
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
003aah739
240
6
VGS (V) = 10
ID
(A)
003aak421
20
RDSon
(mΩ )
5.5
180
15
5
120
10
60
5
4.5
0
4
0
2
4
0
6
VDS(V)
Tj = 25 °C; tp = 300 μs
Fig. 6.
Fig. 7.
003aak425
5
10
15 V (V) 20
GS
Drain-source on-state resistance as a function
of gate-source voltage; typical values
Output characteristics; drain current as a
function of drain-source voltage; typical values
120
0
003aah742
250
ID
(A)
gfs
(S)
200
90
150
60
100
30
Tj = 25 °C
50
0
Fig. 8.
Tj = 175 °C
0
80
160
240
320
ID (A)
0
400
Forward transconductance as a function of
drain current; typical values
PSMN8R5-100ES
Product data sheet
Fig. 9.
0
2
6
8
VGS (V)
10
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
003aah027
5
VGS(th)
(V)
ID
(A)
max
4
10-2
3
typ
10-3
2
min
10-4
0
60
120
T j (°C)
10-6
180
Fig. 10. Gate-source threshold voltage as a function of
junction temperature
003aag818
3
20
1.8
15
1.2
10
0.6
5
60
120
Tj (°C)
0
180
Fig. 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN8R5-100ES
Product data sheet
max
2
4
6
VGS (V)
Fig. 11. Sub-threshold drain current as a function of
gate-source voltage
2.4
0
0
003aak422
25
RDSon
(mΩ )
a
0
-60
typ
min
10-5
1
0
-60
003aah028
10-1
4.5
5.5
5
6
VGS (V) = 10
0
80
160
ID (A)
240
Fig. 13. Drain-source on-state resistance as a function
of drain current; typical values
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
003aak426
10
VGS
(V)
VDS
ID
8
VGS(pl)
20 V
6
80 V
VGS(th)
VDS = 50 V
4
VGS
QGS1
QGS2
QGS
2
QGD
QG(tot)
003aaa508
0
0
40
80
QG (nC)
120
Fig. 15. Gate charge waveform definitions
Fig. 14. Gate-source voltage as a function of gate
charge; typical values
003aak423
104
C
(pF)
003aak424
12000
C
(pF)
Ciss
Ciss
8000
103
Coss
Crss
4000
Crss
102
10-1
1
10
VDS (V)
0
102
0
4
8
VGS (V)
12
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Input and reverse transfer capacitances as a
as a function of drain-source voltage; typical
function of gate-source voltage, typical values
values
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
003aah749
400
IS
(A)
320
240
160
Tj = 175° C
80
0
Tj = 25 °C
0
0.4
0.8
1.2
V SD (V)
1.6
Fig. 18. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
8. Package outline
Plastic single-ended package (I2PAK); low-profile 3-lead TO-262
SOT226
A
A1
E
D1
mounting
base
D
L1
Q
b1
L
1
2
3
b
e
c
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
c
D
max
D1
E
e
L
L1
Q
mm
4.5
4.1
1.40
1.27
0.85
0.60
1.3
1.0
0.7
0.4
11
1.6
1.2
10.3
9.7
2.54
15.0
13.5
3.30
2.79
2.6
2.2
OUTLINE
VERSION
SOT226
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
06-02-14
09-08-25
TO-262
Fig. 19. Package outline I2PAK (SOT226)
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
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punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
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whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
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is deemed to offer functions and qualities beyond those described in the
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or completeness of such information and shall have no liability for the
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PSMN8R5-100ES
Product data sheet
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product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
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Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
grant, conveyance or implication of any license under any copyrights, patents
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9.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN8R5-100ES
Product data sheet
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PSMN8R5-100ES
NXP Semiconductors
N-channel 100 V 8.5 mΩ standard level MOSFET in I2PAK
10. Contents
1
1.1
1.2
1.3
1.4
Product profile ....................................................... 1
General description .............................................. 1
Features and benefits ...........................................1
Applications .......................................................... 1
Quick reference data ............................................ 1
2
Pinning information ............................................... 2
3
Ordering information ............................................. 2
4
Marking ................................................................... 2
5
Limiting values .......................................................2
6
Thermal characteristics .........................................4
7
Characteristics ....................................................... 5
8
Package outline ................................................... 11
9
9.1
9.2
9.3
9.4
Legal information .................................................12
Data sheet status ............................................... 12
Definitions ...........................................................12
Disclaimers .........................................................12
Trademarks ........................................................ 13
© NXP B.V. 2012. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 October 2012
PSMN8R5-100ES
Product data sheet
All information provided in this document is subject to legal disclaimers.
11 October 2012
© NXP B.V. 2012. All rights reserved
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